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1 | 9a64fbe4 | bellard | /*
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2 | a541f297 | bellard | * QEMU PPC PREP hardware System Emulator
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3 | 5fafdf24 | ths | *
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4 | 47103572 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | 9a64fbe4 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "nvram.h" |
26 | 87ecb68b | pbrook | #include "pc.h" |
27 | 87ecb68b | pbrook | #include "fdc.h" |
28 | 87ecb68b | pbrook | #include "net.h" |
29 | 87ecb68b | pbrook | #include "sysemu.h" |
30 | 87ecb68b | pbrook | #include "isa.h" |
31 | 87ecb68b | pbrook | #include "pci.h" |
32 | 87ecb68b | pbrook | #include "ppc.h" |
33 | 87ecb68b | pbrook | #include "boards.h" |
34 | 3b3fb322 | blueswir1 | #include "qemu-log.h" |
35 | 9fddaa0c | bellard | |
36 | 9a64fbe4 | bellard | //#define HARD_DEBUG_PPC_IO
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37 | a541f297 | bellard | //#define DEBUG_PPC_IO
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38 | 9a64fbe4 | bellard | |
39 | fe33cc71 | j_mayer | /* SMP is not enabled, for now */
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40 | fe33cc71 | j_mayer | #define MAX_CPUS 1 |
41 | fe33cc71 | j_mayer | |
42 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
43 | e4bcb14c | ths | |
44 | bba831e8 | Paul Brook | #define BIOS_SIZE (1024 * 1024) |
45 | b6b8bd18 | bellard | #define BIOS_FILENAME "ppc_rom.bin" |
46 | b6b8bd18 | bellard | #define KERNEL_LOAD_ADDR 0x01000000 |
47 | b6b8bd18 | bellard | #define INITRD_LOAD_ADDR 0x01800000 |
48 | 64201201 | bellard | |
49 | 9a64fbe4 | bellard | #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
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50 | 9a64fbe4 | bellard | #define DEBUG_PPC_IO
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51 | 9a64fbe4 | bellard | #endif
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52 | 9a64fbe4 | bellard | |
53 | 9a64fbe4 | bellard | #if defined (HARD_DEBUG_PPC_IO)
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54 | 001faf32 | Blue Swirl | #define PPC_IO_DPRINTF(fmt, ...) \
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55 | 9a64fbe4 | bellard | do { \
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56 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
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57 | 001faf32 | Blue Swirl | qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \ |
58 | 9a64fbe4 | bellard | } else { \
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59 | 001faf32 | Blue Swirl | printf("%s : " fmt, __func__ , ## __VA_ARGS__); \ |
60 | 9a64fbe4 | bellard | } \ |
61 | 9a64fbe4 | bellard | } while (0) |
62 | 9a64fbe4 | bellard | #elif defined (DEBUG_PPC_IO)
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63 | 001faf32 | Blue Swirl | #define PPC_IO_DPRINTF(fmt, ...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__) |
64 | 9a64fbe4 | bellard | #else
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65 | 001faf32 | Blue Swirl | #define PPC_IO_DPRINTF(fmt, ...) do { } while (0) |
66 | 9a64fbe4 | bellard | #endif
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67 | 9a64fbe4 | bellard | |
68 | 64201201 | bellard | /* Constants for devices init */
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69 | a541f297 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
70 | a541f297 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
71 | a541f297 | bellard | static const int ide_irq[2] = { 13, 13 }; |
72 | a541f297 | bellard | |
73 | a541f297 | bellard | #define NE2000_NB_MAX 6 |
74 | a541f297 | bellard | |
75 | a541f297 | bellard | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
76 | a541f297 | bellard | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
77 | 9a64fbe4 | bellard | |
78 | 64201201 | bellard | //static PITState *pit;
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79 | 64201201 | bellard | |
80 | 64201201 | bellard | /* ISA IO ports bridge */
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81 | 9a64fbe4 | bellard | #define PPC_IO_BASE 0x80000000 |
82 | 9a64fbe4 | bellard | |
83 | b1d8e52e | blueswir1 | #if 0
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84 | 64201201 | bellard | /* Speaker port 0x61 */
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85 | b1d8e52e | blueswir1 | static int speaker_data_on;
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86 | b1d8e52e | blueswir1 | static int dummy_refresh_clock;
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87 | b1d8e52e | blueswir1 | #endif
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88 | 64201201 | bellard | |
89 | 36081602 | j_mayer | static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val) |
90 | 9a64fbe4 | bellard | { |
91 | a541f297 | bellard | #if 0
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92 | 64201201 | bellard | speaker_data_on = (val >> 1) & 1;
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93 | 64201201 | bellard | pit_set_gate(pit, 2, val & 1);
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94 | a541f297 | bellard | #endif
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95 | 9a64fbe4 | bellard | } |
96 | 9a64fbe4 | bellard | |
97 | 47103572 | j_mayer | static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) |
98 | 9a64fbe4 | bellard | { |
99 | a541f297 | bellard | #if 0
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100 | 64201201 | bellard | int out;
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101 | 64201201 | bellard | out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
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102 | 64201201 | bellard | dummy_refresh_clock ^= 1;
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103 | 64201201 | bellard | return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
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104 | 47103572 | j_mayer | (dummy_refresh_clock << 4);
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105 | a541f297 | bellard | #endif
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106 | 64201201 | bellard | return 0; |
107 | 9a64fbe4 | bellard | } |
108 | 9a64fbe4 | bellard | |
109 | 64201201 | bellard | /* PCI intack register */
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110 | 64201201 | bellard | /* Read-only register (?) */
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111 | 47103572 | j_mayer | static void _PPC_intack_write (void *opaque, |
112 | 47103572 | j_mayer | target_phys_addr_t addr, uint32_t value) |
113 | 64201201 | bellard | { |
114 | aae9366a | j_mayer | // printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
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115 | 64201201 | bellard | } |
116 | 64201201 | bellard | |
117 | b068d6a7 | j_mayer | static always_inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
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118 | 64201201 | bellard | { |
119 | 64201201 | bellard | uint32_t retval = 0;
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120 | 64201201 | bellard | |
121 | 4dd8c138 | aurel32 | if ((addr & 0xf) == 0) |
122 | 3de388f6 | bellard | retval = pic_intack_read(isa_pic); |
123 | aae9366a | j_mayer | // printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval);
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124 | 64201201 | bellard | |
125 | 64201201 | bellard | return retval;
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126 | 64201201 | bellard | } |
127 | 64201201 | bellard | |
128 | a4193c8a | bellard | static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) |
129 | 64201201 | bellard | { |
130 | 64201201 | bellard | return _PPC_intack_read(addr);
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131 | 64201201 | bellard | } |
132 | 64201201 | bellard | |
133 | a4193c8a | bellard | static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) |
134 | 9a64fbe4 | bellard | { |
135 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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136 | 64201201 | bellard | return bswap16(_PPC_intack_read(addr));
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137 | 64201201 | bellard | #else
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138 | 64201201 | bellard | return _PPC_intack_read(addr);
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139 | f658b4db | bellard | #endif
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140 | 9a64fbe4 | bellard | } |
141 | 9a64fbe4 | bellard | |
142 | a4193c8a | bellard | static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) |
143 | 9a64fbe4 | bellard | { |
144 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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145 | 64201201 | bellard | return bswap32(_PPC_intack_read(addr));
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146 | 64201201 | bellard | #else
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147 | 64201201 | bellard | return _PPC_intack_read(addr);
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148 | f658b4db | bellard | #endif
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149 | 9a64fbe4 | bellard | } |
150 | 9a64fbe4 | bellard | |
151 | 64201201 | bellard | static CPUWriteMemoryFunc *PPC_intack_write[] = {
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152 | 64201201 | bellard | &_PPC_intack_write, |
153 | 64201201 | bellard | &_PPC_intack_write, |
154 | 64201201 | bellard | &_PPC_intack_write, |
155 | 64201201 | bellard | }; |
156 | 64201201 | bellard | |
157 | 64201201 | bellard | static CPUReadMemoryFunc *PPC_intack_read[] = {
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158 | 64201201 | bellard | &PPC_intack_readb, |
159 | 64201201 | bellard | &PPC_intack_readw, |
160 | 64201201 | bellard | &PPC_intack_readl, |
161 | 64201201 | bellard | }; |
162 | 64201201 | bellard | |
163 | 64201201 | bellard | /* PowerPC control and status registers */
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164 | 64201201 | bellard | #if 0 // Not used
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165 | 64201201 | bellard | static struct {
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166 | 64201201 | bellard | /* IDs */
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167 | 64201201 | bellard | uint32_t veni_devi;
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168 | 64201201 | bellard | uint32_t revi;
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169 | 64201201 | bellard | /* Control and status */
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170 | 64201201 | bellard | uint32_t gcsr;
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171 | 64201201 | bellard | uint32_t xcfr;
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172 | 64201201 | bellard | uint32_t ct32;
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173 | 64201201 | bellard | uint32_t mcsr;
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174 | 64201201 | bellard | /* General purpose registers */
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175 | 64201201 | bellard | uint32_t gprg[6];
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176 | 64201201 | bellard | /* Exceptions */
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177 | 64201201 | bellard | uint32_t feen;
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178 | 64201201 | bellard | uint32_t fest;
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179 | 64201201 | bellard | uint32_t fema;
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180 | 64201201 | bellard | uint32_t fecl;
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181 | 64201201 | bellard | uint32_t eeen;
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182 | 64201201 | bellard | uint32_t eest;
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183 | 64201201 | bellard | uint32_t eecl;
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184 | 64201201 | bellard | uint32_t eeint;
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185 | 64201201 | bellard | uint32_t eemck0;
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186 | 64201201 | bellard | uint32_t eemck1;
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187 | 64201201 | bellard | /* Error diagnostic */
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188 | 64201201 | bellard | } XCSR;
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189 | 64201201 | bellard | |
190 | 36081602 | j_mayer | static void PPC_XCSR_writeb (void *opaque,
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191 | 36081602 | j_mayer | target_phys_addr_t addr, uint32_t value)
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192 | 64201201 | bellard | {
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193 | aae9366a | j_mayer | printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value);
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194 | 64201201 | bellard | }
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195 | 64201201 | bellard | |
196 | 36081602 | j_mayer | static void PPC_XCSR_writew (void *opaque,
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197 | 36081602 | j_mayer | target_phys_addr_t addr, uint32_t value)
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198 | 9a64fbe4 | bellard | {
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199 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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200 | 64201201 | bellard | value = bswap16(value);
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201 | f658b4db | bellard | #endif
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202 | aae9366a | j_mayer | printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value); |
203 | 9a64fbe4 | bellard | } |
204 | 9a64fbe4 | bellard | |
205 | 36081602 | j_mayer | static void PPC_XCSR_writel (void *opaque, |
206 | 36081602 | j_mayer | target_phys_addr_t addr, uint32_t value) |
207 | 9a64fbe4 | bellard | { |
208 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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209 | 64201201 | bellard | value = bswap32(value); |
210 | f658b4db | bellard | #endif
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211 | aae9366a | j_mayer | printf("%s: 0x" PADDRX " => 0x%08" PRIx32 "\n", __func__, addr, value); |
212 | 9a64fbe4 | bellard | } |
213 | 9a64fbe4 | bellard | |
214 | a4193c8a | bellard | static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) |
215 | 64201201 | bellard | { |
216 | 64201201 | bellard | uint32_t retval = 0;
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217 | 9a64fbe4 | bellard | |
218 | aae9366a | j_mayer | printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval); |
219 | 9a64fbe4 | bellard | |
220 | 64201201 | bellard | return retval;
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221 | 64201201 | bellard | } |
222 | 64201201 | bellard | |
223 | a4193c8a | bellard | static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) |
224 | 9a64fbe4 | bellard | { |
225 | 64201201 | bellard | uint32_t retval = 0;
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226 | 64201201 | bellard | |
227 | aae9366a | j_mayer | printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval); |
228 | 64201201 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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229 | 64201201 | bellard | retval = bswap16(retval); |
230 | 64201201 | bellard | #endif
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231 | 64201201 | bellard | |
232 | 64201201 | bellard | return retval;
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233 | 9a64fbe4 | bellard | } |
234 | 9a64fbe4 | bellard | |
235 | a4193c8a | bellard | static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) |
236 | 9a64fbe4 | bellard | { |
237 | 9a64fbe4 | bellard | uint32_t retval = 0;
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238 | 9a64fbe4 | bellard | |
239 | aae9366a | j_mayer | printf("%s: 0x" PADDRX " <= %08" PRIx32 "\n", __func__, addr, retval); |
240 | 64201201 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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241 | 64201201 | bellard | retval = bswap32(retval); |
242 | 64201201 | bellard | #endif
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243 | 9a64fbe4 | bellard | |
244 | 9a64fbe4 | bellard | return retval;
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245 | 9a64fbe4 | bellard | } |
246 | 9a64fbe4 | bellard | |
247 | 64201201 | bellard | static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
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248 | 64201201 | bellard | &PPC_XCSR_writeb, |
249 | 64201201 | bellard | &PPC_XCSR_writew, |
250 | 64201201 | bellard | &PPC_XCSR_writel, |
251 | 9a64fbe4 | bellard | }; |
252 | 9a64fbe4 | bellard | |
253 | 64201201 | bellard | static CPUReadMemoryFunc *PPC_XCSR_read[] = {
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254 | 64201201 | bellard | &PPC_XCSR_readb, |
255 | 64201201 | bellard | &PPC_XCSR_readw, |
256 | 64201201 | bellard | &PPC_XCSR_readl, |
257 | 9a64fbe4 | bellard | }; |
258 | b6b8bd18 | bellard | #endif
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259 | 9a64fbe4 | bellard | |
260 | 64201201 | bellard | /* Fake super-io ports for PREP platform (Intel 82378ZB) */
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261 | 64201201 | bellard | typedef struct sysctrl_t { |
262 | c4781a51 | j_mayer | qemu_irq reset_irq; |
263 | 64201201 | bellard | m48t59_t *nvram; |
264 | 64201201 | bellard | uint8_t state; |
265 | 64201201 | bellard | uint8_t syscontrol; |
266 | 64201201 | bellard | uint8_t fake_io[2];
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267 | da9b266b | bellard | int contiguous_map;
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268 | fb3444b8 | bellard | int endian;
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269 | 64201201 | bellard | } sysctrl_t; |
270 | 9a64fbe4 | bellard | |
271 | 64201201 | bellard | enum {
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272 | 64201201 | bellard | STATE_HARDFILE = 0x01,
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273 | 9a64fbe4 | bellard | }; |
274 | 9a64fbe4 | bellard | |
275 | 64201201 | bellard | static sysctrl_t *sysctrl;
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276 | 9a64fbe4 | bellard | |
277 | a541f297 | bellard | static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
278 | 9a64fbe4 | bellard | { |
279 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
280 | 64201201 | bellard | |
281 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
282 | aae9366a | j_mayer | val); |
283 | 64201201 | bellard | sysctrl->fake_io[addr - 0x0398] = val;
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284 | 9a64fbe4 | bellard | } |
285 | 9a64fbe4 | bellard | |
286 | a541f297 | bellard | static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
287 | 9a64fbe4 | bellard | { |
288 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
289 | 9a64fbe4 | bellard | |
290 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE, |
291 | 64201201 | bellard | sysctrl->fake_io[addr - 0x0398]);
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292 | 64201201 | bellard | return sysctrl->fake_io[addr - 0x0398]; |
293 | 64201201 | bellard | } |
294 | 9a64fbe4 | bellard | |
295 | a541f297 | bellard | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
296 | 9a64fbe4 | bellard | { |
297 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
298 | 64201201 | bellard | |
299 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", |
300 | aae9366a | j_mayer | addr - PPC_IO_BASE, val); |
301 | 9a64fbe4 | bellard | switch (addr) {
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302 | 9a64fbe4 | bellard | case 0x0092: |
303 | 9a64fbe4 | bellard | /* Special port 92 */
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304 | 9a64fbe4 | bellard | /* Check soft reset asked */
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305 | 64201201 | bellard | if (val & 0x01) { |
306 | c4781a51 | j_mayer | qemu_irq_raise(sysctrl->reset_irq); |
307 | c4781a51 | j_mayer | } else {
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308 | c4781a51 | j_mayer | qemu_irq_lower(sysctrl->reset_irq); |
309 | 9a64fbe4 | bellard | } |
310 | 9a64fbe4 | bellard | /* Check LE mode */
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311 | 64201201 | bellard | if (val & 0x02) { |
312 | fb3444b8 | bellard | sysctrl->endian = 1;
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313 | fb3444b8 | bellard | } else {
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314 | fb3444b8 | bellard | sysctrl->endian = 0;
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315 | 9a64fbe4 | bellard | } |
316 | 9a64fbe4 | bellard | break;
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317 | 64201201 | bellard | case 0x0800: |
318 | 64201201 | bellard | /* Motorola CPU configuration register : read-only */
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319 | 64201201 | bellard | break;
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320 | 64201201 | bellard | case 0x0802: |
321 | 64201201 | bellard | /* Motorola base module feature register : read-only */
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322 | 64201201 | bellard | break;
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323 | 64201201 | bellard | case 0x0803: |
324 | 64201201 | bellard | /* Motorola base module status register : read-only */
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325 | 64201201 | bellard | break;
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326 | 9a64fbe4 | bellard | case 0x0808: |
327 | 64201201 | bellard | /* Hardfile light register */
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328 | 64201201 | bellard | if (val & 1) |
329 | 64201201 | bellard | sysctrl->state |= STATE_HARDFILE; |
330 | 64201201 | bellard | else
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331 | 64201201 | bellard | sysctrl->state &= ~STATE_HARDFILE; |
332 | 9a64fbe4 | bellard | break;
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333 | 9a64fbe4 | bellard | case 0x0810: |
334 | 9a64fbe4 | bellard | /* Password protect 1 register */
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335 | 64201201 | bellard | if (sysctrl->nvram != NULL) |
336 | 64201201 | bellard | m48t59_toggle_lock(sysctrl->nvram, 1);
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337 | 9a64fbe4 | bellard | break;
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338 | 9a64fbe4 | bellard | case 0x0812: |
339 | 9a64fbe4 | bellard | /* Password protect 2 register */
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340 | 64201201 | bellard | if (sysctrl->nvram != NULL) |
341 | 64201201 | bellard | m48t59_toggle_lock(sysctrl->nvram, 2);
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342 | 9a64fbe4 | bellard | break;
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343 | 9a64fbe4 | bellard | case 0x0814: |
344 | 64201201 | bellard | /* L2 invalidate register */
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345 | c68ea704 | bellard | // tlb_flush(first_cpu, 1);
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346 | 9a64fbe4 | bellard | break;
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347 | 9a64fbe4 | bellard | case 0x081C: |
348 | 9a64fbe4 | bellard | /* system control register */
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349 | 64201201 | bellard | sysctrl->syscontrol = val & 0x0F;
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350 | 9a64fbe4 | bellard | break;
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351 | 9a64fbe4 | bellard | case 0x0850: |
352 | 9a64fbe4 | bellard | /* I/O map type register */
|
353 | da9b266b | bellard | sysctrl->contiguous_map = val & 0x01;
|
354 | 9a64fbe4 | bellard | break;
|
355 | 9a64fbe4 | bellard | default:
|
356 | aae9366a | j_mayer | printf("ERROR: unaffected IO port write: %04" PRIx32
|
357 | aae9366a | j_mayer | " => %02" PRIx32"\n", addr, val); |
358 | 9a64fbe4 | bellard | break;
|
359 | 9a64fbe4 | bellard | } |
360 | 9a64fbe4 | bellard | } |
361 | 9a64fbe4 | bellard | |
362 | a541f297 | bellard | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
363 | 9a64fbe4 | bellard | { |
364 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
365 | 9a64fbe4 | bellard | uint32_t retval = 0xFF;
|
366 | 9a64fbe4 | bellard | |
367 | 9a64fbe4 | bellard | switch (addr) {
|
368 | 9a64fbe4 | bellard | case 0x0092: |
369 | 9a64fbe4 | bellard | /* Special port 92 */
|
370 | 64201201 | bellard | retval = 0x00;
|
371 | 64201201 | bellard | break;
|
372 | 64201201 | bellard | case 0x0800: |
373 | 64201201 | bellard | /* Motorola CPU configuration register */
|
374 | 64201201 | bellard | retval = 0xEF; /* MPC750 */ |
375 | 64201201 | bellard | break;
|
376 | 64201201 | bellard | case 0x0802: |
377 | 64201201 | bellard | /* Motorola Base module feature register */
|
378 | 64201201 | bellard | retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ |
379 | 64201201 | bellard | break;
|
380 | 64201201 | bellard | case 0x0803: |
381 | 64201201 | bellard | /* Motorola base module status register */
|
382 | 64201201 | bellard | retval = 0xE0; /* Standard MPC750 */ |
383 | 9a64fbe4 | bellard | break;
|
384 | 9a64fbe4 | bellard | case 0x080C: |
385 | 9a64fbe4 | bellard | /* Equipment present register:
|
386 | 9a64fbe4 | bellard | * no L2 cache
|
387 | 9a64fbe4 | bellard | * no upgrade processor
|
388 | 9a64fbe4 | bellard | * no cards in PCI slots
|
389 | 9a64fbe4 | bellard | * SCSI fuse is bad
|
390 | 9a64fbe4 | bellard | */
|
391 | 64201201 | bellard | retval = 0x3C;
|
392 | 64201201 | bellard | break;
|
393 | 64201201 | bellard | case 0x0810: |
394 | 64201201 | bellard | /* Motorola base module extended feature register */
|
395 | 64201201 | bellard | retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ |
396 | 9a64fbe4 | bellard | break;
|
397 | da9b266b | bellard | case 0x0814: |
398 | da9b266b | bellard | /* L2 invalidate: don't care */
|
399 | da9b266b | bellard | break;
|
400 | 9a64fbe4 | bellard | case 0x0818: |
401 | 9a64fbe4 | bellard | /* Keylock */
|
402 | 9a64fbe4 | bellard | retval = 0x00;
|
403 | 9a64fbe4 | bellard | break;
|
404 | 9a64fbe4 | bellard | case 0x081C: |
405 | 9a64fbe4 | bellard | /* system control register
|
406 | 9a64fbe4 | bellard | * 7 - 6 / 1 - 0: L2 cache enable
|
407 | 9a64fbe4 | bellard | */
|
408 | 64201201 | bellard | retval = sysctrl->syscontrol; |
409 | 9a64fbe4 | bellard | break;
|
410 | 9a64fbe4 | bellard | case 0x0823: |
411 | 9a64fbe4 | bellard | /* */
|
412 | 9a64fbe4 | bellard | retval = 0x03; /* no L2 cache */ |
413 | 9a64fbe4 | bellard | break;
|
414 | 9a64fbe4 | bellard | case 0x0850: |
415 | 9a64fbe4 | bellard | /* I/O map type register */
|
416 | da9b266b | bellard | retval = sysctrl->contiguous_map; |
417 | 9a64fbe4 | bellard | break;
|
418 | 9a64fbe4 | bellard | default:
|
419 | aae9366a | j_mayer | printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); |
420 | 9a64fbe4 | bellard | break;
|
421 | 9a64fbe4 | bellard | } |
422 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", |
423 | aae9366a | j_mayer | addr - PPC_IO_BASE, retval); |
424 | 9a64fbe4 | bellard | |
425 | 9a64fbe4 | bellard | return retval;
|
426 | 9a64fbe4 | bellard | } |
427 | 9a64fbe4 | bellard | |
428 | b068d6a7 | j_mayer | static always_inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
|
429 | b068d6a7 | j_mayer | target_phys_addr_t |
430 | b068d6a7 | j_mayer | addr) |
431 | da9b266b | bellard | { |
432 | da9b266b | bellard | if (sysctrl->contiguous_map == 0) { |
433 | da9b266b | bellard | /* 64 KB contiguous space for IOs */
|
434 | da9b266b | bellard | addr &= 0xFFFF;
|
435 | da9b266b | bellard | } else {
|
436 | da9b266b | bellard | /* 8 MB non-contiguous space for IOs */
|
437 | da9b266b | bellard | addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); |
438 | da9b266b | bellard | } |
439 | da9b266b | bellard | |
440 | da9b266b | bellard | return addr;
|
441 | da9b266b | bellard | } |
442 | da9b266b | bellard | |
443 | da9b266b | bellard | static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, |
444 | da9b266b | bellard | uint32_t value) |
445 | da9b266b | bellard | { |
446 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
447 | da9b266b | bellard | |
448 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
449 | da9b266b | bellard | cpu_outb(NULL, addr, value);
|
450 | da9b266b | bellard | } |
451 | da9b266b | bellard | |
452 | da9b266b | bellard | static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) |
453 | da9b266b | bellard | { |
454 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
455 | da9b266b | bellard | uint32_t ret; |
456 | da9b266b | bellard | |
457 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
458 | da9b266b | bellard | ret = cpu_inb(NULL, addr);
|
459 | da9b266b | bellard | |
460 | da9b266b | bellard | return ret;
|
461 | da9b266b | bellard | } |
462 | da9b266b | bellard | |
463 | da9b266b | bellard | static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, |
464 | da9b266b | bellard | uint32_t value) |
465 | da9b266b | bellard | { |
466 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
467 | da9b266b | bellard | |
468 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
469 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
470 | da9b266b | bellard | value = bswap16(value); |
471 | da9b266b | bellard | #endif
|
472 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value); |
473 | da9b266b | bellard | cpu_outw(NULL, addr, value);
|
474 | da9b266b | bellard | } |
475 | da9b266b | bellard | |
476 | da9b266b | bellard | static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) |
477 | da9b266b | bellard | { |
478 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
479 | da9b266b | bellard | uint32_t ret; |
480 | da9b266b | bellard | |
481 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
482 | da9b266b | bellard | ret = cpu_inw(NULL, addr);
|
483 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
484 | da9b266b | bellard | ret = bswap16(ret); |
485 | da9b266b | bellard | #endif
|
486 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret); |
487 | da9b266b | bellard | |
488 | da9b266b | bellard | return ret;
|
489 | da9b266b | bellard | } |
490 | da9b266b | bellard | |
491 | da9b266b | bellard | static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, |
492 | da9b266b | bellard | uint32_t value) |
493 | da9b266b | bellard | { |
494 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
495 | da9b266b | bellard | |
496 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
497 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
498 | da9b266b | bellard | value = bswap32(value); |
499 | da9b266b | bellard | #endif
|
500 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x" PADDRX " => 0x%08" PRIx32 "\n", addr, value); |
501 | da9b266b | bellard | cpu_outl(NULL, addr, value);
|
502 | da9b266b | bellard | } |
503 | da9b266b | bellard | |
504 | da9b266b | bellard | static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) |
505 | da9b266b | bellard | { |
506 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
507 | da9b266b | bellard | uint32_t ret; |
508 | da9b266b | bellard | |
509 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
510 | da9b266b | bellard | ret = cpu_inl(NULL, addr);
|
511 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
512 | da9b266b | bellard | ret = bswap32(ret); |
513 | da9b266b | bellard | #endif
|
514 | aae9366a | j_mayer | PPC_IO_DPRINTF("0x" PADDRX " <= 0x%08" PRIx32 "\n", addr, ret); |
515 | da9b266b | bellard | |
516 | da9b266b | bellard | return ret;
|
517 | da9b266b | bellard | } |
518 | da9b266b | bellard | |
519 | b1d8e52e | blueswir1 | static CPUWriteMemoryFunc *PPC_prep_io_write[] = {
|
520 | da9b266b | bellard | &PPC_prep_io_writeb, |
521 | da9b266b | bellard | &PPC_prep_io_writew, |
522 | da9b266b | bellard | &PPC_prep_io_writel, |
523 | da9b266b | bellard | }; |
524 | da9b266b | bellard | |
525 | b1d8e52e | blueswir1 | static CPUReadMemoryFunc *PPC_prep_io_read[] = {
|
526 | da9b266b | bellard | &PPC_prep_io_readb, |
527 | da9b266b | bellard | &PPC_prep_io_readw, |
528 | da9b266b | bellard | &PPC_prep_io_readl, |
529 | da9b266b | bellard | }; |
530 | da9b266b | bellard | |
531 | 64201201 | bellard | #define NVRAM_SIZE 0x2000 |
532 | a541f297 | bellard | |
533 | 26aa7d72 | bellard | /* PowerPC PREP hardware initialisation */
|
534 | fbe1b595 | Paul Brook | static void ppc_prep_init (ram_addr_t ram_size, |
535 | 3023f332 | aliguori | const char *boot_device, |
536 | b881c2c6 | blueswir1 | const char *kernel_filename, |
537 | 94fc95cd | j_mayer | const char *kernel_cmdline, |
538 | 94fc95cd | j_mayer | const char *initrd_filename, |
539 | 94fc95cd | j_mayer | const char *cpu_model) |
540 | a541f297 | bellard | { |
541 | 0d913fdb | j_mayer | CPUState *env = NULL, *envs[MAX_CPUS];
|
542 | a541f297 | bellard | char buf[1024]; |
543 | 3cbee15b | j_mayer | nvram_t nvram; |
544 | 3cbee15b | j_mayer | m48t59_t *m48t59; |
545 | a541f297 | bellard | int PPC_io_memory;
|
546 | 4157a662 | bellard | int linux_boot, i, nb_nics1, bios_size;
|
547 | b584726d | pbrook | ram_addr_t ram_offset, bios_offset; |
548 | 64201201 | bellard | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
549 | 46e50e9d | bellard | PCIBus *pci_bus; |
550 | d537cf6c | pbrook | qemu_irq *i8259; |
551 | 28c5af54 | j_mayer | int ppc_boot_device;
|
552 | e4bcb14c | ths | int index;
|
553 | e4bcb14c | ths | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
554 | e4bcb14c | ths | BlockDriverState *fd[MAX_FD]; |
555 | 64201201 | bellard | |
556 | 64201201 | bellard | sysctrl = qemu_mallocz(sizeof(sysctrl_t));
|
557 | a541f297 | bellard | |
558 | a541f297 | bellard | linux_boot = (kernel_filename != NULL);
|
559 | 0a032cbe | j_mayer | |
560 | c68ea704 | bellard | /* init CPUs */
|
561 | 94fc95cd | j_mayer | if (cpu_model == NULL) |
562 | d12f4c38 | j_mayer | cpu_model = "default";
|
563 | fe33cc71 | j_mayer | for (i = 0; i < smp_cpus; i++) { |
564 | aaed909a | bellard | env = cpu_init(cpu_model); |
565 | aaed909a | bellard | if (!env) {
|
566 | aaed909a | bellard | fprintf(stderr, "Unable to find PowerPC CPU definition\n");
|
567 | aaed909a | bellard | exit(1);
|
568 | aaed909a | bellard | } |
569 | 4018bae9 | j_mayer | if (env->flags & POWERPC_FLAG_RTC_CLK) {
|
570 | 4018bae9 | j_mayer | /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
|
571 | 4018bae9 | j_mayer | cpu_ppc_tb_init(env, 7812500UL);
|
572 | 4018bae9 | j_mayer | } else {
|
573 | 4018bae9 | j_mayer | /* Set time-base frequency to 100 Mhz */
|
574 | 4018bae9 | j_mayer | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
575 | 4018bae9 | j_mayer | } |
576 | 8217606e | Jan Kiszka | qemu_register_reset(&cpu_ppc_reset, 0, env);
|
577 | fe33cc71 | j_mayer | envs[i] = env; |
578 | fe33cc71 | j_mayer | } |
579 | a541f297 | bellard | |
580 | a541f297 | bellard | /* allocate RAM */
|
581 | cf9c147c | blueswir1 | ram_offset = qemu_ram_alloc(ram_size); |
582 | cf9c147c | blueswir1 | cpu_register_physical_memory(0, ram_size, ram_offset);
|
583 | cf9c147c | blueswir1 | |
584 | 64201201 | bellard | /* allocate and load BIOS */
|
585 | cf9c147c | blueswir1 | bios_offset = qemu_ram_alloc(BIOS_SIZE); |
586 | 1192dad8 | j_mayer | if (bios_name == NULL) |
587 | 1192dad8 | j_mayer | bios_name = BIOS_FILENAME; |
588 | 1192dad8 | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
589 | dcac9679 | pbrook | bios_size = get_image_size(buf); |
590 | dcac9679 | pbrook | if (bios_size > 0 && bios_size <= BIOS_SIZE) { |
591 | dcac9679 | pbrook | target_phys_addr_t bios_addr; |
592 | dcac9679 | pbrook | bios_size = (bios_size + 0xfff) & ~0xfff; |
593 | dcac9679 | pbrook | bios_addr = (uint32_t)(-bios_size); |
594 | dcac9679 | pbrook | cpu_register_physical_memory(bios_addr, bios_size, |
595 | dcac9679 | pbrook | bios_offset | IO_MEM_ROM); |
596 | dcac9679 | pbrook | bios_size = load_image_targphys(buf, bios_addr, bios_size); |
597 | dcac9679 | pbrook | } |
598 | 4157a662 | bellard | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
599 | 2ac71179 | Paul Brook | hw_error("qemu: could not load PPC PREP bios '%s'\n", buf);
|
600 | 64201201 | bellard | } |
601 | 4c823cff | j_mayer | if (env->nip < 0xFFF80000 && bios_size < 0x00100000) { |
602 | 2ac71179 | Paul Brook | hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
|
603 | 4c823cff | j_mayer | } |
604 | 26aa7d72 | bellard | |
605 | a541f297 | bellard | if (linux_boot) {
|
606 | 64201201 | bellard | kernel_base = KERNEL_LOAD_ADDR; |
607 | a541f297 | bellard | /* now we can load the kernel */
|
608 | dcac9679 | pbrook | kernel_size = load_image_targphys(kernel_filename, kernel_base, |
609 | dcac9679 | pbrook | ram_size - kernel_base); |
610 | 64201201 | bellard | if (kernel_size < 0) { |
611 | 2ac71179 | Paul Brook | hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
|
612 | a541f297 | bellard | exit(1);
|
613 | a541f297 | bellard | } |
614 | a541f297 | bellard | /* load initrd */
|
615 | a541f297 | bellard | if (initrd_filename) {
|
616 | 64201201 | bellard | initrd_base = INITRD_LOAD_ADDR; |
617 | dcac9679 | pbrook | initrd_size = load_image_targphys(initrd_filename, initrd_base, |
618 | dcac9679 | pbrook | ram_size - initrd_base); |
619 | a541f297 | bellard | if (initrd_size < 0) { |
620 | 2ac71179 | Paul Brook | hw_error("qemu: could not load initial ram disk '%s'\n",
|
621 | 4a057712 | j_mayer | initrd_filename); |
622 | a541f297 | bellard | } |
623 | 64201201 | bellard | } else {
|
624 | 64201201 | bellard | initrd_base = 0;
|
625 | 64201201 | bellard | initrd_size = 0;
|
626 | a541f297 | bellard | } |
627 | 6ac0e82d | balrog | ppc_boot_device = 'm';
|
628 | a541f297 | bellard | } else {
|
629 | 64201201 | bellard | kernel_base = 0;
|
630 | 64201201 | bellard | kernel_size = 0;
|
631 | 64201201 | bellard | initrd_base = 0;
|
632 | 64201201 | bellard | initrd_size = 0;
|
633 | 28c5af54 | j_mayer | ppc_boot_device = '\0';
|
634 | 28c5af54 | j_mayer | /* For now, OHW cannot boot from the network. */
|
635 | 0d913fdb | j_mayer | for (i = 0; boot_device[i] != '\0'; i++) { |
636 | 0d913fdb | j_mayer | if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { |
637 | 0d913fdb | j_mayer | ppc_boot_device = boot_device[i]; |
638 | 28c5af54 | j_mayer | break;
|
639 | 0d913fdb | j_mayer | } |
640 | 28c5af54 | j_mayer | } |
641 | 28c5af54 | j_mayer | if (ppc_boot_device == '\0') { |
642 | 28c5af54 | j_mayer | fprintf(stderr, "No valid boot device for Mac99 machine\n");
|
643 | 28c5af54 | j_mayer | exit(1);
|
644 | 28c5af54 | j_mayer | } |
645 | a541f297 | bellard | } |
646 | a541f297 | bellard | |
647 | 64201201 | bellard | isa_mem_base = 0xc0000000;
|
648 | dd37a5e4 | j_mayer | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
|
649 | 2ac71179 | Paul Brook | hw_error("Only 6xx bus is supported on PREP machine\n");
|
650 | dd37a5e4 | j_mayer | } |
651 | 24be5ae3 | j_mayer | i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); |
652 | d537cf6c | pbrook | pci_bus = pci_prep_init(i8259); |
653 | da9b266b | bellard | // pci_bus = i440fx_init();
|
654 | da9b266b | bellard | /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
|
655 | da9b266b | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
|
656 | da9b266b | bellard | PPC_prep_io_write, sysctrl); |
657 | da9b266b | bellard | cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); |
658 | 64201201 | bellard | |
659 | a541f297 | bellard | /* init basic PC hardware */
|
660 | fbe1b595 | Paul Brook | pci_vga_init(pci_bus, 0, 0); |
661 | 64201201 | bellard | // openpic = openpic_init(0x00000000, 0xF0000000, 1);
|
662 | d537cf6c | pbrook | // pit = pit_init(0x40, i8259[0]);
|
663 | 42fc73a1 | aurel32 | rtc_init(0x70, i8259[8], 2000); |
664 | a541f297 | bellard | |
665 | b6cd0ea1 | aurel32 | serial_init(0x3f8, i8259[4], 115200, serial_hds[0]); |
666 | a541f297 | bellard | nb_nics1 = nb_nics; |
667 | a541f297 | bellard | if (nb_nics1 > NE2000_NB_MAX)
|
668 | a541f297 | bellard | nb_nics1 = NE2000_NB_MAX; |
669 | a541f297 | bellard | for(i = 0; i < nb_nics1; i++) { |
670 | 5652ef78 | aurel32 | if (nd_table[i].model == NULL) { |
671 | 5652ef78 | aurel32 | nd_table[i].model = "ne2k_isa";
|
672 | 5652ef78 | aurel32 | } |
673 | 5652ef78 | aurel32 | if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { |
674 | d537cf6c | pbrook | isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]); |
675 | a41b2ff2 | pbrook | } else {
|
676 | cb457d76 | aliguori | pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci"); |
677 | a41b2ff2 | pbrook | } |
678 | a541f297 | bellard | } |
679 | a541f297 | bellard | |
680 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
681 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
|
682 | e4bcb14c | ths | exit(1);
|
683 | e4bcb14c | ths | } |
684 | e4bcb14c | ths | |
685 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
686 | e4bcb14c | ths | index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS); |
687 | e4bcb14c | ths | if (index != -1) |
688 | e4bcb14c | ths | hd[i] = drives_table[index].bdrv; |
689 | e4bcb14c | ths | else
|
690 | e4bcb14c | ths | hd[i] = NULL;
|
691 | e4bcb14c | ths | } |
692 | e4bcb14c | ths | |
693 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS; i++) { |
694 | d537cf6c | pbrook | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
695 | e4bcb14c | ths | hd[2 * i],
|
696 | e4bcb14c | ths | hd[2 * i + 1]); |
697 | a541f297 | bellard | } |
698 | d537cf6c | pbrook | i8042_init(i8259[1], i8259[12], 0x60); |
699 | b6b8bd18 | bellard | DMA_init(1);
|
700 | a541f297 | bellard | // SB16_init();
|
701 | a541f297 | bellard | |
702 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
703 | e4bcb14c | ths | index = drive_get_index(IF_FLOPPY, 0, i);
|
704 | e4bcb14c | ths | if (index != -1) |
705 | e4bcb14c | ths | fd[i] = drives_table[index].bdrv; |
706 | e4bcb14c | ths | else
|
707 | e4bcb14c | ths | fd[i] = NULL;
|
708 | e4bcb14c | ths | } |
709 | e4bcb14c | ths | fdctrl_init(i8259[6], 2, 0, 0x3f0, fd); |
710 | a541f297 | bellard | |
711 | 64201201 | bellard | /* Register speaker port */
|
712 | 64201201 | bellard | register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); |
713 | 64201201 | bellard | register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); |
714 | a541f297 | bellard | /* Register fake IO ports for PREP */
|
715 | c4781a51 | j_mayer | sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET]; |
716 | 64201201 | bellard | register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
717 | 64201201 | bellard | register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); |
718 | a541f297 | bellard | /* System control ports */
|
719 | 64201201 | bellard | register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
720 | 64201201 | bellard | register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); |
721 | 64201201 | bellard | register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); |
722 | 64201201 | bellard | register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); |
723 | 64201201 | bellard | /* PCI intack location */
|
724 | 64201201 | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
|
725 | a4193c8a | bellard | PPC_intack_write, NULL);
|
726 | a541f297 | bellard | cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
727 | 64201201 | bellard | /* PowerPC control and status register group */
|
728 | b6b8bd18 | bellard | #if 0
|
729 | 36081602 | j_mayer | PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
|
730 | 36081602 | j_mayer | NULL);
|
731 | 64201201 | bellard | cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
|
732 | b6b8bd18 | bellard | #endif
|
733 | a541f297 | bellard | |
734 | 0d92ed30 | pbrook | if (usb_enabled) {
|
735 | e24ad6f1 | pbrook | usb_ohci_init_pci(pci_bus, 3, -1); |
736 | 0d92ed30 | pbrook | } |
737 | 0d92ed30 | pbrook | |
738 | 3cbee15b | j_mayer | m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59); |
739 | 3cbee15b | j_mayer | if (m48t59 == NULL) |
740 | 64201201 | bellard | return;
|
741 | 3cbee15b | j_mayer | sysctrl->nvram = m48t59; |
742 | 64201201 | bellard | |
743 | 64201201 | bellard | /* Initialise NVRAM */
|
744 | 3cbee15b | j_mayer | nvram.opaque = m48t59; |
745 | 3cbee15b | j_mayer | nvram.read_fn = &m48t59_read; |
746 | 3cbee15b | j_mayer | nvram.write_fn = &m48t59_write; |
747 | 6ac0e82d | balrog | PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
|
748 | 64201201 | bellard | kernel_base, kernel_size, |
749 | b6b8bd18 | bellard | kernel_cmdline, |
750 | 64201201 | bellard | initrd_base, initrd_size, |
751 | 64201201 | bellard | /* XXX: need an option to load a NVRAM image */
|
752 | b6b8bd18 | bellard | 0,
|
753 | b6b8bd18 | bellard | graphic_width, graphic_height, graphic_depth); |
754 | c0e564d5 | bellard | |
755 | c0e564d5 | bellard | /* Special port to get debug messages from Open-Firmware */
|
756 | c0e564d5 | bellard | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
757 | a541f297 | bellard | } |
758 | c0e564d5 | bellard | |
759 | f80f9ec9 | Anthony Liguori | static QEMUMachine prep_machine = {
|
760 | 4b32e168 | aliguori | .name = "prep",
|
761 | 4b32e168 | aliguori | .desc = "PowerPC PREP platform",
|
762 | 4b32e168 | aliguori | .init = ppc_prep_init, |
763 | 3d878caa | balrog | .max_cpus = MAX_CPUS, |
764 | c0e564d5 | bellard | }; |
765 | f80f9ec9 | Anthony Liguori | |
766 | f80f9ec9 | Anthony Liguori | static void prep_machine_init(void) |
767 | f80f9ec9 | Anthony Liguori | { |
768 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&prep_machine); |
769 | f80f9ec9 | Anthony Liguori | } |
770 | f80f9ec9 | Anthony Liguori | |
771 | f80f9ec9 | Anthony Liguori | machine_init(prep_machine_init); |