Archipelago » qemu

/*

 *  AArch64 translation

 *

 *  Copyright (c) 2013 Alexander Graf <agraf@suse.de>

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "tcg-op.h"

#include "qemu/log.h"

#include "translate.h"

#include "qemu/host-utils.h"

#include "exec/gen-icount.h"

#include "helper.h"

#define GEN_HELPER 1

#include "helper.h"

static TCGv_i64 cpu_X[32];

static TCGv_i64 cpu_pc;

static TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;

static const char *regnames[] = {

    "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",

    "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",

    "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",

    "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"

};

enum a64_shift_type {

    A64_SHIFT_TYPE_LSL = 0,

    A64_SHIFT_TYPE_LSR = 1,

    A64_SHIFT_TYPE_ASR = 2,

    A64_SHIFT_TYPE_ROR = 3

};

/* initialize TCG globals.  */

void a64_translate_init(void)

{

    int i;

    cpu_pc = tcg_global_mem_new_i64(TCG_AREG0,

                                    offsetof(CPUARMState, pc),

                                    "pc");

    for (i = 0; i < 32; i++) {

        cpu_X[i] = tcg_global_mem_new_i64(TCG_AREG0,

                                          offsetof(CPUARMState, xregs[i]),

                                          regnames[i]);

    }

    cpu_NF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, NF), "NF");

    cpu_ZF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, ZF), "ZF");

    cpu_CF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, CF), "CF");

    cpu_VF = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUARMState, VF), "VF");

}

void aarch64_cpu_dump_state(CPUState *cs, FILE *f,

                            fprintf_function cpu_fprintf, int flags)

{

    ARMCPU *cpu = ARM_CPU(cs);

    CPUARMState *env = &cpu->env;

    uint32_t psr = pstate_read(env);

    int i;

    cpu_fprintf(f, "PC=%016"PRIx64"  SP=%016"PRIx64"\n",

            env->pc, env->xregs[31]);

    for (i = 0; i < 31; i++) {

        cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);

        if ((i % 4) == 3) {

            cpu_fprintf(f, "\n");

        } else {

            cpu_fprintf(f, " ");

        }

    }

    cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n",

                psr,

                psr & PSTATE_N ? 'N' : '-',

                psr & PSTATE_Z ? 'Z' : '-',

                psr & PSTATE_C ? 'C' : '-',

                psr & PSTATE_V ? 'V' : '-');

    cpu_fprintf(f, "\n");

}

void gen_a64_set_pc_im(uint64_t val)

{

    tcg_gen_movi_i64(cpu_pc, val);

}

static void gen_exception(int excp)

{

    TCGv_i32 tmp = tcg_temp_new_i32();

    tcg_gen_movi_i32(tmp, excp);

    gen_helper_exception(cpu_env, tmp);

    tcg_temp_free_i32(tmp);

}

static void gen_exception_insn(DisasContext *s, int offset, int excp)

{

    gen_a64_set_pc_im(s->pc - offset);

    gen_exception(excp);

    s->is_jmp = DISAS_EXC;

}

static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)

{

    /* No direct tb linking with singlestep or deterministic io */

    if (s->singlestep_enabled || (s->tb->cflags & CF_LAST_IO)) {

        return false;

    }

    /* Only link tbs from inside the same guest page */

    if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {

        return false;

    }

    return true;

}

static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)

{

    TranslationBlock *tb;

    tb = s->tb;

    if (use_goto_tb(s, n, dest)) {

        tcg_gen_goto_tb(n);

        gen_a64_set_pc_im(dest);

        tcg_gen_exit_tb((tcg_target_long)tb + n);

        s->is_jmp = DISAS_TB_JUMP;

    } else {

        gen_a64_set_pc_im(dest);

        if (s->singlestep_enabled) {

            gen_exception(EXCP_DEBUG);

        }

        tcg_gen_exit_tb(0);

        s->is_jmp = DISAS_JUMP;

    }

}

static void unallocated_encoding(DisasContext *s)

{

    gen_exception_insn(s, 4, EXCP_UDEF);

}

#define unsupported_encoding(s, insn)                                    \

    do {                                                                 \

        qemu_log_mask(LOG_UNIMP,                                         \

                      "%s:%d: unsupported instruction encoding 0x%08x "  \

                      "at pc=%016" PRIx64 "\n",                          \

                      __FILE__, __LINE__, insn, s->pc - 4);              \

        unallocated_encoding(s);                                         \

    } while (0);

static void init_tmp_a64_array(DisasContext *s)

{

#ifdef CONFIG_DEBUG_TCG

    int i;

    for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) {

        TCGV_UNUSED_I64(s->tmp_a64[i]);

    }

#endif

    s->tmp_a64_count = 0;

}

static void free_tmp_a64(DisasContext *s)

{

    int i;

    for (i = 0; i < s->tmp_a64_count; i++) {

        tcg_temp_free_i64(s->tmp_a64[i]);

    }

    init_tmp_a64_array(s);

}

static TCGv_i64 new_tmp_a64(DisasContext *s)

{

    assert(s->tmp_a64_count < TMP_A64_MAX);

    return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();

}

static TCGv_i64 new_tmp_a64_zero(DisasContext *s)

{

    TCGv_i64 t = new_tmp_a64(s);

    tcg_gen_movi_i64(t, 0);

    return t;

}

static TCGv_i64 cpu_reg(DisasContext *s, int reg)

{

    if (reg == 31) {

        return new_tmp_a64_zero(s);

    } else {

        return cpu_X[reg];

    }

}

/* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64

 * representing the register contents. This TCGv is an auto-freed

 * temporary so it need not be explicitly freed, and may be modified.

 */

static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)

{

    TCGv_i64 v = new_tmp_a64(s);

    if (reg != 31) {

        if (sf) {

            tcg_gen_mov_i64(v, cpu_X[reg]);

        } else {

            tcg_gen_ext32u_i64(v, cpu_X[reg]);

        }

    } else {

        tcg_gen_movi_i64(v, 0);

    }

    return v;

}

/* Set ZF and NF based on a 64 bit result. This is alas fiddlier

 * than the 32 bit equivalent.

 */

static inline void gen_set_NZ64(TCGv_i64 result)

{

    TCGv_i64 flag = tcg_temp_new_i64();

    tcg_gen_setcondi_i64(TCG_COND_NE, flag, result, 0);

    tcg_gen_trunc_i64_i32(cpu_ZF, flag);

    tcg_gen_shri_i64(flag, result, 32);

    tcg_gen_trunc_i64_i32(cpu_NF, flag);

    tcg_temp_free_i64(flag);

}

/* Set NZCV as for a logical operation: NZ as per result, CV cleared. */

static inline void gen_logic_CC(int sf, TCGv_i64 result)

{

    if (sf) {

        gen_set_NZ64(result);

    } else {

        tcg_gen_trunc_i64_i32(cpu_ZF, result);

        tcg_gen_trunc_i64_i32(cpu_NF, result);

    }

    tcg_gen_movi_i32(cpu_CF, 0);

    tcg_gen_movi_i32(cpu_VF, 0);

}

/*

 * the instruction disassembly implemented here matches

 * the instruction encoding classifications in chapter 3 (C3)

 * of the ARM Architecture Reference Manual (DDI0487A_a)

 */

/* C3.2.7 Unconditional branch (immediate)

 *   31  30       26 25                                  0

 * +----+-----------+-------------------------------------+

 * | op | 0 0 1 0 1 |                 imm26               |

 * +----+-----------+-------------------------------------+

 */

static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)

{

    uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;

    if (insn & (1 << 31)) {

        /* C5.6.26 BL Branch with link */

        tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);

    }

    /* C5.6.20 B Branch / C5.6.26 BL Branch with link */

    gen_goto_tb(s, 0, addr);

}

/* C3.2.1 Compare & branch (immediate)

 *   31  30         25  24  23                  5 4      0

 * +----+-------------+----+---------------------+--------+

 * | sf | 0 1 1 0 1 0 | op |         imm19       |   Rt   |

 * +----+-------------+----+---------------------+--------+

 */

static void disas_comp_b_imm(DisasContext *s, uint32_t insn)

{

    unsigned int sf, op, rt;

    uint64_t addr;

    int label_match;

    TCGv_i64 tcg_cmp;

    sf = extract32(insn, 31, 1);

    op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */

    rt = extract32(insn, 0, 5);

    addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;

    tcg_cmp = read_cpu_reg(s, rt, sf);

    label_match = gen_new_label();

    tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,

                        tcg_cmp, 0, label_match);

    gen_goto_tb(s, 0, s->pc);

    gen_set_label(label_match);

    gen_goto_tb(s, 1, addr);

}

/* C3.2.5 Test & branch (immediate)

 *   31  30         25  24  23   19 18          5 4    0

 * +----+-------------+----+-------+-------------+------+

 * | b5 | 0 1 1 0 1 1 | op |  b40  |    imm14    |  Rt  |

 * +----+-------------+----+-------+-------------+------+

 */

static void disas_test_b_imm(DisasContext *s, uint32_t insn)

{

    unsigned int bit_pos, op, rt;

    uint64_t addr;

    int label_match;

    TCGv_i64 tcg_cmp;

    bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);

    op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */

    addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;

    rt = extract32(insn, 0, 5);

    tcg_cmp = tcg_temp_new_i64();

    tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));

    label_match = gen_new_label();

    tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,

                        tcg_cmp, 0, label_match);

    tcg_temp_free_i64(tcg_cmp);

    gen_goto_tb(s, 0, s->pc);

    gen_set_label(label_match);

    gen_goto_tb(s, 1, addr);

}

/* C3.2.2 / C5.6.19 Conditional branch (immediate)

 *  31           25  24  23                  5   4  3    0

 * +---------------+----+---------------------+----+------+

 * | 0 1 0 1 0 1 0 | o1 |         imm19       | o0 | cond |

 * +---------------+----+---------------------+----+------+

 */

static void disas_cond_b_imm(DisasContext *s, uint32_t insn)

{

    unsigned int cond;

    uint64_t addr;

    if ((insn & (1 << 4)) || (insn & (1 << 24))) {

        unallocated_encoding(s);

        return;

    }

    addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;

    cond = extract32(insn, 0, 4);

    if (cond < 0x0e) {

        /* genuinely conditional branches */

        int label_match = gen_new_label();

        arm_gen_test_cc(cond, label_match);

        gen_goto_tb(s, 0, s->pc);

        gen_set_label(label_match);

        gen_goto_tb(s, 1, addr);

    } else {

        /* 0xe and 0xf are both "always" conditions */

        gen_goto_tb(s, 0, addr);

    }

}

/* C5.6.68 HINT */

static void handle_hint(DisasContext *s, uint32_t insn,

                        unsigned int op1, unsigned int op2, unsigned int crm)

{

    unsigned int selector = crm << 3 | op2;

    if (op1 != 3) {

        unallocated_encoding(s);

        return;

    }

    switch (selector) {

    case 0: /* NOP */

        return;

    case 1: /* YIELD */

    case 2: /* WFE */

    case 3: /* WFI */

    case 4: /* SEV */

    case 5: /* SEVL */

        /* we treat all as NOP at least for now */

        return;

    default:

        /* default specified as NOP equivalent */

        return;

    }

}

/* CLREX, DSB, DMB, ISB */

static void handle_sync(DisasContext *s, uint32_t insn,

                        unsigned int op1, unsigned int op2, unsigned int crm)

{

    if (op1 != 3) {

        unallocated_encoding(s);

        return;

    }

    switch (op2) {

    case 2: /* CLREX */

        unsupported_encoding(s, insn);

        return;

    case 4: /* DSB */

    case 5: /* DMB */

    case 6: /* ISB */

        /* We don't emulate caches so barriers are no-ops */

        return;

    default:

        unallocated_encoding(s);

        return;

    }

}

/* C5.6.130 MSR (immediate) - move immediate to processor state field */

static void handle_msr_i(DisasContext *s, uint32_t insn,

                         unsigned int op1, unsigned int op2, unsigned int crm)

{

    unsupported_encoding(s, insn);

}

/* C5.6.204 SYS */

static void handle_sys(DisasContext *s, uint32_t insn, unsigned int l,

                       unsigned int op1, unsigned int op2,

                       unsigned int crn, unsigned int crm, unsigned int rt)

{

    unsupported_encoding(s, insn);

}

/* C5.6.129 MRS - move from system register */

static void handle_mrs(DisasContext *s, uint32_t insn, unsigned int op0,

                       unsigned int op1, unsigned int op2,

                       unsigned int crn, unsigned int crm, unsigned int rt)

{

    unsupported_encoding(s, insn);

}

/* C5.6.131 MSR (register) - move to system register */

static void handle_msr(DisasContext *s, uint32_t insn, unsigned int op0,

                       unsigned int op1, unsigned int op2,

                       unsigned int crn, unsigned int crm, unsigned int rt)

{

    unsupported_encoding(s, insn);

}

/* C3.2.4 System

 *  31                 22 21  20 19 18 16 15   12 11    8 7   5 4    0

 * +---------------------+---+-----+-----+-------+-------+-----+------+

 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 |  CRn  |  CRm  | op2 |  Rt  |

 * +---------------------+---+-----+-----+-------+-------+-----+------+

 */

static void disas_system(DisasContext *s, uint32_t insn)

{

    unsigned int l, op0, op1, crn, crm, op2, rt;

    l = extract32(insn, 21, 1);

    op0 = extract32(insn, 19, 2);

    op1 = extract32(insn, 16, 3);

    crn = extract32(insn, 12, 4);

    crm = extract32(insn, 8, 4);

    op2 = extract32(insn, 5, 3);

    rt = extract32(insn, 0, 5);

    if (op0 == 0) {

        if (l || rt != 31) {

            unallocated_encoding(s);

            return;

        }

        switch (crn) {

        case 2: /* C5.6.68 HINT */

            handle_hint(s, insn, op1, op2, crm);

            break;

        case 3: /* CLREX, DSB, DMB, ISB */

            handle_sync(s, insn, op1, op2, crm);

            break;

        case 4: /* C5.6.130 MSR (immediate) */

            handle_msr_i(s, insn, op1, op2, crm);

            break;

        default:

            unallocated_encoding(s);

            break;

        }

        return;

    }

    if (op0 == 1) {

        /* C5.6.204 SYS */

        handle_sys(s, insn, l, op1, op2, crn, crm, rt);

    } else if (l) { /* op0 > 1 */

        /* C5.6.129 MRS - move from system register */

        handle_mrs(s, insn, op0, op1, op2, crn, crm, rt);

    } else {

        /* C5.6.131 MSR (register) - move to system register */

        handle_msr(s, insn, op0, op1, op2, crn, crm, rt);

    }

}

/* Exception generation */

static void disas_exc(DisasContext *s, uint32_t insn)

{

    unsupported_encoding(s, insn);

}

/* C3.2.7 Unconditional branch (register)

 *  31           25 24   21 20   16 15   10 9    5 4     0

 * +---------------+-------+-------+-------+------+-------+

 * | 1 1 0 1 0 1 1 |  opc  |  op2  |  op3  |  Rn  |  op4  |

 * +---------------+-------+-------+-------+------+-------+

 */

static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)

{

    unsigned int opc, op2, op3, rn, op4;

    opc = extract32(insn, 21, 4);

    op2 = extract32(insn, 16, 5);

    op3 = extract32(insn, 10, 6);

    rn = extract32(insn, 5, 5);

    op4 = extract32(insn, 0, 5);

    if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) {

        unallocated_encoding(s);

        return;

    }

    switch (opc) {

    case 0: /* BR */

    case 2: /* RET */

        break;

    case 1: /* BLR */

        tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);

        break;

    case 4: /* ERET */

    case 5: /* DRPS */

        if (rn != 0x1f) {

            unallocated_encoding(s);

        } else {

            unsupported_encoding(s, insn);

        }

        return;

    default:

        unallocated_encoding(s);

        return;

    }

    tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));

    s->is_jmp = DISAS_JUMP;

}

/* C3.2 Branches, exception generating and system instructions */

static void disas_b_exc_sys(DisasContext *s, uint32_t insn)

{

    switch (extract32(insn, 25, 7)) {

    case 0x0a: case 0x0b:

    case 0x4a: case 0x4b: /* Unconditional branch (immediate) */

        disas_uncond_b_imm(s, insn);

        break;

    case 0x1a: case 0x5a: /* Compare & branch (immediate) */

        disas_comp_b_imm(s, insn);

        break;

    case 0x1b: case 0x5b: /* Test & branch (immediate) */

        disas_test_b_imm(s, insn);

        break;

    case 0x2a: /* Conditional branch (immediate) */

        disas_cond_b_imm(s, insn);

        break;

    case 0x6a: /* Exception generation / System */

        if (insn & (1 << 24)) {

            disas_system(s, insn);

        } else {

            disas_exc(s, insn);

        }

        break;

    case 0x6b: /* Unconditional branch (register) */

        disas_uncond_b_reg(s, insn);

        break;

    default:

        unallocated_encoding(s);

        break;

    }

}

/* Load/store exclusive */

static void disas_ldst_excl(DisasContext *s, uint32_t insn)

{

    unsupported_encoding(s, insn);

}

/* Load register (literal) */

static void disas_ld_lit(DisasContext *s, uint32_t insn)

{

    unsupported_encoding(s, insn);

}

/* Load/store pair (all forms) */

static void disas_ldst_pair(DisasContext *s, uint32_t insn)

{

    unsupported_encoding(s, insn);

}

/* Load/store register (all forms) */

static void disas_ldst_reg(DisasContext *s, uint32_t insn)

{

    unsupported_encoding(s, insn);

}

/* AdvSIMD load/store multiple structures */

static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)

{

    unsupported_encoding(s, insn);

}

/* AdvSIMD load/store single structure */

static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)

{

    unsupported_encoding(s, insn);

}

/* C3.3 Loads and stores */

static void disas_ldst(DisasContext *s, uint32_t insn)

{

    switch (extract32(insn, 24, 6)) {

    case 0x08: /* Load/store exclusive */

        disas_ldst_excl(s, insn);

        break;

    case 0x18: case 0x1c: /* Load register (literal) */

        disas_ld_lit(s, insn);

        break;

    case 0x28: case 0x29:

    case 0x2c: case 0x2d: /* Load/store pair (all forms) */

        disas_ldst_pair(s, insn);

        break;

    case 0x38: case 0x39:

    case 0x3c: case 0x3d: /* Load/store register (all forms) */

        disas_ldst_reg(s, insn);

        break;

    case 0x0c: /* AdvSIMD load/store multiple structures */

        disas_ldst_multiple_struct(s, insn);

        break;

    case 0x0d: /* AdvSIMD load/store single structure */

        disas_ldst_single_struct(s, insn);

        break;

    default:

        unallocated_encoding(s);

        break;

    }

}

/* C3.4.6 PC-rel. addressing

 *   31  30   29 28       24 23                5 4    0

 * +----+-------+-----------+-------------------+------+

 * | op | immlo | 1 0 0 0 0 |       immhi       |  Rd  |

 * +----+-------+-----------+-------------------+------+

 */

static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)

{

    unsigned int page, rd;

    uint64_t base;

    int64_t offset;

    page = extract32(insn, 31, 1);

    /* SignExtend(immhi:immlo) -> offset */

    offset = ((int64_t)sextract32(insn, 5, 19) << 2) | extract32(insn, 29, 2);

    rd = extract32(insn, 0, 5);

    base = s->pc - 4;

    if (page) {

        /* ADRP (page based) */

        base &= ~0xfff;

        offset <<= 12;

    }

    tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);

}

/* Add/subtract (immediate) */

static void disas_add_sub_imm(DisasContext *s, uint32_t insn)

{

    unsupported_encoding(s, insn);

}

/* Logical (immediate) */

static void disas_logic_imm(DisasContext *s, uint32_t insn)

{

    unsupported_encoding(s, insn);

}

/* Move wide (immediate) */

static void disas_movw_imm(DisasContext *s, uint32_t insn)

{

    unsupported_encoding(s, insn);

}

/* Bitfield */

static void disas_bitfield(DisasContext *s, uint32_t insn)

{

    unsupported_encoding(s, insn);

}

/* C3.4.3 Extract

 *   31  30  29 28         23 22   21  20  16 15    10 9    5 4    0

 * +----+------+-------------+---+----+------+--------+------+------+

 * | sf | op21 | 1 0 0 1 1 1 | N | o0 |  Rm  |  imms  |  Rn  |  Rd  |

 * +----+------+-------------+---+----+------+--------+------+------+

 */

static void disas_extract(DisasContext *s, uint32_t insn)

{

    unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0;

    sf = extract32(insn, 31, 1);

    n = extract32(insn, 22, 1);

    rm = extract32(insn, 16, 5);

    imm = extract32(insn, 10, 6);

    rn = extract32(insn, 5, 5);

    rd = extract32(insn, 0, 5);

    op21 = extract32(insn, 29, 2);

    op0 = extract32(insn, 21, 1);

    bitsize = sf ? 64 : 32;

    if (sf != n || op21 || op0 || imm >= bitsize) {

        unallocated_encoding(s);

    } else {

        TCGv_i64 tcg_rd, tcg_rm, tcg_rn;

        tcg_rd = cpu_reg(s, rd);

        if (imm) {

            /* OPTME: we can special case rm==rn as a rotate */

            tcg_rm = read_cpu_reg(s, rm, sf);

            tcg_rn = read_cpu_reg(s, rn, sf);

            tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);

            tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);

            tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);

            if (!sf) {

                tcg_gen_ext32u_i64(tcg_rd, tcg_rd);

            }

        } else {

            /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,

             * so an extract from bit 0 is a special case.

             */

            if (sf) {

                tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm));

            } else {

                tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));

            }

        }

    }

}

/* C3.4 Data processing - immediate */

static void disas_data_proc_imm(DisasContext *s, uint32_t insn)

{

    switch (extract32(insn, 23, 6)) {

    case 0x20: case 0x21: /* PC-rel. addressing */

        disas_pc_rel_adr(s, insn);

        break;

    case 0x22: case 0x23: /* Add/subtract (immediate) */

        disas_add_sub_imm(s, insn);

        break;

    case 0x24: /* Logical (immediate) */

        disas_logic_imm(s, insn);

        break;

    case 0x25: /* Move wide (immediate) */

        disas_movw_imm(s, insn);

        break;

    case 0x26: /* Bitfield */

        disas_bitfield(s, insn);

        break;

    case 0x27: /* Extract */

        disas_extract(s, insn);

        break;

    default:

        unallocated_encoding(s);

        break;

    }

}

/* Shift a TCGv src by TCGv shift_amount, put result in dst.

 * Note that it is the caller's responsibility to ensure that the

 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM

 * mandated semantics for out of range shifts.

 */

static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf,

                      enum a64_shift_type shift_type, TCGv_i64 shift_amount)

{

    switch (shift_type) {

    case A64_SHIFT_TYPE_LSL:

        tcg_gen_shl_i64(dst, src, shift_amount);

        break;

    case A64_SHIFT_TYPE_LSR:

        tcg_gen_shr_i64(dst, src, shift_amount);

        break;

    case A64_SHIFT_TYPE_ASR:

        if (!sf) {

            tcg_gen_ext32s_i64(dst, src);

        }

        tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount);

        break;

    case A64_SHIFT_TYPE_ROR:

        if (sf) {

            tcg_gen_rotr_i64(dst, src, shift_amount);

        } else {

            TCGv_i32 t0, t1;

            t0 = tcg_temp_new_i32();

            t1 = tcg_temp_new_i32();

            tcg_gen_trunc_i64_i32(t0, src);

            tcg_gen_trunc_i64_i32(t1, shift_amount);

            tcg_gen_rotr_i32(t0, t0, t1);

            tcg_gen_extu_i32_i64(dst, t0);

            tcg_temp_free_i32(t0);

            tcg_temp_free_i32(t1);

        }

        break;

    default:

        assert(FALSE); /* all shift types should be handled */

        break;

    }

    if (!sf) { /* zero extend final result */

        tcg_gen_ext32u_i64(dst, dst);

    }

}

/* Shift a TCGv src by immediate, put result in dst.

 * The shift amount must be in range (this should always be true as the

 * relevant instructions will UNDEF on bad shift immediates).

 */

static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,

                          enum a64_shift_type shift_type, unsigned int shift_i)

{

    assert(shift_i < (sf ? 64 : 32));

    if (shift_i == 0) {

        tcg_gen_mov_i64(dst, src);

    } else {

        TCGv_i64 shift_const;

        shift_const = tcg_const_i64(shift_i);

        shift_reg(dst, src, sf, shift_type, shift_const);

        tcg_temp_free_i64(shift_const);

    }

}

/* C3.5.10 Logical (shifted register)

 *   31  30 29 28       24 23   22 21  20  16 15    10 9    5 4    0

 * +----+-----+-----------+-------+---+------+--------+------+------+

 * | sf | opc | 0 1 0 1 0 | shift | N |  Rm  |  imm6  |  Rn  |  Rd  |

 * +----+-----+-----------+-------+---+------+--------+------+------+

 */

static void disas_logic_reg(DisasContext *s, uint32_t insn)

{

    TCGv_i64 tcg_rd, tcg_rn, tcg_rm;

    unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd;

    sf = extract32(insn, 31, 1);

    opc = extract32(insn, 29, 2);

    shift_type = extract32(insn, 22, 2);

    invert = extract32(insn, 21, 1);

    rm = extract32(insn, 16, 5);