target-arm: A64: add support for EXTR
This patch adds emulation support for the EXTR instruction.
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: adapted for new decoder, removed a few temporaries, fixed the 32bit bug, added checks for more...
target-arm: A64: add support for 2-src data processing and DIV
This patch adds support for decoding 2-src data processing insns,and the first users, UDIV and SDIV.
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder adding the 2-src decoding level,...
target-arm: A64: add support for 2-src shift reg insns
This adds 2-src variable shift register instructions:C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder, use enums for shift types]...
target-arm: A64: add support for 1-src data processing and CLZ
This patch adds support for decoding 1-src data processing insns,and the first user, C5.6.40 CLZ (count leading zeroes).
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: A64: add support for 1-src RBIT insn
This adds support for the C5.6.147 RBIT instruction.
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder, use bswap64, make RBIT part standalone from the rest of the patch,...
target-arm: A64: add support for logical (shifted register)
Add support for the instructions described in "C3.5.10 Logical(shifted register)".
We store the flags in the same locations as the 32 bit decoder.This is slightly awkward when calculating 64 bit results, but seems...
target-arm: A64: add support for ADR and ADRP
Add support for the instructions described in"C3.4.6 PC-rel. addressing" (ADR and ADRP).
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder structure]Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>...
target-arm: A64: add support for 'test and branch' imm
This patch adds emulation for the test and branch insns,TBZ and TBNZ.
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted for new decoder always compare with 0 remove a TCG temporary...
target-arm: A64: add support for compare and branch imm
This patch adds emulation for the compare and branch insns,CBZ and CBNZ.
Signed-off-by: Alexander Graf <agraf@suse.de>[claudio: adapted to new decoder, compare with immediate 0, introduce read_cpu_reg to get the 0 extension on (!sf)]...
target-arm: A64: add support for conditional select
This patch adds support for the instruction group "C3.5.6Conditional select": CSEL, CSINC, CSINV, CSNEG.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>[PMM: Improved code generated in the nomatch case as per RTH suggestions]...
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