root / tcg / sparc / tcg-target.c @ 8384dd67
History | View | Annotate | Download (33.8 kB)
1 | 8289b279 | blueswir1 | /*
|
---|---|---|---|
2 | 8289b279 | blueswir1 | * Tiny Code Generator for QEMU
|
3 | 8289b279 | blueswir1 | *
|
4 | 8289b279 | blueswir1 | * Copyright (c) 2008 Fabrice Bellard
|
5 | 8289b279 | blueswir1 | *
|
6 | 8289b279 | blueswir1 | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 8289b279 | blueswir1 | * of this software and associated documentation files (the "Software"), to deal
|
8 | 8289b279 | blueswir1 | * in the Software without restriction, including without limitation the rights
|
9 | 8289b279 | blueswir1 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 8289b279 | blueswir1 | * copies of the Software, and to permit persons to whom the Software is
|
11 | 8289b279 | blueswir1 | * furnished to do so, subject to the following conditions:
|
12 | 8289b279 | blueswir1 | *
|
13 | 8289b279 | blueswir1 | * The above copyright notice and this permission notice shall be included in
|
14 | 8289b279 | blueswir1 | * all copies or substantial portions of the Software.
|
15 | 8289b279 | blueswir1 | *
|
16 | 8289b279 | blueswir1 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 8289b279 | blueswir1 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 8289b279 | blueswir1 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 8289b279 | blueswir1 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 8289b279 | blueswir1 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 8289b279 | blueswir1 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 8289b279 | blueswir1 | * THE SOFTWARE.
|
23 | 8289b279 | blueswir1 | */
|
24 | 8289b279 | blueswir1 | |
25 | 8289b279 | blueswir1 | static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
26 | 8289b279 | blueswir1 | "%g0",
|
27 | 8289b279 | blueswir1 | "%g1",
|
28 | 8289b279 | blueswir1 | "%g2",
|
29 | 8289b279 | blueswir1 | "%g3",
|
30 | 8289b279 | blueswir1 | "%g4",
|
31 | 8289b279 | blueswir1 | "%g5",
|
32 | 8289b279 | blueswir1 | "%g6",
|
33 | 8289b279 | blueswir1 | "%g7",
|
34 | 8289b279 | blueswir1 | "%o0",
|
35 | 8289b279 | blueswir1 | "%o1",
|
36 | 8289b279 | blueswir1 | "%o2",
|
37 | 8289b279 | blueswir1 | "%o3",
|
38 | 8289b279 | blueswir1 | "%o4",
|
39 | 8289b279 | blueswir1 | "%o5",
|
40 | 8289b279 | blueswir1 | "%o6",
|
41 | 8289b279 | blueswir1 | "%o7",
|
42 | 8289b279 | blueswir1 | "%l0",
|
43 | 8289b279 | blueswir1 | "%l1",
|
44 | 8289b279 | blueswir1 | "%l2",
|
45 | 8289b279 | blueswir1 | "%l3",
|
46 | 8289b279 | blueswir1 | "%l4",
|
47 | 8289b279 | blueswir1 | "%l5",
|
48 | 8289b279 | blueswir1 | "%l6",
|
49 | 8289b279 | blueswir1 | "%l7",
|
50 | 8289b279 | blueswir1 | "%i0",
|
51 | 8289b279 | blueswir1 | "%i1",
|
52 | 8289b279 | blueswir1 | "%i2",
|
53 | 8289b279 | blueswir1 | "%i3",
|
54 | 8289b279 | blueswir1 | "%i4",
|
55 | 8289b279 | blueswir1 | "%i5",
|
56 | 8289b279 | blueswir1 | "%i6",
|
57 | 8289b279 | blueswir1 | "%i7",
|
58 | 8289b279 | blueswir1 | }; |
59 | 8289b279 | blueswir1 | |
60 | 0954d0d9 | blueswir1 | static const int tcg_target_reg_alloc_order[] = { |
61 | 8289b279 | blueswir1 | TCG_REG_L0, |
62 | 8289b279 | blueswir1 | TCG_REG_L1, |
63 | 8289b279 | blueswir1 | TCG_REG_L2, |
64 | 8289b279 | blueswir1 | TCG_REG_L3, |
65 | 8289b279 | blueswir1 | TCG_REG_L4, |
66 | 8289b279 | blueswir1 | TCG_REG_L5, |
67 | 8289b279 | blueswir1 | TCG_REG_L6, |
68 | 8289b279 | blueswir1 | TCG_REG_L7, |
69 | 8289b279 | blueswir1 | TCG_REG_I0, |
70 | 8289b279 | blueswir1 | TCG_REG_I1, |
71 | 8289b279 | blueswir1 | TCG_REG_I2, |
72 | 8289b279 | blueswir1 | TCG_REG_I3, |
73 | 8289b279 | blueswir1 | TCG_REG_I4, |
74 | 8289b279 | blueswir1 | }; |
75 | 8289b279 | blueswir1 | |
76 | 8289b279 | blueswir1 | static const int tcg_target_call_iarg_regs[6] = { |
77 | 8289b279 | blueswir1 | TCG_REG_O0, |
78 | 8289b279 | blueswir1 | TCG_REG_O1, |
79 | 8289b279 | blueswir1 | TCG_REG_O2, |
80 | 8289b279 | blueswir1 | TCG_REG_O3, |
81 | 8289b279 | blueswir1 | TCG_REG_O4, |
82 | 8289b279 | blueswir1 | TCG_REG_O5, |
83 | 8289b279 | blueswir1 | }; |
84 | 8289b279 | blueswir1 | |
85 | 8289b279 | blueswir1 | static const int tcg_target_call_oarg_regs[2] = { |
86 | 8289b279 | blueswir1 | TCG_REG_O0, |
87 | 8289b279 | blueswir1 | TCG_REG_O1, |
88 | 8289b279 | blueswir1 | }; |
89 | 8289b279 | blueswir1 | |
90 | 57e49b40 | blueswir1 | static inline int check_fit_tl(tcg_target_long val, unsigned int bits) |
91 | f5ef6aac | blueswir1 | { |
92 | 57e49b40 | blueswir1 | return (val << ((sizeof(tcg_target_long) * 8 - bits)) |
93 | 57e49b40 | blueswir1 | >> (sizeof(tcg_target_long) * 8 - bits)) == val; |
94 | 57e49b40 | blueswir1 | } |
95 | 57e49b40 | blueswir1 | |
96 | 57e49b40 | blueswir1 | static inline int check_fit_i32(uint32_t val, unsigned int bits) |
97 | 57e49b40 | blueswir1 | { |
98 | 57e49b40 | blueswir1 | return ((val << (32 - bits)) >> (32 - bits)) == val; |
99 | f5ef6aac | blueswir1 | } |
100 | f5ef6aac | blueswir1 | |
101 | 8289b279 | blueswir1 | static void patch_reloc(uint8_t *code_ptr, int type, |
102 | f54b3f92 | aurel32 | tcg_target_long value, tcg_target_long addend) |
103 | 8289b279 | blueswir1 | { |
104 | f54b3f92 | aurel32 | value += addend; |
105 | 8289b279 | blueswir1 | switch (type) {
|
106 | 8289b279 | blueswir1 | case R_SPARC_32:
|
107 | 8289b279 | blueswir1 | if (value != (uint32_t)value)
|
108 | 8289b279 | blueswir1 | tcg_abort(); |
109 | 8289b279 | blueswir1 | *(uint32_t *)code_ptr = value; |
110 | 8289b279 | blueswir1 | break;
|
111 | f5ef6aac | blueswir1 | case R_SPARC_WDISP22:
|
112 | f5ef6aac | blueswir1 | value -= (long)code_ptr;
|
113 | f5ef6aac | blueswir1 | value >>= 2;
|
114 | 57e49b40 | blueswir1 | if (!check_fit_tl(value, 22)) |
115 | f5ef6aac | blueswir1 | tcg_abort(); |
116 | f5ef6aac | blueswir1 | *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
|
117 | f5ef6aac | blueswir1 | break;
|
118 | 8289b279 | blueswir1 | default:
|
119 | 8289b279 | blueswir1 | tcg_abort(); |
120 | 8289b279 | blueswir1 | } |
121 | 8289b279 | blueswir1 | } |
122 | 8289b279 | blueswir1 | |
123 | 8289b279 | blueswir1 | /* maximum number of register used for input function arguments */
|
124 | 8289b279 | blueswir1 | static inline int tcg_target_get_call_iarg_regs_count(int flags) |
125 | 8289b279 | blueswir1 | { |
126 | 8289b279 | blueswir1 | return 6; |
127 | 8289b279 | blueswir1 | } |
128 | 8289b279 | blueswir1 | |
129 | 8289b279 | blueswir1 | /* parse target specific constraints */
|
130 | 8289b279 | blueswir1 | static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
131 | 8289b279 | blueswir1 | { |
132 | 8289b279 | blueswir1 | const char *ct_str; |
133 | 8289b279 | blueswir1 | |
134 | 8289b279 | blueswir1 | ct_str = *pct_str; |
135 | 8289b279 | blueswir1 | switch (ct_str[0]) { |
136 | 8289b279 | blueswir1 | case 'r': |
137 | 8289b279 | blueswir1 | case 'L': /* qemu_ld/st constraint */ |
138 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_REG; |
139 | 8289b279 | blueswir1 | tcg_regset_set32(ct->u.regs, 0, 0xffffffff); |
140 | f5ef6aac | blueswir1 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_I0); |
141 | f5ef6aac | blueswir1 | tcg_regset_reset_reg(ct->u.regs, TCG_REG_I1); |
142 | 8289b279 | blueswir1 | break;
|
143 | 8289b279 | blueswir1 | case 'I': |
144 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_CONST_S11; |
145 | 8289b279 | blueswir1 | break;
|
146 | 8289b279 | blueswir1 | case 'J': |
147 | 8289b279 | blueswir1 | ct->ct |= TCG_CT_CONST_S13; |
148 | 8289b279 | blueswir1 | break;
|
149 | 8289b279 | blueswir1 | default:
|
150 | 8289b279 | blueswir1 | return -1; |
151 | 8289b279 | blueswir1 | } |
152 | 8289b279 | blueswir1 | ct_str++; |
153 | 8289b279 | blueswir1 | *pct_str = ct_str; |
154 | 8289b279 | blueswir1 | return 0; |
155 | 8289b279 | blueswir1 | } |
156 | 8289b279 | blueswir1 | |
157 | 8289b279 | blueswir1 | /* test if a constant matches the constraint */
|
158 | 8289b279 | blueswir1 | static inline int tcg_target_const_match(tcg_target_long val, |
159 | 8289b279 | blueswir1 | const TCGArgConstraint *arg_ct)
|
160 | 8289b279 | blueswir1 | { |
161 | 8289b279 | blueswir1 | int ct;
|
162 | 8289b279 | blueswir1 | |
163 | 8289b279 | blueswir1 | ct = arg_ct->ct; |
164 | 8289b279 | blueswir1 | if (ct & TCG_CT_CONST)
|
165 | 8289b279 | blueswir1 | return 1; |
166 | 57e49b40 | blueswir1 | else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) |
167 | 8289b279 | blueswir1 | return 1; |
168 | 57e49b40 | blueswir1 | else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) |
169 | 8289b279 | blueswir1 | return 1; |
170 | 8289b279 | blueswir1 | else
|
171 | 8289b279 | blueswir1 | return 0; |
172 | 8289b279 | blueswir1 | } |
173 | 8289b279 | blueswir1 | |
174 | 8289b279 | blueswir1 | #define INSN_OP(x) ((x) << 30) |
175 | 8289b279 | blueswir1 | #define INSN_OP2(x) ((x) << 22) |
176 | 8289b279 | blueswir1 | #define INSN_OP3(x) ((x) << 19) |
177 | 8289b279 | blueswir1 | #define INSN_OPF(x) ((x) << 5) |
178 | 8289b279 | blueswir1 | #define INSN_RD(x) ((x) << 25) |
179 | 8289b279 | blueswir1 | #define INSN_RS1(x) ((x) << 14) |
180 | 8289b279 | blueswir1 | #define INSN_RS2(x) (x)
|
181 | 8384dd67 | blueswir1 | #define INSN_ASI(x) ((x) << 5) |
182 | 8289b279 | blueswir1 | |
183 | 8289b279 | blueswir1 | #define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff)) |
184 | b3db8758 | blueswir1 | #define INSN_OFF22(x) (((x) >> 2) & 0x3fffff) |
185 | 8289b279 | blueswir1 | |
186 | b3db8758 | blueswir1 | #define INSN_COND(x, a) (((x) << 25) | ((a) << 29)) |
187 | cf7c2ca5 | blueswir1 | #define COND_N 0x0 |
188 | cf7c2ca5 | blueswir1 | #define COND_E 0x1 |
189 | cf7c2ca5 | blueswir1 | #define COND_LE 0x2 |
190 | cf7c2ca5 | blueswir1 | #define COND_L 0x3 |
191 | cf7c2ca5 | blueswir1 | #define COND_LEU 0x4 |
192 | cf7c2ca5 | blueswir1 | #define COND_CS 0x5 |
193 | cf7c2ca5 | blueswir1 | #define COND_NEG 0x6 |
194 | cf7c2ca5 | blueswir1 | #define COND_VS 0x7 |
195 | b3db8758 | blueswir1 | #define COND_A 0x8 |
196 | cf7c2ca5 | blueswir1 | #define COND_NE 0x9 |
197 | cf7c2ca5 | blueswir1 | #define COND_G 0xa |
198 | cf7c2ca5 | blueswir1 | #define COND_GE 0xb |
199 | cf7c2ca5 | blueswir1 | #define COND_GU 0xc |
200 | cf7c2ca5 | blueswir1 | #define COND_CC 0xd |
201 | cf7c2ca5 | blueswir1 | #define COND_POS 0xe |
202 | cf7c2ca5 | blueswir1 | #define COND_VC 0xf |
203 | b3db8758 | blueswir1 | #define BA (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2)) |
204 | 8289b279 | blueswir1 | |
205 | 8289b279 | blueswir1 | #define ARITH_ADD (INSN_OP(2) | INSN_OP3(0x00)) |
206 | 8289b279 | blueswir1 | #define ARITH_AND (INSN_OP(2) | INSN_OP3(0x01)) |
207 | 8289b279 | blueswir1 | #define ARITH_OR (INSN_OP(2) | INSN_OP3(0x02)) |
208 | 9a7f3228 | blueswir1 | #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12)) |
209 | 8289b279 | blueswir1 | #define ARITH_XOR (INSN_OP(2) | INSN_OP3(0x03)) |
210 | f5ef6aac | blueswir1 | #define ARITH_SUB (INSN_OP(2) | INSN_OP3(0x04)) |
211 | f5ef6aac | blueswir1 | #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14)) |
212 | 8289b279 | blueswir1 | #define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10)) |
213 | 8289b279 | blueswir1 | #define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c)) |
214 | 8289b279 | blueswir1 | #define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a)) |
215 | 8289b279 | blueswir1 | #define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e)) |
216 | 8289b279 | blueswir1 | #define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f)) |
217 | 8289b279 | blueswir1 | #define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09)) |
218 | 8289b279 | blueswir1 | #define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d)) |
219 | 8289b279 | blueswir1 | #define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d)) |
220 | 8289b279 | blueswir1 | |
221 | 8289b279 | blueswir1 | #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) |
222 | 8289b279 | blueswir1 | #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) |
223 | 8289b279 | blueswir1 | #define SHIFT_SRA (INSN_OP(2) | INSN_OP3(0x27)) |
224 | 8289b279 | blueswir1 | |
225 | 8289b279 | blueswir1 | #define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12)) |
226 | 8289b279 | blueswir1 | #define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12)) |
227 | 8289b279 | blueswir1 | #define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12)) |
228 | 8289b279 | blueswir1 | |
229 | 8289b279 | blueswir1 | #define WRY (INSN_OP(2) | INSN_OP3(0x30)) |
230 | 8289b279 | blueswir1 | #define JMPL (INSN_OP(2) | INSN_OP3(0x38)) |
231 | 8289b279 | blueswir1 | #define SAVE (INSN_OP(2) | INSN_OP3(0x3c)) |
232 | 8289b279 | blueswir1 | #define RESTORE (INSN_OP(2) | INSN_OP3(0x3d)) |
233 | 8289b279 | blueswir1 | #define SETHI (INSN_OP(0) | INSN_OP2(0x4)) |
234 | 8289b279 | blueswir1 | #define CALL INSN_OP(1) |
235 | 8289b279 | blueswir1 | #define LDUB (INSN_OP(3) | INSN_OP3(0x01)) |
236 | 8289b279 | blueswir1 | #define LDSB (INSN_OP(3) | INSN_OP3(0x09)) |
237 | 8289b279 | blueswir1 | #define LDUH (INSN_OP(3) | INSN_OP3(0x02)) |
238 | 8289b279 | blueswir1 | #define LDSH (INSN_OP(3) | INSN_OP3(0x0a)) |
239 | 8289b279 | blueswir1 | #define LDUW (INSN_OP(3) | INSN_OP3(0x00)) |
240 | 8289b279 | blueswir1 | #define LDSW (INSN_OP(3) | INSN_OP3(0x08)) |
241 | 8289b279 | blueswir1 | #define LDX (INSN_OP(3) | INSN_OP3(0x0b)) |
242 | 8289b279 | blueswir1 | #define STB (INSN_OP(3) | INSN_OP3(0x05)) |
243 | 8289b279 | blueswir1 | #define STH (INSN_OP(3) | INSN_OP3(0x06)) |
244 | 8289b279 | blueswir1 | #define STW (INSN_OP(3) | INSN_OP3(0x04)) |
245 | 8289b279 | blueswir1 | #define STX (INSN_OP(3) | INSN_OP3(0x0e)) |
246 | 8384dd67 | blueswir1 | #define LDUBA (INSN_OP(3) | INSN_OP3(0x11)) |
247 | 8384dd67 | blueswir1 | #define LDSBA (INSN_OP(3) | INSN_OP3(0x19)) |
248 | 8384dd67 | blueswir1 | #define LDUHA (INSN_OP(3) | INSN_OP3(0x12)) |
249 | 8384dd67 | blueswir1 | #define LDSHA (INSN_OP(3) | INSN_OP3(0x1a)) |
250 | 8384dd67 | blueswir1 | #define LDUWA (INSN_OP(3) | INSN_OP3(0x10)) |
251 | 8384dd67 | blueswir1 | #define LDSWA (INSN_OP(3) | INSN_OP3(0x18)) |
252 | 8384dd67 | blueswir1 | #define LDXA (INSN_OP(3) | INSN_OP3(0x1b)) |
253 | 8384dd67 | blueswir1 | #define STBA (INSN_OP(3) | INSN_OP3(0x15)) |
254 | 8384dd67 | blueswir1 | #define STHA (INSN_OP(3) | INSN_OP3(0x16)) |
255 | 8384dd67 | blueswir1 | #define STWA (INSN_OP(3) | INSN_OP3(0x14)) |
256 | 8384dd67 | blueswir1 | #define STXA (INSN_OP(3) | INSN_OP3(0x1e)) |
257 | 8384dd67 | blueswir1 | |
258 | 8384dd67 | blueswir1 | #ifndef ASI_PRIMARY_LITTLE
|
259 | 8384dd67 | blueswir1 | #define ASI_PRIMARY_LITTLE 0x88 |
260 | 8384dd67 | blueswir1 | #endif
|
261 | 8289b279 | blueswir1 | |
262 | 26cc915c | blueswir1 | static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2, |
263 | 26cc915c | blueswir1 | int op)
|
264 | 26cc915c | blueswir1 | { |
265 | 26cc915c | blueswir1 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
266 | 26cc915c | blueswir1 | INSN_RS2(rs2)); |
267 | 26cc915c | blueswir1 | } |
268 | 26cc915c | blueswir1 | |
269 | 26cc915c | blueswir1 | static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1, int offset, |
270 | 26cc915c | blueswir1 | int op)
|
271 | 26cc915c | blueswir1 | { |
272 | 26cc915c | blueswir1 | tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | |
273 | 26cc915c | blueswir1 | INSN_IMM13(offset)); |
274 | 26cc915c | blueswir1 | } |
275 | 26cc915c | blueswir1 | |
276 | 8289b279 | blueswir1 | static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
277 | 8289b279 | blueswir1 | { |
278 | 26cc915c | blueswir1 | tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR); |
279 | 26cc915c | blueswir1 | } |
280 | 26cc915c | blueswir1 | |
281 | 26cc915c | blueswir1 | static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg) |
282 | 26cc915c | blueswir1 | { |
283 | 26cc915c | blueswir1 | tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10)); |
284 | 8289b279 | blueswir1 | } |
285 | 8289b279 | blueswir1 | |
286 | b101234a | blueswir1 | static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg) |
287 | b101234a | blueswir1 | { |
288 | b101234a | blueswir1 | tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR); |
289 | b101234a | blueswir1 | } |
290 | b101234a | blueswir1 | |
291 | b101234a | blueswir1 | static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg) |
292 | 8289b279 | blueswir1 | { |
293 | 57e49b40 | blueswir1 | if (check_fit_i32(arg, 13)) |
294 | b101234a | blueswir1 | tcg_out_movi_imm13(s, ret, arg); |
295 | 8289b279 | blueswir1 | else {
|
296 | 26cc915c | blueswir1 | tcg_out_sethi(s, ret, arg); |
297 | 8289b279 | blueswir1 | if (arg & 0x3ff) |
298 | b101234a | blueswir1 | tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
|
299 | 8289b279 | blueswir1 | } |
300 | 8289b279 | blueswir1 | } |
301 | 8289b279 | blueswir1 | |
302 | b101234a | blueswir1 | static inline void tcg_out_movi(TCGContext *s, TCGType type, |
303 | b101234a | blueswir1 | int ret, tcg_target_long arg)
|
304 | b101234a | blueswir1 | { |
305 | b101234a | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
306 | b101234a | blueswir1 | if (!check_fit_tl(arg, 32) && (arg & ~0xffffffffULL) != 0) { |
307 | b101234a | blueswir1 | // XXX ret may be I5, need another temp
|
308 | b101234a | blueswir1 | tcg_out_movi_imm32(s, TCG_REG_I5, arg >> 32);
|
309 | b101234a | blueswir1 | tcg_out_arithi(s, TCG_REG_I5, TCG_REG_I5, 32, SHIFT_SLLX);
|
310 | b101234a | blueswir1 | tcg_out_movi_imm32(s, ret, arg); |
311 | b101234a | blueswir1 | tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_OR); |
312 | b101234a | blueswir1 | } else
|
313 | b101234a | blueswir1 | #endif
|
314 | b101234a | blueswir1 | tcg_out_movi_imm32(s, ret, arg); |
315 | b101234a | blueswir1 | } |
316 | b101234a | blueswir1 | |
317 | 8289b279 | blueswir1 | static inline void tcg_out_ld_raw(TCGContext *s, int ret, |
318 | 8289b279 | blueswir1 | tcg_target_long arg) |
319 | 8289b279 | blueswir1 | { |
320 | 26cc915c | blueswir1 | tcg_out_sethi(s, ret, arg); |
321 | 8289b279 | blueswir1 | tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | |
322 | 8289b279 | blueswir1 | INSN_IMM13(arg & 0x3ff));
|
323 | 8289b279 | blueswir1 | } |
324 | 8289b279 | blueswir1 | |
325 | b3db8758 | blueswir1 | static inline void tcg_out_ld_ptr(TCGContext *s, int ret, |
326 | b3db8758 | blueswir1 | tcg_target_long arg) |
327 | b3db8758 | blueswir1 | { |
328 | b101234a | blueswir1 | if (!check_fit_tl(arg, 10)) |
329 | b101234a | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
|
330 | b3db8758 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
331 | b3db8758 | blueswir1 | tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) | |
332 | b3db8758 | blueswir1 | INSN_IMM13(arg & 0x3ff));
|
333 | b3db8758 | blueswir1 | #else
|
334 | b101234a | blueswir1 | tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) | |
335 | b101234a | blueswir1 | INSN_IMM13(arg & 0x3ff));
|
336 | b3db8758 | blueswir1 | #endif
|
337 | b3db8758 | blueswir1 | } |
338 | b3db8758 | blueswir1 | |
339 | 8289b279 | blueswir1 | static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op) |
340 | 8289b279 | blueswir1 | { |
341 | 57e49b40 | blueswir1 | if (check_fit_tl(offset, 13)) |
342 | 8289b279 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) | |
343 | 8289b279 | blueswir1 | INSN_IMM13(offset)); |
344 | cf7c2ca5 | blueswir1 | else {
|
345 | cf7c2ca5 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset); |
346 | cf7c2ca5 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) | |
347 | cf7c2ca5 | blueswir1 | INSN_RS2(addr)); |
348 | cf7c2ca5 | blueswir1 | } |
349 | 8289b279 | blueswir1 | } |
350 | 8289b279 | blueswir1 | |
351 | 8384dd67 | blueswir1 | static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr, |
352 | 8384dd67 | blueswir1 | int offset, int op, int asi) |
353 | 8384dd67 | blueswir1 | { |
354 | 8384dd67 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset); |
355 | 8384dd67 | blueswir1 | tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) | |
356 | 8384dd67 | blueswir1 | INSN_ASI(asi) | INSN_RS2(addr)); |
357 | 8384dd67 | blueswir1 | } |
358 | 8384dd67 | blueswir1 | |
359 | e4d5434c | blueswir1 | static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
360 | 8289b279 | blueswir1 | int arg1, tcg_target_long arg2)
|
361 | 8289b279 | blueswir1 | { |
362 | 7d551702 | blueswir1 | if (type == TCG_TYPE_I32)
|
363 | 7d551702 | blueswir1 | tcg_out_ldst(s, ret, arg1, arg2, LDUW); |
364 | 7d551702 | blueswir1 | else
|
365 | 7d551702 | blueswir1 | tcg_out_ldst(s, ret, arg1, arg2, LDX); |
366 | 8289b279 | blueswir1 | } |
367 | 8289b279 | blueswir1 | |
368 | e4d5434c | blueswir1 | static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
369 | 8289b279 | blueswir1 | int arg1, tcg_target_long arg2)
|
370 | 8289b279 | blueswir1 | { |
371 | 7d551702 | blueswir1 | if (type == TCG_TYPE_I32)
|
372 | 7d551702 | blueswir1 | tcg_out_ldst(s, arg, arg1, arg2, STW); |
373 | 7d551702 | blueswir1 | else
|
374 | 7d551702 | blueswir1 | tcg_out_ldst(s, arg, arg1, arg2, STX); |
375 | 8289b279 | blueswir1 | } |
376 | 8289b279 | blueswir1 | |
377 | 8289b279 | blueswir1 | static inline void tcg_out_sety(TCGContext *s, tcg_target_long val) |
378 | 8289b279 | blueswir1 | { |
379 | 8289b279 | blueswir1 | if (val == 0 || val == -1) |
380 | 8289b279 | blueswir1 | tcg_out32(s, WRY | INSN_IMM13(val)); |
381 | 8289b279 | blueswir1 | else
|
382 | 8289b279 | blueswir1 | fprintf(stderr, "unimplemented sety %ld\n", (long)val); |
383 | 8289b279 | blueswir1 | } |
384 | 8289b279 | blueswir1 | |
385 | 8289b279 | blueswir1 | static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
386 | 8289b279 | blueswir1 | { |
387 | 8289b279 | blueswir1 | if (val != 0) { |
388 | 57e49b40 | blueswir1 | if (check_fit_tl(val, 13)) |
389 | 8289b279 | blueswir1 | tcg_out_arithi(s, reg, reg, val, ARITH_ADD); |
390 | f5ef6aac | blueswir1 | else {
|
391 | f5ef6aac | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val); |
392 | f5ef6aac | blueswir1 | tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD); |
393 | f5ef6aac | blueswir1 | } |
394 | 8289b279 | blueswir1 | } |
395 | 8289b279 | blueswir1 | } |
396 | 8289b279 | blueswir1 | |
397 | 8289b279 | blueswir1 | static inline void tcg_out_nop(TCGContext *s) |
398 | 8289b279 | blueswir1 | { |
399 | 26cc915c | blueswir1 | tcg_out_sethi(s, TCG_REG_G0, 0);
|
400 | 8289b279 | blueswir1 | } |
401 | 8289b279 | blueswir1 | |
402 | cf7c2ca5 | blueswir1 | static void tcg_out_branch(TCGContext *s, int opc, int label_index) |
403 | cf7c2ca5 | blueswir1 | { |
404 | cf7c2ca5 | blueswir1 | int32_t val; |
405 | cf7c2ca5 | blueswir1 | TCGLabel *l = &s->labels[label_index]; |
406 | cf7c2ca5 | blueswir1 | |
407 | cf7c2ca5 | blueswir1 | if (l->has_value) {
|
408 | cf7c2ca5 | blueswir1 | val = l->u.value - (tcg_target_long)s->code_ptr; |
409 | f5ef6aac | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) |
410 | cf7c2ca5 | blueswir1 | | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr))); |
411 | f5ef6aac | blueswir1 | } else {
|
412 | f5ef6aac | blueswir1 | tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
|
413 | f5ef6aac | blueswir1 | tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0)); |
414 | f5ef6aac | blueswir1 | } |
415 | cf7c2ca5 | blueswir1 | } |
416 | cf7c2ca5 | blueswir1 | |
417 | cf7c2ca5 | blueswir1 | static const uint8_t tcg_cond_to_bcond[10] = { |
418 | cf7c2ca5 | blueswir1 | [TCG_COND_EQ] = COND_E, |
419 | cf7c2ca5 | blueswir1 | [TCG_COND_NE] = COND_NE, |
420 | cf7c2ca5 | blueswir1 | [TCG_COND_LT] = COND_L, |
421 | cf7c2ca5 | blueswir1 | [TCG_COND_GE] = COND_GE, |
422 | cf7c2ca5 | blueswir1 | [TCG_COND_LE] = COND_LE, |
423 | cf7c2ca5 | blueswir1 | [TCG_COND_GT] = COND_G, |
424 | cf7c2ca5 | blueswir1 | [TCG_COND_LTU] = COND_CS, |
425 | cf7c2ca5 | blueswir1 | [TCG_COND_GEU] = COND_CC, |
426 | cf7c2ca5 | blueswir1 | [TCG_COND_LEU] = COND_LEU, |
427 | cf7c2ca5 | blueswir1 | [TCG_COND_GTU] = COND_GU, |
428 | cf7c2ca5 | blueswir1 | }; |
429 | cf7c2ca5 | blueswir1 | |
430 | cf7c2ca5 | blueswir1 | static void tcg_out_brcond(TCGContext *s, int cond, |
431 | cf7c2ca5 | blueswir1 | TCGArg arg1, TCGArg arg2, int const_arg2,
|
432 | cf7c2ca5 | blueswir1 | int label_index)
|
433 | cf7c2ca5 | blueswir1 | { |
434 | cf7c2ca5 | blueswir1 | if (const_arg2 && arg2 == 0) |
435 | 26cc915c | blueswir1 | /* orcc %g0, r, %g0 */
|
436 | 9a7f3228 | blueswir1 | tcg_out_arith(s, TCG_REG_G0, TCG_REG_G0, arg1, ARITH_ORCC); |
437 | cf7c2ca5 | blueswir1 | else
|
438 | cf7c2ca5 | blueswir1 | /* subcc r1, r2, %g0 */
|
439 | cf7c2ca5 | blueswir1 | tcg_out_arith(s, TCG_REG_G0, arg1, arg2, ARITH_SUBCC); |
440 | cf7c2ca5 | blueswir1 | tcg_out_branch(s, tcg_cond_to_bcond[cond], label_index); |
441 | cf7c2ca5 | blueswir1 | tcg_out_nop(s); |
442 | cf7c2ca5 | blueswir1 | } |
443 | cf7c2ca5 | blueswir1 | |
444 | 7d551702 | blueswir1 | /* Generate global QEMU prologue and epilogue code */
|
445 | 7d551702 | blueswir1 | void tcg_target_qemu_prologue(TCGContext *s)
|
446 | b3db8758 | blueswir1 | { |
447 | b3db8758 | blueswir1 | tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | |
448 | b3db8758 | blueswir1 | INSN_IMM13(-TCG_TARGET_STACK_MINFRAME)); |
449 | cf7c2ca5 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) | |
450 | 7d551702 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
451 | 7d551702 | blueswir1 | tcg_out_nop(s); |
452 | b3db8758 | blueswir1 | } |
453 | b3db8758 | blueswir1 | |
454 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
455 | f5ef6aac | blueswir1 | extern void __ldb_mmu(void); |
456 | f5ef6aac | blueswir1 | extern void __ldw_mmu(void); |
457 | f5ef6aac | blueswir1 | extern void __ldl_mmu(void); |
458 | f5ef6aac | blueswir1 | extern void __ldq_mmu(void); |
459 | f5ef6aac | blueswir1 | |
460 | f5ef6aac | blueswir1 | extern void __stb_mmu(void); |
461 | f5ef6aac | blueswir1 | extern void __stw_mmu(void); |
462 | f5ef6aac | blueswir1 | extern void __stl_mmu(void); |
463 | f5ef6aac | blueswir1 | extern void __stq_mmu(void); |
464 | f5ef6aac | blueswir1 | |
465 | f5ef6aac | blueswir1 | |
466 | 9a7f3228 | blueswir1 | static const void * const qemu_ld_helpers[4] = { |
467 | f5ef6aac | blueswir1 | __ldb_mmu, |
468 | f5ef6aac | blueswir1 | __ldw_mmu, |
469 | f5ef6aac | blueswir1 | __ldl_mmu, |
470 | f5ef6aac | blueswir1 | __ldq_mmu, |
471 | f5ef6aac | blueswir1 | }; |
472 | f5ef6aac | blueswir1 | |
473 | 9a7f3228 | blueswir1 | static const void * const qemu_st_helpers[4] = { |
474 | f5ef6aac | blueswir1 | __stb_mmu, |
475 | f5ef6aac | blueswir1 | __stw_mmu, |
476 | f5ef6aac | blueswir1 | __stl_mmu, |
477 | f5ef6aac | blueswir1 | __stq_mmu, |
478 | f5ef6aac | blueswir1 | }; |
479 | f5ef6aac | blueswir1 | #endif
|
480 | f5ef6aac | blueswir1 | |
481 | f5ef6aac | blueswir1 | static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
482 | f5ef6aac | blueswir1 | int opc)
|
483 | f5ef6aac | blueswir1 | { |
484 | 8384dd67 | blueswir1 | int addr_reg, data_reg, r0, r1, mem_index, s_bits, ld_op;
|
485 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
486 | f5ef6aac | blueswir1 | uint8_t *label1_ptr, *label2_ptr; |
487 | f5ef6aac | blueswir1 | #endif
|
488 | f5ef6aac | blueswir1 | |
489 | f5ef6aac | blueswir1 | data_reg = *args++; |
490 | f5ef6aac | blueswir1 | addr_reg = *args++; |
491 | f5ef6aac | blueswir1 | mem_index = *args; |
492 | f5ef6aac | blueswir1 | s_bits = opc & 3;
|
493 | f5ef6aac | blueswir1 | |
494 | f5ef6aac | blueswir1 | r0 = TCG_REG_I0; |
495 | f5ef6aac | blueswir1 | r1 = TCG_REG_I1; |
496 | f5ef6aac | blueswir1 | |
497 | f5ef6aac | blueswir1 | #if TARGET_LONG_BITS == 32 |
498 | f5ef6aac | blueswir1 | ld_op = LDUW; |
499 | f5ef6aac | blueswir1 | #else
|
500 | f5ef6aac | blueswir1 | ld_op = LDX; |
501 | f5ef6aac | blueswir1 | #endif
|
502 | f5ef6aac | blueswir1 | |
503 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
504 | f5ef6aac | blueswir1 | /* srl addr_reg, x, r1 */
|
505 | f5ef6aac | blueswir1 | tcg_out_arithi(s, r1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, |
506 | f5ef6aac | blueswir1 | SHIFT_SRL); |
507 | f5ef6aac | blueswir1 | /* and addr_reg, x, r0 */
|
508 | f5ef6aac | blueswir1 | tcg_out_arithi(s, r0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
509 | f5ef6aac | blueswir1 | ARITH_AND); |
510 | f5ef6aac | blueswir1 | |
511 | f5ef6aac | blueswir1 | /* and r1, x, r1 */
|
512 | f5ef6aac | blueswir1 | tcg_out_arithi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS,
|
513 | f5ef6aac | blueswir1 | ARITH_AND); |
514 | f5ef6aac | blueswir1 | |
515 | f5ef6aac | blueswir1 | /* add r1, x, r1 */
|
516 | f5ef6aac | blueswir1 | tcg_out_arithi(s, r1, r1, offsetof(CPUState, tlb_table[mem_index][0].addr_read),
|
517 | f5ef6aac | blueswir1 | ARITH_ADD); |
518 | f5ef6aac | blueswir1 | |
519 | f5ef6aac | blueswir1 | /* ld [env + r1], r1 */
|
520 | f5ef6aac | blueswir1 | tcg_out_ldst(s, r1, TCG_AREG0, r1, ld_op); |
521 | f5ef6aac | blueswir1 | |
522 | f5ef6aac | blueswir1 | /* subcc r0, r1, %g0 */
|
523 | f5ef6aac | blueswir1 | tcg_out_arith(s, TCG_REG_G0, r0, r1, ARITH_SUBCC); |
524 | f5ef6aac | blueswir1 | |
525 | f5ef6aac | blueswir1 | /* will become:
|
526 | f5ef6aac | blueswir1 | be label1 */
|
527 | f5ef6aac | blueswir1 | label1_ptr = s->code_ptr; |
528 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
529 | f5ef6aac | blueswir1 | |
530 | f5ef6aac | blueswir1 | /* mov (delay slot)*/
|
531 | f5ef6aac | blueswir1 | tcg_out_mov(s, r0, addr_reg); |
532 | f5ef6aac | blueswir1 | |
533 | f5ef6aac | blueswir1 | /* XXX: move that code at the end of the TB */
|
534 | f5ef6aac | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits] |
535 | f5ef6aac | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
536 | f5ef6aac | blueswir1 | & 0x3fffffff));
|
537 | f5ef6aac | blueswir1 | /* mov (delay slot)*/
|
538 | f5ef6aac | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, r1, mem_index); |
539 | f5ef6aac | blueswir1 | |
540 | f5ef6aac | blueswir1 | switch(opc) {
|
541 | f5ef6aac | blueswir1 | case 0 | 4: |
542 | f5ef6aac | blueswir1 | /* sll i0, 24/56, i0 */
|
543 | f5ef6aac | blueswir1 | tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0, |
544 | f5ef6aac | blueswir1 | sizeof(tcg_target_long) * 8 - 8, SHIFT_SLL); |
545 | f5ef6aac | blueswir1 | /* sra i0, 24/56, data_reg */
|
546 | f5ef6aac | blueswir1 | tcg_out_arithi(s, data_reg, TCG_REG_I0, |
547 | f5ef6aac | blueswir1 | sizeof(tcg_target_long) * 8 - 8, SHIFT_SRA); |
548 | f5ef6aac | blueswir1 | break;
|
549 | f5ef6aac | blueswir1 | case 1 | 4: |
550 | f5ef6aac | blueswir1 | /* sll i0, 16/48, i0 */
|
551 | f5ef6aac | blueswir1 | tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0, |
552 | f5ef6aac | blueswir1 | sizeof(tcg_target_long) * 8 - 16, SHIFT_SLL); |
553 | f5ef6aac | blueswir1 | /* sra i0, 16/48, data_reg */
|
554 | f5ef6aac | blueswir1 | tcg_out_arithi(s, data_reg, TCG_REG_I0, |
555 | f5ef6aac | blueswir1 | sizeof(tcg_target_long) * 8 - 16, SHIFT_SRA); |
556 | f5ef6aac | blueswir1 | break;
|
557 | f5ef6aac | blueswir1 | case 2 | 4: |
558 | f5ef6aac | blueswir1 | /* sll i0, 32, i0 */
|
559 | f5ef6aac | blueswir1 | tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0, 32, SHIFT_SLL);
|
560 | f5ef6aac | blueswir1 | /* sra i0, 32, data_reg */
|
561 | f5ef6aac | blueswir1 | tcg_out_arithi(s, data_reg, TCG_REG_I0, 32, SHIFT_SRA);
|
562 | f5ef6aac | blueswir1 | break;
|
563 | f5ef6aac | blueswir1 | case 0: |
564 | f5ef6aac | blueswir1 | case 1: |
565 | f5ef6aac | blueswir1 | case 2: |
566 | f5ef6aac | blueswir1 | case 3: |
567 | f5ef6aac | blueswir1 | default:
|
568 | f5ef6aac | blueswir1 | /* mov */
|
569 | f5ef6aac | blueswir1 | tcg_out_mov(s, data_reg, TCG_REG_I0); |
570 | f5ef6aac | blueswir1 | break;
|
571 | f5ef6aac | blueswir1 | } |
572 | f5ef6aac | blueswir1 | |
573 | f5ef6aac | blueswir1 | /* will become:
|
574 | f5ef6aac | blueswir1 | ba label2 */
|
575 | f5ef6aac | blueswir1 | label2_ptr = s->code_ptr; |
576 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
577 | f5ef6aac | blueswir1 | |
578 | f5ef6aac | blueswir1 | /* label1: */
|
579 | 9a7f3228 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) | |
580 | f5ef6aac | blueswir1 | INSN_OFF22((unsigned long)label1_ptr - |
581 | f5ef6aac | blueswir1 | (unsigned long)s->code_ptr)); |
582 | f5ef6aac | blueswir1 | |
583 | f5ef6aac | blueswir1 | /* ld [r1 + x], r1 */
|
584 | f5ef6aac | blueswir1 | tcg_out_ldst(s, r1, r1, offsetof(CPUTLBEntry, addend) - |
585 | f5ef6aac | blueswir1 | offsetof(CPUTLBEntry, addr_read), ld_op); |
586 | f5ef6aac | blueswir1 | /* add x(r1), r0 */
|
587 | f5ef6aac | blueswir1 | tcg_out_arith(s, r0, r1, r0, ARITH_ADD); |
588 | f5ef6aac | blueswir1 | #else
|
589 | f5ef6aac | blueswir1 | r0 = addr_reg; |
590 | f5ef6aac | blueswir1 | #endif
|
591 | f5ef6aac | blueswir1 | |
592 | f5ef6aac | blueswir1 | switch(opc) {
|
593 | f5ef6aac | blueswir1 | case 0: |
594 | f5ef6aac | blueswir1 | /* ldub [r0], data_reg */
|
595 | f5ef6aac | blueswir1 | tcg_out_ldst(s, data_reg, r0, 0, LDUB);
|
596 | f5ef6aac | blueswir1 | break;
|
597 | f5ef6aac | blueswir1 | case 0 | 4: |
598 | f5ef6aac | blueswir1 | /* ldsb [r0], data_reg */
|
599 | f5ef6aac | blueswir1 | tcg_out_ldst(s, data_reg, r0, 0, LDSB);
|
600 | f5ef6aac | blueswir1 | break;
|
601 | f5ef6aac | blueswir1 | case 1: |
602 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
603 | f5ef6aac | blueswir1 | /* lduh [r0], data_reg */
|
604 | f5ef6aac | blueswir1 | tcg_out_ldst(s, data_reg, r0, 0, LDUH);
|
605 | 8384dd67 | blueswir1 | #else
|
606 | 8384dd67 | blueswir1 | /* lduha [r0] ASI_PRIMARY_LITTLE, data_reg */
|
607 | 8384dd67 | blueswir1 | tcg_out_ldst_asi(s, data_reg, r0, 0, LDUHA, ASI_PRIMARY_LITTLE);
|
608 | 8384dd67 | blueswir1 | #endif
|
609 | f5ef6aac | blueswir1 | break;
|
610 | f5ef6aac | blueswir1 | case 1 | 4: |
611 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
612 | f5ef6aac | blueswir1 | /* ldsh [r0], data_reg */
|
613 | f5ef6aac | blueswir1 | tcg_out_ldst(s, data_reg, r0, 0, LDSH);
|
614 | 8384dd67 | blueswir1 | #else
|
615 | 8384dd67 | blueswir1 | /* ldsha [r0] ASI_PRIMARY_LITTLE, data_reg */
|
616 | 8384dd67 | blueswir1 | tcg_out_ldst_asi(s, data_reg, r0, 0, LDSHA, ASI_PRIMARY_LITTLE);
|
617 | 8384dd67 | blueswir1 | #endif
|
618 | f5ef6aac | blueswir1 | break;
|
619 | f5ef6aac | blueswir1 | case 2: |
620 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
621 | f5ef6aac | blueswir1 | /* lduw [r0], data_reg */
|
622 | f5ef6aac | blueswir1 | tcg_out_ldst(s, data_reg, r0, 0, LDUW);
|
623 | 8384dd67 | blueswir1 | #else
|
624 | 8384dd67 | blueswir1 | /* lduwa [r0] ASI_PRIMARY_LITTLE, data_reg */
|
625 | 8384dd67 | blueswir1 | tcg_out_ldst_asi(s, data_reg, r0, 0, LDUWA, ASI_PRIMARY_LITTLE);
|
626 | 8384dd67 | blueswir1 | #endif
|
627 | f5ef6aac | blueswir1 | break;
|
628 | f5ef6aac | blueswir1 | case 2 | 4: |
629 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
630 | f5ef6aac | blueswir1 | /* ldsw [r0], data_reg */
|
631 | f5ef6aac | blueswir1 | tcg_out_ldst(s, data_reg, r0, 0, LDSW);
|
632 | 8384dd67 | blueswir1 | #else
|
633 | 8384dd67 | blueswir1 | /* ldswa [r0] ASI_PRIMARY_LITTLE, data_reg */
|
634 | 8384dd67 | blueswir1 | tcg_out_ldst_asi(s, data_reg, r0, 0, LDSWA, ASI_PRIMARY_LITTLE);
|
635 | 8384dd67 | blueswir1 | #endif
|
636 | f5ef6aac | blueswir1 | break;
|
637 | f5ef6aac | blueswir1 | case 3: |
638 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
639 | f5ef6aac | blueswir1 | /* ldx [r0], data_reg */
|
640 | f5ef6aac | blueswir1 | tcg_out_ldst(s, data_reg, r0, 0, LDX);
|
641 | 8384dd67 | blueswir1 | #else
|
642 | 8384dd67 | blueswir1 | /* ldxa [r0] ASI_PRIMARY_LITTLE, data_reg */
|
643 | 8384dd67 | blueswir1 | tcg_out_ldst_asi(s, data_reg, r0, 0, LDXA, ASI_PRIMARY_LITTLE);
|
644 | 8384dd67 | blueswir1 | #endif
|
645 | f5ef6aac | blueswir1 | break;
|
646 | f5ef6aac | blueswir1 | default:
|
647 | f5ef6aac | blueswir1 | tcg_abort(); |
648 | f5ef6aac | blueswir1 | } |
649 | f5ef6aac | blueswir1 | |
650 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
651 | f5ef6aac | blueswir1 | /* label2: */
|
652 | 9a7f3228 | blueswir1 | *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) | |
653 | f5ef6aac | blueswir1 | INSN_OFF22((unsigned long)label2_ptr - |
654 | f5ef6aac | blueswir1 | (unsigned long)s->code_ptr)); |
655 | f5ef6aac | blueswir1 | #endif
|
656 | f5ef6aac | blueswir1 | } |
657 | f5ef6aac | blueswir1 | |
658 | f5ef6aac | blueswir1 | static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
659 | f5ef6aac | blueswir1 | int opc)
|
660 | f5ef6aac | blueswir1 | { |
661 | 8384dd67 | blueswir1 | int addr_reg, data_reg, r0, r1, mem_index, s_bits, ld_op;
|
662 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
663 | f5ef6aac | blueswir1 | uint8_t *label1_ptr, *label2_ptr; |
664 | f5ef6aac | blueswir1 | #endif
|
665 | f5ef6aac | blueswir1 | |
666 | f5ef6aac | blueswir1 | data_reg = *args++; |
667 | f5ef6aac | blueswir1 | addr_reg = *args++; |
668 | f5ef6aac | blueswir1 | mem_index = *args; |
669 | f5ef6aac | blueswir1 | |
670 | f5ef6aac | blueswir1 | s_bits = opc; |
671 | f5ef6aac | blueswir1 | |
672 | f5ef6aac | blueswir1 | r0 = TCG_REG_I5; |
673 | f5ef6aac | blueswir1 | r1 = TCG_REG_I4; |
674 | f5ef6aac | blueswir1 | |
675 | f5ef6aac | blueswir1 | #if TARGET_LONG_BITS == 32 |
676 | f5ef6aac | blueswir1 | ld_op = LDUW; |
677 | f5ef6aac | blueswir1 | #else
|
678 | f5ef6aac | blueswir1 | ld_op = LDX; |
679 | f5ef6aac | blueswir1 | #endif
|
680 | f5ef6aac | blueswir1 | |
681 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
682 | f5ef6aac | blueswir1 | /* srl addr_reg, x, r1 */
|
683 | f5ef6aac | blueswir1 | tcg_out_arithi(s, r1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS, |
684 | f5ef6aac | blueswir1 | SHIFT_SRL); |
685 | f5ef6aac | blueswir1 | /* and addr_reg, x, r0 */
|
686 | f5ef6aac | blueswir1 | tcg_out_arithi(s, r0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1), |
687 | f5ef6aac | blueswir1 | ARITH_AND); |
688 | f5ef6aac | blueswir1 | |
689 | f5ef6aac | blueswir1 | /* and r1, x, r1 */
|
690 | f5ef6aac | blueswir1 | tcg_out_arithi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS,
|
691 | f5ef6aac | blueswir1 | ARITH_AND); |
692 | f5ef6aac | blueswir1 | |
693 | f5ef6aac | blueswir1 | /* add r1, x, r1 */
|
694 | f5ef6aac | blueswir1 | tcg_out_arithi(s, r1, r1, |
695 | f5ef6aac | blueswir1 | offsetof(CPUState, tlb_table[mem_index][0].addr_write),
|
696 | f5ef6aac | blueswir1 | ARITH_ADD); |
697 | f5ef6aac | blueswir1 | |
698 | f5ef6aac | blueswir1 | /* ld [env + r1], r1 */
|
699 | f5ef6aac | blueswir1 | tcg_out_ldst(s, r1, TCG_AREG0, r1, ld_op); |
700 | f5ef6aac | blueswir1 | |
701 | f5ef6aac | blueswir1 | /* subcc r0, r1, %g0 */
|
702 | f5ef6aac | blueswir1 | tcg_out_arith(s, TCG_REG_G0, r0, r1, ARITH_SUBCC); |
703 | f5ef6aac | blueswir1 | |
704 | f5ef6aac | blueswir1 | /* will become:
|
705 | f5ef6aac | blueswir1 | be label1 */
|
706 | f5ef6aac | blueswir1 | label1_ptr = s->code_ptr; |
707 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
708 | f5ef6aac | blueswir1 | /* mov (delay slot)*/
|
709 | f5ef6aac | blueswir1 | tcg_out_mov(s, r0, addr_reg); |
710 | f5ef6aac | blueswir1 | |
711 | f5ef6aac | blueswir1 | switch(opc) {
|
712 | f5ef6aac | blueswir1 | case 0 | 4: |
713 | f5ef6aac | blueswir1 | /* sll i0, 24/56, i0 */
|
714 | f5ef6aac | blueswir1 | tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0, |
715 | f5ef6aac | blueswir1 | sizeof(tcg_target_long) * 8 - 8, SHIFT_SLL); |
716 | f5ef6aac | blueswir1 | /* sra i0, 24/56, data_reg */
|
717 | f5ef6aac | blueswir1 | tcg_out_arithi(s, data_reg, TCG_REG_I0, |
718 | f5ef6aac | blueswir1 | sizeof(tcg_target_long) * 8 - 8, SHIFT_SRA); |
719 | f5ef6aac | blueswir1 | break;
|
720 | f5ef6aac | blueswir1 | case 1 | 4: |
721 | f5ef6aac | blueswir1 | /* sll i0, 16/48, i0 */
|
722 | f5ef6aac | blueswir1 | tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0, |
723 | f5ef6aac | blueswir1 | sizeof(tcg_target_long) * 8 - 16, SHIFT_SLL); |
724 | f5ef6aac | blueswir1 | /* sra i0, 16/48, data_reg */
|
725 | f5ef6aac | blueswir1 | tcg_out_arithi(s, data_reg, TCG_REG_I0, |
726 | f5ef6aac | blueswir1 | sizeof(tcg_target_long) * 8 - 16, SHIFT_SRA); |
727 | f5ef6aac | blueswir1 | break;
|
728 | f5ef6aac | blueswir1 | case 2 | 4: |
729 | f5ef6aac | blueswir1 | /* sll i0, 32, i0 */
|
730 | f5ef6aac | blueswir1 | tcg_out_arithi(s, TCG_REG_I0, TCG_REG_I0, 32, SHIFT_SLL);
|
731 | f5ef6aac | blueswir1 | /* sra i0, 32, data_reg */
|
732 | f5ef6aac | blueswir1 | tcg_out_arithi(s, data_reg, TCG_REG_I0, 32, SHIFT_SRA);
|
733 | f5ef6aac | blueswir1 | break;
|
734 | f5ef6aac | blueswir1 | case 0: |
735 | f5ef6aac | blueswir1 | case 1: |
736 | f5ef6aac | blueswir1 | case 2: |
737 | f5ef6aac | blueswir1 | case 3: |
738 | f5ef6aac | blueswir1 | default:
|
739 | f5ef6aac | blueswir1 | /* mov */
|
740 | f5ef6aac | blueswir1 | tcg_out_mov(s, data_reg, TCG_REG_I0); |
741 | f5ef6aac | blueswir1 | break;
|
742 | f5ef6aac | blueswir1 | } |
743 | f5ef6aac | blueswir1 | |
744 | f5ef6aac | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits] |
745 | f5ef6aac | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
746 | f5ef6aac | blueswir1 | & 0x3fffffff));
|
747 | f5ef6aac | blueswir1 | /* mov (delay slot)*/
|
748 | f5ef6aac | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, r1, mem_index); |
749 | f5ef6aac | blueswir1 | |
750 | f5ef6aac | blueswir1 | /* will become:
|
751 | f5ef6aac | blueswir1 | ba label2 */
|
752 | f5ef6aac | blueswir1 | label2_ptr = s->code_ptr; |
753 | f5ef6aac | blueswir1 | tcg_out32(s, 0);
|
754 | f5ef6aac | blueswir1 | |
755 | f5ef6aac | blueswir1 | /* label1: */
|
756 | 9a7f3228 | blueswir1 | *label1_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) | |
757 | f5ef6aac | blueswir1 | INSN_OFF22((unsigned long)label1_ptr - |
758 | f5ef6aac | blueswir1 | (unsigned long)s->code_ptr)); |
759 | f5ef6aac | blueswir1 | |
760 | f5ef6aac | blueswir1 | /* ld [r1 + x], r1 */
|
761 | f5ef6aac | blueswir1 | tcg_out_ldst(s, r1, r1, offsetof(CPUTLBEntry, addend) - |
762 | f5ef6aac | blueswir1 | offsetof(CPUTLBEntry, addr_write), ld_op); |
763 | f5ef6aac | blueswir1 | /* add x(r1), r0 */
|
764 | f5ef6aac | blueswir1 | tcg_out_arith(s, r0, r1, r0, ARITH_ADD); |
765 | f5ef6aac | blueswir1 | #else
|
766 | f5ef6aac | blueswir1 | r0 = addr_reg; |
767 | f5ef6aac | blueswir1 | #endif
|
768 | f5ef6aac | blueswir1 | |
769 | f5ef6aac | blueswir1 | switch(opc) {
|
770 | f5ef6aac | blueswir1 | case 0: |
771 | f5ef6aac | blueswir1 | /* stb data_reg, [r0] */
|
772 | f5ef6aac | blueswir1 | tcg_out_ldst(s, data_reg, r0, 0, STB);
|
773 | f5ef6aac | blueswir1 | break;
|
774 | f5ef6aac | blueswir1 | case 1: |
775 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
776 | f5ef6aac | blueswir1 | /* sth data_reg, [r0] */
|
777 | f5ef6aac | blueswir1 | tcg_out_ldst(s, data_reg, r0, 0, STH);
|
778 | 8384dd67 | blueswir1 | #else
|
779 | 8384dd67 | blueswir1 | /* stha data_reg, [r0] ASI_PRIMARY_LITTLE */
|
780 | 8384dd67 | blueswir1 | tcg_out_ldst_asi(s, data_reg, r0, 0, STHA, ASI_PRIMARY_LITTLE);
|
781 | 8384dd67 | blueswir1 | #endif
|
782 | f5ef6aac | blueswir1 | break;
|
783 | f5ef6aac | blueswir1 | case 2: |
784 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
785 | f5ef6aac | blueswir1 | /* stw data_reg, [r0] */
|
786 | f5ef6aac | blueswir1 | tcg_out_ldst(s, data_reg, r0, 0, STW);
|
787 | 8384dd67 | blueswir1 | #else
|
788 | 8384dd67 | blueswir1 | /* stwa data_reg, [r0] ASI_PRIMARY_LITTLE */
|
789 | 8384dd67 | blueswir1 | tcg_out_ldst_asi(s, data_reg, r0, 0, STWA, ASI_PRIMARY_LITTLE);
|
790 | 8384dd67 | blueswir1 | #endif
|
791 | f5ef6aac | blueswir1 | break;
|
792 | f5ef6aac | blueswir1 | case 3: |
793 | 8384dd67 | blueswir1 | #ifdef TARGET_WORDS_BIGENDIAN
|
794 | f5ef6aac | blueswir1 | /* stx data_reg, [r0] */
|
795 | f5ef6aac | blueswir1 | tcg_out_ldst(s, data_reg, r0, 0, STX);
|
796 | 8384dd67 | blueswir1 | #else
|
797 | 8384dd67 | blueswir1 | /* stxa data_reg, [r0] ASI_PRIMARY_LITTLE */
|
798 | 8384dd67 | blueswir1 | tcg_out_ldst_asi(s, data_reg, r0, 0, STXA, ASI_PRIMARY_LITTLE);
|
799 | 8384dd67 | blueswir1 | #endif
|
800 | f5ef6aac | blueswir1 | break;
|
801 | f5ef6aac | blueswir1 | default:
|
802 | f5ef6aac | blueswir1 | tcg_abort(); |
803 | f5ef6aac | blueswir1 | } |
804 | f5ef6aac | blueswir1 | |
805 | f5ef6aac | blueswir1 | #if defined(CONFIG_SOFTMMU)
|
806 | f5ef6aac | blueswir1 | /* label2: */
|
807 | 9a7f3228 | blueswir1 | *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) | |
808 | f5ef6aac | blueswir1 | INSN_OFF22((unsigned long)label2_ptr - |
809 | f5ef6aac | blueswir1 | (unsigned long)s->code_ptr)); |
810 | f5ef6aac | blueswir1 | #endif
|
811 | f5ef6aac | blueswir1 | } |
812 | f5ef6aac | blueswir1 | |
813 | 8289b279 | blueswir1 | static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, |
814 | 8289b279 | blueswir1 | const int *const_args) |
815 | 8289b279 | blueswir1 | { |
816 | 8289b279 | blueswir1 | int c;
|
817 | 8289b279 | blueswir1 | |
818 | 8289b279 | blueswir1 | switch (opc) {
|
819 | 8289b279 | blueswir1 | case INDEX_op_exit_tb:
|
820 | b3db8758 | blueswir1 | tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
|
821 | b3db8758 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) | |
822 | 8289b279 | blueswir1 | INSN_IMM13(8));
|
823 | b3db8758 | blueswir1 | tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) | |
824 | b3db8758 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
825 | 8289b279 | blueswir1 | break;
|
826 | 8289b279 | blueswir1 | case INDEX_op_goto_tb:
|
827 | 8289b279 | blueswir1 | if (s->tb_jmp_offset) {
|
828 | 8289b279 | blueswir1 | /* direct jump method */
|
829 | 26cc915c | blueswir1 | tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000); |
830 | cf7c2ca5 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
831 | cf7c2ca5 | blueswir1 | INSN_IMM13((args[0] & 0x1fff))); |
832 | 8289b279 | blueswir1 | s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
833 | 8289b279 | blueswir1 | } else {
|
834 | 8289b279 | blueswir1 | /* indirect jump method */
|
835 | b3db8758 | blueswir1 | tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
|
836 | b3db8758 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) | |
837 | b3db8758 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
838 | 8289b279 | blueswir1 | } |
839 | 53cd9273 | blueswir1 | tcg_out_nop(s); |
840 | 8289b279 | blueswir1 | s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
841 | 8289b279 | blueswir1 | break;
|
842 | 8289b279 | blueswir1 | case INDEX_op_call:
|
843 | 8289b279 | blueswir1 | if (const_args[0]) { |
844 | 8289b279 | blueswir1 | tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
|
845 | 8289b279 | blueswir1 | - (tcg_target_ulong)s->code_ptr) >> 2)
|
846 | 8289b279 | blueswir1 | & 0x3fffffff));
|
847 | 8289b279 | blueswir1 | tcg_out_nop(s); |
848 | 8289b279 | blueswir1 | } else {
|
849 | cf7c2ca5 | blueswir1 | tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
|
850 | cf7c2ca5 | blueswir1 | tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) | |
851 | 2f0a5008 | blueswir1 | INSN_RS2(TCG_REG_G0)); |
852 | 8289b279 | blueswir1 | tcg_out_nop(s); |
853 | 8289b279 | blueswir1 | } |
854 | 8289b279 | blueswir1 | break;
|
855 | 8289b279 | blueswir1 | case INDEX_op_jmp:
|
856 | 8289b279 | blueswir1 | case INDEX_op_br:
|
857 | f5ef6aac | blueswir1 | tcg_out_branch(s, COND_A, args[0]);
|
858 | f5ef6aac | blueswir1 | tcg_out_nop(s); |
859 | 8289b279 | blueswir1 | break;
|
860 | 8289b279 | blueswir1 | case INDEX_op_movi_i32:
|
861 | 8289b279 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]); |
862 | 8289b279 | blueswir1 | break;
|
863 | 8289b279 | blueswir1 | |
864 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
865 | 8289b279 | blueswir1 | #define OP_32_64(x) \
|
866 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i32:) \
|
867 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i64:)
|
868 | 8289b279 | blueswir1 | #else
|
869 | 8289b279 | blueswir1 | #define OP_32_64(x) \
|
870 | 8289b279 | blueswir1 | glue(glue(case INDEX_op_, x), _i32:)
|
871 | 8289b279 | blueswir1 | #endif
|
872 | 8289b279 | blueswir1 | OP_32_64(ld8u); |
873 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUB); |
874 | 8289b279 | blueswir1 | break;
|
875 | 8289b279 | blueswir1 | OP_32_64(ld8s); |
876 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSB); |
877 | 8289b279 | blueswir1 | break;
|
878 | 8289b279 | blueswir1 | OP_32_64(ld16u); |
879 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUH); |
880 | 8289b279 | blueswir1 | break;
|
881 | 8289b279 | blueswir1 | OP_32_64(ld16s); |
882 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSH); |
883 | 8289b279 | blueswir1 | break;
|
884 | 8289b279 | blueswir1 | case INDEX_op_ld_i32:
|
885 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
886 | 53cd9273 | blueswir1 | case INDEX_op_ld32u_i64:
|
887 | 8289b279 | blueswir1 | #endif
|
888 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDUW); |
889 | 8289b279 | blueswir1 | break;
|
890 | 8289b279 | blueswir1 | OP_32_64(st8); |
891 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STB); |
892 | 8289b279 | blueswir1 | break;
|
893 | 8289b279 | blueswir1 | OP_32_64(st16); |
894 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STH); |
895 | 8289b279 | blueswir1 | break;
|
896 | 8289b279 | blueswir1 | case INDEX_op_st_i32:
|
897 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
898 | 53cd9273 | blueswir1 | case INDEX_op_st32_i64:
|
899 | 8289b279 | blueswir1 | #endif
|
900 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STW); |
901 | 8289b279 | blueswir1 | break;
|
902 | 53cd9273 | blueswir1 | OP_32_64(add); |
903 | 53cd9273 | blueswir1 | c = ARITH_ADD; |
904 | 53cd9273 | blueswir1 | goto gen_arith32;
|
905 | 8289b279 | blueswir1 | OP_32_64(sub); |
906 | 8289b279 | blueswir1 | c = ARITH_SUB; |
907 | 8289b279 | blueswir1 | goto gen_arith32;
|
908 | 8289b279 | blueswir1 | OP_32_64(and); |
909 | 8289b279 | blueswir1 | c = ARITH_AND; |
910 | 8289b279 | blueswir1 | goto gen_arith32;
|
911 | 8289b279 | blueswir1 | OP_32_64(or); |
912 | 8289b279 | blueswir1 | c = ARITH_OR; |
913 | 8289b279 | blueswir1 | goto gen_arith32;
|
914 | 8289b279 | blueswir1 | OP_32_64(xor); |
915 | 8289b279 | blueswir1 | c = ARITH_XOR; |
916 | 8289b279 | blueswir1 | goto gen_arith32;
|
917 | 8289b279 | blueswir1 | case INDEX_op_shl_i32:
|
918 | 8289b279 | blueswir1 | c = SHIFT_SLL; |
919 | 8289b279 | blueswir1 | goto gen_arith32;
|
920 | 8289b279 | blueswir1 | case INDEX_op_shr_i32:
|
921 | 8289b279 | blueswir1 | c = SHIFT_SRL; |
922 | 8289b279 | blueswir1 | goto gen_arith32;
|
923 | 8289b279 | blueswir1 | case INDEX_op_sar_i32:
|
924 | 8289b279 | blueswir1 | c = SHIFT_SRA; |
925 | 8289b279 | blueswir1 | goto gen_arith32;
|
926 | 8289b279 | blueswir1 | case INDEX_op_mul_i32:
|
927 | 8289b279 | blueswir1 | c = ARITH_UMUL; |
928 | 8289b279 | blueswir1 | goto gen_arith32;
|
929 | 8289b279 | blueswir1 | case INDEX_op_div2_i32:
|
930 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
931 | 8289b279 | blueswir1 | c = ARITH_SDIVX; |
932 | 8289b279 | blueswir1 | goto gen_arith32;
|
933 | 8289b279 | blueswir1 | #else
|
934 | 8289b279 | blueswir1 | tcg_out_sety(s, 0);
|
935 | 8289b279 | blueswir1 | c = ARITH_SDIV; |
936 | 8289b279 | blueswir1 | goto gen_arith32;
|
937 | 8289b279 | blueswir1 | #endif
|
938 | 8289b279 | blueswir1 | case INDEX_op_divu2_i32:
|
939 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) || defined(__sparc_v8plus__)
|
940 | 8289b279 | blueswir1 | c = ARITH_UDIVX; |
941 | 8289b279 | blueswir1 | goto gen_arith32;
|
942 | 8289b279 | blueswir1 | #else
|
943 | 8289b279 | blueswir1 | tcg_out_sety(s, 0);
|
944 | 8289b279 | blueswir1 | c = ARITH_UDIV; |
945 | 8289b279 | blueswir1 | goto gen_arith32;
|
946 | 8289b279 | blueswir1 | #endif
|
947 | 8289b279 | blueswir1 | |
948 | 8289b279 | blueswir1 | case INDEX_op_brcond_i32:
|
949 | cf7c2ca5 | blueswir1 | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
950 | cf7c2ca5 | blueswir1 | args[3]);
|
951 | 8289b279 | blueswir1 | break;
|
952 | 8289b279 | blueswir1 | |
953 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld8u:
|
954 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 0);
|
955 | 8289b279 | blueswir1 | break;
|
956 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld8s:
|
957 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 0 | 4); |
958 | 8289b279 | blueswir1 | break;
|
959 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld16u:
|
960 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 1);
|
961 | 8289b279 | blueswir1 | break;
|
962 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld16s:
|
963 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 1 | 4); |
964 | 8289b279 | blueswir1 | break;
|
965 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld32u:
|
966 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 2);
|
967 | 8289b279 | blueswir1 | break;
|
968 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld32s:
|
969 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 2 | 4); |
970 | 8289b279 | blueswir1 | break;
|
971 | 8289b279 | blueswir1 | case INDEX_op_qemu_st8:
|
972 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 0);
|
973 | 8289b279 | blueswir1 | break;
|
974 | 8289b279 | blueswir1 | case INDEX_op_qemu_st16:
|
975 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 1);
|
976 | 8289b279 | blueswir1 | break;
|
977 | 8289b279 | blueswir1 | case INDEX_op_qemu_st32:
|
978 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 2);
|
979 | 8289b279 | blueswir1 | break;
|
980 | 8289b279 | blueswir1 | |
981 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
982 | 8289b279 | blueswir1 | case INDEX_op_movi_i64:
|
983 | 8289b279 | blueswir1 | tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); |
984 | 8289b279 | blueswir1 | break;
|
985 | 53cd9273 | blueswir1 | case INDEX_op_ld32s_i64:
|
986 | 53cd9273 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDSW); |
987 | 53cd9273 | blueswir1 | break;
|
988 | 8289b279 | blueswir1 | case INDEX_op_ld_i64:
|
989 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], LDX); |
990 | 8289b279 | blueswir1 | break;
|
991 | 8289b279 | blueswir1 | case INDEX_op_st_i64:
|
992 | 8289b279 | blueswir1 | tcg_out_ldst(s, args[0], args[1], args[2], STX); |
993 | 8289b279 | blueswir1 | break;
|
994 | 8289b279 | blueswir1 | case INDEX_op_shl_i64:
|
995 | 8289b279 | blueswir1 | c = SHIFT_SLLX; |
996 | 8289b279 | blueswir1 | goto gen_arith32;
|
997 | 8289b279 | blueswir1 | case INDEX_op_shr_i64:
|
998 | 8289b279 | blueswir1 | c = SHIFT_SRLX; |
999 | 8289b279 | blueswir1 | goto gen_arith32;
|
1000 | 8289b279 | blueswir1 | case INDEX_op_sar_i64:
|
1001 | 8289b279 | blueswir1 | c = SHIFT_SRAX; |
1002 | 8289b279 | blueswir1 | goto gen_arith32;
|
1003 | 8289b279 | blueswir1 | case INDEX_op_mul_i64:
|
1004 | 8289b279 | blueswir1 | c = ARITH_MULX; |
1005 | 8289b279 | blueswir1 | goto gen_arith32;
|
1006 | 8289b279 | blueswir1 | case INDEX_op_div2_i64:
|
1007 | 53cd9273 | blueswir1 | c = ARITH_SDIVX; |
1008 | 8289b279 | blueswir1 | goto gen_arith32;
|
1009 | 8289b279 | blueswir1 | case INDEX_op_divu2_i64:
|
1010 | 8289b279 | blueswir1 | c = ARITH_UDIVX; |
1011 | 8289b279 | blueswir1 | goto gen_arith32;
|
1012 | 8289b279 | blueswir1 | |
1013 | 8289b279 | blueswir1 | case INDEX_op_brcond_i64:
|
1014 | f5ef6aac | blueswir1 | tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], |
1015 | f5ef6aac | blueswir1 | args[3]);
|
1016 | 8289b279 | blueswir1 | break;
|
1017 | 8289b279 | blueswir1 | case INDEX_op_qemu_ld64:
|
1018 | f5ef6aac | blueswir1 | tcg_out_qemu_ld(s, args, 3);
|
1019 | 8289b279 | blueswir1 | break;
|
1020 | 8289b279 | blueswir1 | case INDEX_op_qemu_st64:
|
1021 | f5ef6aac | blueswir1 | tcg_out_qemu_st(s, args, 3);
|
1022 | 8289b279 | blueswir1 | break;
|
1023 | 8289b279 | blueswir1 | |
1024 | 8289b279 | blueswir1 | #endif
|
1025 | 53cd9273 | blueswir1 | gen_arith32:
|
1026 | 53cd9273 | blueswir1 | if (const_args[2]) { |
1027 | 53cd9273 | blueswir1 | tcg_out_arithi(s, args[0], args[1], args[2], c); |
1028 | 53cd9273 | blueswir1 | } else {
|
1029 | 53cd9273 | blueswir1 | tcg_out_arith(s, args[0], args[1], args[2], c); |
1030 | 53cd9273 | blueswir1 | } |
1031 | 53cd9273 | blueswir1 | break;
|
1032 | 53cd9273 | blueswir1 | |
1033 | 8289b279 | blueswir1 | default:
|
1034 | 8289b279 | blueswir1 | fprintf(stderr, "unknown opcode 0x%x\n", opc);
|
1035 | 8289b279 | blueswir1 | tcg_abort(); |
1036 | 8289b279 | blueswir1 | } |
1037 | 8289b279 | blueswir1 | } |
1038 | 8289b279 | blueswir1 | |
1039 | 8289b279 | blueswir1 | static const TCGTargetOpDef sparc_op_defs[] = { |
1040 | 8289b279 | blueswir1 | { INDEX_op_exit_tb, { } }, |
1041 | b3db8758 | blueswir1 | { INDEX_op_goto_tb, { } }, |
1042 | 8289b279 | blueswir1 | { INDEX_op_call, { "ri" } },
|
1043 | 8289b279 | blueswir1 | { INDEX_op_jmp, { "ri" } },
|
1044 | 8289b279 | blueswir1 | { INDEX_op_br, { } }, |
1045 | 8289b279 | blueswir1 | |
1046 | 8289b279 | blueswir1 | { INDEX_op_mov_i32, { "r", "r" } }, |
1047 | 8289b279 | blueswir1 | { INDEX_op_movi_i32, { "r" } },
|
1048 | 8289b279 | blueswir1 | { INDEX_op_ld8u_i32, { "r", "r" } }, |
1049 | 8289b279 | blueswir1 | { INDEX_op_ld8s_i32, { "r", "r" } }, |
1050 | 8289b279 | blueswir1 | { INDEX_op_ld16u_i32, { "r", "r" } }, |
1051 | 8289b279 | blueswir1 | { INDEX_op_ld16s_i32, { "r", "r" } }, |
1052 | 8289b279 | blueswir1 | { INDEX_op_ld_i32, { "r", "r" } }, |
1053 | 8289b279 | blueswir1 | { INDEX_op_st8_i32, { "r", "r" } }, |
1054 | 8289b279 | blueswir1 | { INDEX_op_st16_i32, { "r", "r" } }, |
1055 | 8289b279 | blueswir1 | { INDEX_op_st_i32, { "r", "r" } }, |
1056 | 8289b279 | blueswir1 | |
1057 | 53cd9273 | blueswir1 | { INDEX_op_add_i32, { "r", "r", "rJ" } }, |
1058 | 53cd9273 | blueswir1 | { INDEX_op_mul_i32, { "r", "r", "rJ" } }, |
1059 | 8289b279 | blueswir1 | { INDEX_op_div2_i32, { "r", "r", "0", "1", "r" } }, |
1060 | 8289b279 | blueswir1 | { INDEX_op_divu2_i32, { "r", "r", "0", "1", "r" } }, |
1061 | 53cd9273 | blueswir1 | { INDEX_op_sub_i32, { "r", "r", "rJ" } }, |
1062 | 53cd9273 | blueswir1 | { INDEX_op_and_i32, { "r", "r", "rJ" } }, |
1063 | 53cd9273 | blueswir1 | { INDEX_op_or_i32, { "r", "r", "rJ" } }, |
1064 | 53cd9273 | blueswir1 | { INDEX_op_xor_i32, { "r", "r", "rJ" } }, |
1065 | 8289b279 | blueswir1 | |
1066 | 53cd9273 | blueswir1 | { INDEX_op_shl_i32, { "r", "r", "rJ" } }, |
1067 | 53cd9273 | blueswir1 | { INDEX_op_shr_i32, { "r", "r", "rJ" } }, |
1068 | 53cd9273 | blueswir1 | { INDEX_op_sar_i32, { "r", "r", "rJ" } }, |
1069 | 8289b279 | blueswir1 | |
1070 | 8289b279 | blueswir1 | { INDEX_op_brcond_i32, { "r", "ri" } }, |
1071 | 8289b279 | blueswir1 | |
1072 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld8u, { "r", "L" } }, |
1073 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld8s, { "r", "L" } }, |
1074 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld16u, { "r", "L" } }, |
1075 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld16s, { "r", "L" } }, |
1076 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld32u, { "r", "L" } }, |
1077 | 8289b279 | blueswir1 | { INDEX_op_qemu_ld32s, { "r", "L" } }, |
1078 | 8289b279 | blueswir1 | |
1079 | 8289b279 | blueswir1 | { INDEX_op_qemu_st8, { "L", "L" } }, |
1080 | 8289b279 | blueswir1 | { INDEX_op_qemu_st16, { "L", "L" } }, |
1081 | 8289b279 | blueswir1 | { INDEX_op_qemu_st32, { "L", "L" } }, |
1082 | 8289b279 | blueswir1 | |
1083 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
1084 | 8289b279 | blueswir1 | { INDEX_op_mov_i64, { "r", "r" } }, |
1085 | 8289b279 | blueswir1 | { INDEX_op_movi_i64, { "r" } },
|
1086 | 8289b279 | blueswir1 | { INDEX_op_ld8u_i64, { "r", "r" } }, |
1087 | 8289b279 | blueswir1 | { INDEX_op_ld8s_i64, { "r", "r" } }, |
1088 | 8289b279 | blueswir1 | { INDEX_op_ld16u_i64, { "r", "r" } }, |
1089 | 8289b279 | blueswir1 | { INDEX_op_ld16s_i64, { "r", "r" } }, |
1090 | 8289b279 | blueswir1 | { INDEX_op_ld32u_i64, { "r", "r" } }, |
1091 | 8289b279 | blueswir1 | { INDEX_op_ld32s_i64, { "r", "r" } }, |
1092 | 8289b279 | blueswir1 | { INDEX_op_ld_i64, { "r", "r" } }, |
1093 | 8289b279 | blueswir1 | { INDEX_op_st8_i64, { "r", "r" } }, |
1094 | 8289b279 | blueswir1 | { INDEX_op_st16_i64, { "r", "r" } }, |
1095 | 8289b279 | blueswir1 | { INDEX_op_st32_i64, { "r", "r" } }, |
1096 | 8289b279 | blueswir1 | { INDEX_op_st_i64, { "r", "r" } }, |
1097 | 8289b279 | blueswir1 | |
1098 | 53cd9273 | blueswir1 | { INDEX_op_add_i64, { "r", "r", "rJ" } }, |
1099 | 53cd9273 | blueswir1 | { INDEX_op_mul_i64, { "r", "r", "rJ" } }, |
1100 | 8289b279 | blueswir1 | { INDEX_op_div2_i64, { "r", "r", "0", "1", "r" } }, |
1101 | 8289b279 | blueswir1 | { INDEX_op_divu2_i64, { "r", "r", "0", "1", "r" } }, |
1102 | 53cd9273 | blueswir1 | { INDEX_op_sub_i64, { "r", "r", "rJ" } }, |
1103 | 53cd9273 | blueswir1 | { INDEX_op_and_i64, { "r", "r", "rJ" } }, |
1104 | 53cd9273 | blueswir1 | { INDEX_op_or_i64, { "r", "r", "rJ" } }, |
1105 | 53cd9273 | blueswir1 | { INDEX_op_xor_i64, { "r", "r", "rJ" } }, |
1106 | 8289b279 | blueswir1 | |
1107 | 53cd9273 | blueswir1 | { INDEX_op_shl_i64, { "r", "r", "rJ" } }, |
1108 | 53cd9273 | blueswir1 | { INDEX_op_shr_i64, { "r", "r", "rJ" } }, |
1109 | 53cd9273 | blueswir1 | { INDEX_op_sar_i64, { "r", "r", "rJ" } }, |
1110 | 8289b279 | blueswir1 | |
1111 | 8289b279 | blueswir1 | { INDEX_op_brcond_i64, { "r", "ri" } }, |
1112 | 8289b279 | blueswir1 | #endif
|
1113 | 8289b279 | blueswir1 | { -1 },
|
1114 | 8289b279 | blueswir1 | }; |
1115 | 8289b279 | blueswir1 | |
1116 | 8289b279 | blueswir1 | void tcg_target_init(TCGContext *s)
|
1117 | 8289b279 | blueswir1 | { |
1118 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); |
1119 | 8289b279 | blueswir1 | #if defined(__sparc_v9__) && !defined(__sparc_v8plus__)
|
1120 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); |
1121 | 8289b279 | blueswir1 | #endif
|
1122 | 8289b279 | blueswir1 | tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
1123 | b3db8758 | blueswir1 | (1 << TCG_REG_G1) |
|
1124 | b3db8758 | blueswir1 | (1 << TCG_REG_G2) |
|
1125 | b3db8758 | blueswir1 | (1 << TCG_REG_G3) |
|
1126 | b3db8758 | blueswir1 | (1 << TCG_REG_G4) |
|
1127 | b3db8758 | blueswir1 | (1 << TCG_REG_G5) |
|
1128 | b3db8758 | blueswir1 | (1 << TCG_REG_G6) |
|
1129 | b3db8758 | blueswir1 | (1 << TCG_REG_G7) |
|
1130 | 8289b279 | blueswir1 | (1 << TCG_REG_O0) |
|
1131 | 8289b279 | blueswir1 | (1 << TCG_REG_O1) |
|
1132 | 8289b279 | blueswir1 | (1 << TCG_REG_O2) |
|
1133 | 8289b279 | blueswir1 | (1 << TCG_REG_O3) |
|
1134 | 8289b279 | blueswir1 | (1 << TCG_REG_O4) |
|
1135 | 8289b279 | blueswir1 | (1 << TCG_REG_O5) |
|
1136 | 8289b279 | blueswir1 | (1 << TCG_REG_O7));
|
1137 | 8289b279 | blueswir1 | |
1138 | 8289b279 | blueswir1 | tcg_regset_clear(s->reserved_regs); |
1139 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0); |
1140 | 53cd9273 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
|
1141 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6); |
1142 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7); |
1143 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6); |
1144 | 8289b279 | blueswir1 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7); |
1145 | 8289b279 | blueswir1 | tcg_add_target_add_op_defs(sparc_op_defs); |
1146 | 8289b279 | blueswir1 | } |