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Revision 8387da81


Added by Peter Maydell almost 11 years ago

target-arm: Handle VMOV between two core and VFP single regs

Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry and
VMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and a
pair of VFP single precision registers):

  • An incorrect condition meant these instruction patterns were being
    treated as load/store multiple, which resulted in the generation
    of bad code and a runtime segfault
  • The order of the core register pair was reversed so the values would
    go to the wrong registers

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>


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