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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * ARM virtual CPU header
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3 | 5fafdf24 | ths | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 2c0262af | bellard | */
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19 | 2c0262af | bellard | #ifndef CPU_ARM_H
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20 | 2c0262af | bellard | #define CPU_ARM_H
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21 | 2c0262af | bellard | |
22 | 3926cc84 | Alexander Graf | #include "config.h" |
23 | 3cf1e035 | bellard | |
24 | 3926cc84 | Alexander Graf | #if defined(TARGET_AARCH64)
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25 | 3926cc84 | Alexander Graf | /* AArch64 definitions */
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26 | 3926cc84 | Alexander Graf | # define TARGET_LONG_BITS 64 |
27 | 3926cc84 | Alexander Graf | # define ELF_MACHINE EM_AARCH64
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28 | 3926cc84 | Alexander Graf | #else
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29 | 3926cc84 | Alexander Graf | # define TARGET_LONG_BITS 32 |
30 | 3926cc84 | Alexander Graf | # define ELF_MACHINE EM_ARM
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31 | 3926cc84 | Alexander Graf | #endif
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32 | 9042c0e2 | ths | |
33 | 9349b4f9 | Andreas Färber | #define CPUArchState struct CPUARMState |
34 | c2764719 | pbrook | |
35 | 9a78eead | Stefan Weil | #include "qemu-common.h" |
36 | 022c62cb | Paolo Bonzini | #include "exec/cpu-defs.h" |
37 | 2c0262af | bellard | |
38 | 6b4c305c | Paolo Bonzini | #include "fpu/softfloat.h" |
39 | 53cd6637 | bellard | |
40 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
41 | 1fddef4b | bellard | |
42 | b8a9e8f1 | bellard | #define EXCP_UDEF 1 /* undefined instruction */ |
43 | b8a9e8f1 | bellard | #define EXCP_SWI 2 /* software interrupt */ |
44 | b8a9e8f1 | bellard | #define EXCP_PREFETCH_ABORT 3 |
45 | b8a9e8f1 | bellard | #define EXCP_DATA_ABORT 4 |
46 | b5ff1b31 | bellard | #define EXCP_IRQ 5 |
47 | b5ff1b31 | bellard | #define EXCP_FIQ 6 |
48 | 06c949e6 | pbrook | #define EXCP_BKPT 7 |
49 | 9ee6e8bb | pbrook | #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */ |
50 | fbb4a2e3 | pbrook | #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */ |
51 | 426f5abc | Paul Brook | #define EXCP_STREX 10 |
52 | 9ee6e8bb | pbrook | |
53 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_RESET 1 |
54 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_NMI 2 |
55 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_HARD 3 |
56 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_MEM 4 |
57 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_BUS 5 |
58 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_USAGE 6 |
59 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_SVC 11 |
60 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_DEBUG 12 |
61 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_PENDSV 14 |
62 | 9ee6e8bb | pbrook | #define ARMV7M_EXCP_SYSTICK 15 |
63 | 2c0262af | bellard | |
64 | 403946c0 | Richard Henderson | /* ARM-specific interrupt pending bits. */
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65 | 403946c0 | Richard Henderson | #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
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66 | 403946c0 | Richard Henderson | |
67 | 7c1840b6 | Peter Maydell | /* Meanings of the ARMCPU object's two inbound GPIO lines */
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68 | 7c1840b6 | Peter Maydell | #define ARM_CPU_IRQ 0 |
69 | 7c1840b6 | Peter Maydell | #define ARM_CPU_FIQ 1 |
70 | 403946c0 | Richard Henderson | |
71 | c1713132 | balrog | typedef void ARMWriteCPFunc(void *opaque, int cp_info, |
72 | c1713132 | balrog | int srcreg, int operand, uint32_t value); |
73 | c1713132 | balrog | typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, |
74 | c1713132 | balrog | int dstreg, int operand); |
75 | c1713132 | balrog | |
76 | f93eb9ff | balrog | struct arm_boot_info;
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77 | f93eb9ff | balrog | |
78 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
79 | 6ebbf390 | j_mayer | |
80 | b7bcbe95 | bellard | /* We currently assume float and double are IEEE single and double
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81 | b7bcbe95 | bellard | precision respectively.
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82 | b7bcbe95 | bellard | Doing runtime conversions is tricky because VFP registers may contain
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83 | b7bcbe95 | bellard | integer values (eg. as the result of a FTOSI instruction).
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84 | 8e96005d | bellard | s<2n> maps to the least significant half of d<n>
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85 | 8e96005d | bellard | s<2n+1> maps to the most significant half of d<n>
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86 | 8e96005d | bellard | */
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87 | b7bcbe95 | bellard | |
88 | 55d284af | Peter Maydell | /* CPU state for each instance of a generic timer (in cp15 c14) */
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89 | 55d284af | Peter Maydell | typedef struct ARMGenericTimer { |
90 | 55d284af | Peter Maydell | uint64_t cval; /* Timer CompareValue register */
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91 | 55d284af | Peter Maydell | uint32_t ctl; /* Timer Control register */
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92 | 55d284af | Peter Maydell | } ARMGenericTimer; |
93 | 55d284af | Peter Maydell | |
94 | 55d284af | Peter Maydell | #define GTIMER_PHYS 0 |
95 | 55d284af | Peter Maydell | #define GTIMER_VIRT 1 |
96 | 55d284af | Peter Maydell | #define NUM_GTIMERS 2 |
97 | 55d284af | Peter Maydell | |
98 | 55d284af | Peter Maydell | /* Scale factor for generic timers, ie number of ns per tick.
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99 | 55d284af | Peter Maydell | * This gives a 62.5MHz timer.
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100 | 55d284af | Peter Maydell | */
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101 | 55d284af | Peter Maydell | #define GTIMER_SCALE 16 |
102 | 55d284af | Peter Maydell | |
103 | 2c0262af | bellard | typedef struct CPUARMState { |
104 | b5ff1b31 | bellard | /* Regs for current mode. */
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105 | 2c0262af | bellard | uint32_t regs[16];
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106 | 3926cc84 | Alexander Graf | |
107 | 3926cc84 | Alexander Graf | /* 32/64 switch only happens when taking and returning from
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108 | 3926cc84 | Alexander Graf | * exceptions so the overlap semantics are taken care of then
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109 | 3926cc84 | Alexander Graf | * instead of having a complicated union.
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110 | 3926cc84 | Alexander Graf | */
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111 | 3926cc84 | Alexander Graf | /* Regs for A64 mode. */
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112 | 3926cc84 | Alexander Graf | uint64_t xregs[32];
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113 | 3926cc84 | Alexander Graf | uint64_t pc; |
114 | 3926cc84 | Alexander Graf | /* TODO: pstate doesn't correspond to an architectural register;
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115 | 3926cc84 | Alexander Graf | * it would be better modelled as the underlying fields.
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116 | 3926cc84 | Alexander Graf | */
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117 | 3926cc84 | Alexander Graf | uint32_t pstate; |
118 | 3926cc84 | Alexander Graf | uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
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119 | 3926cc84 | Alexander Graf | |
120 | b90372ad | Peter Maydell | /* Frequently accessed CPSR bits are stored separately for efficiency.
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121 | d37aca66 | pbrook | This contains all the other bits. Use cpsr_{read,write} to access
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122 | b5ff1b31 | bellard | the whole CPSR. */
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123 | b5ff1b31 | bellard | uint32_t uncached_cpsr; |
124 | b5ff1b31 | bellard | uint32_t spsr; |
125 | b5ff1b31 | bellard | |
126 | b5ff1b31 | bellard | /* Banked registers. */
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127 | b5ff1b31 | bellard | uint32_t banked_spsr[6];
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128 | b5ff1b31 | bellard | uint32_t banked_r13[6];
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129 | b5ff1b31 | bellard | uint32_t banked_r14[6];
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130 | 3b46e624 | ths | |
131 | b5ff1b31 | bellard | /* These hold r8-r12. */
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132 | b5ff1b31 | bellard | uint32_t usr_regs[5];
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133 | b5ff1b31 | bellard | uint32_t fiq_regs[5];
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134 | 3b46e624 | ths | |
135 | 2c0262af | bellard | /* cpsr flag cache for faster execution */
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136 | 2c0262af | bellard | uint32_t CF; /* 0 or 1 */
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137 | 2c0262af | bellard | uint32_t VF; /* V is the bit 31. All other bits are undefined */
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138 | 6fbe23d5 | pbrook | uint32_t NF; /* N is bit 31. All other bits are undefined. */
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139 | 6fbe23d5 | pbrook | uint32_t ZF; /* Z set if zero. */
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140 | 99c475ab | bellard | uint32_t QF; /* 0 or 1 */
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141 | 9ee6e8bb | pbrook | uint32_t GE; /* cpsr[19:16] */
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142 | b26eefb6 | pbrook | uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
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143 | 9ee6e8bb | pbrook | uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
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144 | 2c0262af | bellard | |
145 | b5ff1b31 | bellard | /* System control coprocessor (cp15) */
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146 | b5ff1b31 | bellard | struct {
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147 | 40f137e1 | pbrook | uint32_t c0_cpuid; |
148 | a49ea279 | pbrook | uint32_t c0_cssel; /* Cache size selection. */
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149 | b5ff1b31 | bellard | uint32_t c1_sys; /* System control register. */
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150 | b5ff1b31 | bellard | uint32_t c1_coproc; /* Coprocessor access register. */
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151 | 610c3c8a | balrog | uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
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152 | 2be27624 | Rob Herring | uint32_t c1_scr; /* secure config register. */
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153 | 9ee6e8bb | pbrook | uint32_t c2_base0; /* MMU translation table base 0. */
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154 | 891a2fe7 | Peter Maydell | uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */
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155 | 891a2fe7 | Peter Maydell | uint32_t c2_base1; /* MMU translation table base 0. */
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156 | 891a2fe7 | Peter Maydell | uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */
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157 | b2fa1797 | pbrook | uint32_t c2_control; /* MMU translation table base control. */
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158 | b2fa1797 | pbrook | uint32_t c2_mask; /* MMU translation table base selection mask. */
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159 | b2fa1797 | pbrook | uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
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160 | ce819861 | pbrook | uint32_t c2_data; /* MPU data cachable bits. */
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161 | ce819861 | pbrook | uint32_t c2_insn; /* MPU instruction cachable bits. */
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162 | ce819861 | pbrook | uint32_t c3; /* MMU domain access control register
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163 | ce819861 | pbrook | MPU write buffer control. */
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164 | b5ff1b31 | bellard | uint32_t c5_insn; /* Fault status registers. */
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165 | b5ff1b31 | bellard | uint32_t c5_data; |
166 | ce819861 | pbrook | uint32_t c6_region[8]; /* MPU base/size registers. */ |
167 | b5ff1b31 | bellard | uint32_t c6_insn; /* Fault address registers. */
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168 | b5ff1b31 | bellard | uint32_t c6_data; |
169 | f8bf8606 | Adam Lackorzynski | uint32_t c7_par; /* Translation result. */
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170 | 891a2fe7 | Peter Maydell | uint32_t c7_par_hi; /* Translation result, high 32 bits */
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171 | b5ff1b31 | bellard | uint32_t c9_insn; /* Cache lockdown registers. */
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172 | b5ff1b31 | bellard | uint32_t c9_data; |
173 | 74594c9d | Peter Maydell | uint32_t c9_pmcr; /* performance monitor control register */
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174 | 74594c9d | Peter Maydell | uint32_t c9_pmcnten; /* perf monitor counter enables */
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175 | 74594c9d | Peter Maydell | uint32_t c9_pmovsr; /* perf monitor overflow status */
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176 | 74594c9d | Peter Maydell | uint32_t c9_pmxevtyper; /* perf monitor event type */
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177 | 74594c9d | Peter Maydell | uint32_t c9_pmuserenr; /* perf monitor user enable */
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178 | 74594c9d | Peter Maydell | uint32_t c9_pminten; /* perf monitor interrupt enables */
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179 | 8641136c | Nathan Rossi | uint32_t c12_vbar; /* vector base address register */
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180 | b5ff1b31 | bellard | uint32_t c13_fcse; /* FCSE PID. */
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181 | b5ff1b31 | bellard | uint32_t c13_context; /* Context ID. */
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182 | 9ee6e8bb | pbrook | uint32_t c13_tls1; /* User RW Thread register. */
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183 | 9ee6e8bb | pbrook | uint32_t c13_tls2; /* User RO Thread register. */
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184 | 9ee6e8bb | pbrook | uint32_t c13_tls3; /* Privileged Thread register. */
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185 | 55d284af | Peter Maydell | uint32_t c14_cntfrq; /* Counter Frequency register */
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186 | 55d284af | Peter Maydell | uint32_t c14_cntkctl; /* Timer Control register */
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187 | 55d284af | Peter Maydell | ARMGenericTimer c14_timer[NUM_GTIMERS]; |
188 | c1713132 | balrog | uint32_t c15_cpar; /* XScale Coprocessor Access Register */
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189 | c3d2689d | balrog | uint32_t c15_ticonfig; /* TI925T configuration byte. */
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190 | c3d2689d | balrog | uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
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191 | c3d2689d | balrog | uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
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192 | c3d2689d | balrog | uint32_t c15_threadid; /* TI debugger thread-ID. */
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193 | 7da362d0 | Mark Langsdorf | uint32_t c15_config_base_address; /* SCU base address. */
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194 | 7da362d0 | Mark Langsdorf | uint32_t c15_diagnostic; /* diagnostic register */
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195 | 7da362d0 | Mark Langsdorf | uint32_t c15_power_diagnostic; |
196 | 7da362d0 | Mark Langsdorf | uint32_t c15_power_control; /* power control */
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197 | b5ff1b31 | bellard | } cp15; |
198 | 40f137e1 | pbrook | |
199 | 3926cc84 | Alexander Graf | /* System registers (AArch64) */
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200 | 3926cc84 | Alexander Graf | struct {
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201 | 3926cc84 | Alexander Graf | uint64_t tpidr_el0; |
202 | 3926cc84 | Alexander Graf | } sr; |
203 | 3926cc84 | Alexander Graf | |
204 | 9ee6e8bb | pbrook | struct {
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205 | 9ee6e8bb | pbrook | uint32_t other_sp; |
206 | 9ee6e8bb | pbrook | uint32_t vecbase; |
207 | 9ee6e8bb | pbrook | uint32_t basepri; |
208 | 9ee6e8bb | pbrook | uint32_t control; |
209 | 9ee6e8bb | pbrook | int current_sp;
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210 | 9ee6e8bb | pbrook | int exception;
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211 | 9ee6e8bb | pbrook | int pending_exception;
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212 | 9ee6e8bb | pbrook | } v7m; |
213 | 9ee6e8bb | pbrook | |
214 | fe1479c3 | pbrook | /* Thumb-2 EE state. */
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215 | fe1479c3 | pbrook | uint32_t teecr; |
216 | fe1479c3 | pbrook | uint32_t teehbr; |
217 | fe1479c3 | pbrook | |
218 | b7bcbe95 | bellard | /* VFP coprocessor state. */
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219 | b7bcbe95 | bellard | struct {
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220 | 3926cc84 | Alexander Graf | /* VFP/Neon register state. Note that the mapping between S, D and Q
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221 | 3926cc84 | Alexander Graf | * views of the register bank differs between AArch64 and AArch32:
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222 | 3926cc84 | Alexander Graf | * In AArch32:
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223 | 3926cc84 | Alexander Graf | * Qn = regs[2n+1]:regs[2n]
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224 | 3926cc84 | Alexander Graf | * Dn = regs[n]
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225 | 3926cc84 | Alexander Graf | * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
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226 | 3926cc84 | Alexander Graf | * (and regs[32] to regs[63] are inaccessible)
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227 | 3926cc84 | Alexander Graf | * In AArch64:
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228 | 3926cc84 | Alexander Graf | * Qn = regs[2n+1]:regs[2n]
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229 | 3926cc84 | Alexander Graf | * Dn = regs[2n]
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230 | 3926cc84 | Alexander Graf | * Sn = regs[2n] bits 31..0
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231 | 3926cc84 | Alexander Graf | * This corresponds to the architecturally defined mapping between
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232 | 3926cc84 | Alexander Graf | * the two execution states, and means we do not need to explicitly
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233 | 3926cc84 | Alexander Graf | * map these registers when changing states.
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234 | 3926cc84 | Alexander Graf | */
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235 | 3926cc84 | Alexander Graf | float64 regs[64];
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236 | b7bcbe95 | bellard | |
237 | 40f137e1 | pbrook | uint32_t xregs[16];
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238 | b7bcbe95 | bellard | /* We store these fpcsr fields separately for convenience. */
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239 | b7bcbe95 | bellard | int vec_len;
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240 | b7bcbe95 | bellard | int vec_stride;
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241 | b7bcbe95 | bellard | |
242 | 9ee6e8bb | pbrook | /* scratch space when Tn are not sufficient. */
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243 | 9ee6e8bb | pbrook | uint32_t scratch[8];
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244 | 3b46e624 | ths | |
245 | 3a492f3a | Peter Maydell | /* fp_status is the "normal" fp status. standard_fp_status retains
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246 | 3a492f3a | Peter Maydell | * values corresponding to the ARM "Standard FPSCR Value", ie
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247 | 3a492f3a | Peter Maydell | * default-NaN, flush-to-zero, round-to-nearest and is used by
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248 | 3a492f3a | Peter Maydell | * any operations (generally Neon) which the architecture defines
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249 | 3a492f3a | Peter Maydell | * as controlled by the standard FPSCR value rather than the FPSCR.
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250 | 3a492f3a | Peter Maydell | *
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251 | 3a492f3a | Peter Maydell | * To avoid having to transfer exception bits around, we simply
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252 | 3a492f3a | Peter Maydell | * say that the FPSCR cumulative exception flags are the logical
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253 | 3a492f3a | Peter Maydell | * OR of the flags in the two fp statuses. This relies on the
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254 | 3a492f3a | Peter Maydell | * only thing which needs to read the exception flags being
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255 | 3a492f3a | Peter Maydell | * an explicit FPSCR read.
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256 | 3a492f3a | Peter Maydell | */
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257 | 53cd6637 | bellard | float_status fp_status; |
258 | 3a492f3a | Peter Maydell | float_status standard_fp_status; |
259 | b7bcbe95 | bellard | } vfp; |
260 | 426f5abc | Paul Brook | uint32_t exclusive_addr; |
261 | 426f5abc | Paul Brook | uint32_t exclusive_val; |
262 | 426f5abc | Paul Brook | uint32_t exclusive_high; |
263 | 9ee6e8bb | pbrook | #if defined(CONFIG_USER_ONLY)
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264 | 426f5abc | Paul Brook | uint32_t exclusive_test; |
265 | 426f5abc | Paul Brook | uint32_t exclusive_info; |
266 | 9ee6e8bb | pbrook | #endif
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267 | b7bcbe95 | bellard | |
268 | 18c9b560 | balrog | /* iwMMXt coprocessor state. */
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269 | 18c9b560 | balrog | struct {
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270 | 18c9b560 | balrog | uint64_t regs[16];
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271 | 18c9b560 | balrog | uint64_t val; |
272 | 18c9b560 | balrog | |
273 | 18c9b560 | balrog | uint32_t cregs[16];
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274 | 18c9b560 | balrog | } iwmmxt; |
275 | 18c9b560 | balrog | |
276 | d8fd2954 | Paul Brook | /* For mixed endian mode. */
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277 | d8fd2954 | Paul Brook | bool bswap_code;
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278 | d8fd2954 | Paul Brook | |
279 | ce4defa0 | pbrook | #if defined(CONFIG_USER_ONLY)
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280 | ce4defa0 | pbrook | /* For usermode syscall translation. */
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281 | ce4defa0 | pbrook | int eabi;
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282 | ce4defa0 | pbrook | #endif
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283 | ce4defa0 | pbrook | |
284 | a316d335 | bellard | CPU_COMMON |
285 | a316d335 | bellard | |
286 | 9d551997 | balrog | /* These fields after the common ones so they are preserved on reset. */
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287 | 9ba8c3f4 | Lars Munch | |
288 | 581be094 | Peter Maydell | /* Internal CPU feature flags. */
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289 | 918f5dca | Peter Maydell | uint64_t features; |
290 | 581be094 | Peter Maydell | |
291 | 983fe826 | Paul Brook | void *nvic;
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292 | 462a8bc6 | Stefan Weil | const struct arm_boot_info *boot_info; |
293 | 2c0262af | bellard | } CPUARMState; |
294 | 2c0262af | bellard | |
295 | 778c3a06 | Andreas Färber | #include "cpu-qom.h" |
296 | 778c3a06 | Andreas Färber | |
297 | 778c3a06 | Andreas Färber | ARMCPU *cpu_arm_init(const char *cpu_model); |
298 | b26eefb6 | pbrook | void arm_translate_init(void); |
299 | 14969266 | Andreas Färber | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
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300 | 2c0262af | bellard | int cpu_arm_exec(CPUARMState *s);
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301 | 494b00c7 | Christoffer Dall | int bank_number(int mode); |
302 | b5ff1b31 | bellard | void switch_mode(CPUARMState *, int); |
303 | 9ee6e8bb | pbrook | uint32_t do_arm_semihosting(CPUARMState *env); |
304 | b5ff1b31 | bellard | |
305 | 3926cc84 | Alexander Graf | static inline bool is_a64(CPUARMState *env) |
306 | 3926cc84 | Alexander Graf | { |
307 | 3926cc84 | Alexander Graf | return env->aarch64;
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308 | 3926cc84 | Alexander Graf | } |
309 | 3926cc84 | Alexander Graf | |
310 | 3926cc84 | Alexander Graf | #define PSTATE_N_SHIFT 3 |
311 | 3926cc84 | Alexander Graf | #define PSTATE_N (1 << PSTATE_N_SHIFT) |
312 | 3926cc84 | Alexander Graf | #define PSTATE_Z_SHIFT 2 |
313 | 3926cc84 | Alexander Graf | #define PSTATE_Z (1 << PSTATE_Z_SHIFT) |
314 | 3926cc84 | Alexander Graf | #define PSTATE_C_SHIFT 1 |
315 | 3926cc84 | Alexander Graf | #define PSTATE_C (1 << PSTATE_C_SHIFT) |
316 | 3926cc84 | Alexander Graf | #define PSTATE_V_SHIFT 0 |
317 | 3926cc84 | Alexander Graf | #define PSTATE_V (1 << PSTATE_V_SHIFT) |
318 | 3926cc84 | Alexander Graf | |
319 | 2c0262af | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
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320 | 2c0262af | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
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321 | 2c0262af | bellard | is returned if the signal was handled by the virtual CPU. */
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322 | 5fafdf24 | ths | int cpu_arm_signal_handler(int host_signum, void *pinfo, |
323 | 2c0262af | bellard | void *puc);
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324 | 84a031c6 | aurel32 | int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, |
325 | 97b348e7 | Blue Swirl | int mmu_idx);
|
326 | 0b5c1ce8 | Nathan Froyd | #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
|
327 | 2c0262af | bellard | |
328 | 78dbbbe4 | Peter Maydell | #define CPSR_M (0x1fU) |
329 | 78dbbbe4 | Peter Maydell | #define CPSR_T (1U << 5) |
330 | 78dbbbe4 | Peter Maydell | #define CPSR_F (1U << 6) |
331 | 78dbbbe4 | Peter Maydell | #define CPSR_I (1U << 7) |
332 | 78dbbbe4 | Peter Maydell | #define CPSR_A (1U << 8) |
333 | 78dbbbe4 | Peter Maydell | #define CPSR_E (1U << 9) |
334 | 78dbbbe4 | Peter Maydell | #define CPSR_IT_2_7 (0xfc00U) |
335 | 78dbbbe4 | Peter Maydell | #define CPSR_GE (0xfU << 16) |
336 | 78dbbbe4 | Peter Maydell | #define CPSR_RESERVED (0xfU << 20) |
337 | 78dbbbe4 | Peter Maydell | #define CPSR_J (1U << 24) |
338 | 78dbbbe4 | Peter Maydell | #define CPSR_IT_0_1 (3U << 25) |
339 | 78dbbbe4 | Peter Maydell | #define CPSR_Q (1U << 27) |
340 | 78dbbbe4 | Peter Maydell | #define CPSR_V (1U << 28) |
341 | 78dbbbe4 | Peter Maydell | #define CPSR_C (1U << 29) |
342 | 78dbbbe4 | Peter Maydell | #define CPSR_Z (1U << 30) |
343 | 78dbbbe4 | Peter Maydell | #define CPSR_N (1U << 31) |
344 | 9ee6e8bb | pbrook | #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
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345 | 9ee6e8bb | pbrook | |
346 | 9ee6e8bb | pbrook | #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
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347 | 9ee6e8bb | pbrook | #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
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348 | 9ee6e8bb | pbrook | /* Bits writable in user mode. */
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349 | 9ee6e8bb | pbrook | #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
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350 | 9ee6e8bb | pbrook | /* Execution state bits. MRS read as zero, MSR writes ignored. */
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351 | 9ee6e8bb | pbrook | #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
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352 | b5ff1b31 | bellard | |
353 | b5ff1b31 | bellard | /* Return the current CPSR value. */
|
354 | 2f4a40e5 | balrog | uint32_t cpsr_read(CPUARMState *env); |
355 | 2f4a40e5 | balrog | /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
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356 | 2f4a40e5 | balrog | void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
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357 | 9ee6e8bb | pbrook | |
358 | 9ee6e8bb | pbrook | /* Return the current xPSR value. */
|
359 | 9ee6e8bb | pbrook | static inline uint32_t xpsr_read(CPUARMState *env) |
360 | 9ee6e8bb | pbrook | { |
361 | 9ee6e8bb | pbrook | int ZF;
|
362 | 6fbe23d5 | pbrook | ZF = (env->ZF == 0);
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363 | 6fbe23d5 | pbrook | return (env->NF & 0x80000000) | (ZF << 30) |
364 | 9ee6e8bb | pbrook | | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) |
365 | 9ee6e8bb | pbrook | | (env->thumb << 24) | ((env->condexec_bits & 3) << 25) |
366 | 9ee6e8bb | pbrook | | ((env->condexec_bits & 0xfc) << 8) |
367 | 9ee6e8bb | pbrook | | env->v7m.exception; |
368 | b5ff1b31 | bellard | } |
369 | b5ff1b31 | bellard | |
370 | 9ee6e8bb | pbrook | /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
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371 | 9ee6e8bb | pbrook | static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) |
372 | 9ee6e8bb | pbrook | { |
373 | 9ee6e8bb | pbrook | if (mask & CPSR_NZCV) {
|
374 | 6fbe23d5 | pbrook | env->ZF = (~val) & CPSR_Z; |
375 | 6fbe23d5 | pbrook | env->NF = val; |
376 | 9ee6e8bb | pbrook | env->CF = (val >> 29) & 1; |
377 | 9ee6e8bb | pbrook | env->VF = (val << 3) & 0x80000000; |
378 | 9ee6e8bb | pbrook | } |
379 | 9ee6e8bb | pbrook | if (mask & CPSR_Q)
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380 | 9ee6e8bb | pbrook | env->QF = ((val & CPSR_Q) != 0);
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381 | 9ee6e8bb | pbrook | if (mask & (1 << 24)) |
382 | 9ee6e8bb | pbrook | env->thumb = ((val & (1 << 24)) != 0); |
383 | 9ee6e8bb | pbrook | if (mask & CPSR_IT_0_1) {
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384 | 9ee6e8bb | pbrook | env->condexec_bits &= ~3;
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385 | 9ee6e8bb | pbrook | env->condexec_bits |= (val >> 25) & 3; |
386 | 9ee6e8bb | pbrook | } |
387 | 9ee6e8bb | pbrook | if (mask & CPSR_IT_2_7) {
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388 | 9ee6e8bb | pbrook | env->condexec_bits &= 3;
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389 | 9ee6e8bb | pbrook | env->condexec_bits |= (val >> 8) & 0xfc; |
390 | 9ee6e8bb | pbrook | } |
391 | 9ee6e8bb | pbrook | if (mask & 0x1ff) { |
392 | 9ee6e8bb | pbrook | env->v7m.exception = val & 0x1ff;
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393 | 9ee6e8bb | pbrook | } |
394 | 9ee6e8bb | pbrook | } |
395 | 9ee6e8bb | pbrook | |
396 | 01653295 | Peter Maydell | /* Return the current FPSCR value. */
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397 | 01653295 | Peter Maydell | uint32_t vfp_get_fpscr(CPUARMState *env); |
398 | 01653295 | Peter Maydell | void vfp_set_fpscr(CPUARMState *env, uint32_t val);
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399 | 01653295 | Peter Maydell | |
400 | b5ff1b31 | bellard | enum arm_cpu_mode {
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401 | b5ff1b31 | bellard | ARM_CPU_MODE_USR = 0x10,
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402 | b5ff1b31 | bellard | ARM_CPU_MODE_FIQ = 0x11,
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403 | b5ff1b31 | bellard | ARM_CPU_MODE_IRQ = 0x12,
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404 | b5ff1b31 | bellard | ARM_CPU_MODE_SVC = 0x13,
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405 | b5ff1b31 | bellard | ARM_CPU_MODE_ABT = 0x17,
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406 | b5ff1b31 | bellard | ARM_CPU_MODE_UND = 0x1b,
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407 | b5ff1b31 | bellard | ARM_CPU_MODE_SYS = 0x1f
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408 | b5ff1b31 | bellard | }; |
409 | b5ff1b31 | bellard | |
410 | 40f137e1 | pbrook | /* VFP system registers. */
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411 | 40f137e1 | pbrook | #define ARM_VFP_FPSID 0 |
412 | 40f137e1 | pbrook | #define ARM_VFP_FPSCR 1 |
413 | 9ee6e8bb | pbrook | #define ARM_VFP_MVFR1 6 |
414 | 9ee6e8bb | pbrook | #define ARM_VFP_MVFR0 7 |
415 | 40f137e1 | pbrook | #define ARM_VFP_FPEXC 8 |
416 | 40f137e1 | pbrook | #define ARM_VFP_FPINST 9 |
417 | 40f137e1 | pbrook | #define ARM_VFP_FPINST2 10 |
418 | 40f137e1 | pbrook | |
419 | 18c9b560 | balrog | /* iwMMXt coprocessor control registers. */
|
420 | 18c9b560 | balrog | #define ARM_IWMMXT_wCID 0 |
421 | 18c9b560 | balrog | #define ARM_IWMMXT_wCon 1 |
422 | 18c9b560 | balrog | #define ARM_IWMMXT_wCSSF 2 |
423 | 18c9b560 | balrog | #define ARM_IWMMXT_wCASF 3 |
424 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR0 8 |
425 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR1 9 |
426 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR2 10 |
427 | 18c9b560 | balrog | #define ARM_IWMMXT_wCGR3 11 |
428 | 18c9b560 | balrog | |
429 | ce854d7c | Benoit Canet | /* If adding a feature bit which corresponds to a Linux ELF
|
430 | ce854d7c | Benoit Canet | * HWCAP bit, remember to update the feature-bit-to-hwcap
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431 | ce854d7c | Benoit Canet | * mapping in linux-user/elfload.c:get_elf_hwcap().
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432 | ce854d7c | Benoit Canet | */
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433 | 40f137e1 | pbrook | enum arm_features {
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434 | 40f137e1 | pbrook | ARM_FEATURE_VFP, |
435 | c1713132 | balrog | ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
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436 | c1713132 | balrog | ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
|
437 | ce819861 | pbrook | ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
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438 | 9ee6e8bb | pbrook | ARM_FEATURE_V6, |
439 | 9ee6e8bb | pbrook | ARM_FEATURE_V6K, |
440 | 9ee6e8bb | pbrook | ARM_FEATURE_V7, |
441 | 9ee6e8bb | pbrook | ARM_FEATURE_THUMB2, |
442 | c3d2689d | balrog | ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
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443 | 9ee6e8bb | pbrook | ARM_FEATURE_VFP3, |
444 | 60011498 | Paul Brook | ARM_FEATURE_VFP_FP16, |
445 | 9ee6e8bb | pbrook | ARM_FEATURE_NEON, |
446 | 47789990 | Peter Maydell | ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
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447 | 9ee6e8bb | pbrook | ARM_FEATURE_M, /* Microcontroller profile. */
|
448 | fe1479c3 | pbrook | ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
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449 | e1bbf446 | Peter Maydell | ARM_FEATURE_THUMB2EE, |
450 | be5e7a76 | Dmitry Eremin-Solenikov | ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
|
451 | be5e7a76 | Dmitry Eremin-Solenikov | ARM_FEATURE_V4T, |
452 | be5e7a76 | Dmitry Eremin-Solenikov | ARM_FEATURE_V5, |
453 | 5bc95aa2 | Dmitry Eremin-Solenikov | ARM_FEATURE_STRONGARM, |
454 | 906879a9 | Peter Maydell | ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
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455 | b8b8ea05 | Peter Maydell | ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
|
456 | da97f52c | Peter Maydell | ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
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457 | 0383ac00 | Peter Maydell | ARM_FEATURE_GENERIC_TIMER, |
458 | 06ed5d66 | Andrew Towers | ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
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459 | 1047b9d7 | Peter Maydell | ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
|
460 | c4804214 | Peter Maydell | ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
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461 | c4804214 | Peter Maydell | ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
|
462 | c4804214 | Peter Maydell | ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
|
463 | 81bdde9d | Peter Maydell | ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
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464 | de9b05b8 | Peter Maydell | ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
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465 | de9b05b8 | Peter Maydell | ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
|
466 | 81e69fb0 | Mans Rullgard | ARM_FEATURE_V8, |
467 | 3926cc84 | Alexander Graf | ARM_FEATURE_AARCH64, /* supports 64 bit mode */
|
468 | 40f137e1 | pbrook | }; |
469 | 40f137e1 | pbrook | |
470 | 40f137e1 | pbrook | static inline int arm_feature(CPUARMState *env, int feature) |
471 | 40f137e1 | pbrook | { |
472 | 918f5dca | Peter Maydell | return (env->features & (1ULL << feature)) != 0; |
473 | 40f137e1 | pbrook | } |
474 | 40f137e1 | pbrook | |
475 | 9a78eead | Stefan Weil | void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
|
476 | 40f137e1 | pbrook | |
477 | 9ee6e8bb | pbrook | /* Interface between CPU and Interrupt controller. */
|
478 | 9ee6e8bb | pbrook | void armv7m_nvic_set_pending(void *opaque, int irq); |
479 | 9ee6e8bb | pbrook | int armv7m_nvic_acknowledge_irq(void *opaque); |
480 | 9ee6e8bb | pbrook | void armv7m_nvic_complete_irq(void *opaque, int irq); |
481 | 9ee6e8bb | pbrook | |
482 | 4b6a83fb | Peter Maydell | /* Interface for defining coprocessor registers.
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483 | 4b6a83fb | Peter Maydell | * Registers are defined in tables of arm_cp_reginfo structs
|
484 | 4b6a83fb | Peter Maydell | * which are passed to define_arm_cp_regs().
|
485 | 4b6a83fb | Peter Maydell | */
|
486 | 4b6a83fb | Peter Maydell | |
487 | 4b6a83fb | Peter Maydell | /* When looking up a coprocessor register we look for it
|
488 | 4b6a83fb | Peter Maydell | * via an integer which encodes all of:
|
489 | 4b6a83fb | Peter Maydell | * coprocessor number
|
490 | 4b6a83fb | Peter Maydell | * Crn, Crm, opc1, opc2 fields
|
491 | 4b6a83fb | Peter Maydell | * 32 or 64 bit register (ie is it accessed via MRC/MCR
|
492 | 4b6a83fb | Peter Maydell | * or via MRRC/MCRR?)
|
493 | 4b6a83fb | Peter Maydell | * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
|
494 | 4b6a83fb | Peter Maydell | * (In this case crn and opc2 should be zero.)
|
495 | 4b6a83fb | Peter Maydell | */
|
496 | 4b6a83fb | Peter Maydell | #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2) \
|
497 | 4b6a83fb | Peter Maydell | (((cp) << 16) | ((is64) << 15) | ((crn) << 11) | \ |
498 | 4b6a83fb | Peter Maydell | ((crm) << 7) | ((opc1) << 3) | (opc2)) |
499 | 4b6a83fb | Peter Maydell | |
500 | 721fae12 | Peter Maydell | /* Note that these must line up with the KVM/ARM register
|
501 | 721fae12 | Peter Maydell | * ID field definitions (kvm.c will check this, but we
|
502 | 721fae12 | Peter Maydell | * can't just use the KVM defines here as the kvm headers
|
503 | 721fae12 | Peter Maydell | * are unavailable to non-KVM-specific files)
|
504 | 721fae12 | Peter Maydell | */
|
505 | 721fae12 | Peter Maydell | #define CP_REG_SIZE_SHIFT 52 |
506 | 721fae12 | Peter Maydell | #define CP_REG_SIZE_MASK 0x00f0000000000000ULL |
507 | 721fae12 | Peter Maydell | #define CP_REG_SIZE_U32 0x0020000000000000ULL |
508 | 721fae12 | Peter Maydell | #define CP_REG_SIZE_U64 0x0030000000000000ULL |
509 | 721fae12 | Peter Maydell | #define CP_REG_ARM 0x4000000000000000ULL |
510 | 721fae12 | Peter Maydell | |
511 | 721fae12 | Peter Maydell | /* Convert a full 64 bit KVM register ID to the truncated 32 bit
|
512 | 721fae12 | Peter Maydell | * version used as a key for the coprocessor register hashtable
|
513 | 721fae12 | Peter Maydell | */
|
514 | 721fae12 | Peter Maydell | static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) |
515 | 721fae12 | Peter Maydell | { |
516 | 721fae12 | Peter Maydell | uint32_t cpregid = kvmid; |
517 | 721fae12 | Peter Maydell | if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
|
518 | 721fae12 | Peter Maydell | cpregid |= (1 << 15); |
519 | 721fae12 | Peter Maydell | } |
520 | 721fae12 | Peter Maydell | return cpregid;
|
521 | 721fae12 | Peter Maydell | } |
522 | 721fae12 | Peter Maydell | |
523 | 721fae12 | Peter Maydell | /* Convert a truncated 32 bit hashtable key into the full
|
524 | 721fae12 | Peter Maydell | * 64 bit KVM register ID.
|
525 | 721fae12 | Peter Maydell | */
|
526 | 721fae12 | Peter Maydell | static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) |
527 | 721fae12 | Peter Maydell | { |
528 | 721fae12 | Peter Maydell | uint64_t kvmid = cpregid & ~(1 << 15); |
529 | 721fae12 | Peter Maydell | if (cpregid & (1 << 15)) { |
530 | 721fae12 | Peter Maydell | kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM; |
531 | 721fae12 | Peter Maydell | } else {
|
532 | 721fae12 | Peter Maydell | kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM; |
533 | 721fae12 | Peter Maydell | } |
534 | 721fae12 | Peter Maydell | return kvmid;
|
535 | 721fae12 | Peter Maydell | } |
536 | 721fae12 | Peter Maydell | |
537 | 4b6a83fb | Peter Maydell | /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
|
538 | 4b6a83fb | Peter Maydell | * special-behaviour cp reg and bits [15..8] indicate what behaviour
|
539 | 4b6a83fb | Peter Maydell | * it has. Otherwise it is a simple cp reg, where CONST indicates that
|
540 | 4b6a83fb | Peter Maydell | * TCG can assume the value to be constant (ie load at translate time)
|
541 | 4b6a83fb | Peter Maydell | * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
|
542 | 4b6a83fb | Peter Maydell | * indicates that the TB should not be ended after a write to this register
|
543 | 4b6a83fb | Peter Maydell | * (the default is that the TB ends after cp writes). OVERRIDE permits
|
544 | 4b6a83fb | Peter Maydell | * a register definition to override a previous definition for the
|
545 | 4b6a83fb | Peter Maydell | * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
|
546 | 4b6a83fb | Peter Maydell | * old must have the OVERRIDE bit set.
|
547 | 7023ec7e | Peter Maydell | * NO_MIGRATE indicates that this register should be ignored for migration;
|
548 | 7023ec7e | Peter Maydell | * (eg because any state is accessed via some other coprocessor register).
|
549 | 2452731c | Peter Maydell | * IO indicates that this register does I/O and therefore its accesses
|
550 | 2452731c | Peter Maydell | * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
|
551 | 2452731c | Peter Maydell | * registers which implement clocks or timers require this.
|
552 | 4b6a83fb | Peter Maydell | */
|
553 | 4b6a83fb | Peter Maydell | #define ARM_CP_SPECIAL 1 |
554 | 4b6a83fb | Peter Maydell | #define ARM_CP_CONST 2 |
555 | 4b6a83fb | Peter Maydell | #define ARM_CP_64BIT 4 |
556 | 4b6a83fb | Peter Maydell | #define ARM_CP_SUPPRESS_TB_END 8 |
557 | 4b6a83fb | Peter Maydell | #define ARM_CP_OVERRIDE 16 |
558 | 7023ec7e | Peter Maydell | #define ARM_CP_NO_MIGRATE 32 |
559 | 2452731c | Peter Maydell | #define ARM_CP_IO 64 |
560 | 4b6a83fb | Peter Maydell | #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8)) |
561 | 4b6a83fb | Peter Maydell | #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8)) |
562 | 4b6a83fb | Peter Maydell | #define ARM_LAST_SPECIAL ARM_CP_WFI
|
563 | 4b6a83fb | Peter Maydell | /* Used only as a terminator for ARMCPRegInfo lists */
|
564 | 4b6a83fb | Peter Maydell | #define ARM_CP_SENTINEL 0xffff |
565 | 4b6a83fb | Peter Maydell | /* Mask of only the flag bits in a type field */
|
566 | 2452731c | Peter Maydell | #define ARM_CP_FLAG_MASK 0x7f |
567 | 4b6a83fb | Peter Maydell | |
568 | 4b6a83fb | Peter Maydell | /* Return true if cptype is a valid type field. This is used to try to
|
569 | 4b6a83fb | Peter Maydell | * catch errors where the sentinel has been accidentally left off the end
|
570 | 4b6a83fb | Peter Maydell | * of a list of registers.
|
571 | 4b6a83fb | Peter Maydell | */
|
572 | 4b6a83fb | Peter Maydell | static inline bool cptype_valid(int cptype) |
573 | 4b6a83fb | Peter Maydell | { |
574 | 4b6a83fb | Peter Maydell | return ((cptype & ~ARM_CP_FLAG_MASK) == 0) |
575 | 4b6a83fb | Peter Maydell | || ((cptype & ARM_CP_SPECIAL) && |
576 | 34affeef | Peter Maydell | ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL)); |
577 | 4b6a83fb | Peter Maydell | } |
578 | 4b6a83fb | Peter Maydell | |
579 | 4b6a83fb | Peter Maydell | /* Access rights:
|
580 | 4b6a83fb | Peter Maydell | * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
|
581 | 4b6a83fb | Peter Maydell | * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
|
582 | 4b6a83fb | Peter Maydell | * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
|
583 | 4b6a83fb | Peter Maydell | * (ie any of the privileged modes in Secure state, or Monitor mode).
|
584 | 4b6a83fb | Peter Maydell | * If a register is accessible in one privilege level it's always accessible
|
585 | 4b6a83fb | Peter Maydell | * in higher privilege levels too. Since "Secure PL1" also follows this rule
|
586 | 4b6a83fb | Peter Maydell | * (ie anything visible in PL2 is visible in S-PL1, some things are only
|
587 | 4b6a83fb | Peter Maydell | * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
|
588 | 4b6a83fb | Peter Maydell | * terminology a little and call this PL3.
|
589 | 4b6a83fb | Peter Maydell | *
|
590 | 4b6a83fb | Peter Maydell | * If access permissions for a register are more complex than can be
|
591 | 4b6a83fb | Peter Maydell | * described with these bits, then use a laxer set of restrictions, and
|
592 | 4b6a83fb | Peter Maydell | * do the more restrictive/complex check inside a helper function.
|
593 | 4b6a83fb | Peter Maydell | */
|
594 | 4b6a83fb | Peter Maydell | #define PL3_R 0x80 |
595 | 4b6a83fb | Peter Maydell | #define PL3_W 0x40 |
596 | 4b6a83fb | Peter Maydell | #define PL2_R (0x20 | PL3_R) |
597 | 4b6a83fb | Peter Maydell | #define PL2_W (0x10 | PL3_W) |
598 | 4b6a83fb | Peter Maydell | #define PL1_R (0x08 | PL2_R) |
599 | 4b6a83fb | Peter Maydell | #define PL1_W (0x04 | PL2_W) |
600 | 4b6a83fb | Peter Maydell | #define PL0_R (0x02 | PL1_R) |
601 | 4b6a83fb | Peter Maydell | #define PL0_W (0x01 | PL1_W) |
602 | 4b6a83fb | Peter Maydell | |
603 | 4b6a83fb | Peter Maydell | #define PL3_RW (PL3_R | PL3_W)
|
604 | 4b6a83fb | Peter Maydell | #define PL2_RW (PL2_R | PL2_W)
|
605 | 4b6a83fb | Peter Maydell | #define PL1_RW (PL1_R | PL1_W)
|
606 | 4b6a83fb | Peter Maydell | #define PL0_RW (PL0_R | PL0_W)
|
607 | 4b6a83fb | Peter Maydell | |
608 | 4b6a83fb | Peter Maydell | static inline int arm_current_pl(CPUARMState *env) |
609 | 4b6a83fb | Peter Maydell | { |
610 | 4b6a83fb | Peter Maydell | if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) { |
611 | 4b6a83fb | Peter Maydell | return 0; |
612 | 4b6a83fb | Peter Maydell | } |
613 | 4b6a83fb | Peter Maydell | /* We don't currently implement the Virtualization or TrustZone
|
614 | 4b6a83fb | Peter Maydell | * extensions, so PL2 and PL3 don't exist for us.
|
615 | 4b6a83fb | Peter Maydell | */
|
616 | 4b6a83fb | Peter Maydell | return 1; |
617 | 4b6a83fb | Peter Maydell | } |
618 | 4b6a83fb | Peter Maydell | |
619 | 4b6a83fb | Peter Maydell | typedef struct ARMCPRegInfo ARMCPRegInfo; |
620 | 4b6a83fb | Peter Maydell | |
621 | 4b6a83fb | Peter Maydell | /* Access functions for coprocessor registers. These should return
|
622 | 4b6a83fb | Peter Maydell | * 0 on success, or one of the EXCP_* constants if access should cause
|
623 | 4b6a83fb | Peter Maydell | * an exception (in which case *value is not written).
|
624 | 4b6a83fb | Peter Maydell | */
|
625 | 4b6a83fb | Peter Maydell | typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque, |
626 | 4b6a83fb | Peter Maydell | uint64_t *value); |
627 | 4b6a83fb | Peter Maydell | typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, |
628 | 4b6a83fb | Peter Maydell | uint64_t value); |
629 | 4b6a83fb | Peter Maydell | /* Hook function for register reset */
|
630 | 4b6a83fb | Peter Maydell | typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); |
631 | 4b6a83fb | Peter Maydell | |
632 | 4b6a83fb | Peter Maydell | #define CP_ANY 0xff |
633 | 4b6a83fb | Peter Maydell | |
634 | 4b6a83fb | Peter Maydell | /* Definition of an ARM coprocessor register */
|
635 | 4b6a83fb | Peter Maydell | struct ARMCPRegInfo {
|
636 | 4b6a83fb | Peter Maydell | /* Name of register (useful mainly for debugging, need not be unique) */
|
637 | 4b6a83fb | Peter Maydell | const char *name; |
638 | 4b6a83fb | Peter Maydell | /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
|
639 | 4b6a83fb | Peter Maydell | * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
|
640 | 4b6a83fb | Peter Maydell | * 'wildcard' field -- any value of that field in the MRC/MCR insn
|
641 | 4b6a83fb | Peter Maydell | * will be decoded to this register. The register read and write
|
642 | 4b6a83fb | Peter Maydell | * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
|
643 | 4b6a83fb | Peter Maydell | * used by the program, so it is possible to register a wildcard and
|
644 | 4b6a83fb | Peter Maydell | * then behave differently on read/write if necessary.
|
645 | 4b6a83fb | Peter Maydell | * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
|
646 | 4b6a83fb | Peter Maydell | * must both be zero.
|
647 | 4b6a83fb | Peter Maydell | */
|
648 | 4b6a83fb | Peter Maydell | uint8_t cp; |
649 | 4b6a83fb | Peter Maydell | uint8_t crn; |
650 | 4b6a83fb | Peter Maydell | uint8_t crm; |
651 | 4b6a83fb | Peter Maydell | uint8_t opc1; |
652 | 4b6a83fb | Peter Maydell | uint8_t opc2; |
653 | 4b6a83fb | Peter Maydell | /* Register type: ARM_CP_* bits/values */
|
654 | 4b6a83fb | Peter Maydell | int type;
|
655 | 4b6a83fb | Peter Maydell | /* Access rights: PL*_[RW] */
|
656 | 4b6a83fb | Peter Maydell | int access;
|
657 | 4b6a83fb | Peter Maydell | /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
|
658 | 4b6a83fb | Peter Maydell | * this register was defined: can be used to hand data through to the
|
659 | 4b6a83fb | Peter Maydell | * register read/write functions, since they are passed the ARMCPRegInfo*.
|
660 | 4b6a83fb | Peter Maydell | */
|
661 | 4b6a83fb | Peter Maydell | void *opaque;
|
662 | 4b6a83fb | Peter Maydell | /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
|
663 | 4b6a83fb | Peter Maydell | * fieldoffset is non-zero, the reset value of the register.
|
664 | 4b6a83fb | Peter Maydell | */
|
665 | 4b6a83fb | Peter Maydell | uint64_t resetvalue; |
666 | 4b6a83fb | Peter Maydell | /* Offset of the field in CPUARMState for this register. This is not
|
667 | 4b6a83fb | Peter Maydell | * needed if either:
|
668 | 4b6a83fb | Peter Maydell | * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
|
669 | 4b6a83fb | Peter Maydell | * 2. both readfn and writefn are specified
|
670 | 4b6a83fb | Peter Maydell | */
|
671 | 4b6a83fb | Peter Maydell | ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
|
672 | 4b6a83fb | Peter Maydell | /* Function for handling reads of this register. If NULL, then reads
|
673 | 4b6a83fb | Peter Maydell | * will be done by loading from the offset into CPUARMState specified
|
674 | 4b6a83fb | Peter Maydell | * by fieldoffset.
|
675 | 4b6a83fb | Peter Maydell | */
|
676 | 4b6a83fb | Peter Maydell | CPReadFn *readfn; |
677 | 4b6a83fb | Peter Maydell | /* Function for handling writes of this register. If NULL, then writes
|
678 | 4b6a83fb | Peter Maydell | * will be done by writing to the offset into CPUARMState specified
|
679 | 4b6a83fb | Peter Maydell | * by fieldoffset.
|
680 | 4b6a83fb | Peter Maydell | */
|
681 | 4b6a83fb | Peter Maydell | CPWriteFn *writefn; |
682 | 7023ec7e | Peter Maydell | /* Function for doing a "raw" read; used when we need to copy
|
683 | 7023ec7e | Peter Maydell | * coprocessor state to the kernel for KVM or out for
|
684 | 7023ec7e | Peter Maydell | * migration. This only needs to be provided if there is also a
|
685 | 7023ec7e | Peter Maydell | * readfn and it makes an access permission check.
|
686 | 7023ec7e | Peter Maydell | */
|
687 | 7023ec7e | Peter Maydell | CPReadFn *raw_readfn; |
688 | 7023ec7e | Peter Maydell | /* Function for doing a "raw" write; used when we need to copy KVM
|
689 | 7023ec7e | Peter Maydell | * kernel coprocessor state into userspace, or for inbound
|
690 | 7023ec7e | Peter Maydell | * migration. This only needs to be provided if there is also a
|
691 | 7023ec7e | Peter Maydell | * writefn and it makes an access permission check or masks out
|
692 | 7023ec7e | Peter Maydell | * "unwritable" bits or has write-one-to-clear or similar behaviour.
|
693 | 7023ec7e | Peter Maydell | */
|
694 | 7023ec7e | Peter Maydell | CPWriteFn *raw_writefn; |
695 | 4b6a83fb | Peter Maydell | /* Function for resetting the register. If NULL, then reset will be done
|
696 | 4b6a83fb | Peter Maydell | * by writing resetvalue to the field specified in fieldoffset. If
|
697 | 4b6a83fb | Peter Maydell | * fieldoffset is 0 then no reset will be done.
|
698 | 4b6a83fb | Peter Maydell | */
|
699 | 4b6a83fb | Peter Maydell | CPResetFn *resetfn; |
700 | 4b6a83fb | Peter Maydell | }; |
701 | 4b6a83fb | Peter Maydell | |
702 | 4b6a83fb | Peter Maydell | /* Macros which are lvalues for the field in CPUARMState for the
|
703 | 4b6a83fb | Peter Maydell | * ARMCPRegInfo *ri.
|
704 | 4b6a83fb | Peter Maydell | */
|
705 | 4b6a83fb | Peter Maydell | #define CPREG_FIELD32(env, ri) \
|
706 | 4b6a83fb | Peter Maydell | (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
|
707 | 4b6a83fb | Peter Maydell | #define CPREG_FIELD64(env, ri) \
|
708 | 4b6a83fb | Peter Maydell | (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
|
709 | 4b6a83fb | Peter Maydell | |
710 | 4b6a83fb | Peter Maydell | #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
|
711 | 4b6a83fb | Peter Maydell | |
712 | 4b6a83fb | Peter Maydell | void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
|
713 | 4b6a83fb | Peter Maydell | const ARMCPRegInfo *regs, void *opaque); |
714 | 4b6a83fb | Peter Maydell | void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
|
715 | 4b6a83fb | Peter Maydell | const ARMCPRegInfo *regs, void *opaque); |
716 | 4b6a83fb | Peter Maydell | static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs) |
717 | 4b6a83fb | Peter Maydell | { |
718 | 4b6a83fb | Peter Maydell | define_arm_cp_regs_with_opaque(cpu, regs, 0);
|
719 | 4b6a83fb | Peter Maydell | } |
720 | 4b6a83fb | Peter Maydell | static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) |
721 | 4b6a83fb | Peter Maydell | { |
722 | 4b6a83fb | Peter Maydell | define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
|
723 | 4b6a83fb | Peter Maydell | } |
724 | 4b6a83fb | Peter Maydell | const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp);
|
725 | 4b6a83fb | Peter Maydell | |
726 | 4b6a83fb | Peter Maydell | /* CPWriteFn that can be used to implement writes-ignored behaviour */
|
727 | 4b6a83fb | Peter Maydell | int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, |
728 | 4b6a83fb | Peter Maydell | uint64_t value); |
729 | 4b6a83fb | Peter Maydell | /* CPReadFn that can be used for read-as-zero behaviour */
|
730 | 4b6a83fb | Peter Maydell | int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value); |
731 | 4b6a83fb | Peter Maydell | |
732 | 4b6a83fb | Peter Maydell | static inline bool cp_access_ok(CPUARMState *env, |
733 | 4b6a83fb | Peter Maydell | const ARMCPRegInfo *ri, int isread) |
734 | 4b6a83fb | Peter Maydell | { |
735 | 4b6a83fb | Peter Maydell | return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1; |
736 | 4b6a83fb | Peter Maydell | } |
737 | 4b6a83fb | Peter Maydell | |
738 | 721fae12 | Peter Maydell | /**
|
739 | 721fae12 | Peter Maydell | * write_list_to_cpustate
|
740 | 721fae12 | Peter Maydell | * @cpu: ARMCPU
|
741 | 721fae12 | Peter Maydell | *
|
742 | 721fae12 | Peter Maydell | * For each register listed in the ARMCPU cpreg_indexes list, write
|
743 | 721fae12 | Peter Maydell | * its value from the cpreg_values list into the ARMCPUState structure.
|
744 | 721fae12 | Peter Maydell | * This updates TCG's working data structures from KVM data or
|
745 | 721fae12 | Peter Maydell | * from incoming migration state.
|
746 | 721fae12 | Peter Maydell | *
|
747 | 721fae12 | Peter Maydell | * Returns: true if all register values were updated correctly,
|
748 | 721fae12 | Peter Maydell | * false if some register was unknown or could not be written.
|
749 | 721fae12 | Peter Maydell | * Note that we do not stop early on failure -- we will attempt
|
750 | 721fae12 | Peter Maydell | * writing all registers in the list.
|
751 | 721fae12 | Peter Maydell | */
|
752 | 721fae12 | Peter Maydell | bool write_list_to_cpustate(ARMCPU *cpu);
|
753 | 721fae12 | Peter Maydell | |
754 | 721fae12 | Peter Maydell | /**
|
755 | 721fae12 | Peter Maydell | * write_cpustate_to_list:
|
756 | 721fae12 | Peter Maydell | * @cpu: ARMCPU
|
757 | 721fae12 | Peter Maydell | *
|
758 | 721fae12 | Peter Maydell | * For each register listed in the ARMCPU cpreg_indexes list, write
|
759 | 721fae12 | Peter Maydell | * its value from the ARMCPUState structure into the cpreg_values list.
|
760 | 721fae12 | Peter Maydell | * This is used to copy info from TCG's working data structures into
|
761 | 721fae12 | Peter Maydell | * KVM or for outbound migration.
|
762 | 721fae12 | Peter Maydell | *
|
763 | 721fae12 | Peter Maydell | * Returns: true if all register values were read correctly,
|
764 | 721fae12 | Peter Maydell | * false if some register was unknown or could not be read.
|
765 | 721fae12 | Peter Maydell | * Note that we do not stop early on failure -- we will attempt
|
766 | 721fae12 | Peter Maydell | * reading all registers in the list.
|
767 | 721fae12 | Peter Maydell | */
|
768 | 721fae12 | Peter Maydell | bool write_cpustate_to_list(ARMCPU *cpu);
|
769 | 721fae12 | Peter Maydell | |
770 | 9ee6e8bb | pbrook | /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
|
771 | 9ee6e8bb | pbrook | Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
|
772 | 9ee6e8bb | pbrook | conventional cores (ie. Application or Realtime profile). */
|
773 | 9ee6e8bb | pbrook | |
774 | 9ee6e8bb | pbrook | #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
|
775 | 9ee6e8bb | pbrook | |
776 | 9ee6e8bb | pbrook | #define ARM_CPUID_TI915T 0x54029152 |
777 | 9ee6e8bb | pbrook | #define ARM_CPUID_TI925T 0x54029252 |
778 | 40f137e1 | pbrook | |
779 | b5ff1b31 | bellard | #if defined(CONFIG_USER_ONLY)
|
780 | 2c0262af | bellard | #define TARGET_PAGE_BITS 12 |
781 | b5ff1b31 | bellard | #else
|
782 | b5ff1b31 | bellard | /* The ARM MMU allows 1k pages. */
|
783 | b5ff1b31 | bellard | /* ??? Linux doesn't actually use these, and they're deprecated in recent
|
784 | 82d17978 | balrog | architecture revisions. Maybe a configure option to disable them. */
|
785 | b5ff1b31 | bellard | #define TARGET_PAGE_BITS 10 |
786 | b5ff1b31 | bellard | #endif
|
787 | 9467d44c | ths | |
788 | 3926cc84 | Alexander Graf | #if defined(TARGET_AARCH64)
|
789 | 3926cc84 | Alexander Graf | # define TARGET_PHYS_ADDR_SPACE_BITS 48 |
790 | 3926cc84 | Alexander Graf | # define TARGET_VIRT_ADDR_SPACE_BITS 64 |
791 | 3926cc84 | Alexander Graf | #else
|
792 | 3926cc84 | Alexander Graf | # define TARGET_PHYS_ADDR_SPACE_BITS 40 |
793 | 3926cc84 | Alexander Graf | # define TARGET_VIRT_ADDR_SPACE_BITS 32 |
794 | 3926cc84 | Alexander Graf | #endif
|
795 | 52705890 | Richard Henderson | |
796 | ad37ad5b | Peter Maydell | static inline CPUARMState *cpu_init(const char *cpu_model) |
797 | ad37ad5b | Peter Maydell | { |
798 | ad37ad5b | Peter Maydell | ARMCPU *cpu = cpu_arm_init(cpu_model); |
799 | ad37ad5b | Peter Maydell | if (cpu) {
|
800 | ad37ad5b | Peter Maydell | return &cpu->env;
|
801 | ad37ad5b | Peter Maydell | } |
802 | ad37ad5b | Peter Maydell | return NULL; |
803 | ad37ad5b | Peter Maydell | } |
804 | ad37ad5b | Peter Maydell | |
805 | 9467d44c | ths | #define cpu_exec cpu_arm_exec
|
806 | 9467d44c | ths | #define cpu_gen_code cpu_arm_gen_code
|
807 | 9467d44c | ths | #define cpu_signal_handler cpu_arm_signal_handler
|
808 | c732abe2 | j_mayer | #define cpu_list arm_cpu_list
|
809 | 9467d44c | ths | |
810 | 6ebbf390 | j_mayer | /* MMU modes definitions */
|
811 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
|
812 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _user
|
813 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 1 |
814 | 0ecb72a5 | Andreas Färber | static inline int cpu_mmu_index (CPUARMState *env) |
815 | 6ebbf390 | j_mayer | { |
816 | 6ebbf390 | j_mayer | return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0; |
817 | 6ebbf390 | j_mayer | } |
818 | 6ebbf390 | j_mayer | |
819 | 022c62cb | Paolo Bonzini | #include "exec/cpu-all.h" |
820 | 622ed360 | aliguori | |
821 | 3926cc84 | Alexander Graf | /* Bit usage in the TB flags field: bit 31 indicates whether we are
|
822 | 3926cc84 | Alexander Graf | * in 32 or 64 bit mode. The meaning of the other bits depends on that.
|
823 | 3926cc84 | Alexander Graf | */
|
824 | 3926cc84 | Alexander Graf | #define ARM_TBFLAG_AARCH64_STATE_SHIFT 31 |
825 | 3926cc84 | Alexander Graf | #define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT) |
826 | 3926cc84 | Alexander Graf | |
827 | 3926cc84 | Alexander Graf | /* Bit usage when in AArch32 state: */
|
828 | a1705768 | Peter Maydell | #define ARM_TBFLAG_THUMB_SHIFT 0 |
829 | a1705768 | Peter Maydell | #define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) |
830 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VECLEN_SHIFT 1 |
831 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) |
832 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VECSTRIDE_SHIFT 4 |
833 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) |
834 | a1705768 | Peter Maydell | #define ARM_TBFLAG_PRIV_SHIFT 6 |
835 | a1705768 | Peter Maydell | #define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT) |
836 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VFPEN_SHIFT 7 |
837 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) |
838 | a1705768 | Peter Maydell | #define ARM_TBFLAG_CONDEXEC_SHIFT 8 |
839 | a1705768 | Peter Maydell | #define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) |
840 | d8fd2954 | Paul Brook | #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16 |
841 | d8fd2954 | Paul Brook | #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT) |
842 | 3926cc84 | Alexander Graf | |
843 | 3926cc84 | Alexander Graf | /* Bit usage when in AArch64 state: currently no bits defined */
|
844 | a1705768 | Peter Maydell | |
845 | a1705768 | Peter Maydell | /* some convenience accessor macros */
|
846 | 3926cc84 | Alexander Graf | #define ARM_TBFLAG_AARCH64_STATE(F) \
|
847 | 3926cc84 | Alexander Graf | (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT) |
848 | a1705768 | Peter Maydell | #define ARM_TBFLAG_THUMB(F) \
|
849 | a1705768 | Peter Maydell | (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) |
850 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VECLEN(F) \
|
851 | a1705768 | Peter Maydell | (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) |
852 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VECSTRIDE(F) \
|
853 | a1705768 | Peter Maydell | (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) |
854 | a1705768 | Peter Maydell | #define ARM_TBFLAG_PRIV(F) \
|
855 | a1705768 | Peter Maydell | (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT) |
856 | a1705768 | Peter Maydell | #define ARM_TBFLAG_VFPEN(F) \
|
857 | a1705768 | Peter Maydell | (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) |
858 | a1705768 | Peter Maydell | #define ARM_TBFLAG_CONDEXEC(F) \
|
859 | a1705768 | Peter Maydell | (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) |
860 | d8fd2954 | Paul Brook | #define ARM_TBFLAG_BSWAP_CODE(F) \
|
861 | d8fd2954 | Paul Brook | (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT) |
862 | a1705768 | Peter Maydell | |
863 | 0ecb72a5 | Andreas Färber | static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, |
864 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
|
865 | 6b917547 | aliguori | { |
866 | 3926cc84 | Alexander Graf | if (is_a64(env)) {
|
867 | 3926cc84 | Alexander Graf | *pc = env->pc; |
868 | 3926cc84 | Alexander Graf | *flags = ARM_TBFLAG_AARCH64_STATE_MASK; |
869 | 05ed9a99 | Peter Maydell | } else {
|
870 | 3926cc84 | Alexander Graf | int privmode;
|
871 | 3926cc84 | Alexander Graf | *pc = env->regs[15];
|
872 | 3926cc84 | Alexander Graf | *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) |
873 | 3926cc84 | Alexander Graf | | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) |
874 | 3926cc84 | Alexander Graf | | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) |
875 | 3926cc84 | Alexander Graf | | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) |
876 | 3926cc84 | Alexander Graf | | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT); |
877 | 3926cc84 | Alexander Graf | if (arm_feature(env, ARM_FEATURE_M)) {
|
878 | 3926cc84 | Alexander Graf | privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1)); |
879 | 3926cc84 | Alexander Graf | } else {
|
880 | 3926cc84 | Alexander Graf | privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR; |
881 | 3926cc84 | Alexander Graf | } |
882 | 3926cc84 | Alexander Graf | if (privmode) {
|
883 | 3926cc84 | Alexander Graf | *flags |= ARM_TBFLAG_PRIV_MASK; |
884 | 3926cc84 | Alexander Graf | } |
885 | 3926cc84 | Alexander Graf | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { |
886 | 3926cc84 | Alexander Graf | *flags |= ARM_TBFLAG_VFPEN_MASK; |
887 | 3926cc84 | Alexander Graf | } |
888 | a1705768 | Peter Maydell | } |
889 | 3926cc84 | Alexander Graf | |
890 | 3926cc84 | Alexander Graf | *cs_base = 0;
|
891 | 6b917547 | aliguori | } |
892 | 6b917547 | aliguori | |
893 | 3993c6bd | Andreas Färber | static inline bool cpu_has_work(CPUState *cpu) |
894 | f081c76c | Blue Swirl | { |
895 | 259186a7 | Andreas Färber | return cpu->interrupt_request &
|
896 | f081c76c | Blue Swirl | (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); |
897 | f081c76c | Blue Swirl | } |
898 | f081c76c | Blue Swirl | |
899 | 022c62cb | Paolo Bonzini | #include "exec/exec-all.h" |
900 | f081c76c | Blue Swirl | |
901 | 3926cc84 | Alexander Graf | static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb) |
902 | 3926cc84 | Alexander Graf | { |
903 | 3926cc84 | Alexander Graf | if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
|
904 | 3926cc84 | Alexander Graf | env->pc = tb->pc; |
905 | 3926cc84 | Alexander Graf | } else {
|
906 | 3926cc84 | Alexander Graf | env->regs[15] = tb->pc;
|
907 | 3926cc84 | Alexander Graf | } |
908 | 3926cc84 | Alexander Graf | } |
909 | 3926cc84 | Alexander Graf | |
910 | d8fd2954 | Paul Brook | /* Load an instruction and return it in the standard little-endian order */
|
911 | 0a2461fa | Alexander Graf | static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr, |
912 | d31dd73e | Blue Swirl | bool do_swap)
|
913 | d8fd2954 | Paul Brook | { |
914 | d31dd73e | Blue Swirl | uint32_t insn = cpu_ldl_code(env, addr); |
915 | d8fd2954 | Paul Brook | if (do_swap) {
|
916 | d8fd2954 | Paul Brook | return bswap32(insn);
|
917 | d8fd2954 | Paul Brook | } |
918 | d8fd2954 | Paul Brook | return insn;
|
919 | d8fd2954 | Paul Brook | } |
920 | d8fd2954 | Paul Brook | |
921 | d8fd2954 | Paul Brook | /* Ditto, for a halfword (Thumb) instruction */
|
922 | 0a2461fa | Alexander Graf | static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr, |
923 | d31dd73e | Blue Swirl | bool do_swap)
|
924 | d8fd2954 | Paul Brook | { |
925 | d31dd73e | Blue Swirl | uint16_t insn = cpu_lduw_code(env, addr); |
926 | d8fd2954 | Paul Brook | if (do_swap) {
|
927 | d8fd2954 | Paul Brook | return bswap16(insn);
|
928 | d8fd2954 | Paul Brook | } |
929 | d8fd2954 | Paul Brook | return insn;
|
930 | d8fd2954 | Paul Brook | } |
931 | d8fd2954 | Paul Brook | |
932 | 2c0262af | bellard | #endif |