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Remove someexplicit alignment checks (initial patch by Fabrice Bellard)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4431 c046a42c-6fe2-441c-8c8c-71466251a162
Add a TODO file
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4410 c046a42c-6fe2-441c-8c8c-71466251a162
suppressed fixed registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4408 c046a42c-6fe2-441c-8c8c-71466251a162
Fix compiler warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4404 c046a42c-6fe2-441c-8c8c-71466251a162
CPU feature selection support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4399 c046a42c-6fe2-441c-8c8c-71466251a162
Simplify some constant loads
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4383 c046a42c-6fe2-441c-8c8c-71466251a162
Fix potential condition code problems
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4382 c046a42c-6fe2-441c-8c8c-71466251a162
Complete the TCG conversion
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4323 c046a42c-6fe2-441c-8c8c-71466251a162
Avoid some brconds
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4318 c046a42c-6fe2-441c-8c8c-71466251a162
Use memory based registers in functions containing brconds
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4311 c046a42c-6fe2-441c-8c8c-71466251a162
Factorize code in translate.c
(Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
Document the shift values
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4243 c046a42c-6fe2-441c-8c8c-71466251a162
Remove incorrect discards and old unused defines (blueswir1).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4137 c046a42c-6fe2-441c-8c8c-71466251a162
Change handling of source 2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4135 c046a42c-6fe2-441c-8c8c-71466251a162
Change handling of source register 1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4134 c046a42c-6fe2-441c-8c8c-71466251a162
Move CPU stuff unrelated to translation to helper.c
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4133 c046a42c-6fe2-441c-8c8c-71466251a162
Rename T012 according to their roles
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4131 c046a42c-6fe2-441c-8c8c-71466251a162
Avoid writes to T1 except for loads/stores, convert some T0 uses to cpu_tmp0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4130 c046a42c-6fe2-441c-8c8c-71466251a162
Accidentally dropped one change from previous commit
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4129 c046a42c-6fe2-441c-8c8c-71466251a162
Concentrate cpu_T012 use to one function
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4110 c046a42c-6fe2-441c-8c8c-71466251a162
Split icc and xcc flag calculations
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4109 c046a42c-6fe2-441c-8c8c-71466251a162
Remove some legacy definitions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4108 c046a42c-6fe2-441c-8c8c-71466251a162
Fix a sign extension problem
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4105 c046a42c-6fe2-441c-8c8c-71466251a162
Fix mulscc
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4103 c046a42c-6fe2-441c-8c8c-71466251a162
Convert ldf/ldfsr and stf/stfsr to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4101 c046a42c-6fe2-441c-8c8c-71466251a162
Fix i32/i64/TL mismatches
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4100 c046a42c-6fe2-441c-8c8c-71466251a162
Convert align checks to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4097 c046a42c-6fe2-441c-8c8c-71466251a162
Convert jumps to labels to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4094 c046a42c-6fe2-441c-8c8c-71466251a162
Convert save, restore, saved, restored, and flushw to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4092 c046a42c-6fe2-441c-8c8c-71466251a162
Convert other float and VIS ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4091 c046a42c-6fe2-441c-8c8c-71466251a162
Convert float move ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4090 c046a42c-6fe2-441c-8c8c-71466251a162
Convert udiv and sdiv ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4088 c046a42c-6fe2-441c-8c8c-71466251a162
Use ext_i32_i64 instead of ext32s_i64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4087 c046a42c-6fe2-441c-8c8c-71466251a162
Convert CCR and CWP ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4086 c046a42c-6fe2-441c-8c8c-71466251a162
Convert array8/16/32 and alignaddr to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4085 c046a42c-6fe2-441c-8c8c-71466251a162
Convert umul and smul to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4077 c046a42c-6fe2-441c-8c8c-71466251a162
Use a TCG global for pc and npc
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4076 c046a42c-6fe2-441c-8c8c-71466251a162
Convert mulscc to TCG, add cc_src2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4075 c046a42c-6fe2-441c-8c8c-71466251a162
Discard unused data, use less temps
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4073 c046a42c-6fe2-441c-8c8c-71466251a162
Use a TCG global for fsr
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4068 c046a42c-6fe2-441c-8c8c-71466251a162
Convert ldfsr and stfsr to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4067 c046a42c-6fe2-441c-8c8c-71466251a162
Eliminate some uses of T2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4065 c046a42c-6fe2-441c-8c8c-71466251a162
Convert udivx and sdivx to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4064 c046a42c-6fe2-441c-8c8c-71466251a162
Use memory globals for G registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4062 c046a42c-6fe2-441c-8c8c-71466251a162
Use tcg_const_tl for zero constant
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4054 c046a42c-6fe2-441c-8c8c-71466251a162
Convert condition code changing versions of add, sub, logic, and div to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4052 c046a42c-6fe2-441c-8c8c-71466251a162
Use a TCG global for regwptr
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4038 c046a42c-6fe2-441c-8c8c-71466251a162
Convert andn, orn and xnor to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4030 c046a42c-6fe2-441c-8c8c-71466251a162
Convert branches and conditional moves to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4028 c046a42c-6fe2-441c-8c8c-71466251a162
Convert exception ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4022 c046a42c-6fe2-441c-8c8c-71466251a162
Fix microSPARC II SFSR mask (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4021 c046a42c-6fe2-441c-8c8c-71466251a162
Convert Sparc64 trap state ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4018 c046a42c-6fe2-441c-8c8c-71466251a162
Convert float helpers to TCG, fix fabsq in the process
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4014 c046a42c-6fe2-441c-8c8c-71466251a162
Convert fmovr to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4013 c046a42c-6fe2-441c-8c8c-71466251a162
Convert tick operations to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4011 c046a42c-6fe2-441c-8c8c-71466251a162
Convert movr and (partially) movcc to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4010 c046a42c-6fe2-441c-8c8c-71466251a162
Convert addx, subx, next_insn and mov_pc_npc to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4009 c046a42c-6fe2-441c-8c8c-71466251a162
Temporary fix for i386 host
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3994 c046a42c-6fe2-441c-8c8c-71466251a162
Modify Sparc32/64 to use TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3989 c046a42c-6fe2-441c-8c8c-71466251a162
Fix remote debugger memory access problems reported by Matthias Stein
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3982 c046a42c-6fe2-441c-8c8c-71466251a162
Sparc32 MMU register fixes (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3979 c046a42c-6fe2-441c-8c8c-71466251a162
use the TCG code generator
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
Handle cpu_model in copy_cpu(), by Kirill A. Shutemov.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3778 c046a42c-6fe2-441c-8c8c-71466251a162
Fix floating point register decoding
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3742 c046a42c-6fe2-441c-8c8c-71466251a162
128-bit float support for user mode
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3740 c046a42c-6fe2-441c-8c8c-71466251a162
added cpu_model parameter to cpu_init()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
More Sparc64 CPU definitions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3561 c046a42c-6fe2-441c-8c8c-71466251a162
More CPU definitions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3559 c046a42c-6fe2-441c-8c8c-71466251a162
CPU specific boot mode (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3542 c046a42c-6fe2-441c-8c8c-71466251a162
Enable all alignment checks
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3404 c046a42c-6fe2-441c-8c8c-71466251a162
Sparc64 hypervisor mode
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3398 c046a42c-6fe2-441c-8c8c-71466251a162
SuperSparc MXCC support (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3397 c046a42c-6fe2-441c-8c8c-71466251a162
Replace is_user variable with mmu_idx in softmmu core, allowing support of more than 2 mmu access modes.Add backward compatibility is_user variable in targets code when needed.Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions....
Fix taddcctv and tsubcctv (David Matthews)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3379 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc64 ldfa/stfa and float ops with fpr >= 32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3318 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc64 ldfa, lddfa, stfa, and stdfa instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3298 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc64 wrasr instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3297 c046a42c-6fe2-441c-8c8c-71466251a162
CPU boot mode
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3231 c046a42c-6fe2-441c-8c8c-71466251a162
Rework ASI instructions (Aurelien Jarno)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3205 c046a42c-6fe2-441c-8c8c-71466251a162
Detabify
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3195 c046a42c-6fe2-441c-8c8c-71466251a162
find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
Fix tb->size mishandling, by Daniel Jacobowitz.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3160 c046a42c-6fe2-441c-8c8c-71466251a162
More alignment checks
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3060 c046a42c-6fe2-441c-8c8c-71466251a162
Save state in Sparc64 return op
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3054 c046a42c-6fe2-441c-8c8c-71466251a162
Use unsigned 32-bit load for ld/lduw
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3051 c046a42c-6fe2-441c-8c8c-71466251a162
Fix wrong number of clean/saveable windows, match Linux startup register values
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3050 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc64 movr
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3045 c046a42c-6fe2-441c-8c8c-71466251a162
Drop unused parameters
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3022 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc64 prefetcha op
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2978 c046a42c-6fe2-441c-8c8c-71466251a162
Implement Sparc64 CPU timers using ptimers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2860 c046a42c-6fe2-441c-8c8c-71466251a162
Enable faults for unassigned memory accesses and unimplemented ASIs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2824 c046a42c-6fe2-441c-8c8c-71466251a162
Fix pc/npc for unaligned load/stores, maybe other exceptions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2780 c046a42c-6fe2-441c-8c8c-71466251a162
More Sparc32 CPUs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2744 c046a42c-6fe2-441c-8c8c-71466251a162
Fix CPU type zapped by system_reset
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2743 c046a42c-6fe2-441c-8c8c-71466251a162
Sparc64 update: more VIS ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2714 c046a42c-6fe2-441c-8c8c-71466251a162
Constification
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2711 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc64 wrfprs, move VIS ops where they belong, more VIS ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2656 c046a42c-6fe2-441c-8c8c-71466251a162
Alignment check mechanism (not fully enabled yet) (Aurelien Jarno)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2655 c046a42c-6fe2-441c-8c8c-71466251a162
cpu_get_phys_page_debug should return target_phys_addr_t instead of target_ulong to be consistent.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2633 c046a42c-6fe2-441c-8c8c-71466251a162
Full implementation of IEEE exceptions (Aurelien Jarno)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2625 c046a42c-6fe2-441c-8c8c-71466251a162