root / hw / mac_dbdma.c @ 86948bb1
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1 | 3cbee15b | j_mayer | /*
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2 | 3cbee15b | j_mayer | * PowerMac descriptor-based DMA emulation
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3 | 3cbee15b | j_mayer | *
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4 | 3cbee15b | j_mayer | * Copyright (c) 2005-2007 Fabrice Bellard
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5 | 3cbee15b | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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6 | 28ce5ce6 | aurel32 | * Copyright (c) 2009 Laurent Vivier
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7 | 28ce5ce6 | aurel32 | *
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8 | 28ce5ce6 | aurel32 | * some parts from linux-2.6.28, arch/powerpc/include/asm/dbdma.h
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9 | 28ce5ce6 | aurel32 | *
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10 | 28ce5ce6 | aurel32 | * Definitions for using the Apple Descriptor-Based DMA controller
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11 | 28ce5ce6 | aurel32 | * in Power Macintosh computers.
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12 | 28ce5ce6 | aurel32 | *
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13 | 28ce5ce6 | aurel32 | * Copyright (C) 1996 Paul Mackerras.
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14 | 28ce5ce6 | aurel32 | *
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15 | 28ce5ce6 | aurel32 | * some parts from mol 0.9.71
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16 | 28ce5ce6 | aurel32 | *
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17 | 28ce5ce6 | aurel32 | * Descriptor based DMA emulation
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18 | 28ce5ce6 | aurel32 | *
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19 | 28ce5ce6 | aurel32 | * Copyright (C) 1998-2004 Samuel Rydh (samuel@ibrium.se)
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20 | 3cbee15b | j_mayer | *
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21 | 3cbee15b | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
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22 | 3cbee15b | j_mayer | * of this software and associated documentation files (the "Software"), to deal
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23 | 3cbee15b | j_mayer | * in the Software without restriction, including without limitation the rights
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24 | 3cbee15b | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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25 | 3cbee15b | j_mayer | * copies of the Software, and to permit persons to whom the Software is
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26 | 3cbee15b | j_mayer | * furnished to do so, subject to the following conditions:
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27 | 3cbee15b | j_mayer | *
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28 | 3cbee15b | j_mayer | * The above copyright notice and this permission notice shall be included in
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29 | 3cbee15b | j_mayer | * all copies or substantial portions of the Software.
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30 | 3cbee15b | j_mayer | *
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31 | 3cbee15b | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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32 | 3cbee15b | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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33 | 3cbee15b | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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34 | 3cbee15b | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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35 | 3cbee15b | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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36 | 3cbee15b | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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37 | 3cbee15b | j_mayer | * THE SOFTWARE.
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38 | 3cbee15b | j_mayer | */
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39 | 87ecb68b | pbrook | #include "hw.h" |
40 | 28ce5ce6 | aurel32 | #include "isa.h" |
41 | 28ce5ce6 | aurel32 | #include "mac_dbdma.h" |
42 | 3cbee15b | j_mayer | |
43 | ea026b2f | blueswir1 | /* debug DBDMA */
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44 | ea026b2f | blueswir1 | //#define DEBUG_DBDMA
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45 | ea026b2f | blueswir1 | |
46 | ea026b2f | blueswir1 | #ifdef DEBUG_DBDMA
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47 | 001faf32 | Blue Swirl | #define DBDMA_DPRINTF(fmt, ...) \
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48 | 001faf32 | Blue Swirl | do { printf("DBDMA: " fmt , ## __VA_ARGS__); } while (0) |
49 | ea026b2f | blueswir1 | #else
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50 | 001faf32 | Blue Swirl | #define DBDMA_DPRINTF(fmt, ...)
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51 | ea026b2f | blueswir1 | #endif
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52 | ea026b2f | blueswir1 | |
53 | 28ce5ce6 | aurel32 | /*
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54 | 28ce5ce6 | aurel32 | */
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55 | 28ce5ce6 | aurel32 | |
56 | 28ce5ce6 | aurel32 | /*
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57 | 28ce5ce6 | aurel32 | * DBDMA control/status registers. All little-endian.
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58 | 28ce5ce6 | aurel32 | */
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59 | 3cbee15b | j_mayer | |
60 | 28ce5ce6 | aurel32 | #define DBDMA_CONTROL 0x00 |
61 | 28ce5ce6 | aurel32 | #define DBDMA_STATUS 0x01 |
62 | 28ce5ce6 | aurel32 | #define DBDMA_CMDPTR_HI 0x02 |
63 | 28ce5ce6 | aurel32 | #define DBDMA_CMDPTR_LO 0x03 |
64 | 28ce5ce6 | aurel32 | #define DBDMA_INTR_SEL 0x04 |
65 | 28ce5ce6 | aurel32 | #define DBDMA_BRANCH_SEL 0x05 |
66 | 28ce5ce6 | aurel32 | #define DBDMA_WAIT_SEL 0x06 |
67 | 28ce5ce6 | aurel32 | #define DBDMA_XFER_MODE 0x07 |
68 | 28ce5ce6 | aurel32 | #define DBDMA_DATA2PTR_HI 0x08 |
69 | 28ce5ce6 | aurel32 | #define DBDMA_DATA2PTR_LO 0x09 |
70 | 28ce5ce6 | aurel32 | #define DBDMA_RES1 0x0A |
71 | 28ce5ce6 | aurel32 | #define DBDMA_ADDRESS_HI 0x0B |
72 | 28ce5ce6 | aurel32 | #define DBDMA_BRANCH_ADDR_HI 0x0C |
73 | 28ce5ce6 | aurel32 | #define DBDMA_RES2 0x0D |
74 | 28ce5ce6 | aurel32 | #define DBDMA_RES3 0x0E |
75 | 28ce5ce6 | aurel32 | #define DBDMA_RES4 0x0F |
76 | 28ce5ce6 | aurel32 | |
77 | 28ce5ce6 | aurel32 | #define DBDMA_REGS 16 |
78 | 28ce5ce6 | aurel32 | #define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t)) |
79 | 28ce5ce6 | aurel32 | |
80 | 28ce5ce6 | aurel32 | #define DBDMA_CHANNEL_SHIFT 7 |
81 | 28ce5ce6 | aurel32 | #define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT) |
82 | 28ce5ce6 | aurel32 | |
83 | 28ce5ce6 | aurel32 | #define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT) |
84 | 28ce5ce6 | aurel32 | |
85 | 28ce5ce6 | aurel32 | /* Bits in control and status registers */
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86 | 28ce5ce6 | aurel32 | |
87 | 28ce5ce6 | aurel32 | #define RUN 0x8000 |
88 | 28ce5ce6 | aurel32 | #define PAUSE 0x4000 |
89 | 28ce5ce6 | aurel32 | #define FLUSH 0x2000 |
90 | 28ce5ce6 | aurel32 | #define WAKE 0x1000 |
91 | 28ce5ce6 | aurel32 | #define DEAD 0x0800 |
92 | 28ce5ce6 | aurel32 | #define ACTIVE 0x0400 |
93 | 28ce5ce6 | aurel32 | #define BT 0x0100 |
94 | 28ce5ce6 | aurel32 | #define DEVSTAT 0x00ff |
95 | 28ce5ce6 | aurel32 | |
96 | 28ce5ce6 | aurel32 | /*
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97 | 28ce5ce6 | aurel32 | * DBDMA command structure. These fields are all little-endian!
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98 | 28ce5ce6 | aurel32 | */
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99 | 28ce5ce6 | aurel32 | |
100 | 28ce5ce6 | aurel32 | typedef struct dbdma_cmd { |
101 | 28ce5ce6 | aurel32 | uint16_t req_count; /* requested byte transfer count */
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102 | 28ce5ce6 | aurel32 | uint16_t command; /* command word (has bit-fields) */
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103 | 28ce5ce6 | aurel32 | uint32_t phy_addr; /* physical data address */
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104 | 28ce5ce6 | aurel32 | uint32_t cmd_dep; /* command-dependent field */
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105 | 28ce5ce6 | aurel32 | uint16_t res_count; /* residual count after completion */
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106 | 28ce5ce6 | aurel32 | uint16_t xfer_status; /* transfer status */
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107 | 28ce5ce6 | aurel32 | } dbdma_cmd; |
108 | 28ce5ce6 | aurel32 | |
109 | 28ce5ce6 | aurel32 | /* DBDMA command values in command field */
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110 | 28ce5ce6 | aurel32 | |
111 | 28ce5ce6 | aurel32 | #define COMMAND_MASK 0xf000 |
112 | 28ce5ce6 | aurel32 | #define OUTPUT_MORE 0x0000 /* transfer memory data to stream */ |
113 | 28ce5ce6 | aurel32 | #define OUTPUT_LAST 0x1000 /* ditto followed by end marker */ |
114 | 28ce5ce6 | aurel32 | #define INPUT_MORE 0x2000 /* transfer stream data to memory */ |
115 | 28ce5ce6 | aurel32 | #define INPUT_LAST 0x3000 /* ditto, expect end marker */ |
116 | 28ce5ce6 | aurel32 | #define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */ |
117 | 28ce5ce6 | aurel32 | #define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */ |
118 | 28ce5ce6 | aurel32 | #define DBDMA_NOP 0x6000 /* do nothing */ |
119 | 28ce5ce6 | aurel32 | #define DBDMA_STOP 0x7000 /* suspend processing */ |
120 | 28ce5ce6 | aurel32 | |
121 | 28ce5ce6 | aurel32 | /* Key values in command field */
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122 | 28ce5ce6 | aurel32 | |
123 | 28ce5ce6 | aurel32 | #define KEY_MASK 0x0700 |
124 | 28ce5ce6 | aurel32 | #define KEY_STREAM0 0x0000 /* usual data stream */ |
125 | 28ce5ce6 | aurel32 | #define KEY_STREAM1 0x0100 /* control/status stream */ |
126 | 28ce5ce6 | aurel32 | #define KEY_STREAM2 0x0200 /* device-dependent stream */ |
127 | 28ce5ce6 | aurel32 | #define KEY_STREAM3 0x0300 /* device-dependent stream */ |
128 | 28ce5ce6 | aurel32 | #define KEY_STREAM4 0x0400 /* reserved */ |
129 | 28ce5ce6 | aurel32 | #define KEY_REGS 0x0500 /* device register space */ |
130 | 28ce5ce6 | aurel32 | #define KEY_SYSTEM 0x0600 /* system memory-mapped space */ |
131 | 28ce5ce6 | aurel32 | #define KEY_DEVICE 0x0700 /* device memory-mapped space */ |
132 | 28ce5ce6 | aurel32 | |
133 | 28ce5ce6 | aurel32 | /* Interrupt control values in command field */
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134 | 28ce5ce6 | aurel32 | |
135 | 28ce5ce6 | aurel32 | #define INTR_MASK 0x0030 |
136 | 28ce5ce6 | aurel32 | #define INTR_NEVER 0x0000 /* don't interrupt */ |
137 | 28ce5ce6 | aurel32 | #define INTR_IFSET 0x0010 /* intr if condition bit is 1 */ |
138 | 28ce5ce6 | aurel32 | #define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */ |
139 | 28ce5ce6 | aurel32 | #define INTR_ALWAYS 0x0030 /* always interrupt */ |
140 | 28ce5ce6 | aurel32 | |
141 | 28ce5ce6 | aurel32 | /* Branch control values in command field */
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142 | 28ce5ce6 | aurel32 | |
143 | 28ce5ce6 | aurel32 | #define BR_MASK 0x000c |
144 | 28ce5ce6 | aurel32 | #define BR_NEVER 0x0000 /* don't branch */ |
145 | 28ce5ce6 | aurel32 | #define BR_IFSET 0x0004 /* branch if condition bit is 1 */ |
146 | 28ce5ce6 | aurel32 | #define BR_IFCLR 0x0008 /* branch if condition bit is 0 */ |
147 | 28ce5ce6 | aurel32 | #define BR_ALWAYS 0x000c /* always branch */ |
148 | 28ce5ce6 | aurel32 | |
149 | 28ce5ce6 | aurel32 | /* Wait control values in command field */
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150 | 28ce5ce6 | aurel32 | |
151 | 28ce5ce6 | aurel32 | #define WAIT_MASK 0x0003 |
152 | 28ce5ce6 | aurel32 | #define WAIT_NEVER 0x0000 /* don't wait */ |
153 | 28ce5ce6 | aurel32 | #define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */ |
154 | 28ce5ce6 | aurel32 | #define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */ |
155 | 28ce5ce6 | aurel32 | #define WAIT_ALWAYS 0x0003 /* always wait */ |
156 | 28ce5ce6 | aurel32 | |
157 | 28ce5ce6 | aurel32 | typedef struct DBDMA_channel { |
158 | 28ce5ce6 | aurel32 | int channel;
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159 | 28ce5ce6 | aurel32 | uint32_t regs[DBDMA_REGS]; |
160 | 28ce5ce6 | aurel32 | qemu_irq irq; |
161 | b42ec42d | aurel32 | DBDMA_io io; |
162 | b42ec42d | aurel32 | DBDMA_rw rw; |
163 | 862c9280 | aurel32 | DBDMA_flush flush; |
164 | 28ce5ce6 | aurel32 | dbdma_cmd current; |
165 | b42ec42d | aurel32 | int processing;
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166 | 28ce5ce6 | aurel32 | } DBDMA_channel; |
167 | 28ce5ce6 | aurel32 | |
168 | 28ce5ce6 | aurel32 | #ifdef DEBUG_DBDMA
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169 | 28ce5ce6 | aurel32 | static void dump_dbdma_cmd(dbdma_cmd *cmd) |
170 | 28ce5ce6 | aurel32 | { |
171 | 28ce5ce6 | aurel32 | printf("dbdma_cmd %p\n", cmd);
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172 | 28ce5ce6 | aurel32 | printf(" req_count 0x%04x\n", le16_to_cpu(cmd->req_count));
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173 | 28ce5ce6 | aurel32 | printf(" command 0x%04x\n", le16_to_cpu(cmd->command));
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174 | 28ce5ce6 | aurel32 | printf(" phy_addr 0x%08x\n", le32_to_cpu(cmd->phy_addr));
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175 | 28ce5ce6 | aurel32 | printf(" cmd_dep 0x%08x\n", le32_to_cpu(cmd->cmd_dep));
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176 | 28ce5ce6 | aurel32 | printf(" res_count 0x%04x\n", le16_to_cpu(cmd->res_count));
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177 | 28ce5ce6 | aurel32 | printf(" xfer_status 0x%04x\n", le16_to_cpu(cmd->xfer_status));
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178 | 28ce5ce6 | aurel32 | } |
179 | 28ce5ce6 | aurel32 | #else
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180 | 28ce5ce6 | aurel32 | static void dump_dbdma_cmd(dbdma_cmd *cmd) |
181 | 3cbee15b | j_mayer | { |
182 | 28ce5ce6 | aurel32 | } |
183 | 28ce5ce6 | aurel32 | #endif
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184 | 28ce5ce6 | aurel32 | static void dbdma_cmdptr_load(DBDMA_channel *ch) |
185 | 28ce5ce6 | aurel32 | { |
186 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("dbdma_cmdptr_load 0x%08x\n",
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187 | 28ce5ce6 | aurel32 | be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO])); |
188 | 28ce5ce6 | aurel32 | cpu_physical_memory_read(be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]), |
189 | 28ce5ce6 | aurel32 | (uint8_t*)&ch->current, sizeof(dbdma_cmd));
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190 | 3cbee15b | j_mayer | } |
191 | 3cbee15b | j_mayer | |
192 | 28ce5ce6 | aurel32 | static void dbdma_cmdptr_save(DBDMA_channel *ch) |
193 | 3cbee15b | j_mayer | { |
194 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("dbdma_cmdptr_save 0x%08x\n",
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195 | 28ce5ce6 | aurel32 | be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO])); |
196 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("xfer_status 0x%08x res_count 0x%04x\n",
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197 | 28ce5ce6 | aurel32 | le16_to_cpu(ch->current.xfer_status), |
198 | 28ce5ce6 | aurel32 | le16_to_cpu(ch->current.res_count)); |
199 | 28ce5ce6 | aurel32 | cpu_physical_memory_write(be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]), |
200 | 28ce5ce6 | aurel32 | (uint8_t*)&ch->current, sizeof(dbdma_cmd));
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201 | 3cbee15b | j_mayer | } |
202 | 3cbee15b | j_mayer | |
203 | 28ce5ce6 | aurel32 | static void kill_channel(DBDMA_channel *ch) |
204 | 3cbee15b | j_mayer | { |
205 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("kill_channel\n");
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206 | 28ce5ce6 | aurel32 | |
207 | 28ce5ce6 | aurel32 | ch->regs[DBDMA_STATUS] |= cpu_to_be32(DEAD); |
208 | 28ce5ce6 | aurel32 | ch->regs[DBDMA_STATUS] &= cpu_to_be32(~ACTIVE); |
209 | 28ce5ce6 | aurel32 | |
210 | 28ce5ce6 | aurel32 | qemu_irq_raise(ch->irq); |
211 | 28ce5ce6 | aurel32 | } |
212 | 28ce5ce6 | aurel32 | |
213 | 28ce5ce6 | aurel32 | static void conditional_interrupt(DBDMA_channel *ch) |
214 | 28ce5ce6 | aurel32 | { |
215 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
216 | 28ce5ce6 | aurel32 | uint16_t intr; |
217 | 28ce5ce6 | aurel32 | uint16_t sel_mask, sel_value; |
218 | 28ce5ce6 | aurel32 | uint32_t status; |
219 | 28ce5ce6 | aurel32 | int cond;
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220 | 28ce5ce6 | aurel32 | |
221 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("conditional_interrupt\n");
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222 | 28ce5ce6 | aurel32 | |
223 | b42ec42d | aurel32 | intr = le16_to_cpu(current->command) & INTR_MASK; |
224 | 28ce5ce6 | aurel32 | |
225 | 28ce5ce6 | aurel32 | switch(intr) {
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226 | 28ce5ce6 | aurel32 | case INTR_NEVER: /* don't interrupt */ |
227 | 28ce5ce6 | aurel32 | return;
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228 | 28ce5ce6 | aurel32 | case INTR_ALWAYS: /* always interrupt */ |
229 | 28ce5ce6 | aurel32 | qemu_irq_raise(ch->irq); |
230 | 28ce5ce6 | aurel32 | return;
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231 | 28ce5ce6 | aurel32 | } |
232 | 28ce5ce6 | aurel32 | |
233 | 28ce5ce6 | aurel32 | status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT; |
234 | 28ce5ce6 | aurel32 | |
235 | 28ce5ce6 | aurel32 | sel_mask = (be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) >> 16) & 0x0f; |
236 | 28ce5ce6 | aurel32 | sel_value = be32_to_cpu(ch->regs[DBDMA_INTR_SEL]) & 0x0f;
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237 | 28ce5ce6 | aurel32 | |
238 | 28ce5ce6 | aurel32 | cond = (status & sel_mask) == (sel_value & sel_mask); |
239 | 28ce5ce6 | aurel32 | |
240 | 28ce5ce6 | aurel32 | switch(intr) {
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241 | 28ce5ce6 | aurel32 | case INTR_IFSET: /* intr if condition bit is 1 */ |
242 | 28ce5ce6 | aurel32 | if (cond)
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243 | 28ce5ce6 | aurel32 | qemu_irq_raise(ch->irq); |
244 | 28ce5ce6 | aurel32 | return;
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245 | 28ce5ce6 | aurel32 | case INTR_IFCLR: /* intr if condition bit is 0 */ |
246 | 28ce5ce6 | aurel32 | if (!cond)
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247 | 28ce5ce6 | aurel32 | qemu_irq_raise(ch->irq); |
248 | 28ce5ce6 | aurel32 | return;
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249 | 28ce5ce6 | aurel32 | } |
250 | 28ce5ce6 | aurel32 | } |
251 | 28ce5ce6 | aurel32 | |
252 | 28ce5ce6 | aurel32 | static int conditional_wait(DBDMA_channel *ch) |
253 | 28ce5ce6 | aurel32 | { |
254 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
255 | 28ce5ce6 | aurel32 | uint16_t wait; |
256 | 28ce5ce6 | aurel32 | uint16_t sel_mask, sel_value; |
257 | 28ce5ce6 | aurel32 | uint32_t status; |
258 | 28ce5ce6 | aurel32 | int cond;
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259 | 28ce5ce6 | aurel32 | |
260 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("conditional_wait\n");
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261 | 28ce5ce6 | aurel32 | |
262 | b42ec42d | aurel32 | wait = le16_to_cpu(current->command) & WAIT_MASK; |
263 | 28ce5ce6 | aurel32 | |
264 | 28ce5ce6 | aurel32 | switch(wait) {
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265 | 28ce5ce6 | aurel32 | case WAIT_NEVER: /* don't wait */ |
266 | 28ce5ce6 | aurel32 | return 0; |
267 | 28ce5ce6 | aurel32 | case WAIT_ALWAYS: /* always wait */ |
268 | 28ce5ce6 | aurel32 | return 1; |
269 | 28ce5ce6 | aurel32 | } |
270 | 28ce5ce6 | aurel32 | |
271 | 28ce5ce6 | aurel32 | status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT; |
272 | 28ce5ce6 | aurel32 | |
273 | 28ce5ce6 | aurel32 | sel_mask = (be32_to_cpu(ch->regs[DBDMA_WAIT_SEL]) >> 16) & 0x0f; |
274 | 28ce5ce6 | aurel32 | sel_value = be32_to_cpu(ch->regs[DBDMA_WAIT_SEL]) & 0x0f;
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275 | 28ce5ce6 | aurel32 | |
276 | 28ce5ce6 | aurel32 | cond = (status & sel_mask) == (sel_value & sel_mask); |
277 | 28ce5ce6 | aurel32 | |
278 | 28ce5ce6 | aurel32 | switch(wait) {
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279 | 28ce5ce6 | aurel32 | case WAIT_IFSET: /* wait if condition bit is 1 */ |
280 | 28ce5ce6 | aurel32 | if (cond)
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281 | 28ce5ce6 | aurel32 | return 1; |
282 | 28ce5ce6 | aurel32 | return 0; |
283 | 28ce5ce6 | aurel32 | case WAIT_IFCLR: /* wait if condition bit is 0 */ |
284 | 28ce5ce6 | aurel32 | if (!cond)
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285 | 28ce5ce6 | aurel32 | return 1; |
286 | 28ce5ce6 | aurel32 | return 0; |
287 | 28ce5ce6 | aurel32 | } |
288 | 28ce5ce6 | aurel32 | return 0; |
289 | 28ce5ce6 | aurel32 | } |
290 | 28ce5ce6 | aurel32 | |
291 | 28ce5ce6 | aurel32 | static void next(DBDMA_channel *ch) |
292 | 28ce5ce6 | aurel32 | { |
293 | 28ce5ce6 | aurel32 | uint32_t cp; |
294 | 28ce5ce6 | aurel32 | |
295 | 28ce5ce6 | aurel32 | ch->regs[DBDMA_STATUS] &= cpu_to_be32(~BT); |
296 | 28ce5ce6 | aurel32 | |
297 | 28ce5ce6 | aurel32 | cp = be32_to_cpu(ch->regs[DBDMA_CMDPTR_LO]); |
298 | 28ce5ce6 | aurel32 | ch->regs[DBDMA_CMDPTR_LO] = cpu_to_be32(cp + sizeof(dbdma_cmd));
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299 | 28ce5ce6 | aurel32 | dbdma_cmdptr_load(ch); |
300 | 28ce5ce6 | aurel32 | } |
301 | 28ce5ce6 | aurel32 | |
302 | 28ce5ce6 | aurel32 | static void branch(DBDMA_channel *ch) |
303 | 28ce5ce6 | aurel32 | { |
304 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
305 | 28ce5ce6 | aurel32 | |
306 | 28ce5ce6 | aurel32 | ch->regs[DBDMA_CMDPTR_LO] = current->cmd_dep; |
307 | 28ce5ce6 | aurel32 | ch->regs[DBDMA_STATUS] |= cpu_to_be32(BT); |
308 | 28ce5ce6 | aurel32 | dbdma_cmdptr_load(ch); |
309 | 28ce5ce6 | aurel32 | } |
310 | 28ce5ce6 | aurel32 | |
311 | 28ce5ce6 | aurel32 | static void conditional_branch(DBDMA_channel *ch) |
312 | 28ce5ce6 | aurel32 | { |
313 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
314 | 28ce5ce6 | aurel32 | uint16_t br; |
315 | 28ce5ce6 | aurel32 | uint16_t sel_mask, sel_value; |
316 | 28ce5ce6 | aurel32 | uint32_t status; |
317 | 28ce5ce6 | aurel32 | int cond;
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318 | 28ce5ce6 | aurel32 | |
319 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("conditional_branch\n");
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320 | 28ce5ce6 | aurel32 | |
321 | 28ce5ce6 | aurel32 | /* check if we must branch */
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322 | 28ce5ce6 | aurel32 | |
323 | b42ec42d | aurel32 | br = le16_to_cpu(current->command) & BR_MASK; |
324 | 28ce5ce6 | aurel32 | |
325 | 28ce5ce6 | aurel32 | switch(br) {
|
326 | 28ce5ce6 | aurel32 | case BR_NEVER: /* don't branch */ |
327 | 28ce5ce6 | aurel32 | next(ch); |
328 | 28ce5ce6 | aurel32 | return;
|
329 | 28ce5ce6 | aurel32 | case BR_ALWAYS: /* always branch */ |
330 | 28ce5ce6 | aurel32 | branch(ch); |
331 | 28ce5ce6 | aurel32 | return;
|
332 | 28ce5ce6 | aurel32 | } |
333 | 28ce5ce6 | aurel32 | |
334 | 28ce5ce6 | aurel32 | status = be32_to_cpu(ch->regs[DBDMA_STATUS]) & DEVSTAT; |
335 | 28ce5ce6 | aurel32 | |
336 | 28ce5ce6 | aurel32 | sel_mask = (be32_to_cpu(ch->regs[DBDMA_BRANCH_SEL]) >> 16) & 0x0f; |
337 | 28ce5ce6 | aurel32 | sel_value = be32_to_cpu(ch->regs[DBDMA_BRANCH_SEL]) & 0x0f;
|
338 | 28ce5ce6 | aurel32 | |
339 | 28ce5ce6 | aurel32 | cond = (status & sel_mask) == (sel_value & sel_mask); |
340 | 28ce5ce6 | aurel32 | |
341 | 28ce5ce6 | aurel32 | switch(br) {
|
342 | 28ce5ce6 | aurel32 | case BR_IFSET: /* branch if condition bit is 1 */ |
343 | 28ce5ce6 | aurel32 | if (cond)
|
344 | 28ce5ce6 | aurel32 | branch(ch); |
345 | 28ce5ce6 | aurel32 | else
|
346 | 28ce5ce6 | aurel32 | next(ch); |
347 | 28ce5ce6 | aurel32 | return;
|
348 | 28ce5ce6 | aurel32 | case BR_IFCLR: /* branch if condition bit is 0 */ |
349 | 28ce5ce6 | aurel32 | if (!cond)
|
350 | 28ce5ce6 | aurel32 | branch(ch); |
351 | 28ce5ce6 | aurel32 | else
|
352 | 28ce5ce6 | aurel32 | next(ch); |
353 | 28ce5ce6 | aurel32 | return;
|
354 | 28ce5ce6 | aurel32 | } |
355 | 28ce5ce6 | aurel32 | } |
356 | 28ce5ce6 | aurel32 | |
357 | b42ec42d | aurel32 | static QEMUBH *dbdma_bh;
|
358 | b42ec42d | aurel32 | static void channel_run(DBDMA_channel *ch); |
359 | 28ce5ce6 | aurel32 | |
360 | b42ec42d | aurel32 | static void dbdma_end(DBDMA_io *io) |
361 | 28ce5ce6 | aurel32 | { |
362 | 28ce5ce6 | aurel32 | DBDMA_channel *ch = io->channel; |
363 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
364 | 28ce5ce6 | aurel32 | |
365 | b42ec42d | aurel32 | if (conditional_wait(ch))
|
366 | b42ec42d | aurel32 | goto wait;
|
367 | 28ce5ce6 | aurel32 | |
368 | b42ec42d | aurel32 | current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS])); |
369 | b42ec42d | aurel32 | current->res_count = cpu_to_le16(be32_to_cpu(io->len)); |
370 | b42ec42d | aurel32 | dbdma_cmdptr_save(ch); |
371 | 862c9280 | aurel32 | if (io->is_last)
|
372 | 862c9280 | aurel32 | ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH); |
373 | b42ec42d | aurel32 | |
374 | b42ec42d | aurel32 | conditional_interrupt(ch); |
375 | b42ec42d | aurel32 | conditional_branch(ch); |
376 | 28ce5ce6 | aurel32 | |
377 | b42ec42d | aurel32 | wait:
|
378 | b42ec42d | aurel32 | ch->processing = 0;
|
379 | b42ec42d | aurel32 | if ((ch->regs[DBDMA_STATUS] & cpu_to_be32(RUN)) &&
|
380 | b42ec42d | aurel32 | (ch->regs[DBDMA_STATUS] & cpu_to_be32(ACTIVE))) |
381 | b42ec42d | aurel32 | channel_run(ch); |
382 | 28ce5ce6 | aurel32 | } |
383 | 28ce5ce6 | aurel32 | |
384 | b42ec42d | aurel32 | static void start_output(DBDMA_channel *ch, int key, uint32_t addr, |
385 | 28ce5ce6 | aurel32 | uint16_t req_count, int is_last)
|
386 | 28ce5ce6 | aurel32 | { |
387 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("start_output\n");
|
388 | 28ce5ce6 | aurel32 | |
389 | 28ce5ce6 | aurel32 | /* KEY_REGS, KEY_DEVICE and KEY_STREAM
|
390 | 28ce5ce6 | aurel32 | * are not implemented in the mac-io chip
|
391 | 28ce5ce6 | aurel32 | */
|
392 | 28ce5ce6 | aurel32 | |
393 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("addr 0x%x key 0x%x\n", addr, key);
|
394 | 28ce5ce6 | aurel32 | if (!addr || key > KEY_STREAM3) {
|
395 | 28ce5ce6 | aurel32 | kill_channel(ch); |
396 | b42ec42d | aurel32 | return;
|
397 | 28ce5ce6 | aurel32 | } |
398 | 28ce5ce6 | aurel32 | |
399 | b42ec42d | aurel32 | ch->io.addr = addr; |
400 | 28ce5ce6 | aurel32 | ch->io.len = req_count; |
401 | 28ce5ce6 | aurel32 | ch->io.is_last = is_last; |
402 | b42ec42d | aurel32 | ch->io.dma_end = dbdma_end; |
403 | b42ec42d | aurel32 | ch->io.is_dma_out = 1;
|
404 | b42ec42d | aurel32 | ch->processing = 1;
|
405 | b42ec42d | aurel32 | ch->rw(&ch->io); |
406 | 28ce5ce6 | aurel32 | } |
407 | 28ce5ce6 | aurel32 | |
408 | b42ec42d | aurel32 | static void start_input(DBDMA_channel *ch, int key, uint32_t addr, |
409 | 28ce5ce6 | aurel32 | uint16_t req_count, int is_last)
|
410 | 28ce5ce6 | aurel32 | { |
411 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("start_input\n");
|
412 | 28ce5ce6 | aurel32 | |
413 | 28ce5ce6 | aurel32 | /* KEY_REGS, KEY_DEVICE and KEY_STREAM
|
414 | 28ce5ce6 | aurel32 | * are not implemented in the mac-io chip
|
415 | 28ce5ce6 | aurel32 | */
|
416 | 28ce5ce6 | aurel32 | |
417 | 28ce5ce6 | aurel32 | if (!addr || key > KEY_STREAM3) {
|
418 | 28ce5ce6 | aurel32 | kill_channel(ch); |
419 | b42ec42d | aurel32 | return;
|
420 | 28ce5ce6 | aurel32 | } |
421 | 28ce5ce6 | aurel32 | |
422 | b42ec42d | aurel32 | ch->io.addr = addr; |
423 | 28ce5ce6 | aurel32 | ch->io.len = req_count; |
424 | 28ce5ce6 | aurel32 | ch->io.is_last = is_last; |
425 | b42ec42d | aurel32 | ch->io.dma_end = dbdma_end; |
426 | b42ec42d | aurel32 | ch->io.is_dma_out = 0;
|
427 | b42ec42d | aurel32 | ch->processing = 1;
|
428 | b42ec42d | aurel32 | ch->rw(&ch->io); |
429 | 28ce5ce6 | aurel32 | } |
430 | 28ce5ce6 | aurel32 | |
431 | b42ec42d | aurel32 | static void load_word(DBDMA_channel *ch, int key, uint32_t addr, |
432 | 28ce5ce6 | aurel32 | uint16_t len) |
433 | 28ce5ce6 | aurel32 | { |
434 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
435 | 28ce5ce6 | aurel32 | uint32_t val; |
436 | 28ce5ce6 | aurel32 | |
437 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("load_word\n");
|
438 | 28ce5ce6 | aurel32 | |
439 | 28ce5ce6 | aurel32 | /* only implements KEY_SYSTEM */
|
440 | 28ce5ce6 | aurel32 | |
441 | 28ce5ce6 | aurel32 | if (key != KEY_SYSTEM) {
|
442 | 28ce5ce6 | aurel32 | printf("DBDMA: LOAD_WORD, unimplemented key %x\n", key);
|
443 | 28ce5ce6 | aurel32 | kill_channel(ch); |
444 | b42ec42d | aurel32 | return;
|
445 | 28ce5ce6 | aurel32 | } |
446 | 28ce5ce6 | aurel32 | |
447 | 28ce5ce6 | aurel32 | cpu_physical_memory_read(addr, (uint8_t*)&val, len); |
448 | 28ce5ce6 | aurel32 | |
449 | 28ce5ce6 | aurel32 | if (len == 2) |
450 | 28ce5ce6 | aurel32 | val = (val << 16) | (current->cmd_dep & 0x0000ffff); |
451 | 28ce5ce6 | aurel32 | else if (len == 1) |
452 | 28ce5ce6 | aurel32 | val = (val << 24) | (current->cmd_dep & 0x00ffffff); |
453 | 28ce5ce6 | aurel32 | |
454 | 28ce5ce6 | aurel32 | current->cmd_dep = val; |
455 | 28ce5ce6 | aurel32 | |
456 | 28ce5ce6 | aurel32 | if (conditional_wait(ch))
|
457 | b42ec42d | aurel32 | goto wait;
|
458 | 28ce5ce6 | aurel32 | |
459 | 28ce5ce6 | aurel32 | current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS])); |
460 | 28ce5ce6 | aurel32 | dbdma_cmdptr_save(ch); |
461 | b42ec42d | aurel32 | ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH); |
462 | 28ce5ce6 | aurel32 | |
463 | 28ce5ce6 | aurel32 | conditional_interrupt(ch); |
464 | 28ce5ce6 | aurel32 | next(ch); |
465 | 28ce5ce6 | aurel32 | |
466 | b42ec42d | aurel32 | wait:
|
467 | b42ec42d | aurel32 | qemu_bh_schedule(dbdma_bh); |
468 | 28ce5ce6 | aurel32 | } |
469 | 28ce5ce6 | aurel32 | |
470 | b42ec42d | aurel32 | static void store_word(DBDMA_channel *ch, int key, uint32_t addr, |
471 | 28ce5ce6 | aurel32 | uint16_t len) |
472 | 28ce5ce6 | aurel32 | { |
473 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
474 | 28ce5ce6 | aurel32 | uint32_t val; |
475 | 28ce5ce6 | aurel32 | |
476 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("store_word\n");
|
477 | 28ce5ce6 | aurel32 | |
478 | 28ce5ce6 | aurel32 | /* only implements KEY_SYSTEM */
|
479 | 28ce5ce6 | aurel32 | |
480 | 28ce5ce6 | aurel32 | if (key != KEY_SYSTEM) {
|
481 | 28ce5ce6 | aurel32 | printf("DBDMA: STORE_WORD, unimplemented key %x\n", key);
|
482 | 28ce5ce6 | aurel32 | kill_channel(ch); |
483 | b42ec42d | aurel32 | return;
|
484 | 28ce5ce6 | aurel32 | } |
485 | 28ce5ce6 | aurel32 | |
486 | 28ce5ce6 | aurel32 | val = current->cmd_dep; |
487 | 28ce5ce6 | aurel32 | if (len == 2) |
488 | 28ce5ce6 | aurel32 | val >>= 16;
|
489 | 28ce5ce6 | aurel32 | else if (len == 1) |
490 | 28ce5ce6 | aurel32 | val >>= 24;
|
491 | 28ce5ce6 | aurel32 | |
492 | 28ce5ce6 | aurel32 | cpu_physical_memory_write(addr, (uint8_t*)&val, len); |
493 | 28ce5ce6 | aurel32 | |
494 | 28ce5ce6 | aurel32 | if (conditional_wait(ch))
|
495 | b42ec42d | aurel32 | goto wait;
|
496 | 28ce5ce6 | aurel32 | |
497 | 28ce5ce6 | aurel32 | current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS])); |
498 | 28ce5ce6 | aurel32 | dbdma_cmdptr_save(ch); |
499 | b42ec42d | aurel32 | ch->regs[DBDMA_STATUS] &= cpu_to_be32(~FLUSH); |
500 | 28ce5ce6 | aurel32 | |
501 | 28ce5ce6 | aurel32 | conditional_interrupt(ch); |
502 | 28ce5ce6 | aurel32 | next(ch); |
503 | 28ce5ce6 | aurel32 | |
504 | b42ec42d | aurel32 | wait:
|
505 | b42ec42d | aurel32 | qemu_bh_schedule(dbdma_bh); |
506 | 28ce5ce6 | aurel32 | } |
507 | 28ce5ce6 | aurel32 | |
508 | b42ec42d | aurel32 | static void nop(DBDMA_channel *ch) |
509 | 28ce5ce6 | aurel32 | { |
510 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
511 | 28ce5ce6 | aurel32 | |
512 | 28ce5ce6 | aurel32 | if (conditional_wait(ch))
|
513 | b42ec42d | aurel32 | goto wait;
|
514 | 28ce5ce6 | aurel32 | |
515 | 28ce5ce6 | aurel32 | current->xfer_status = cpu_to_le16(be32_to_cpu(ch->regs[DBDMA_STATUS])); |
516 | 28ce5ce6 | aurel32 | dbdma_cmdptr_save(ch); |
517 | 28ce5ce6 | aurel32 | |
518 | 28ce5ce6 | aurel32 | conditional_interrupt(ch); |
519 | 28ce5ce6 | aurel32 | conditional_branch(ch); |
520 | 28ce5ce6 | aurel32 | |
521 | b42ec42d | aurel32 | wait:
|
522 | b42ec42d | aurel32 | qemu_bh_schedule(dbdma_bh); |
523 | 3cbee15b | j_mayer | } |
524 | 3cbee15b | j_mayer | |
525 | b42ec42d | aurel32 | static void stop(DBDMA_channel *ch) |
526 | 3cbee15b | j_mayer | { |
527 | b42ec42d | aurel32 | ch->regs[DBDMA_STATUS] &= cpu_to_be32(~(ACTIVE|DEAD|FLUSH)); |
528 | 28ce5ce6 | aurel32 | |
529 | 28ce5ce6 | aurel32 | /* the stop command does not increment command pointer */
|
530 | 3cbee15b | j_mayer | } |
531 | 3cbee15b | j_mayer | |
532 | b42ec42d | aurel32 | static void channel_run(DBDMA_channel *ch) |
533 | 3cbee15b | j_mayer | { |
534 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
535 | 28ce5ce6 | aurel32 | uint16_t cmd, key; |
536 | 28ce5ce6 | aurel32 | uint16_t req_count; |
537 | 28ce5ce6 | aurel32 | uint32_t phy_addr; |
538 | 28ce5ce6 | aurel32 | |
539 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("channel_run\n");
|
540 | 28ce5ce6 | aurel32 | dump_dbdma_cmd(current); |
541 | 28ce5ce6 | aurel32 | |
542 | 28ce5ce6 | aurel32 | /* clear WAKE flag at command fetch */
|
543 | 28ce5ce6 | aurel32 | |
544 | 28ce5ce6 | aurel32 | ch->regs[DBDMA_STATUS] &= cpu_to_be32(~WAKE); |
545 | 28ce5ce6 | aurel32 | |
546 | 28ce5ce6 | aurel32 | cmd = le16_to_cpu(current->command) & COMMAND_MASK; |
547 | 28ce5ce6 | aurel32 | |
548 | 28ce5ce6 | aurel32 | switch (cmd) {
|
549 | 28ce5ce6 | aurel32 | case DBDMA_NOP:
|
550 | b42ec42d | aurel32 | nop(ch); |
551 | b42ec42d | aurel32 | return;
|
552 | 28ce5ce6 | aurel32 | |
553 | 28ce5ce6 | aurel32 | case DBDMA_STOP:
|
554 | b42ec42d | aurel32 | stop(ch); |
555 | b42ec42d | aurel32 | return;
|
556 | 28ce5ce6 | aurel32 | } |
557 | 28ce5ce6 | aurel32 | |
558 | 28ce5ce6 | aurel32 | key = le16_to_cpu(current->command) & 0x0700;
|
559 | 28ce5ce6 | aurel32 | req_count = le16_to_cpu(current->req_count); |
560 | 28ce5ce6 | aurel32 | phy_addr = le32_to_cpu(current->phy_addr); |
561 | 28ce5ce6 | aurel32 | |
562 | 28ce5ce6 | aurel32 | if (key == KEY_STREAM4) {
|
563 | 28ce5ce6 | aurel32 | printf("command %x, invalid key 4\n", cmd);
|
564 | 28ce5ce6 | aurel32 | kill_channel(ch); |
565 | b42ec42d | aurel32 | return;
|
566 | 28ce5ce6 | aurel32 | } |
567 | 28ce5ce6 | aurel32 | |
568 | 28ce5ce6 | aurel32 | switch (cmd) {
|
569 | 28ce5ce6 | aurel32 | case OUTPUT_MORE:
|
570 | b42ec42d | aurel32 | start_output(ch, key, phy_addr, req_count, 0);
|
571 | b42ec42d | aurel32 | return;
|
572 | 28ce5ce6 | aurel32 | |
573 | 28ce5ce6 | aurel32 | case OUTPUT_LAST:
|
574 | b42ec42d | aurel32 | start_output(ch, key, phy_addr, req_count, 1);
|
575 | b42ec42d | aurel32 | return;
|
576 | 28ce5ce6 | aurel32 | |
577 | 28ce5ce6 | aurel32 | case INPUT_MORE:
|
578 | b42ec42d | aurel32 | start_input(ch, key, phy_addr, req_count, 0);
|
579 | b42ec42d | aurel32 | return;
|
580 | 28ce5ce6 | aurel32 | |
581 | 28ce5ce6 | aurel32 | case INPUT_LAST:
|
582 | b42ec42d | aurel32 | start_input(ch, key, phy_addr, req_count, 1);
|
583 | b42ec42d | aurel32 | return;
|
584 | 28ce5ce6 | aurel32 | } |
585 | 28ce5ce6 | aurel32 | |
586 | 28ce5ce6 | aurel32 | if (key < KEY_REGS) {
|
587 | 28ce5ce6 | aurel32 | printf("command %x, invalid key %x\n", cmd, key);
|
588 | 28ce5ce6 | aurel32 | key = KEY_SYSTEM; |
589 | 28ce5ce6 | aurel32 | } |
590 | 28ce5ce6 | aurel32 | |
591 | 28ce5ce6 | aurel32 | /* for LOAD_WORD and STORE_WORD, req_count is on 3 bits
|
592 | 28ce5ce6 | aurel32 | * and BRANCH is invalid
|
593 | 28ce5ce6 | aurel32 | */
|
594 | 28ce5ce6 | aurel32 | |
595 | 28ce5ce6 | aurel32 | req_count = req_count & 0x0007;
|
596 | 28ce5ce6 | aurel32 | if (req_count & 0x4) { |
597 | 28ce5ce6 | aurel32 | req_count = 4;
|
598 | 28ce5ce6 | aurel32 | phy_addr &= ~3;
|
599 | 28ce5ce6 | aurel32 | } else if (req_count & 0x2) { |
600 | 28ce5ce6 | aurel32 | req_count = 2;
|
601 | 28ce5ce6 | aurel32 | phy_addr &= ~1;
|
602 | 28ce5ce6 | aurel32 | } else
|
603 | 28ce5ce6 | aurel32 | req_count = 1;
|
604 | 28ce5ce6 | aurel32 | |
605 | 28ce5ce6 | aurel32 | switch (cmd) {
|
606 | 28ce5ce6 | aurel32 | case LOAD_WORD:
|
607 | b42ec42d | aurel32 | load_word(ch, key, phy_addr, req_count); |
608 | b42ec42d | aurel32 | return;
|
609 | 28ce5ce6 | aurel32 | |
610 | 28ce5ce6 | aurel32 | case STORE_WORD:
|
611 | b42ec42d | aurel32 | store_word(ch, key, phy_addr, req_count); |
612 | b42ec42d | aurel32 | return;
|
613 | 28ce5ce6 | aurel32 | } |
614 | 3cbee15b | j_mayer | } |
615 | 3cbee15b | j_mayer | |
616 | 28ce5ce6 | aurel32 | static void DBDMA_run (DBDMA_channel *ch) |
617 | 28ce5ce6 | aurel32 | { |
618 | 28ce5ce6 | aurel32 | int channel;
|
619 | 28ce5ce6 | aurel32 | |
620 | 28ce5ce6 | aurel32 | for (channel = 0; channel < DBDMA_CHANNELS; channel++, ch++) { |
621 | 28ce5ce6 | aurel32 | uint32_t status = be32_to_cpu(ch->regs[DBDMA_STATUS]); |
622 | b42ec42d | aurel32 | if (!ch->processing && (status & RUN) && (status & ACTIVE))
|
623 | b42ec42d | aurel32 | channel_run(ch); |
624 | 28ce5ce6 | aurel32 | } |
625 | 28ce5ce6 | aurel32 | } |
626 | 28ce5ce6 | aurel32 | |
627 | 28ce5ce6 | aurel32 | static void DBDMA_run_bh(void *opaque) |
628 | 28ce5ce6 | aurel32 | { |
629 | 28ce5ce6 | aurel32 | DBDMA_channel *ch = opaque; |
630 | 28ce5ce6 | aurel32 | |
631 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("DBDMA_run_bh\n");
|
632 | 28ce5ce6 | aurel32 | |
633 | 28ce5ce6 | aurel32 | DBDMA_run(ch); |
634 | 28ce5ce6 | aurel32 | } |
635 | 28ce5ce6 | aurel32 | |
636 | 28ce5ce6 | aurel32 | void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq, |
637 | 862c9280 | aurel32 | DBDMA_rw rw, DBDMA_flush flush, |
638 | 28ce5ce6 | aurel32 | void *opaque)
|
639 | 28ce5ce6 | aurel32 | { |
640 | 28ce5ce6 | aurel32 | DBDMA_channel *ch = ( DBDMA_channel *)dbdma + nchan; |
641 | 28ce5ce6 | aurel32 | |
642 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("DBDMA_register_channel 0x%x\n", nchan);
|
643 | 28ce5ce6 | aurel32 | |
644 | 28ce5ce6 | aurel32 | ch->irq = irq; |
645 | 28ce5ce6 | aurel32 | ch->channel = nchan; |
646 | b42ec42d | aurel32 | ch->rw = rw; |
647 | 862c9280 | aurel32 | ch->flush = flush; |
648 | 28ce5ce6 | aurel32 | ch->io.opaque = opaque; |
649 | 28ce5ce6 | aurel32 | ch->io.channel = ch; |
650 | 28ce5ce6 | aurel32 | } |
651 | 28ce5ce6 | aurel32 | |
652 | 28ce5ce6 | aurel32 | void DBDMA_schedule(void) |
653 | 28ce5ce6 | aurel32 | { |
654 | d9f75a4e | aliguori | qemu_notify_event(); |
655 | 28ce5ce6 | aurel32 | } |
656 | 28ce5ce6 | aurel32 | |
657 | 28ce5ce6 | aurel32 | static void |
658 | 28ce5ce6 | aurel32 | dbdma_control_write(DBDMA_channel *ch) |
659 | 28ce5ce6 | aurel32 | { |
660 | 28ce5ce6 | aurel32 | uint16_t mask, value; |
661 | 28ce5ce6 | aurel32 | uint32_t status; |
662 | 28ce5ce6 | aurel32 | |
663 | 28ce5ce6 | aurel32 | mask = (be32_to_cpu(ch->regs[DBDMA_CONTROL]) >> 16) & 0xffff; |
664 | 28ce5ce6 | aurel32 | value = be32_to_cpu(ch->regs[DBDMA_CONTROL]) & 0xffff;
|
665 | 28ce5ce6 | aurel32 | |
666 | 28ce5ce6 | aurel32 | value &= (RUN | PAUSE | FLUSH | WAKE | DEVSTAT); |
667 | 28ce5ce6 | aurel32 | |
668 | 28ce5ce6 | aurel32 | status = be32_to_cpu(ch->regs[DBDMA_STATUS]); |
669 | 28ce5ce6 | aurel32 | |
670 | 28ce5ce6 | aurel32 | status = (value & mask) | (status & ~mask); |
671 | 28ce5ce6 | aurel32 | |
672 | 28ce5ce6 | aurel32 | if (status & WAKE)
|
673 | 28ce5ce6 | aurel32 | status |= ACTIVE; |
674 | 28ce5ce6 | aurel32 | if (status & RUN) {
|
675 | 28ce5ce6 | aurel32 | status |= ACTIVE; |
676 | 28ce5ce6 | aurel32 | status &= ~DEAD; |
677 | 28ce5ce6 | aurel32 | } |
678 | 28ce5ce6 | aurel32 | if (status & PAUSE)
|
679 | 28ce5ce6 | aurel32 | status &= ~ACTIVE; |
680 | 28ce5ce6 | aurel32 | if ((be32_to_cpu(ch->regs[DBDMA_STATUS]) & RUN) && !(status & RUN)) {
|
681 | 28ce5ce6 | aurel32 | /* RUN is cleared */
|
682 | 28ce5ce6 | aurel32 | status &= ~(ACTIVE|DEAD); |
683 | 28ce5ce6 | aurel32 | } |
684 | 28ce5ce6 | aurel32 | |
685 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF(" status 0x%08x\n", status);
|
686 | 28ce5ce6 | aurel32 | |
687 | 28ce5ce6 | aurel32 | ch->regs[DBDMA_STATUS] = cpu_to_be32(status); |
688 | 28ce5ce6 | aurel32 | |
689 | b42ec42d | aurel32 | if (status & ACTIVE)
|
690 | b42ec42d | aurel32 | qemu_bh_schedule(dbdma_bh); |
691 | 862c9280 | aurel32 | if (status & FLUSH)
|
692 | 862c9280 | aurel32 | ch->flush(&ch->io); |
693 | 28ce5ce6 | aurel32 | } |
694 | 28ce5ce6 | aurel32 | |
695 | 28ce5ce6 | aurel32 | static void dbdma_writel (void *opaque, |
696 | 28ce5ce6 | aurel32 | target_phys_addr_t addr, uint32_t value) |
697 | 28ce5ce6 | aurel32 | { |
698 | 28ce5ce6 | aurel32 | int channel = addr >> DBDMA_CHANNEL_SHIFT;
|
699 | 28ce5ce6 | aurel32 | DBDMA_channel *ch = (DBDMA_channel *)opaque + channel; |
700 | 28ce5ce6 | aurel32 | int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2; |
701 | 28ce5ce6 | aurel32 | |
702 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value); |
703 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
|
704 | 28ce5ce6 | aurel32 | (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); |
705 | 28ce5ce6 | aurel32 | |
706 | 28ce5ce6 | aurel32 | /* cmdptr cannot be modified if channel is RUN or ACTIVE */
|
707 | 28ce5ce6 | aurel32 | |
708 | 28ce5ce6 | aurel32 | if (reg == DBDMA_CMDPTR_LO &&
|
709 | 28ce5ce6 | aurel32 | (ch->regs[DBDMA_STATUS] & cpu_to_be32(RUN | ACTIVE))) |
710 | 28ce5ce6 | aurel32 | return;
|
711 | 28ce5ce6 | aurel32 | |
712 | 28ce5ce6 | aurel32 | ch->regs[reg] = value; |
713 | 28ce5ce6 | aurel32 | |
714 | 28ce5ce6 | aurel32 | switch(reg) {
|
715 | 28ce5ce6 | aurel32 | case DBDMA_CONTROL:
|
716 | 28ce5ce6 | aurel32 | dbdma_control_write(ch); |
717 | 28ce5ce6 | aurel32 | break;
|
718 | 28ce5ce6 | aurel32 | case DBDMA_CMDPTR_LO:
|
719 | 28ce5ce6 | aurel32 | /* 16-byte aligned */
|
720 | 28ce5ce6 | aurel32 | ch->regs[DBDMA_CMDPTR_LO] &= cpu_to_be32(~0xf);
|
721 | 28ce5ce6 | aurel32 | dbdma_cmdptr_load(ch); |
722 | 28ce5ce6 | aurel32 | break;
|
723 | 28ce5ce6 | aurel32 | case DBDMA_STATUS:
|
724 | 28ce5ce6 | aurel32 | case DBDMA_INTR_SEL:
|
725 | 28ce5ce6 | aurel32 | case DBDMA_BRANCH_SEL:
|
726 | 28ce5ce6 | aurel32 | case DBDMA_WAIT_SEL:
|
727 | 28ce5ce6 | aurel32 | /* nothing to do */
|
728 | 28ce5ce6 | aurel32 | break;
|
729 | 28ce5ce6 | aurel32 | case DBDMA_XFER_MODE:
|
730 | 28ce5ce6 | aurel32 | case DBDMA_CMDPTR_HI:
|
731 | 28ce5ce6 | aurel32 | case DBDMA_DATA2PTR_HI:
|
732 | 28ce5ce6 | aurel32 | case DBDMA_DATA2PTR_LO:
|
733 | 28ce5ce6 | aurel32 | case DBDMA_ADDRESS_HI:
|
734 | 28ce5ce6 | aurel32 | case DBDMA_BRANCH_ADDR_HI:
|
735 | 28ce5ce6 | aurel32 | case DBDMA_RES1:
|
736 | 28ce5ce6 | aurel32 | case DBDMA_RES2:
|
737 | 28ce5ce6 | aurel32 | case DBDMA_RES3:
|
738 | 28ce5ce6 | aurel32 | case DBDMA_RES4:
|
739 | 28ce5ce6 | aurel32 | /* unused */
|
740 | 28ce5ce6 | aurel32 | break;
|
741 | 28ce5ce6 | aurel32 | } |
742 | 28ce5ce6 | aurel32 | } |
743 | 28ce5ce6 | aurel32 | |
744 | 3cbee15b | j_mayer | static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr) |
745 | 3cbee15b | j_mayer | { |
746 | 28ce5ce6 | aurel32 | uint32_t value; |
747 | 28ce5ce6 | aurel32 | int channel = addr >> DBDMA_CHANNEL_SHIFT;
|
748 | 28ce5ce6 | aurel32 | DBDMA_channel *ch = (DBDMA_channel *)opaque + channel; |
749 | 28ce5ce6 | aurel32 | int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2; |
750 | ea026b2f | blueswir1 | |
751 | 28ce5ce6 | aurel32 | value = ch->regs[reg]; |
752 | 28ce5ce6 | aurel32 | |
753 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("readl 0x" TARGET_FMT_plx " => 0x%08x\n", addr, value); |
754 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
|
755 | 28ce5ce6 | aurel32 | (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); |
756 | 28ce5ce6 | aurel32 | |
757 | 28ce5ce6 | aurel32 | switch(reg) {
|
758 | 28ce5ce6 | aurel32 | case DBDMA_CONTROL:
|
759 | 28ce5ce6 | aurel32 | value = 0;
|
760 | 28ce5ce6 | aurel32 | break;
|
761 | 28ce5ce6 | aurel32 | case DBDMA_STATUS:
|
762 | 28ce5ce6 | aurel32 | case DBDMA_CMDPTR_LO:
|
763 | 28ce5ce6 | aurel32 | case DBDMA_INTR_SEL:
|
764 | 28ce5ce6 | aurel32 | case DBDMA_BRANCH_SEL:
|
765 | 28ce5ce6 | aurel32 | case DBDMA_WAIT_SEL:
|
766 | 28ce5ce6 | aurel32 | /* nothing to do */
|
767 | 28ce5ce6 | aurel32 | break;
|
768 | 28ce5ce6 | aurel32 | case DBDMA_XFER_MODE:
|
769 | 28ce5ce6 | aurel32 | case DBDMA_CMDPTR_HI:
|
770 | 28ce5ce6 | aurel32 | case DBDMA_DATA2PTR_HI:
|
771 | 28ce5ce6 | aurel32 | case DBDMA_DATA2PTR_LO:
|
772 | 28ce5ce6 | aurel32 | case DBDMA_ADDRESS_HI:
|
773 | 28ce5ce6 | aurel32 | case DBDMA_BRANCH_ADDR_HI:
|
774 | 28ce5ce6 | aurel32 | /* unused */
|
775 | 28ce5ce6 | aurel32 | value = 0;
|
776 | 28ce5ce6 | aurel32 | break;
|
777 | 28ce5ce6 | aurel32 | case DBDMA_RES1:
|
778 | 28ce5ce6 | aurel32 | case DBDMA_RES2:
|
779 | 28ce5ce6 | aurel32 | case DBDMA_RES3:
|
780 | 28ce5ce6 | aurel32 | case DBDMA_RES4:
|
781 | 28ce5ce6 | aurel32 | /* reserved */
|
782 | 28ce5ce6 | aurel32 | break;
|
783 | 28ce5ce6 | aurel32 | } |
784 | 28ce5ce6 | aurel32 | |
785 | 28ce5ce6 | aurel32 | return value;
|
786 | 3cbee15b | j_mayer | } |
787 | 3cbee15b | j_mayer | |
788 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const dbdma_write[] = { |
789 | 28ce5ce6 | aurel32 | NULL,
|
790 | 28ce5ce6 | aurel32 | NULL,
|
791 | 28ce5ce6 | aurel32 | dbdma_writel, |
792 | 3cbee15b | j_mayer | }; |
793 | 3cbee15b | j_mayer | |
794 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const dbdma_read[] = { |
795 | 28ce5ce6 | aurel32 | NULL,
|
796 | 28ce5ce6 | aurel32 | NULL,
|
797 | 28ce5ce6 | aurel32 | dbdma_readl, |
798 | 3cbee15b | j_mayer | }; |
799 | 3cbee15b | j_mayer | |
800 | 9b64997f | blueswir1 | static void dbdma_save(QEMUFile *f, void *opaque) |
801 | 9b64997f | blueswir1 | { |
802 | 28ce5ce6 | aurel32 | DBDMA_channel *s = opaque; |
803 | 28ce5ce6 | aurel32 | unsigned int i, j; |
804 | 28ce5ce6 | aurel32 | |
805 | 28ce5ce6 | aurel32 | for (i = 0; i < DBDMA_CHANNELS; i++) |
806 | 28ce5ce6 | aurel32 | for (j = 0; j < DBDMA_REGS; j++) |
807 | 28ce5ce6 | aurel32 | qemu_put_be32s(f, &s[i].regs[j]); |
808 | 9b64997f | blueswir1 | } |
809 | 9b64997f | blueswir1 | |
810 | 9b64997f | blueswir1 | static int dbdma_load(QEMUFile *f, void *opaque, int version_id) |
811 | 9b64997f | blueswir1 | { |
812 | 28ce5ce6 | aurel32 | DBDMA_channel *s = opaque; |
813 | 28ce5ce6 | aurel32 | unsigned int i, j; |
814 | 28ce5ce6 | aurel32 | |
815 | 28ce5ce6 | aurel32 | if (version_id != 2) |
816 | 9b64997f | blueswir1 | return -EINVAL;
|
817 | 9b64997f | blueswir1 | |
818 | 28ce5ce6 | aurel32 | for (i = 0; i < DBDMA_CHANNELS; i++) |
819 | 28ce5ce6 | aurel32 | for (j = 0; j < DBDMA_REGS; j++) |
820 | 28ce5ce6 | aurel32 | qemu_get_be32s(f, &s[i].regs[j]); |
821 | 28ce5ce6 | aurel32 | |
822 | 9b64997f | blueswir1 | return 0; |
823 | 9b64997f | blueswir1 | } |
824 | 9b64997f | blueswir1 | |
825 | 6e6b7363 | blueswir1 | static void dbdma_reset(void *opaque) |
826 | 6e6b7363 | blueswir1 | { |
827 | 28ce5ce6 | aurel32 | DBDMA_channel *s = opaque; |
828 | 28ce5ce6 | aurel32 | int i;
|
829 | 28ce5ce6 | aurel32 | |
830 | 28ce5ce6 | aurel32 | for (i = 0; i < DBDMA_CHANNELS; i++) |
831 | 28ce5ce6 | aurel32 | memset(s[i].regs, 0, DBDMA_SIZE);
|
832 | 6e6b7363 | blueswir1 | } |
833 | 6e6b7363 | blueswir1 | |
834 | 28ce5ce6 | aurel32 | void* DBDMA_init (int *dbdma_mem_index) |
835 | 3cbee15b | j_mayer | { |
836 | 28ce5ce6 | aurel32 | DBDMA_channel *s; |
837 | 28ce5ce6 | aurel32 | |
838 | 28ce5ce6 | aurel32 | s = qemu_mallocz(sizeof(DBDMA_channel) * DBDMA_CHANNELS);
|
839 | 28ce5ce6 | aurel32 | |
840 | 1eed09cb | Avi Kivity | *dbdma_mem_index = cpu_register_io_memory(dbdma_read, dbdma_write, s); |
841 | 28ce5ce6 | aurel32 | register_savevm("dbdma", -1, 1, dbdma_save, dbdma_load, s); |
842 | a08d4367 | Jan Kiszka | qemu_register_reset(dbdma_reset, s); |
843 | 28ce5ce6 | aurel32 | dbdma_reset(s); |
844 | 28ce5ce6 | aurel32 | |
845 | 28ce5ce6 | aurel32 | dbdma_bh = qemu_bh_new(DBDMA_run_bh, s); |
846 | 28ce5ce6 | aurel32 | |
847 | 28ce5ce6 | aurel32 | return s;
|
848 | 3cbee15b | j_mayer | } |