root / hw / ppc.c @ 86d86414
History | View | Annotate | Download (38.1 kB)
1 | a541f297 | bellard | /*
|
---|---|---|---|
2 | e9df014c | j_mayer | * QEMU generic PowerPC hardware System Emulator
|
3 | 5fafdf24 | ths | *
|
4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
|
5 | 5fafdf24 | ths | *
|
6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
|
9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
|
12 | a541f297 | bellard | *
|
13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | a541f297 | bellard | * all copies or substantial portions of the Software.
|
15 | a541f297 | bellard | *
|
16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | a541f297 | bellard | * THE SOFTWARE.
|
23 | a541f297 | bellard | */
|
24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "ppc.h" |
26 | 87ecb68b | pbrook | #include "qemu-timer.h" |
27 | 87ecb68b | pbrook | #include "sysemu.h" |
28 | 87ecb68b | pbrook | #include "nvram.h" |
29 | 3b3fb322 | blueswir1 | #include "qemu-log.h" |
30 | ca20cf32 | Blue Swirl | #include "loader.h" |
31 | fc87e185 | Alexander Graf | #include "kvm.h" |
32 | fc87e185 | Alexander Graf | #include "kvm_ppc.h" |
33 | a541f297 | bellard | |
34 | e9df014c | j_mayer | //#define PPC_DEBUG_IRQ
|
35 | 4b6d0a4c | j_mayer | //#define PPC_DEBUG_TB
|
36 | e9df014c | j_mayer | |
37 | d12d51d5 | aliguori | #ifdef PPC_DEBUG_IRQ
|
38 | 93fcfe39 | aliguori | # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) |
39 | d12d51d5 | aliguori | #else
|
40 | d12d51d5 | aliguori | # define LOG_IRQ(...) do { } while (0) |
41 | d12d51d5 | aliguori | #endif
|
42 | d12d51d5 | aliguori | |
43 | d12d51d5 | aliguori | |
44 | d12d51d5 | aliguori | #ifdef PPC_DEBUG_TB
|
45 | 93fcfe39 | aliguori | # define LOG_TB(...) qemu_log(__VA_ARGS__)
|
46 | d12d51d5 | aliguori | #else
|
47 | d12d51d5 | aliguori | # define LOG_TB(...) do { } while (0) |
48 | d12d51d5 | aliguori | #endif
|
49 | d12d51d5 | aliguori | |
50 | dbdd2506 | j_mayer | static void cpu_ppc_tb_stop (CPUState *env); |
51 | dbdd2506 | j_mayer | static void cpu_ppc_tb_start (CPUState *env); |
52 | dbdd2506 | j_mayer | |
53 | 00af685f | j_mayer | static void ppc_set_irq (CPUState *env, int n_IRQ, int level) |
54 | 47103572 | j_mayer | { |
55 | fc87e185 | Alexander Graf | unsigned int old_pending = env->pending_interrupts; |
56 | fc87e185 | Alexander Graf | |
57 | 47103572 | j_mayer | if (level) {
|
58 | 47103572 | j_mayer | env->pending_interrupts |= 1 << n_IRQ;
|
59 | 47103572 | j_mayer | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
60 | 47103572 | j_mayer | } else {
|
61 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << n_IRQ);
|
62 | 47103572 | j_mayer | if (env->pending_interrupts == 0) |
63 | 47103572 | j_mayer | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
64 | 47103572 | j_mayer | } |
65 | fc87e185 | Alexander Graf | |
66 | fc87e185 | Alexander Graf | if (old_pending != env->pending_interrupts) {
|
67 | fc87e185 | Alexander Graf | #ifdef CONFIG_KVM
|
68 | fc87e185 | Alexander Graf | kvmppc_set_interrupt(env, n_IRQ, level); |
69 | fc87e185 | Alexander Graf | #endif
|
70 | fc87e185 | Alexander Graf | } |
71 | fc87e185 | Alexander Graf | |
72 | d12d51d5 | aliguori | LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
|
73 | aae9366a | j_mayer | "req %08x\n", __func__, env, n_IRQ, level,
|
74 | a496775f | j_mayer | env->pending_interrupts, env->interrupt_request); |
75 | 47103572 | j_mayer | } |
76 | 47103572 | j_mayer | |
77 | e9df014c | j_mayer | /* PowerPC 6xx / 7xx internal IRQ controller */
|
78 | e9df014c | j_mayer | static void ppc6xx_set_irq (void *opaque, int pin, int level) |
79 | d537cf6c | pbrook | { |
80 | e9df014c | j_mayer | CPUState *env = opaque; |
81 | e9df014c | j_mayer | int cur_level;
|
82 | d537cf6c | pbrook | |
83 | d12d51d5 | aliguori | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
|
84 | a496775f | j_mayer | env, pin, level); |
85 | e9df014c | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
|
86 | e9df014c | j_mayer | /* Don't generate spurious events */
|
87 | 24be5ae3 | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
88 | e9df014c | j_mayer | switch (pin) {
|
89 | dbdd2506 | j_mayer | case PPC6xx_INPUT_TBEN:
|
90 | dbdd2506 | j_mayer | /* Level sensitive - active high */
|
91 | d12d51d5 | aliguori | LOG_IRQ("%s: %s the time base\n",
|
92 | dbdd2506 | j_mayer | __func__, level ? "start" : "stop"); |
93 | dbdd2506 | j_mayer | if (level) {
|
94 | dbdd2506 | j_mayer | cpu_ppc_tb_start(env); |
95 | dbdd2506 | j_mayer | } else {
|
96 | dbdd2506 | j_mayer | cpu_ppc_tb_stop(env); |
97 | dbdd2506 | j_mayer | } |
98 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_INT:
|
99 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
100 | d12d51d5 | aliguori | LOG_IRQ("%s: set the external IRQ state to %d\n",
|
101 | a496775f | j_mayer | __func__, level); |
102 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
103 | e9df014c | j_mayer | break;
|
104 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_SMI:
|
105 | e9df014c | j_mayer | /* Level sensitive - active high */
|
106 | d12d51d5 | aliguori | LOG_IRQ("%s: set the SMI IRQ state to %d\n",
|
107 | a496775f | j_mayer | __func__, level); |
108 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_SMI, level); |
109 | e9df014c | j_mayer | break;
|
110 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_MCP:
|
111 | e9df014c | j_mayer | /* Negative edge sensitive */
|
112 | e9df014c | j_mayer | /* XXX: TODO: actual reaction may depends on HID0 status
|
113 | e9df014c | j_mayer | * 603/604/740/750: check HID0[EMCP]
|
114 | e9df014c | j_mayer | */
|
115 | e9df014c | j_mayer | if (cur_level == 1 && level == 0) { |
116 | d12d51d5 | aliguori | LOG_IRQ("%s: raise machine check state\n",
|
117 | a496775f | j_mayer | __func__); |
118 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
|
119 | e9df014c | j_mayer | } |
120 | e9df014c | j_mayer | break;
|
121 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_CKSTP_IN:
|
122 | e9df014c | j_mayer | /* Level sensitive - active low */
|
123 | e9df014c | j_mayer | /* XXX: TODO: relay the signal to CKSTP_OUT pin */
|
124 | e63ecc6f | j_mayer | /* XXX: Note that the only way to restart the CPU is to reset it */
|
125 | e9df014c | j_mayer | if (level) {
|
126 | d12d51d5 | aliguori | LOG_IRQ("%s: stop the CPU\n", __func__);
|
127 | e9df014c | j_mayer | env->halted = 1;
|
128 | e9df014c | j_mayer | } |
129 | e9df014c | j_mayer | break;
|
130 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_HRESET:
|
131 | e9df014c | j_mayer | /* Level sensitive - active low */
|
132 | e9df014c | j_mayer | if (level) {
|
133 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the CPU\n", __func__);
|
134 | ef397e88 | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
135 | ef397e88 | j_mayer | /* XXX: TOFIX */
|
136 | ef397e88 | j_mayer | #if 0
|
137 | d84bda46 | Blue Swirl | cpu_reset(env);
|
138 | ef397e88 | j_mayer | #else
|
139 | ef397e88 | j_mayer | qemu_system_reset_request(); |
140 | e9df014c | j_mayer | #endif
|
141 | e9df014c | j_mayer | } |
142 | e9df014c | j_mayer | break;
|
143 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_SRESET:
|
144 | d12d51d5 | aliguori | LOG_IRQ("%s: set the RESET IRQ state to %d\n",
|
145 | a496775f | j_mayer | __func__, level); |
146 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
147 | e9df014c | j_mayer | break;
|
148 | e9df014c | j_mayer | default:
|
149 | e9df014c | j_mayer | /* Unknown pin - do nothing */
|
150 | d12d51d5 | aliguori | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
|
151 | e9df014c | j_mayer | return;
|
152 | e9df014c | j_mayer | } |
153 | e9df014c | j_mayer | if (level)
|
154 | e9df014c | j_mayer | env->irq_input_state |= 1 << pin;
|
155 | e9df014c | j_mayer | else
|
156 | e9df014c | j_mayer | env->irq_input_state &= ~(1 << pin);
|
157 | d537cf6c | pbrook | } |
158 | d537cf6c | pbrook | } |
159 | d537cf6c | pbrook | |
160 | e9df014c | j_mayer | void ppc6xx_irq_init (CPUState *env)
|
161 | 47103572 | j_mayer | { |
162 | 7b62a955 | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env,
|
163 | 7b62a955 | j_mayer | PPC6xx_INPUT_NB); |
164 | 47103572 | j_mayer | } |
165 | 47103572 | j_mayer | |
166 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
167 | d0dfae6e | j_mayer | /* PowerPC 970 internal IRQ controller */
|
168 | d0dfae6e | j_mayer | static void ppc970_set_irq (void *opaque, int pin, int level) |
169 | d0dfae6e | j_mayer | { |
170 | d0dfae6e | j_mayer | CPUState *env = opaque; |
171 | d0dfae6e | j_mayer | int cur_level;
|
172 | d0dfae6e | j_mayer | |
173 | d12d51d5 | aliguori | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
|
174 | d0dfae6e | j_mayer | env, pin, level); |
175 | d0dfae6e | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
|
176 | d0dfae6e | j_mayer | /* Don't generate spurious events */
|
177 | d0dfae6e | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
178 | d0dfae6e | j_mayer | switch (pin) {
|
179 | d0dfae6e | j_mayer | case PPC970_INPUT_INT:
|
180 | d0dfae6e | j_mayer | /* Level sensitive - active high */
|
181 | d12d51d5 | aliguori | LOG_IRQ("%s: set the external IRQ state to %d\n",
|
182 | d0dfae6e | j_mayer | __func__, level); |
183 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
184 | d0dfae6e | j_mayer | break;
|
185 | d0dfae6e | j_mayer | case PPC970_INPUT_THINT:
|
186 | d0dfae6e | j_mayer | /* Level sensitive - active high */
|
187 | d12d51d5 | aliguori | LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
|
188 | d0dfae6e | j_mayer | level); |
189 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_THERM, level); |
190 | d0dfae6e | j_mayer | break;
|
191 | d0dfae6e | j_mayer | case PPC970_INPUT_MCP:
|
192 | d0dfae6e | j_mayer | /* Negative edge sensitive */
|
193 | d0dfae6e | j_mayer | /* XXX: TODO: actual reaction may depends on HID0 status
|
194 | d0dfae6e | j_mayer | * 603/604/740/750: check HID0[EMCP]
|
195 | d0dfae6e | j_mayer | */
|
196 | d0dfae6e | j_mayer | if (cur_level == 1 && level == 0) { |
197 | d12d51d5 | aliguori | LOG_IRQ("%s: raise machine check state\n",
|
198 | d0dfae6e | j_mayer | __func__); |
199 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
|
200 | d0dfae6e | j_mayer | } |
201 | d0dfae6e | j_mayer | break;
|
202 | d0dfae6e | j_mayer | case PPC970_INPUT_CKSTP:
|
203 | d0dfae6e | j_mayer | /* Level sensitive - active low */
|
204 | d0dfae6e | j_mayer | /* XXX: TODO: relay the signal to CKSTP_OUT pin */
|
205 | d0dfae6e | j_mayer | if (level) {
|
206 | d12d51d5 | aliguori | LOG_IRQ("%s: stop the CPU\n", __func__);
|
207 | d0dfae6e | j_mayer | env->halted = 1;
|
208 | d0dfae6e | j_mayer | } else {
|
209 | d12d51d5 | aliguori | LOG_IRQ("%s: restart the CPU\n", __func__);
|
210 | d0dfae6e | j_mayer | env->halted = 0;
|
211 | d0dfae6e | j_mayer | } |
212 | d0dfae6e | j_mayer | break;
|
213 | d0dfae6e | j_mayer | case PPC970_INPUT_HRESET:
|
214 | d0dfae6e | j_mayer | /* Level sensitive - active low */
|
215 | d0dfae6e | j_mayer | if (level) {
|
216 | d0dfae6e | j_mayer | #if 0 // XXX: TOFIX
|
217 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the CPU\n", __func__);
|
218 | d0dfae6e | j_mayer | cpu_reset(env);
|
219 | d0dfae6e | j_mayer | #endif
|
220 | d0dfae6e | j_mayer | } |
221 | d0dfae6e | j_mayer | break;
|
222 | d0dfae6e | j_mayer | case PPC970_INPUT_SRESET:
|
223 | d12d51d5 | aliguori | LOG_IRQ("%s: set the RESET IRQ state to %d\n",
|
224 | d0dfae6e | j_mayer | __func__, level); |
225 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
226 | d0dfae6e | j_mayer | break;
|
227 | d0dfae6e | j_mayer | case PPC970_INPUT_TBEN:
|
228 | d12d51d5 | aliguori | LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
|
229 | d0dfae6e | j_mayer | level); |
230 | d0dfae6e | j_mayer | /* XXX: TODO */
|
231 | d0dfae6e | j_mayer | break;
|
232 | d0dfae6e | j_mayer | default:
|
233 | d0dfae6e | j_mayer | /* Unknown pin - do nothing */
|
234 | d12d51d5 | aliguori | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
|
235 | d0dfae6e | j_mayer | return;
|
236 | d0dfae6e | j_mayer | } |
237 | d0dfae6e | j_mayer | if (level)
|
238 | d0dfae6e | j_mayer | env->irq_input_state |= 1 << pin;
|
239 | d0dfae6e | j_mayer | else
|
240 | d0dfae6e | j_mayer | env->irq_input_state &= ~(1 << pin);
|
241 | d0dfae6e | j_mayer | } |
242 | d0dfae6e | j_mayer | } |
243 | d0dfae6e | j_mayer | |
244 | d0dfae6e | j_mayer | void ppc970_irq_init (CPUState *env)
|
245 | d0dfae6e | j_mayer | { |
246 | 7b62a955 | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env,
|
247 | 7b62a955 | j_mayer | PPC970_INPUT_NB); |
248 | d0dfae6e | j_mayer | } |
249 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
250 | d0dfae6e | j_mayer | |
251 | 4e290a0b | j_mayer | /* PowerPC 40x internal IRQ controller */
|
252 | 4e290a0b | j_mayer | static void ppc40x_set_irq (void *opaque, int pin, int level) |
253 | 24be5ae3 | j_mayer | { |
254 | 24be5ae3 | j_mayer | CPUState *env = opaque; |
255 | 24be5ae3 | j_mayer | int cur_level;
|
256 | 24be5ae3 | j_mayer | |
257 | d12d51d5 | aliguori | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
|
258 | 8ecc7913 | j_mayer | env, pin, level); |
259 | 24be5ae3 | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
|
260 | 24be5ae3 | j_mayer | /* Don't generate spurious events */
|
261 | 24be5ae3 | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
262 | 24be5ae3 | j_mayer | switch (pin) {
|
263 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_SYS:
|
264 | 8ecc7913 | j_mayer | if (level) {
|
265 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the PowerPC system\n",
|
266 | 8ecc7913 | j_mayer | __func__); |
267 | 8ecc7913 | j_mayer | ppc40x_system_reset(env); |
268 | 8ecc7913 | j_mayer | } |
269 | 8ecc7913 | j_mayer | break;
|
270 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_CHIP:
|
271 | 8ecc7913 | j_mayer | if (level) {
|
272 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
|
273 | 8ecc7913 | j_mayer | ppc40x_chip_reset(env); |
274 | 8ecc7913 | j_mayer | } |
275 | 8ecc7913 | j_mayer | break;
|
276 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_CORE:
|
277 | 24be5ae3 | j_mayer | /* XXX: TODO: update DBSR[MRR] */
|
278 | 24be5ae3 | j_mayer | if (level) {
|
279 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the PowerPC core\n", __func__);
|
280 | 8ecc7913 | j_mayer | ppc40x_core_reset(env); |
281 | 24be5ae3 | j_mayer | } |
282 | 24be5ae3 | j_mayer | break;
|
283 | 4e290a0b | j_mayer | case PPC40x_INPUT_CINT:
|
284 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
285 | d12d51d5 | aliguori | LOG_IRQ("%s: set the critical IRQ state to %d\n",
|
286 | 8ecc7913 | j_mayer | __func__, level); |
287 | 4e290a0b | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); |
288 | 24be5ae3 | j_mayer | break;
|
289 | 4e290a0b | j_mayer | case PPC40x_INPUT_INT:
|
290 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
291 | d12d51d5 | aliguori | LOG_IRQ("%s: set the external IRQ state to %d\n",
|
292 | a496775f | j_mayer | __func__, level); |
293 | 24be5ae3 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
294 | 24be5ae3 | j_mayer | break;
|
295 | 4e290a0b | j_mayer | case PPC40x_INPUT_HALT:
|
296 | 24be5ae3 | j_mayer | /* Level sensitive - active low */
|
297 | 24be5ae3 | j_mayer | if (level) {
|
298 | d12d51d5 | aliguori | LOG_IRQ("%s: stop the CPU\n", __func__);
|
299 | 24be5ae3 | j_mayer | env->halted = 1;
|
300 | 24be5ae3 | j_mayer | } else {
|
301 | d12d51d5 | aliguori | LOG_IRQ("%s: restart the CPU\n", __func__);
|
302 | 24be5ae3 | j_mayer | env->halted = 0;
|
303 | 24be5ae3 | j_mayer | } |
304 | 24be5ae3 | j_mayer | break;
|
305 | 4e290a0b | j_mayer | case PPC40x_INPUT_DEBUG:
|
306 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
307 | d12d51d5 | aliguori | LOG_IRQ("%s: set the debug pin state to %d\n",
|
308 | a496775f | j_mayer | __func__, level); |
309 | a750fc0b | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); |
310 | 24be5ae3 | j_mayer | break;
|
311 | 24be5ae3 | j_mayer | default:
|
312 | 24be5ae3 | j_mayer | /* Unknown pin - do nothing */
|
313 | d12d51d5 | aliguori | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
|
314 | 24be5ae3 | j_mayer | return;
|
315 | 24be5ae3 | j_mayer | } |
316 | 24be5ae3 | j_mayer | if (level)
|
317 | 24be5ae3 | j_mayer | env->irq_input_state |= 1 << pin;
|
318 | 24be5ae3 | j_mayer | else
|
319 | 24be5ae3 | j_mayer | env->irq_input_state &= ~(1 << pin);
|
320 | 24be5ae3 | j_mayer | } |
321 | 24be5ae3 | j_mayer | } |
322 | 24be5ae3 | j_mayer | |
323 | 4e290a0b | j_mayer | void ppc40x_irq_init (CPUState *env)
|
324 | 24be5ae3 | j_mayer | { |
325 | 4e290a0b | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
|
326 | 4e290a0b | j_mayer | env, PPC40x_INPUT_NB); |
327 | 24be5ae3 | j_mayer | } |
328 | 24be5ae3 | j_mayer | |
329 | 9fdc60bf | aurel32 | /* PowerPC E500 internal IRQ controller */
|
330 | 9fdc60bf | aurel32 | static void ppce500_set_irq (void *opaque, int pin, int level) |
331 | 9fdc60bf | aurel32 | { |
332 | 9fdc60bf | aurel32 | CPUState *env = opaque; |
333 | 9fdc60bf | aurel32 | int cur_level;
|
334 | 9fdc60bf | aurel32 | |
335 | 9fdc60bf | aurel32 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
|
336 | 9fdc60bf | aurel32 | env, pin, level); |
337 | 9fdc60bf | aurel32 | cur_level = (env->irq_input_state >> pin) & 1;
|
338 | 9fdc60bf | aurel32 | /* Don't generate spurious events */
|
339 | 9fdc60bf | aurel32 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
340 | 9fdc60bf | aurel32 | switch (pin) {
|
341 | 9fdc60bf | aurel32 | case PPCE500_INPUT_MCK:
|
342 | 9fdc60bf | aurel32 | if (level) {
|
343 | 9fdc60bf | aurel32 | LOG_IRQ("%s: reset the PowerPC system\n",
|
344 | 9fdc60bf | aurel32 | __func__); |
345 | 9fdc60bf | aurel32 | qemu_system_reset_request(); |
346 | 9fdc60bf | aurel32 | } |
347 | 9fdc60bf | aurel32 | break;
|
348 | 9fdc60bf | aurel32 | case PPCE500_INPUT_RESET_CORE:
|
349 | 9fdc60bf | aurel32 | if (level) {
|
350 | 9fdc60bf | aurel32 | LOG_IRQ("%s: reset the PowerPC core\n", __func__);
|
351 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_MCK, level); |
352 | 9fdc60bf | aurel32 | } |
353 | 9fdc60bf | aurel32 | break;
|
354 | 9fdc60bf | aurel32 | case PPCE500_INPUT_CINT:
|
355 | 9fdc60bf | aurel32 | /* Level sensitive - active high */
|
356 | 9fdc60bf | aurel32 | LOG_IRQ("%s: set the critical IRQ state to %d\n",
|
357 | 9fdc60bf | aurel32 | __func__, level); |
358 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); |
359 | 9fdc60bf | aurel32 | break;
|
360 | 9fdc60bf | aurel32 | case PPCE500_INPUT_INT:
|
361 | 9fdc60bf | aurel32 | /* Level sensitive - active high */
|
362 | 9fdc60bf | aurel32 | LOG_IRQ("%s: set the core IRQ state to %d\n",
|
363 | 9fdc60bf | aurel32 | __func__, level); |
364 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
365 | 9fdc60bf | aurel32 | break;
|
366 | 9fdc60bf | aurel32 | case PPCE500_INPUT_DEBUG:
|
367 | 9fdc60bf | aurel32 | /* Level sensitive - active high */
|
368 | 9fdc60bf | aurel32 | LOG_IRQ("%s: set the debug pin state to %d\n",
|
369 | 9fdc60bf | aurel32 | __func__, level); |
370 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); |
371 | 9fdc60bf | aurel32 | break;
|
372 | 9fdc60bf | aurel32 | default:
|
373 | 9fdc60bf | aurel32 | /* Unknown pin - do nothing */
|
374 | 9fdc60bf | aurel32 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
|
375 | 9fdc60bf | aurel32 | return;
|
376 | 9fdc60bf | aurel32 | } |
377 | 9fdc60bf | aurel32 | if (level)
|
378 | 9fdc60bf | aurel32 | env->irq_input_state |= 1 << pin;
|
379 | 9fdc60bf | aurel32 | else
|
380 | 9fdc60bf | aurel32 | env->irq_input_state &= ~(1 << pin);
|
381 | 9fdc60bf | aurel32 | } |
382 | 9fdc60bf | aurel32 | } |
383 | 9fdc60bf | aurel32 | |
384 | 9fdc60bf | aurel32 | void ppce500_irq_init (CPUState *env)
|
385 | 9fdc60bf | aurel32 | { |
386 | 9fdc60bf | aurel32 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
|
387 | 9fdc60bf | aurel32 | env, PPCE500_INPUT_NB); |
388 | 9fdc60bf | aurel32 | } |
389 | 9fddaa0c | bellard | /*****************************************************************************/
|
390 | e9df014c | j_mayer | /* PowerPC time base and decrementer emulation */
|
391 | c227f099 | Anthony Liguori | struct ppc_tb_t {
|
392 | 9fddaa0c | bellard | /* Time base management */
|
393 | dbdd2506 | j_mayer | int64_t tb_offset; /* Compensation */
|
394 | dbdd2506 | j_mayer | int64_t atb_offset; /* Compensation */
|
395 | dbdd2506 | j_mayer | uint32_t tb_freq; /* TB frequency */
|
396 | 9fddaa0c | bellard | /* Decrementer management */
|
397 | dbdd2506 | j_mayer | uint64_t decr_next; /* Tick for next decr interrupt */
|
398 | dbdd2506 | j_mayer | uint32_t decr_freq; /* decrementer frequency */
|
399 | 9fddaa0c | bellard | struct QEMUTimer *decr_timer;
|
400 | 58a7d328 | j_mayer | /* Hypervisor decrementer management */
|
401 | 58a7d328 | j_mayer | uint64_t hdecr_next; /* Tick for next hdecr interrupt */
|
402 | 58a7d328 | j_mayer | struct QEMUTimer *hdecr_timer;
|
403 | 58a7d328 | j_mayer | uint64_t purr_load; |
404 | 58a7d328 | j_mayer | uint64_t purr_start; |
405 | 47103572 | j_mayer | void *opaque;
|
406 | 9fddaa0c | bellard | }; |
407 | 9fddaa0c | bellard | |
408 | c227f099 | Anthony Liguori | static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, |
409 | 636aa200 | Blue Swirl | int64_t tb_offset) |
410 | 9fddaa0c | bellard | { |
411 | 9fddaa0c | bellard | /* TB time in tb periods */
|
412 | 6ee093c9 | Juan Quintela | return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset;
|
413 | 9fddaa0c | bellard | } |
414 | 9fddaa0c | bellard | |
415 | e3ea6529 | Alexander Graf | uint64_t cpu_ppc_load_tbl (CPUState *env) |
416 | 9fddaa0c | bellard | { |
417 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
418 | 9fddaa0c | bellard | uint64_t tb; |
419 | 9fddaa0c | bellard | |
420 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
421 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
422 | 9fddaa0c | bellard | |
423 | e3ea6529 | Alexander Graf | return tb;
|
424 | 9fddaa0c | bellard | } |
425 | 9fddaa0c | bellard | |
426 | 636aa200 | Blue Swirl | static inline uint32_t _cpu_ppc_load_tbu(CPUState *env) |
427 | 9fddaa0c | bellard | { |
428 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
429 | 9fddaa0c | bellard | uint64_t tb; |
430 | 9fddaa0c | bellard | |
431 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
432 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
433 | 76a66253 | j_mayer | |
434 | 9fddaa0c | bellard | return tb >> 32; |
435 | 9fddaa0c | bellard | } |
436 | 9fddaa0c | bellard | |
437 | 8a84de23 | j_mayer | uint32_t cpu_ppc_load_tbu (CPUState *env) |
438 | 8a84de23 | j_mayer | { |
439 | 8a84de23 | j_mayer | return _cpu_ppc_load_tbu(env);
|
440 | 8a84de23 | j_mayer | } |
441 | 8a84de23 | j_mayer | |
442 | c227f099 | Anthony Liguori | static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, |
443 | 636aa200 | Blue Swirl | int64_t *tb_offsetp, uint64_t value) |
444 | 9fddaa0c | bellard | { |
445 | 6ee093c9 | Juan Quintela | *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()); |
446 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", |
447 | aae9366a | j_mayer | __func__, value, *tb_offsetp); |
448 | 9fddaa0c | bellard | } |
449 | 9fddaa0c | bellard | |
450 | a062e36c | j_mayer | void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
|
451 | a062e36c | j_mayer | { |
452 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
453 | a062e36c | j_mayer | uint64_t tb; |
454 | a062e36c | j_mayer | |
455 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
456 | a062e36c | j_mayer | tb &= 0xFFFFFFFF00000000ULL;
|
457 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
458 | dbdd2506 | j_mayer | &tb_env->tb_offset, tb | (uint64_t)value); |
459 | a062e36c | j_mayer | } |
460 | a062e36c | j_mayer | |
461 | 636aa200 | Blue Swirl | static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value) |
462 | 9fddaa0c | bellard | { |
463 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
464 | a062e36c | j_mayer | uint64_t tb; |
465 | 9fddaa0c | bellard | |
466 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
467 | a062e36c | j_mayer | tb &= 0x00000000FFFFFFFFULL;
|
468 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
469 | dbdd2506 | j_mayer | &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
|
470 | 9fddaa0c | bellard | } |
471 | 9fddaa0c | bellard | |
472 | 8a84de23 | j_mayer | void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
|
473 | 8a84de23 | j_mayer | { |
474 | 8a84de23 | j_mayer | _cpu_ppc_store_tbu(env, value); |
475 | 8a84de23 | j_mayer | } |
476 | 8a84de23 | j_mayer | |
477 | b711de95 | Aurelien Jarno | uint64_t cpu_ppc_load_atbl (CPUState *env) |
478 | a062e36c | j_mayer | { |
479 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
480 | a062e36c | j_mayer | uint64_t tb; |
481 | a062e36c | j_mayer | |
482 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
483 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
484 | a062e36c | j_mayer | |
485 | b711de95 | Aurelien Jarno | return tb;
|
486 | a062e36c | j_mayer | } |
487 | a062e36c | j_mayer | |
488 | a062e36c | j_mayer | uint32_t cpu_ppc_load_atbu (CPUState *env) |
489 | a062e36c | j_mayer | { |
490 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
491 | a062e36c | j_mayer | uint64_t tb; |
492 | a062e36c | j_mayer | |
493 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
494 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
495 | a062e36c | j_mayer | |
496 | a062e36c | j_mayer | return tb >> 32; |
497 | a062e36c | j_mayer | } |
498 | a062e36c | j_mayer | |
499 | a062e36c | j_mayer | void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
|
500 | a062e36c | j_mayer | { |
501 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
502 | a062e36c | j_mayer | uint64_t tb; |
503 | a062e36c | j_mayer | |
504 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
505 | a062e36c | j_mayer | tb &= 0xFFFFFFFF00000000ULL;
|
506 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
507 | dbdd2506 | j_mayer | &tb_env->atb_offset, tb | (uint64_t)value); |
508 | a062e36c | j_mayer | } |
509 | a062e36c | j_mayer | |
510 | a062e36c | j_mayer | void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
|
511 | 9fddaa0c | bellard | { |
512 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
513 | a062e36c | j_mayer | uint64_t tb; |
514 | 9fddaa0c | bellard | |
515 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
516 | a062e36c | j_mayer | tb &= 0x00000000FFFFFFFFULL;
|
517 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
518 | dbdd2506 | j_mayer | &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
|
519 | dbdd2506 | j_mayer | } |
520 | dbdd2506 | j_mayer | |
521 | dbdd2506 | j_mayer | static void cpu_ppc_tb_stop (CPUState *env) |
522 | dbdd2506 | j_mayer | { |
523 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
524 | dbdd2506 | j_mayer | uint64_t tb, atb, vmclk; |
525 | dbdd2506 | j_mayer | |
526 | dbdd2506 | j_mayer | /* If the time base is already frozen, do nothing */
|
527 | dbdd2506 | j_mayer | if (tb_env->tb_freq != 0) { |
528 | dbdd2506 | j_mayer | vmclk = qemu_get_clock(vm_clock); |
529 | dbdd2506 | j_mayer | /* Get the time base */
|
530 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); |
531 | dbdd2506 | j_mayer | /* Get the alternate time base */
|
532 | dbdd2506 | j_mayer | atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); |
533 | dbdd2506 | j_mayer | /* Store the time base value (ie compute the current offset) */
|
534 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
535 | dbdd2506 | j_mayer | /* Store the alternate time base value (compute the current offset) */
|
536 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
537 | dbdd2506 | j_mayer | /* Set the time base frequency to zero */
|
538 | dbdd2506 | j_mayer | tb_env->tb_freq = 0;
|
539 | dbdd2506 | j_mayer | /* Now, the time bases are frozen to tb_offset / atb_offset value */
|
540 | dbdd2506 | j_mayer | } |
541 | dbdd2506 | j_mayer | } |
542 | dbdd2506 | j_mayer | |
543 | dbdd2506 | j_mayer | static void cpu_ppc_tb_start (CPUState *env) |
544 | dbdd2506 | j_mayer | { |
545 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
546 | dbdd2506 | j_mayer | uint64_t tb, atb, vmclk; |
547 | aae9366a | j_mayer | |
548 | dbdd2506 | j_mayer | /* If the time base is not frozen, do nothing */
|
549 | dbdd2506 | j_mayer | if (tb_env->tb_freq == 0) { |
550 | dbdd2506 | j_mayer | vmclk = qemu_get_clock(vm_clock); |
551 | dbdd2506 | j_mayer | /* Get the time base from tb_offset */
|
552 | dbdd2506 | j_mayer | tb = tb_env->tb_offset; |
553 | dbdd2506 | j_mayer | /* Get the alternate time base from atb_offset */
|
554 | dbdd2506 | j_mayer | atb = tb_env->atb_offset; |
555 | dbdd2506 | j_mayer | /* Restore the tb frequency from the decrementer frequency */
|
556 | dbdd2506 | j_mayer | tb_env->tb_freq = tb_env->decr_freq; |
557 | dbdd2506 | j_mayer | /* Store the time base value */
|
558 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
559 | dbdd2506 | j_mayer | /* Store the alternate time base value */
|
560 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
561 | dbdd2506 | j_mayer | } |
562 | 9fddaa0c | bellard | } |
563 | 9fddaa0c | bellard | |
564 | 636aa200 | Blue Swirl | static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) |
565 | 9fddaa0c | bellard | { |
566 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
567 | 9fddaa0c | bellard | uint32_t decr; |
568 | 4e588a4d | bellard | int64_t diff; |
569 | 9fddaa0c | bellard | |
570 | f55e9d9a | Tristan Gingold | diff = next - qemu_get_clock(vm_clock); |
571 | 4e588a4d | bellard | if (diff >= 0) |
572 | 6ee093c9 | Juan Quintela | decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec()); |
573 | 4e588a4d | bellard | else
|
574 | 6ee093c9 | Juan Quintela | decr = -muldiv64(-diff, tb_env->decr_freq, get_ticks_per_sec()); |
575 | d12d51d5 | aliguori | LOG_TB("%s: %08" PRIx32 "\n", __func__, decr); |
576 | 76a66253 | j_mayer | |
577 | 9fddaa0c | bellard | return decr;
|
578 | 9fddaa0c | bellard | } |
579 | 9fddaa0c | bellard | |
580 | 58a7d328 | j_mayer | uint32_t cpu_ppc_load_decr (CPUState *env) |
581 | 58a7d328 | j_mayer | { |
582 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
583 | 58a7d328 | j_mayer | |
584 | f55e9d9a | Tristan Gingold | return _cpu_ppc_load_decr(env, tb_env->decr_next);
|
585 | 58a7d328 | j_mayer | } |
586 | 58a7d328 | j_mayer | |
587 | 58a7d328 | j_mayer | uint32_t cpu_ppc_load_hdecr (CPUState *env) |
588 | 58a7d328 | j_mayer | { |
589 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
590 | 58a7d328 | j_mayer | |
591 | f55e9d9a | Tristan Gingold | return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
|
592 | 58a7d328 | j_mayer | } |
593 | 58a7d328 | j_mayer | |
594 | 58a7d328 | j_mayer | uint64_t cpu_ppc_load_purr (CPUState *env) |
595 | 58a7d328 | j_mayer | { |
596 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
597 | 58a7d328 | j_mayer | uint64_t diff; |
598 | 58a7d328 | j_mayer | |
599 | 58a7d328 | j_mayer | diff = qemu_get_clock(vm_clock) - tb_env->purr_start; |
600 | b33c17e1 | j_mayer | |
601 | 6ee093c9 | Juan Quintela | return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec());
|
602 | 58a7d328 | j_mayer | } |
603 | 58a7d328 | j_mayer | |
604 | 9fddaa0c | bellard | /* When decrementer expires,
|
605 | 9fddaa0c | bellard | * all we need to do is generate or queue a CPU exception
|
606 | 9fddaa0c | bellard | */
|
607 | 636aa200 | Blue Swirl | static inline void cpu_ppc_decr_excp(CPUState *env) |
608 | 9fddaa0c | bellard | { |
609 | 9fddaa0c | bellard | /* Raise it */
|
610 | d12d51d5 | aliguori | LOG_TB("raise decrementer exception\n");
|
611 | 47103572 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
|
612 | 9fddaa0c | bellard | } |
613 | 9fddaa0c | bellard | |
614 | 636aa200 | Blue Swirl | static inline void cpu_ppc_hdecr_excp(CPUState *env) |
615 | 58a7d328 | j_mayer | { |
616 | 58a7d328 | j_mayer | /* Raise it */
|
617 | d12d51d5 | aliguori | LOG_TB("raise decrementer exception\n");
|
618 | 58a7d328 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
|
619 | 58a7d328 | j_mayer | } |
620 | 58a7d328 | j_mayer | |
621 | 58a7d328 | j_mayer | static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, |
622 | b33c17e1 | j_mayer | struct QEMUTimer *timer,
|
623 | b33c17e1 | j_mayer | void (*raise_excp)(CPUState *),
|
624 | b33c17e1 | j_mayer | uint32_t decr, uint32_t value, |
625 | b33c17e1 | j_mayer | int is_excp)
|
626 | 9fddaa0c | bellard | { |
627 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
628 | 9fddaa0c | bellard | uint64_t now, next; |
629 | 9fddaa0c | bellard | |
630 | d12d51d5 | aliguori | LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, |
631 | aae9366a | j_mayer | decr, value); |
632 | 9fddaa0c | bellard | now = qemu_get_clock(vm_clock); |
633 | 6ee093c9 | Juan Quintela | next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq); |
634 | 9fddaa0c | bellard | if (is_excp)
|
635 | 58a7d328 | j_mayer | next += *nextp - now; |
636 | 9fddaa0c | bellard | if (next == now)
|
637 | 76a66253 | j_mayer | next++; |
638 | 58a7d328 | j_mayer | *nextp = next; |
639 | 9fddaa0c | bellard | /* Adjust timer */
|
640 | 58a7d328 | j_mayer | qemu_mod_timer(timer, next); |
641 | 9fddaa0c | bellard | /* If we set a negative value and the decrementer was positive,
|
642 | 9fddaa0c | bellard | * raise an exception.
|
643 | 9fddaa0c | bellard | */
|
644 | 9fddaa0c | bellard | if ((value & 0x80000000) && !(decr & 0x80000000)) |
645 | 58a7d328 | j_mayer | (*raise_excp)(env); |
646 | 58a7d328 | j_mayer | } |
647 | 58a7d328 | j_mayer | |
648 | 636aa200 | Blue Swirl | static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr, |
649 | 636aa200 | Blue Swirl | uint32_t value, int is_excp)
|
650 | 58a7d328 | j_mayer | { |
651 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
652 | 58a7d328 | j_mayer | |
653 | 58a7d328 | j_mayer | __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer, |
654 | 58a7d328 | j_mayer | &cpu_ppc_decr_excp, decr, value, is_excp); |
655 | 9fddaa0c | bellard | } |
656 | 9fddaa0c | bellard | |
657 | 9fddaa0c | bellard | void cpu_ppc_store_decr (CPUState *env, uint32_t value)
|
658 | 9fddaa0c | bellard | { |
659 | 9fddaa0c | bellard | _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
|
660 | 9fddaa0c | bellard | } |
661 | 9fddaa0c | bellard | |
662 | 9fddaa0c | bellard | static void cpu_ppc_decr_cb (void *opaque) |
663 | 9fddaa0c | bellard | { |
664 | 9fddaa0c | bellard | _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
665 | 9fddaa0c | bellard | } |
666 | 9fddaa0c | bellard | |
667 | 636aa200 | Blue Swirl | static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr, |
668 | 636aa200 | Blue Swirl | uint32_t value, int is_excp)
|
669 | 58a7d328 | j_mayer | { |
670 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
671 | 58a7d328 | j_mayer | |
672 | b172c56a | j_mayer | if (tb_env->hdecr_timer != NULL) { |
673 | b172c56a | j_mayer | __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer, |
674 | b172c56a | j_mayer | &cpu_ppc_hdecr_excp, hdecr, value, is_excp); |
675 | b172c56a | j_mayer | } |
676 | 58a7d328 | j_mayer | } |
677 | 58a7d328 | j_mayer | |
678 | 58a7d328 | j_mayer | void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
|
679 | 58a7d328 | j_mayer | { |
680 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
|
681 | 58a7d328 | j_mayer | } |
682 | 58a7d328 | j_mayer | |
683 | 58a7d328 | j_mayer | static void cpu_ppc_hdecr_cb (void *opaque) |
684 | 58a7d328 | j_mayer | { |
685 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
686 | 58a7d328 | j_mayer | } |
687 | 58a7d328 | j_mayer | |
688 | 58a7d328 | j_mayer | void cpu_ppc_store_purr (CPUState *env, uint64_t value)
|
689 | 58a7d328 | j_mayer | { |
690 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
691 | 58a7d328 | j_mayer | |
692 | 58a7d328 | j_mayer | tb_env->purr_load = value; |
693 | 58a7d328 | j_mayer | tb_env->purr_start = qemu_get_clock(vm_clock); |
694 | 58a7d328 | j_mayer | } |
695 | 58a7d328 | j_mayer | |
696 | 8ecc7913 | j_mayer | static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) |
697 | 8ecc7913 | j_mayer | { |
698 | 8ecc7913 | j_mayer | CPUState *env = opaque; |
699 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
700 | 8ecc7913 | j_mayer | |
701 | 8ecc7913 | j_mayer | tb_env->tb_freq = freq; |
702 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
703 | 8ecc7913 | j_mayer | /* There is a bug in Linux 2.4 kernels:
|
704 | 8ecc7913 | j_mayer | * if a decrementer exception is pending when it enables msr_ee at startup,
|
705 | 8ecc7913 | j_mayer | * it's not ready to handle it...
|
706 | 8ecc7913 | j_mayer | */
|
707 | 8ecc7913 | j_mayer | _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
708 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
709 | 58a7d328 | j_mayer | cpu_ppc_store_purr(env, 0x0000000000000000ULL);
|
710 | 8ecc7913 | j_mayer | } |
711 | 8ecc7913 | j_mayer | |
712 | 9fddaa0c | bellard | /* Set up (once) timebase frequency (in Hz) */
|
713 | 8ecc7913 | j_mayer | clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) |
714 | 9fddaa0c | bellard | { |
715 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
716 | 9fddaa0c | bellard | |
717 | c227f099 | Anthony Liguori | tb_env = qemu_mallocz(sizeof(ppc_tb_t));
|
718 | 9fddaa0c | bellard | env->tb_env = tb_env; |
719 | 8ecc7913 | j_mayer | /* Create new timer */
|
720 | 8ecc7913 | j_mayer | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); |
721 | b172c56a | j_mayer | if (0) { |
722 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor decrementer
|
723 | b172c56a | j_mayer | */
|
724 | b172c56a | j_mayer | tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env); |
725 | b172c56a | j_mayer | } else {
|
726 | b172c56a | j_mayer | tb_env->hdecr_timer = NULL;
|
727 | b172c56a | j_mayer | } |
728 | 8ecc7913 | j_mayer | cpu_ppc_set_tb_clk(env, freq); |
729 | 9fddaa0c | bellard | |
730 | 8ecc7913 | j_mayer | return &cpu_ppc_set_tb_clk;
|
731 | 9fddaa0c | bellard | } |
732 | 9fddaa0c | bellard | |
733 | 76a66253 | j_mayer | /* Specific helpers for POWER & PowerPC 601 RTC */
|
734 | b1d8e52e | blueswir1 | #if 0
|
735 | b1d8e52e | blueswir1 | static clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)
|
736 | 76a66253 | j_mayer | {
|
737 | 76a66253 | j_mayer | return cpu_ppc_tb_init(env, 7812500);
|
738 | 76a66253 | j_mayer | }
|
739 | b1d8e52e | blueswir1 | #endif
|
740 | 76a66253 | j_mayer | |
741 | 76a66253 | j_mayer | void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
|
742 | 8a84de23 | j_mayer | { |
743 | 8a84de23 | j_mayer | _cpu_ppc_store_tbu(env, value); |
744 | 8a84de23 | j_mayer | } |
745 | 76a66253 | j_mayer | |
746 | 76a66253 | j_mayer | uint32_t cpu_ppc601_load_rtcu (CPUState *env) |
747 | 8a84de23 | j_mayer | { |
748 | 8a84de23 | j_mayer | return _cpu_ppc_load_tbu(env);
|
749 | 8a84de23 | j_mayer | } |
750 | 76a66253 | j_mayer | |
751 | 76a66253 | j_mayer | void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
|
752 | 76a66253 | j_mayer | { |
753 | 76a66253 | j_mayer | cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
|
754 | 76a66253 | j_mayer | } |
755 | 76a66253 | j_mayer | |
756 | 76a66253 | j_mayer | uint32_t cpu_ppc601_load_rtcl (CPUState *env) |
757 | 76a66253 | j_mayer | { |
758 | 76a66253 | j_mayer | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
759 | 76a66253 | j_mayer | } |
760 | 76a66253 | j_mayer | |
761 | 636aaad7 | j_mayer | /*****************************************************************************/
|
762 | 76a66253 | j_mayer | /* Embedded PowerPC timers */
|
763 | 636aaad7 | j_mayer | |
764 | 636aaad7 | j_mayer | /* PIT, FIT & WDT */
|
765 | c227f099 | Anthony Liguori | typedef struct ppcemb_timer_t ppcemb_timer_t; |
766 | c227f099 | Anthony Liguori | struct ppcemb_timer_t {
|
767 | 636aaad7 | j_mayer | uint64_t pit_reload; /* PIT auto-reload value */
|
768 | 636aaad7 | j_mayer | uint64_t fit_next; /* Tick for next FIT interrupt */
|
769 | 636aaad7 | j_mayer | struct QEMUTimer *fit_timer;
|
770 | 636aaad7 | j_mayer | uint64_t wdt_next; /* Tick for next WDT interrupt */
|
771 | 636aaad7 | j_mayer | struct QEMUTimer *wdt_timer;
|
772 | d63cb48d | Edgar E. Iglesias | |
773 | d63cb48d | Edgar E. Iglesias | /* 405 have the PIT, 440 have a DECR. */
|
774 | d63cb48d | Edgar E. Iglesias | unsigned int decr_excp; |
775 | 636aaad7 | j_mayer | }; |
776 | 3b46e624 | ths | |
777 | 636aaad7 | j_mayer | /* Fixed interval timer */
|
778 | 636aaad7 | j_mayer | static void cpu_4xx_fit_cb (void *opaque) |
779 | 636aaad7 | j_mayer | { |
780 | 636aaad7 | j_mayer | CPUState *env; |
781 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
782 | c227f099 | Anthony Liguori | ppcemb_timer_t *ppcemb_timer; |
783 | 636aaad7 | j_mayer | uint64_t now, next; |
784 | 636aaad7 | j_mayer | |
785 | 636aaad7 | j_mayer | env = opaque; |
786 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
787 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
788 | 636aaad7 | j_mayer | now = qemu_get_clock(vm_clock); |
789 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { |
790 | 636aaad7 | j_mayer | case 0: |
791 | 636aaad7 | j_mayer | next = 1 << 9; |
792 | 636aaad7 | j_mayer | break;
|
793 | 636aaad7 | j_mayer | case 1: |
794 | 636aaad7 | j_mayer | next = 1 << 13; |
795 | 636aaad7 | j_mayer | break;
|
796 | 636aaad7 | j_mayer | case 2: |
797 | 636aaad7 | j_mayer | next = 1 << 17; |
798 | 636aaad7 | j_mayer | break;
|
799 | 636aaad7 | j_mayer | case 3: |
800 | 636aaad7 | j_mayer | next = 1 << 21; |
801 | 636aaad7 | j_mayer | break;
|
802 | 636aaad7 | j_mayer | default:
|
803 | 636aaad7 | j_mayer | /* Cannot occur, but makes gcc happy */
|
804 | 636aaad7 | j_mayer | return;
|
805 | 636aaad7 | j_mayer | } |
806 | 6ee093c9 | Juan Quintela | next = now + muldiv64(next, get_ticks_per_sec(), tb_env->tb_freq); |
807 | 636aaad7 | j_mayer | if (next == now)
|
808 | 636aaad7 | j_mayer | next++; |
809 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->fit_timer, next); |
810 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 26; |
811 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) |
812 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
|
813 | 90e189ec | Blue Swirl | LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, |
814 | 90e189ec | Blue Swirl | (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), |
815 | 90e189ec | Blue Swirl | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
816 | 636aaad7 | j_mayer | } |
817 | 636aaad7 | j_mayer | |
818 | 636aaad7 | j_mayer | /* Programmable interval timer */
|
819 | c227f099 | Anthony Liguori | static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) |
820 | 76a66253 | j_mayer | { |
821 | c227f099 | Anthony Liguori | ppcemb_timer_t *ppcemb_timer; |
822 | 636aaad7 | j_mayer | uint64_t now, next; |
823 | 636aaad7 | j_mayer | |
824 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
825 | 4b6d0a4c | j_mayer | if (ppcemb_timer->pit_reload <= 1 || |
826 | 4b6d0a4c | j_mayer | !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || |
827 | 4b6d0a4c | j_mayer | (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { |
828 | 4b6d0a4c | j_mayer | /* Stop PIT */
|
829 | d12d51d5 | aliguori | LOG_TB("%s: stop PIT\n", __func__);
|
830 | 4b6d0a4c | j_mayer | qemu_del_timer(tb_env->decr_timer); |
831 | 4b6d0a4c | j_mayer | } else {
|
832 | d12d51d5 | aliguori | LOG_TB("%s: start PIT %016" PRIx64 "\n", |
833 | 4b6d0a4c | j_mayer | __func__, ppcemb_timer->pit_reload); |
834 | 4b6d0a4c | j_mayer | now = qemu_get_clock(vm_clock); |
835 | 636aaad7 | j_mayer | next = now + muldiv64(ppcemb_timer->pit_reload, |
836 | 6ee093c9 | Juan Quintela | get_ticks_per_sec(), tb_env->decr_freq); |
837 | 4b6d0a4c | j_mayer | if (is_excp)
|
838 | 4b6d0a4c | j_mayer | next += tb_env->decr_next - now; |
839 | 636aaad7 | j_mayer | if (next == now)
|
840 | 636aaad7 | j_mayer | next++; |
841 | 636aaad7 | j_mayer | qemu_mod_timer(tb_env->decr_timer, next); |
842 | 636aaad7 | j_mayer | tb_env->decr_next = next; |
843 | 636aaad7 | j_mayer | } |
844 | 4b6d0a4c | j_mayer | } |
845 | 4b6d0a4c | j_mayer | |
846 | 4b6d0a4c | j_mayer | static void cpu_4xx_pit_cb (void *opaque) |
847 | 4b6d0a4c | j_mayer | { |
848 | 4b6d0a4c | j_mayer | CPUState *env; |
849 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
850 | c227f099 | Anthony Liguori | ppcemb_timer_t *ppcemb_timer; |
851 | 4b6d0a4c | j_mayer | |
852 | 4b6d0a4c | j_mayer | env = opaque; |
853 | 4b6d0a4c | j_mayer | tb_env = env->tb_env; |
854 | 4b6d0a4c | j_mayer | ppcemb_timer = tb_env->opaque; |
855 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 27; |
856 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) |
857 | d63cb48d | Edgar E. Iglesias | ppc_set_irq(env, ppcemb_timer->decr_excp, 1);
|
858 | 4b6d0a4c | j_mayer | start_stop_pit(env, tb_env, 1);
|
859 | 90e189ec | Blue Swirl | LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " " |
860 | 90e189ec | Blue Swirl | "%016" PRIx64 "\n", __func__, |
861 | 90e189ec | Blue Swirl | (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), |
862 | 90e189ec | Blue Swirl | (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), |
863 | 90e189ec | Blue Swirl | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
864 | 90e189ec | Blue Swirl | ppcemb_timer->pit_reload); |
865 | 636aaad7 | j_mayer | } |
866 | 636aaad7 | j_mayer | |
867 | 636aaad7 | j_mayer | /* Watchdog timer */
|
868 | 636aaad7 | j_mayer | static void cpu_4xx_wdt_cb (void *opaque) |
869 | 636aaad7 | j_mayer | { |
870 | 636aaad7 | j_mayer | CPUState *env; |
871 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
872 | c227f099 | Anthony Liguori | ppcemb_timer_t *ppcemb_timer; |
873 | 636aaad7 | j_mayer | uint64_t now, next; |
874 | 636aaad7 | j_mayer | |
875 | 636aaad7 | j_mayer | env = opaque; |
876 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
877 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
878 | 636aaad7 | j_mayer | now = qemu_get_clock(vm_clock); |
879 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { |
880 | 636aaad7 | j_mayer | case 0: |
881 | 636aaad7 | j_mayer | next = 1 << 17; |
882 | 636aaad7 | j_mayer | break;
|
883 | 636aaad7 | j_mayer | case 1: |
884 | 636aaad7 | j_mayer | next = 1 << 21; |
885 | 636aaad7 | j_mayer | break;
|
886 | 636aaad7 | j_mayer | case 2: |
887 | 636aaad7 | j_mayer | next = 1 << 25; |
888 | 636aaad7 | j_mayer | break;
|
889 | 636aaad7 | j_mayer | case 3: |
890 | 636aaad7 | j_mayer | next = 1 << 29; |
891 | 636aaad7 | j_mayer | break;
|
892 | 636aaad7 | j_mayer | default:
|
893 | 636aaad7 | j_mayer | /* Cannot occur, but makes gcc happy */
|
894 | 636aaad7 | j_mayer | return;
|
895 | 636aaad7 | j_mayer | } |
896 | 6ee093c9 | Juan Quintela | next = now + muldiv64(next, get_ticks_per_sec(), tb_env->decr_freq); |
897 | 636aaad7 | j_mayer | if (next == now)
|
898 | 636aaad7 | j_mayer | next++; |
899 | 90e189ec | Blue Swirl | LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, |
900 | 90e189ec | Blue Swirl | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
901 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
902 | 636aaad7 | j_mayer | case 0x0: |
903 | 636aaad7 | j_mayer | case 0x1: |
904 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
905 | 636aaad7 | j_mayer | ppcemb_timer->wdt_next = next; |
906 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 31; |
907 | 636aaad7 | j_mayer | break;
|
908 | 636aaad7 | j_mayer | case 0x2: |
909 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
910 | 636aaad7 | j_mayer | ppcemb_timer->wdt_next = next; |
911 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 30; |
912 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) |
913 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
|
914 | 636aaad7 | j_mayer | break;
|
915 | 636aaad7 | j_mayer | case 0x3: |
916 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] &= ~0x30000000;
|
917 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
|
918 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { |
919 | 636aaad7 | j_mayer | case 0x0: |
920 | 636aaad7 | j_mayer | /* No reset */
|
921 | 636aaad7 | j_mayer | break;
|
922 | 636aaad7 | j_mayer | case 0x1: /* Core reset */ |
923 | 8ecc7913 | j_mayer | ppc40x_core_reset(env); |
924 | 8ecc7913 | j_mayer | break;
|
925 | 636aaad7 | j_mayer | case 0x2: /* Chip reset */ |
926 | 8ecc7913 | j_mayer | ppc40x_chip_reset(env); |
927 | 8ecc7913 | j_mayer | break;
|
928 | 636aaad7 | j_mayer | case 0x3: /* System reset */ |
929 | 8ecc7913 | j_mayer | ppc40x_system_reset(env); |
930 | 8ecc7913 | j_mayer | break;
|
931 | 636aaad7 | j_mayer | } |
932 | 636aaad7 | j_mayer | } |
933 | 76a66253 | j_mayer | } |
934 | 76a66253 | j_mayer | |
935 | 76a66253 | j_mayer | void store_40x_pit (CPUState *env, target_ulong val)
|
936 | 76a66253 | j_mayer | { |
937 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
938 | c227f099 | Anthony Liguori | ppcemb_timer_t *ppcemb_timer; |
939 | 636aaad7 | j_mayer | |
940 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
941 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
942 | 90e189ec | Blue Swirl | LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val); |
943 | 636aaad7 | j_mayer | ppcemb_timer->pit_reload = val; |
944 | 4b6d0a4c | j_mayer | start_stop_pit(env, tb_env, 0);
|
945 | 76a66253 | j_mayer | } |
946 | 76a66253 | j_mayer | |
947 | 636aaad7 | j_mayer | target_ulong load_40x_pit (CPUState *env) |
948 | 76a66253 | j_mayer | { |
949 | 636aaad7 | j_mayer | return cpu_ppc_load_decr(env);
|
950 | 76a66253 | j_mayer | } |
951 | 76a66253 | j_mayer | |
952 | 76a66253 | j_mayer | void store_booke_tsr (CPUState *env, target_ulong val)
|
953 | 76a66253 | j_mayer | { |
954 | d63cb48d | Edgar E. Iglesias | ppc_tb_t *tb_env = env->tb_env; |
955 | d63cb48d | Edgar E. Iglesias | ppcemb_timer_t *ppcemb_timer; |
956 | d63cb48d | Edgar E. Iglesias | |
957 | d63cb48d | Edgar E. Iglesias | ppcemb_timer = tb_env->opaque; |
958 | d63cb48d | Edgar E. Iglesias | |
959 | 90e189ec | Blue Swirl | LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val); |
960 | 4b6d0a4c | j_mayer | env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
|
961 | 4b6d0a4c | j_mayer | if (val & 0x80000000) |
962 | d63cb48d | Edgar E. Iglesias | ppc_set_irq(env, ppcemb_timer->decr_excp, 0);
|
963 | 636aaad7 | j_mayer | } |
964 | 636aaad7 | j_mayer | |
965 | 636aaad7 | j_mayer | void store_booke_tcr (CPUState *env, target_ulong val)
|
966 | 636aaad7 | j_mayer | { |
967 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
968 | 4b6d0a4c | j_mayer | |
969 | 4b6d0a4c | j_mayer | tb_env = env->tb_env; |
970 | 90e189ec | Blue Swirl | LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val); |
971 | 4b6d0a4c | j_mayer | env->spr[SPR_40x_TCR] = val & 0xFFC00000;
|
972 | 4b6d0a4c | j_mayer | start_stop_pit(env, tb_env, 1);
|
973 | 8ecc7913 | j_mayer | cpu_4xx_wdt_cb(env); |
974 | 636aaad7 | j_mayer | } |
975 | 636aaad7 | j_mayer | |
976 | 4b6d0a4c | j_mayer | static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq) |
977 | 4b6d0a4c | j_mayer | { |
978 | 4b6d0a4c | j_mayer | CPUState *env = opaque; |
979 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
980 | 4b6d0a4c | j_mayer | |
981 | d12d51d5 | aliguori | LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, |
982 | aae9366a | j_mayer | freq); |
983 | 4b6d0a4c | j_mayer | tb_env->tb_freq = freq; |
984 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
985 | 4b6d0a4c | j_mayer | /* XXX: we should also update all timers */
|
986 | 4b6d0a4c | j_mayer | } |
987 | 4b6d0a4c | j_mayer | |
988 | d63cb48d | Edgar E. Iglesias | clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq, |
989 | d63cb48d | Edgar E. Iglesias | unsigned int decr_excp) |
990 | 636aaad7 | j_mayer | { |
991 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
992 | c227f099 | Anthony Liguori | ppcemb_timer_t *ppcemb_timer; |
993 | 636aaad7 | j_mayer | |
994 | c227f099 | Anthony Liguori | tb_env = qemu_mallocz(sizeof(ppc_tb_t));
|
995 | 8ecc7913 | j_mayer | env->tb_env = tb_env; |
996 | c227f099 | Anthony Liguori | ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
|
997 | 8ecc7913 | j_mayer | tb_env->tb_freq = freq; |
998 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
999 | 636aaad7 | j_mayer | tb_env->opaque = ppcemb_timer; |
1000 | d12d51d5 | aliguori | LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); |
1001 | 636aaad7 | j_mayer | if (ppcemb_timer != NULL) { |
1002 | 636aaad7 | j_mayer | /* We use decr timer for PIT */
|
1003 | 636aaad7 | j_mayer | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); |
1004 | 636aaad7 | j_mayer | ppcemb_timer->fit_timer = |
1005 | 636aaad7 | j_mayer | qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env); |
1006 | 636aaad7 | j_mayer | ppcemb_timer->wdt_timer = |
1007 | 636aaad7 | j_mayer | qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env); |
1008 | d63cb48d | Edgar E. Iglesias | ppcemb_timer->decr_excp = decr_excp; |
1009 | 636aaad7 | j_mayer | } |
1010 | 8ecc7913 | j_mayer | |
1011 | 4b6d0a4c | j_mayer | return &ppc_emb_set_tb_clk;
|
1012 | 76a66253 | j_mayer | } |
1013 | 76a66253 | j_mayer | |
1014 | 2e719ba3 | j_mayer | /*****************************************************************************/
|
1015 | 2e719ba3 | j_mayer | /* Embedded PowerPC Device Control Registers */
|
1016 | c227f099 | Anthony Liguori | typedef struct ppc_dcrn_t ppc_dcrn_t; |
1017 | c227f099 | Anthony Liguori | struct ppc_dcrn_t {
|
1018 | 2e719ba3 | j_mayer | dcr_read_cb dcr_read; |
1019 | 2e719ba3 | j_mayer | dcr_write_cb dcr_write; |
1020 | 2e719ba3 | j_mayer | void *opaque;
|
1021 | 2e719ba3 | j_mayer | }; |
1022 | 2e719ba3 | j_mayer | |
1023 | a750fc0b | j_mayer | /* XXX: on 460, DCR addresses are 32 bits wide,
|
1024 | a750fc0b | j_mayer | * using DCRIPR to get the 22 upper bits of the DCR address
|
1025 | a750fc0b | j_mayer | */
|
1026 | 2e719ba3 | j_mayer | #define DCRN_NB 1024 |
1027 | c227f099 | Anthony Liguori | struct ppc_dcr_t {
|
1028 | c227f099 | Anthony Liguori | ppc_dcrn_t dcrn[DCRN_NB]; |
1029 | 2e719ba3 | j_mayer | int (*read_error)(int dcrn); |
1030 | 2e719ba3 | j_mayer | int (*write_error)(int dcrn); |
1031 | 2e719ba3 | j_mayer | }; |
1032 | 2e719ba3 | j_mayer | |
1033 | 73b01960 | Alexander Graf | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) |
1034 | 2e719ba3 | j_mayer | { |
1035 | c227f099 | Anthony Liguori | ppc_dcrn_t *dcr; |
1036 | 2e719ba3 | j_mayer | |
1037 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1038 | 2e719ba3 | j_mayer | goto error;
|
1039 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1040 | 2e719ba3 | j_mayer | if (dcr->dcr_read == NULL) |
1041 | 2e719ba3 | j_mayer | goto error;
|
1042 | 2e719ba3 | j_mayer | *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); |
1043 | 2e719ba3 | j_mayer | |
1044 | 2e719ba3 | j_mayer | return 0; |
1045 | 2e719ba3 | j_mayer | |
1046 | 2e719ba3 | j_mayer | error:
|
1047 | 2e719ba3 | j_mayer | if (dcr_env->read_error != NULL) |
1048 | 2e719ba3 | j_mayer | return (*dcr_env->read_error)(dcrn);
|
1049 | 2e719ba3 | j_mayer | |
1050 | 2e719ba3 | j_mayer | return -1; |
1051 | 2e719ba3 | j_mayer | } |
1052 | 2e719ba3 | j_mayer | |
1053 | 73b01960 | Alexander Graf | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) |
1054 | 2e719ba3 | j_mayer | { |
1055 | c227f099 | Anthony Liguori | ppc_dcrn_t *dcr; |
1056 | 2e719ba3 | j_mayer | |
1057 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1058 | 2e719ba3 | j_mayer | goto error;
|
1059 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1060 | 2e719ba3 | j_mayer | if (dcr->dcr_write == NULL) |
1061 | 2e719ba3 | j_mayer | goto error;
|
1062 | 2e719ba3 | j_mayer | (*dcr->dcr_write)(dcr->opaque, dcrn, val); |
1063 | 2e719ba3 | j_mayer | |
1064 | 2e719ba3 | j_mayer | return 0; |
1065 | 2e719ba3 | j_mayer | |
1066 | 2e719ba3 | j_mayer | error:
|
1067 | 2e719ba3 | j_mayer | if (dcr_env->write_error != NULL) |
1068 | 2e719ba3 | j_mayer | return (*dcr_env->write_error)(dcrn);
|
1069 | 2e719ba3 | j_mayer | |
1070 | 2e719ba3 | j_mayer | return -1; |
1071 | 2e719ba3 | j_mayer | } |
1072 | 2e719ba3 | j_mayer | |
1073 | 2e719ba3 | j_mayer | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
1074 | 2e719ba3 | j_mayer | dcr_read_cb dcr_read, dcr_write_cb dcr_write) |
1075 | 2e719ba3 | j_mayer | { |
1076 | c227f099 | Anthony Liguori | ppc_dcr_t *dcr_env; |
1077 | c227f099 | Anthony Liguori | ppc_dcrn_t *dcr; |
1078 | 2e719ba3 | j_mayer | |
1079 | 2e719ba3 | j_mayer | dcr_env = env->dcr_env; |
1080 | 2e719ba3 | j_mayer | if (dcr_env == NULL) |
1081 | 2e719ba3 | j_mayer | return -1; |
1082 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1083 | 2e719ba3 | j_mayer | return -1; |
1084 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1085 | 2e719ba3 | j_mayer | if (dcr->opaque != NULL || |
1086 | 2e719ba3 | j_mayer | dcr->dcr_read != NULL ||
|
1087 | 2e719ba3 | j_mayer | dcr->dcr_write != NULL)
|
1088 | 2e719ba3 | j_mayer | return -1; |
1089 | 2e719ba3 | j_mayer | dcr->opaque = opaque; |
1090 | 2e719ba3 | j_mayer | dcr->dcr_read = dcr_read; |
1091 | 2e719ba3 | j_mayer | dcr->dcr_write = dcr_write; |
1092 | 2e719ba3 | j_mayer | |
1093 | 2e719ba3 | j_mayer | return 0; |
1094 | 2e719ba3 | j_mayer | } |
1095 | 2e719ba3 | j_mayer | |
1096 | 2e719ba3 | j_mayer | int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), |
1097 | 2e719ba3 | j_mayer | int (*write_error)(int dcrn)) |
1098 | 2e719ba3 | j_mayer | { |
1099 | c227f099 | Anthony Liguori | ppc_dcr_t *dcr_env; |
1100 | 2e719ba3 | j_mayer | |
1101 | c227f099 | Anthony Liguori | dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
|
1102 | 2e719ba3 | j_mayer | dcr_env->read_error = read_error; |
1103 | 2e719ba3 | j_mayer | dcr_env->write_error = write_error; |
1104 | 2e719ba3 | j_mayer | env->dcr_env = dcr_env; |
1105 | 2e719ba3 | j_mayer | |
1106 | 2e719ba3 | j_mayer | return 0; |
1107 | 2e719ba3 | j_mayer | } |
1108 | 2e719ba3 | j_mayer | |
1109 | 64201201 | bellard | /*****************************************************************************/
|
1110 | 64201201 | bellard | /* Debug port */
|
1111 | fd0bbb12 | bellard | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
1112 | 64201201 | bellard | { |
1113 | 64201201 | bellard | addr &= 0xF;
|
1114 | 64201201 | bellard | switch (addr) {
|
1115 | 64201201 | bellard | case 0: |
1116 | 64201201 | bellard | printf("%c", val);
|
1117 | 64201201 | bellard | break;
|
1118 | 64201201 | bellard | case 1: |
1119 | 64201201 | bellard | printf("\n");
|
1120 | 64201201 | bellard | fflush(stdout); |
1121 | 64201201 | bellard | break;
|
1122 | 64201201 | bellard | case 2: |
1123 | aae9366a | j_mayer | printf("Set loglevel to %04" PRIx32 "\n", val); |
1124 | fd0bbb12 | bellard | cpu_set_log(val | 0x100);
|
1125 | 64201201 | bellard | break;
|
1126 | 64201201 | bellard | } |
1127 | 64201201 | bellard | } |
1128 | 64201201 | bellard | |
1129 | 64201201 | bellard | /*****************************************************************************/
|
1130 | 64201201 | bellard | /* NVRAM helpers */
|
1131 | c227f099 | Anthony Liguori | static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr) |
1132 | 64201201 | bellard | { |
1133 | 3cbee15b | j_mayer | return (*nvram->read_fn)(nvram->opaque, addr);;
|
1134 | 64201201 | bellard | } |
1135 | 64201201 | bellard | |
1136 | c227f099 | Anthony Liguori | static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val) |
1137 | 64201201 | bellard | { |
1138 | 3cbee15b | j_mayer | (*nvram->write_fn)(nvram->opaque, addr, val); |
1139 | 64201201 | bellard | } |
1140 | 64201201 | bellard | |
1141 | c227f099 | Anthony Liguori | void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value)
|
1142 | 64201201 | bellard | { |
1143 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value); |
1144 | 64201201 | bellard | } |
1145 | 64201201 | bellard | |
1146 | c227f099 | Anthony Liguori | uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr) |
1147 | 3cbee15b | j_mayer | { |
1148 | 3cbee15b | j_mayer | return nvram_read(nvram, addr);
|
1149 | 3cbee15b | j_mayer | } |
1150 | 3cbee15b | j_mayer | |
1151 | c227f099 | Anthony Liguori | void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value)
|
1152 | 3cbee15b | j_mayer | { |
1153 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value >> 8);
|
1154 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 1, value & 0xFF); |
1155 | 3cbee15b | j_mayer | } |
1156 | 3cbee15b | j_mayer | |
1157 | c227f099 | Anthony Liguori | uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr) |
1158 | 64201201 | bellard | { |
1159 | 64201201 | bellard | uint16_t tmp; |
1160 | 64201201 | bellard | |
1161 | 3cbee15b | j_mayer | tmp = nvram_read(nvram, addr) << 8;
|
1162 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 1);
|
1163 | 3cbee15b | j_mayer | |
1164 | 64201201 | bellard | return tmp;
|
1165 | 64201201 | bellard | } |
1166 | 64201201 | bellard | |
1167 | c227f099 | Anthony Liguori | void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value)
|
1168 | 64201201 | bellard | { |
1169 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value >> 24);
|
1170 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); |
1171 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); |
1172 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 3, value & 0xFF); |
1173 | 64201201 | bellard | } |
1174 | 64201201 | bellard | |
1175 | c227f099 | Anthony Liguori | uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) |
1176 | 64201201 | bellard | { |
1177 | 64201201 | bellard | uint32_t tmp; |
1178 | 64201201 | bellard | |
1179 | 3cbee15b | j_mayer | tmp = nvram_read(nvram, addr) << 24;
|
1180 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 1) << 16; |
1181 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 2) << 8; |
1182 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 3);
|
1183 | 76a66253 | j_mayer | |
1184 | 64201201 | bellard | return tmp;
|
1185 | 64201201 | bellard | } |
1186 | 64201201 | bellard | |
1187 | c227f099 | Anthony Liguori | void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
|
1188 | b55266b5 | blueswir1 | const char *str, uint32_t max) |
1189 | 64201201 | bellard | { |
1190 | 64201201 | bellard | int i;
|
1191 | 64201201 | bellard | |
1192 | 64201201 | bellard | for (i = 0; i < max && str[i] != '\0'; i++) { |
1193 | 3cbee15b | j_mayer | nvram_write(nvram, addr + i, str[i]); |
1194 | 64201201 | bellard | } |
1195 | 3cbee15b | j_mayer | nvram_write(nvram, addr + i, str[i]); |
1196 | 3cbee15b | j_mayer | nvram_write(nvram, addr + max - 1, '\0'); |
1197 | 64201201 | bellard | } |
1198 | 64201201 | bellard | |
1199 | c227f099 | Anthony Liguori | int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max) |
1200 | 64201201 | bellard | { |
1201 | 64201201 | bellard | int i;
|
1202 | 64201201 | bellard | |
1203 | 64201201 | bellard | memset(dst, 0, max);
|
1204 | 64201201 | bellard | for (i = 0; i < max; i++) { |
1205 | 64201201 | bellard | dst[i] = NVRAM_get_byte(nvram, addr + i); |
1206 | 64201201 | bellard | if (dst[i] == '\0') |
1207 | 64201201 | bellard | break;
|
1208 | 64201201 | bellard | } |
1209 | 64201201 | bellard | |
1210 | 64201201 | bellard | return i;
|
1211 | 64201201 | bellard | } |
1212 | 64201201 | bellard | |
1213 | 64201201 | bellard | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
|
1214 | 64201201 | bellard | { |
1215 | 64201201 | bellard | uint16_t tmp; |
1216 | 64201201 | bellard | uint16_t pd, pd1, pd2; |
1217 | 64201201 | bellard | |
1218 | 64201201 | bellard | tmp = prev >> 8;
|
1219 | 64201201 | bellard | pd = prev ^ value; |
1220 | 64201201 | bellard | pd1 = pd & 0x000F;
|
1221 | 64201201 | bellard | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
1222 | 64201201 | bellard | tmp ^= (pd1 << 3) | (pd1 << 8); |
1223 | 64201201 | bellard | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
1224 | 64201201 | bellard | |
1225 | 64201201 | bellard | return tmp;
|
1226 | 64201201 | bellard | } |
1227 | 64201201 | bellard | |
1228 | c227f099 | Anthony Liguori | static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count)
|
1229 | 64201201 | bellard | { |
1230 | 64201201 | bellard | uint32_t i; |
1231 | 64201201 | bellard | uint16_t crc = 0xFFFF;
|
1232 | 64201201 | bellard | int odd;
|
1233 | 64201201 | bellard | |
1234 | 64201201 | bellard | odd = count & 1;
|
1235 | 64201201 | bellard | count &= ~1;
|
1236 | 64201201 | bellard | for (i = 0; i != count; i++) { |
1237 | 76a66253 | j_mayer | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
1238 | 64201201 | bellard | } |
1239 | 64201201 | bellard | if (odd) {
|
1240 | 76a66253 | j_mayer | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
|
1241 | 64201201 | bellard | } |
1242 | 64201201 | bellard | |
1243 | 64201201 | bellard | return crc;
|
1244 | 64201201 | bellard | } |
1245 | 64201201 | bellard | |
1246 | fd0bbb12 | bellard | #define CMDLINE_ADDR 0x017ff000 |
1247 | fd0bbb12 | bellard | |
1248 | c227f099 | Anthony Liguori | int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
|
1249 | b55266b5 | blueswir1 | const char *arch, |
1250 | 64201201 | bellard | uint32_t RAM_size, int boot_device,
|
1251 | 64201201 | bellard | uint32_t kernel_image, uint32_t kernel_size, |
1252 | fd0bbb12 | bellard | const char *cmdline, |
1253 | 64201201 | bellard | uint32_t initrd_image, uint32_t initrd_size, |
1254 | fd0bbb12 | bellard | uint32_t NVRAM_image, |
1255 | fd0bbb12 | bellard | int width, int height, int depth) |
1256 | 64201201 | bellard | { |
1257 | 64201201 | bellard | uint16_t crc; |
1258 | 64201201 | bellard | |
1259 | 64201201 | bellard | /* Set parameters for Open Hack'Ware BIOS */
|
1260 | 64201201 | bellard | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
1261 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
1262 | 64201201 | bellard | NVRAM_set_word(nvram, 0x14, NVRAM_size);
|
1263 | 64201201 | bellard | NVRAM_set_string(nvram, 0x20, arch, 16); |
1264 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x30, RAM_size);
|
1265 | 64201201 | bellard | NVRAM_set_byte(nvram, 0x34, boot_device);
|
1266 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x38, kernel_image);
|
1267 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x3C, kernel_size);
|
1268 | fd0bbb12 | bellard | if (cmdline) {
|
1269 | fd0bbb12 | bellard | /* XXX: put the cmdline in NVRAM too ? */
|
1270 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline);
|
1271 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
1272 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
|
1273 | fd0bbb12 | bellard | } else {
|
1274 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, 0); |
1275 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, 0); |
1276 | fd0bbb12 | bellard | } |
1277 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x48, initrd_image);
|
1278 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x4C, initrd_size);
|
1279 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x50, NVRAM_image);
|
1280 | fd0bbb12 | bellard | |
1281 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x54, width);
|
1282 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x56, height);
|
1283 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x58, depth);
|
1284 | fd0bbb12 | bellard | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
1285 | 3cbee15b | j_mayer | NVRAM_set_word(nvram, 0xFC, crc);
|
1286 | 64201201 | bellard | |
1287 | 64201201 | bellard | return 0; |
1288 | a541f297 | bellard | } |