root / target-sparc / cpu.h @ 86f1f2ae
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1 | 7a3f1944 | bellard | #ifndef CPU_SPARC_H
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2 | 7a3f1944 | bellard | #define CPU_SPARC_H
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3 | 7a3f1944 | bellard | |
4 | af7bf89b | bellard | #include "config.h" |
5 | 047b39e4 | Stefan Weil | #include "qemu-common.h" |
6 | af7bf89b | bellard | |
7 | af7bf89b | bellard | #if !defined(TARGET_SPARC64)
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8 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
9 | af7bf89b | bellard | #define TARGET_FPREGS 32 |
10 | 83469015 | bellard | #define TARGET_PAGE_BITS 12 /* 4k */ |
11 | 058ed88c | Richard Henderson | #define TARGET_PHYS_ADDR_SPACE_BITS 36 |
12 | 058ed88c | Richard Henderson | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
13 | 058ed88c | Richard Henderson | #else
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14 | 058ed88c | Richard Henderson | #define TARGET_LONG_BITS 64 |
15 | 058ed88c | Richard Henderson | #define TARGET_FPREGS 64 |
16 | 058ed88c | Richard Henderson | #define TARGET_PAGE_BITS 13 /* 8k */ |
17 | 52705890 | Richard Henderson | #define TARGET_PHYS_ADDR_SPACE_BITS 41 |
18 | 52705890 | Richard Henderson | # ifdef TARGET_ABI32
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19 | 52705890 | Richard Henderson | # define TARGET_VIRT_ADDR_SPACE_BITS 32 |
20 | 52705890 | Richard Henderson | # else
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21 | 52705890 | Richard Henderson | # define TARGET_VIRT_ADDR_SPACE_BITS 44 |
22 | 52705890 | Richard Henderson | # endif
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23 | af7bf89b | bellard | #endif
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24 | 3cf1e035 | bellard | |
25 | c2764719 | pbrook | #define CPUState struct CPUSPARCState |
26 | c2764719 | pbrook | |
27 | 7a3f1944 | bellard | #include "cpu-defs.h" |
28 | 7a3f1944 | bellard | |
29 | 7a0e1f41 | bellard | #include "softfloat.h" |
30 | 7a0e1f41 | bellard | |
31 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
32 | 1fddef4b | bellard | |
33 | 9042c0e2 | ths | #if !defined(TARGET_SPARC64)
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34 | 0f8a249a | blueswir1 | #define ELF_MACHINE EM_SPARC
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35 | 9042c0e2 | ths | #else
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36 | 0f8a249a | blueswir1 | #define ELF_MACHINE EM_SPARCV9
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37 | 9042c0e2 | ths | #endif
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38 | 9042c0e2 | ths | |
39 | 7a3f1944 | bellard | /*#define EXCP_INTERRUPT 0x100*/
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40 | 7a3f1944 | bellard | |
41 | cf495bcf | bellard | /* trap definitions */
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42 | 3475187d | bellard | #ifndef TARGET_SPARC64
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43 | 878d3096 | bellard | #define TT_TFAULT 0x01 |
44 | cf495bcf | bellard | #define TT_ILL_INSN 0x02 |
45 | e8af50a3 | bellard | #define TT_PRIV_INSN 0x03 |
46 | e80cfcfc | bellard | #define TT_NFPU_INSN 0x04 |
47 | cf495bcf | bellard | #define TT_WIN_OVF 0x05 |
48 | 5fafdf24 | ths | #define TT_WIN_UNF 0x06 |
49 | d2889a3e | blueswir1 | #define TT_UNALIGNED 0x07 |
50 | e8af50a3 | bellard | #define TT_FP_EXCP 0x08 |
51 | 878d3096 | bellard | #define TT_DFAULT 0x09 |
52 | e32f879d | blueswir1 | #define TT_TOVF 0x0a |
53 | 878d3096 | bellard | #define TT_EXTINT 0x10 |
54 | 1b2e93c1 | blueswir1 | #define TT_CODE_ACCESS 0x21 |
55 | 64a88d5d | blueswir1 | #define TT_UNIMP_FLUSH 0x25 |
56 | b4f0a316 | blueswir1 | #define TT_DATA_ACCESS 0x29 |
57 | cf495bcf | bellard | #define TT_DIV_ZERO 0x2a |
58 | fcc72045 | blueswir1 | #define TT_NCP_INSN 0x24 |
59 | cf495bcf | bellard | #define TT_TRAP 0x80 |
60 | 3475187d | bellard | #else
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61 | 8194f35a | Igor Kovalenko | #define TT_POWER_ON_RESET 0x01 |
62 | 3475187d | bellard | #define TT_TFAULT 0x08 |
63 | 1b2e93c1 | blueswir1 | #define TT_CODE_ACCESS 0x0a |
64 | 3475187d | bellard | #define TT_ILL_INSN 0x10 |
65 | 64a88d5d | blueswir1 | #define TT_UNIMP_FLUSH TT_ILL_INSN
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66 | 3475187d | bellard | #define TT_PRIV_INSN 0x11 |
67 | 3475187d | bellard | #define TT_NFPU_INSN 0x20 |
68 | 3475187d | bellard | #define TT_FP_EXCP 0x21 |
69 | e32f879d | blueswir1 | #define TT_TOVF 0x23 |
70 | 3475187d | bellard | #define TT_CLRWIN 0x24 |
71 | 3475187d | bellard | #define TT_DIV_ZERO 0x28 |
72 | 3475187d | bellard | #define TT_DFAULT 0x30 |
73 | b4f0a316 | blueswir1 | #define TT_DATA_ACCESS 0x32 |
74 | d2889a3e | blueswir1 | #define TT_UNALIGNED 0x34 |
75 | 83469015 | bellard | #define TT_PRIV_ACT 0x37 |
76 | 3475187d | bellard | #define TT_EXTINT 0x40 |
77 | 74b9decc | blueswir1 | #define TT_IVEC 0x60 |
78 | e19e4efe | blueswir1 | #define TT_TMISS 0x64 |
79 | e19e4efe | blueswir1 | #define TT_DMISS 0x68 |
80 | 74b9decc | blueswir1 | #define TT_DPROT 0x6c |
81 | 3475187d | bellard | #define TT_SPILL 0x80 |
82 | 3475187d | bellard | #define TT_FILL 0xc0 |
83 | 88c8e03f | Igor V. Kovalenko | #define TT_WOTHER (1 << 5) |
84 | 3475187d | bellard | #define TT_TRAP 0x100 |
85 | 3475187d | bellard | #endif
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86 | 7a3f1944 | bellard | |
87 | 4b8b8b76 | blueswir1 | #define PSR_NEG_SHIFT 23 |
88 | 4b8b8b76 | blueswir1 | #define PSR_NEG (1 << PSR_NEG_SHIFT) |
89 | 4b8b8b76 | blueswir1 | #define PSR_ZERO_SHIFT 22 |
90 | 4b8b8b76 | blueswir1 | #define PSR_ZERO (1 << PSR_ZERO_SHIFT) |
91 | 4b8b8b76 | blueswir1 | #define PSR_OVF_SHIFT 21 |
92 | 4b8b8b76 | blueswir1 | #define PSR_OVF (1 << PSR_OVF_SHIFT) |
93 | 4b8b8b76 | blueswir1 | #define PSR_CARRY_SHIFT 20 |
94 | 4b8b8b76 | blueswir1 | #define PSR_CARRY (1 << PSR_CARRY_SHIFT) |
95 | e8af50a3 | bellard | #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
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96 | 2aae2b8e | Igor V. Kovalenko | #if !defined(TARGET_SPARC64)
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97 | e80cfcfc | bellard | #define PSR_EF (1<<12) |
98 | e80cfcfc | bellard | #define PSR_PIL 0xf00 |
99 | e8af50a3 | bellard | #define PSR_S (1<<7) |
100 | e8af50a3 | bellard | #define PSR_PS (1<<6) |
101 | e8af50a3 | bellard | #define PSR_ET (1<<5) |
102 | e8af50a3 | bellard | #define PSR_CWP 0x1f |
103 | 2aae2b8e | Igor V. Kovalenko | #endif
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104 | e8af50a3 | bellard | |
105 | 8393617c | Blue Swirl | #define CC_SRC (env->cc_src)
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106 | 8393617c | Blue Swirl | #define CC_SRC2 (env->cc_src2)
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107 | 8393617c | Blue Swirl | #define CC_DST (env->cc_dst)
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108 | 8393617c | Blue Swirl | #define CC_OP (env->cc_op)
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109 | 8393617c | Blue Swirl | |
110 | 8393617c | Blue Swirl | enum {
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111 | 8393617c | Blue Swirl | CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
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112 | 8393617c | Blue Swirl | CC_OP_FLAGS, /* all cc are back in status register */
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113 | 8393617c | Blue Swirl | CC_OP_DIV, /* modify N, Z and V, C = 0*/
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114 | 8393617c | Blue Swirl | CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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115 | 8393617c | Blue Swirl | CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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116 | 8393617c | Blue Swirl | CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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117 | 8393617c | Blue Swirl | CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
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118 | 8393617c | Blue Swirl | CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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119 | 8393617c | Blue Swirl | CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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120 | 8393617c | Blue Swirl | CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
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121 | 8393617c | Blue Swirl | CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
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122 | 8393617c | Blue Swirl | CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */
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123 | 8393617c | Blue Swirl | CC_OP_NB, |
124 | 8393617c | Blue Swirl | }; |
125 | 8393617c | Blue Swirl | |
126 | e8af50a3 | bellard | /* Trap base register */
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127 | e8af50a3 | bellard | #define TBR_BASE_MASK 0xfffff000 |
128 | e8af50a3 | bellard | |
129 | 3475187d | bellard | #if defined(TARGET_SPARC64)
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130 | 5210977a | Igor Kovalenko | #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ |
131 | 5210977a | Igor Kovalenko | #define PS_IG (1<<11) /* v9, zero on UA2007 */ |
132 | 5210977a | Igor Kovalenko | #define PS_MG (1<<10) /* v9, zero on UA2007 */ |
133 | 5210977a | Igor Kovalenko | #define PS_CLE (1<<9) /* UA2007 */ |
134 | 5210977a | Igor Kovalenko | #define PS_TLE (1<<8) /* UA2007 */ |
135 | 6ef905f6 | blueswir1 | #define PS_RMO (1<<7) |
136 | 5210977a | Igor Kovalenko | #define PS_RED (1<<5) /* v9, zero on UA2007 */ |
137 | 5210977a | Igor Kovalenko | #define PS_PEF (1<<4) /* enable fpu */ |
138 | 5210977a | Igor Kovalenko | #define PS_AM (1<<3) /* address mask */ |
139 | 3475187d | bellard | #define PS_PRIV (1<<2) |
140 | 3475187d | bellard | #define PS_IE (1<<1) |
141 | 5210977a | Igor Kovalenko | #define PS_AG (1<<0) /* v9, zero on UA2007 */ |
142 | a80dde08 | bellard | |
143 | a80dde08 | bellard | #define FPRS_FEF (1<<2) |
144 | 6f27aba6 | blueswir1 | |
145 | 6f27aba6 | blueswir1 | #define HS_PRIV (1<<2) |
146 | 3475187d | bellard | #endif
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147 | 3475187d | bellard | |
148 | e8af50a3 | bellard | /* Fcc */
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149 | ba6a9d8c | blueswir1 | #define FSR_RD1 (1ULL << 31) |
150 | ba6a9d8c | blueswir1 | #define FSR_RD0 (1ULL << 30) |
151 | e8af50a3 | bellard | #define FSR_RD_MASK (FSR_RD1 | FSR_RD0)
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152 | e8af50a3 | bellard | #define FSR_RD_NEAREST 0 |
153 | e8af50a3 | bellard | #define FSR_RD_ZERO FSR_RD0
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154 | e8af50a3 | bellard | #define FSR_RD_POS FSR_RD1
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155 | e8af50a3 | bellard | #define FSR_RD_NEG (FSR_RD1 | FSR_RD0)
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156 | e8af50a3 | bellard | |
157 | ba6a9d8c | blueswir1 | #define FSR_NVM (1ULL << 27) |
158 | ba6a9d8c | blueswir1 | #define FSR_OFM (1ULL << 26) |
159 | ba6a9d8c | blueswir1 | #define FSR_UFM (1ULL << 25) |
160 | ba6a9d8c | blueswir1 | #define FSR_DZM (1ULL << 24) |
161 | ba6a9d8c | blueswir1 | #define FSR_NXM (1ULL << 23) |
162 | e8af50a3 | bellard | #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
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163 | e8af50a3 | bellard | |
164 | ba6a9d8c | blueswir1 | #define FSR_NVA (1ULL << 9) |
165 | ba6a9d8c | blueswir1 | #define FSR_OFA (1ULL << 8) |
166 | ba6a9d8c | blueswir1 | #define FSR_UFA (1ULL << 7) |
167 | ba6a9d8c | blueswir1 | #define FSR_DZA (1ULL << 6) |
168 | ba6a9d8c | blueswir1 | #define FSR_NXA (1ULL << 5) |
169 | e8af50a3 | bellard | #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
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170 | e8af50a3 | bellard | |
171 | ba6a9d8c | blueswir1 | #define FSR_NVC (1ULL << 4) |
172 | ba6a9d8c | blueswir1 | #define FSR_OFC (1ULL << 3) |
173 | ba6a9d8c | blueswir1 | #define FSR_UFC (1ULL << 2) |
174 | ba6a9d8c | blueswir1 | #define FSR_DZC (1ULL << 1) |
175 | ba6a9d8c | blueswir1 | #define FSR_NXC (1ULL << 0) |
176 | e8af50a3 | bellard | #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
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177 | e8af50a3 | bellard | |
178 | ba6a9d8c | blueswir1 | #define FSR_FTT2 (1ULL << 16) |
179 | ba6a9d8c | blueswir1 | #define FSR_FTT1 (1ULL << 15) |
180 | ba6a9d8c | blueswir1 | #define FSR_FTT0 (1ULL << 14) |
181 | 47ad35f1 | blueswir1 | //gcc warns about constant overflow for ~FSR_FTT_MASK
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182 | 47ad35f1 | blueswir1 | //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
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183 | 47ad35f1 | blueswir1 | #ifdef TARGET_SPARC64
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184 | 47ad35f1 | blueswir1 | #define FSR_FTT_NMASK 0xfffffffffffe3fffULL |
185 | 47ad35f1 | blueswir1 | #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL |
186 | 3a3b925d | blueswir1 | #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL |
187 | 3a3b925d | blueswir1 | #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL |
188 | 3a3b925d | blueswir1 | #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL |
189 | 47ad35f1 | blueswir1 | #else
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190 | 47ad35f1 | blueswir1 | #define FSR_FTT_NMASK 0xfffe3fffULL |
191 | 47ad35f1 | blueswir1 | #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL |
192 | 3a3b925d | blueswir1 | #define FSR_LDFSR_OLDMASK 0x000fc000ULL |
193 | 47ad35f1 | blueswir1 | #endif
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194 | 3a3b925d | blueswir1 | #define FSR_LDFSR_MASK 0xcfc00fffULL |
195 | ba6a9d8c | blueswir1 | #define FSR_FTT_IEEE_EXCP (1ULL << 14) |
196 | ba6a9d8c | blueswir1 | #define FSR_FTT_UNIMPFPOP (3ULL << 14) |
197 | ba6a9d8c | blueswir1 | #define FSR_FTT_SEQ_ERROR (4ULL << 14) |
198 | ba6a9d8c | blueswir1 | #define FSR_FTT_INVAL_FPR (6ULL << 14) |
199 | e8af50a3 | bellard | |
200 | 4b8b8b76 | blueswir1 | #define FSR_FCC1_SHIFT 11 |
201 | ba6a9d8c | blueswir1 | #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) |
202 | 4b8b8b76 | blueswir1 | #define FSR_FCC0_SHIFT 10 |
203 | ba6a9d8c | blueswir1 | #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) |
204 | e8af50a3 | bellard | |
205 | e8af50a3 | bellard | /* MMU */
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206 | 0f8a249a | blueswir1 | #define MMU_E (1<<0) |
207 | 0f8a249a | blueswir1 | #define MMU_NF (1<<1) |
208 | e8af50a3 | bellard | |
209 | e8af50a3 | bellard | #define PTE_ENTRYTYPE_MASK 3 |
210 | e8af50a3 | bellard | #define PTE_ACCESS_MASK 0x1c |
211 | e8af50a3 | bellard | #define PTE_ACCESS_SHIFT 2 |
212 | 8d5f07fa | bellard | #define PTE_PPN_SHIFT 7 |
213 | e8af50a3 | bellard | #define PTE_ADDR_MASK 0xffffff00 |
214 | e8af50a3 | bellard | |
215 | 0f8a249a | blueswir1 | #define PG_ACCESSED_BIT 5 |
216 | 0f8a249a | blueswir1 | #define PG_MODIFIED_BIT 6 |
217 | e8af50a3 | bellard | #define PG_CACHE_BIT 7 |
218 | e8af50a3 | bellard | |
219 | e8af50a3 | bellard | #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) |
220 | e8af50a3 | bellard | #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) |
221 | e8af50a3 | bellard | #define PG_CACHE_MASK (1 << PG_CACHE_BIT) |
222 | e8af50a3 | bellard | |
223 | 1a14026e | blueswir1 | /* 3 <= NWINDOWS <= 32. */
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224 | 1a14026e | blueswir1 | #define MIN_NWINDOWS 3 |
225 | 1a14026e | blueswir1 | #define MAX_NWINDOWS 32 |
226 | cf495bcf | bellard | |
227 | 6f27aba6 | blueswir1 | #if !defined(TARGET_SPARC64)
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228 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
229 | 6f27aba6 | blueswir1 | #else
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230 | 2065061e | Igor V. Kovalenko | #define NB_MMU_MODES 6 |
231 | 375ee38b | blueswir1 | typedef struct trap_state { |
232 | 375ee38b | blueswir1 | uint64_t tpc; |
233 | 375ee38b | blueswir1 | uint64_t tnpc; |
234 | 375ee38b | blueswir1 | uint64_t tstate; |
235 | 375ee38b | blueswir1 | uint32_t tt; |
236 | 375ee38b | blueswir1 | } trap_state; |
237 | 6f27aba6 | blueswir1 | #endif
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238 | 6ebbf390 | j_mayer | |
239 | 5578ceab | blueswir1 | typedef struct sparc_def_t { |
240 | 5578ceab | blueswir1 | const char *name; |
241 | 5578ceab | blueswir1 | target_ulong iu_version; |
242 | 5578ceab | blueswir1 | uint32_t fpu_version; |
243 | 5578ceab | blueswir1 | uint32_t mmu_version; |
244 | 5578ceab | blueswir1 | uint32_t mmu_bm; |
245 | 5578ceab | blueswir1 | uint32_t mmu_ctpr_mask; |
246 | 5578ceab | blueswir1 | uint32_t mmu_cxr_mask; |
247 | 5578ceab | blueswir1 | uint32_t mmu_sfsr_mask; |
248 | 5578ceab | blueswir1 | uint32_t mmu_trcr_mask; |
249 | 963262de | blueswir1 | uint32_t mxcc_version; |
250 | 5578ceab | blueswir1 | uint32_t features; |
251 | 5578ceab | blueswir1 | uint32_t nwindows; |
252 | 5578ceab | blueswir1 | uint32_t maxtl; |
253 | 5578ceab | blueswir1 | } sparc_def_t; |
254 | 5578ceab | blueswir1 | |
255 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_FLOAT (1 << 0) |
256 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_FLOAT128 (1 << 1) |
257 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_SWAP (1 << 2) |
258 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_MUL (1 << 3) |
259 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_DIV (1 << 4) |
260 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_FLUSH (1 << 5) |
261 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_FSQRT (1 << 6) |
262 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_FMUL (1 << 7) |
263 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_VIS1 (1 << 8) |
264 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_VIS2 (1 << 9) |
265 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_FSMULD (1 << 10) |
266 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_HYPV (1 << 11) |
267 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_CMT (1 << 12) |
268 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_GL (1 << 13) |
269 | b04d9890 | Fabien Chouteau | #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */ |
270 | 4a2ba232 | Fabien Chouteau | #define CPU_FEATURE_ASR17 (1 << 15) |
271 | 60f356e8 | Fabien Chouteau | #define CPU_FEATURE_CACHE_CTRL (1 << 16) |
272 | 60f356e8 | Fabien Chouteau | |
273 | 5578ceab | blueswir1 | #ifndef TARGET_SPARC64
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274 | 5578ceab | blueswir1 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
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275 | 5578ceab | blueswir1 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ |
276 | 5578ceab | blueswir1 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ |
277 | 5578ceab | blueswir1 | CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) |
278 | 5578ceab | blueswir1 | #else
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279 | 5578ceab | blueswir1 | #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
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280 | 5578ceab | blueswir1 | CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ |
281 | 5578ceab | blueswir1 | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ |
282 | 5578ceab | blueswir1 | CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ |
283 | 5578ceab | blueswir1 | CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD) |
284 | 5578ceab | blueswir1 | enum {
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285 | 5578ceab | blueswir1 | mmu_us_12, // Ultrasparc < III (64 entry TLB)
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286 | 5578ceab | blueswir1 | mmu_us_3, // Ultrasparc III (512 entry TLB)
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287 | 5578ceab | blueswir1 | mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages)
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288 | 5578ceab | blueswir1 | mmu_sun4v, // T1, T2
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289 | 5578ceab | blueswir1 | }; |
290 | 5578ceab | blueswir1 | #endif
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291 | 5578ceab | blueswir1 | |
292 | f707726e | Igor Kovalenko | #define TTE_VALID_BIT (1ULL << 63) |
293 | f707726e | Igor Kovalenko | #define TTE_USED_BIT (1ULL << 41) |
294 | f707726e | Igor Kovalenko | #define TTE_LOCKED_BIT (1ULL << 6) |
295 | 2a90358f | Blue Swirl | #define TTE_GLOBAL_BIT (1ULL << 0) |
296 | f707726e | Igor Kovalenko | |
297 | f707726e | Igor Kovalenko | #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT)
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298 | f707726e | Igor Kovalenko | #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT)
|
299 | f707726e | Igor Kovalenko | #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT)
|
300 | 2a90358f | Blue Swirl | #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT)
|
301 | f707726e | Igor Kovalenko | |
302 | f707726e | Igor Kovalenko | #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT)
|
303 | f707726e | Igor Kovalenko | #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
|
304 | f707726e | Igor Kovalenko | |
305 | 6e8e7d4c | Igor Kovalenko | typedef struct SparcTLBEntry { |
306 | 6e8e7d4c | Igor Kovalenko | uint64_t tag; |
307 | 6e8e7d4c | Igor Kovalenko | uint64_t tte; |
308 | 6e8e7d4c | Igor Kovalenko | } SparcTLBEntry; |
309 | 6e8e7d4c | Igor Kovalenko | |
310 | 8f4efc55 | Igor V. Kovalenko | struct CPUTimer
|
311 | 8f4efc55 | Igor V. Kovalenko | { |
312 | 8f4efc55 | Igor V. Kovalenko | const char *name; |
313 | 8f4efc55 | Igor V. Kovalenko | uint32_t frequency; |
314 | 8f4efc55 | Igor V. Kovalenko | uint32_t disabled; |
315 | 8f4efc55 | Igor V. Kovalenko | uint64_t disabled_mask; |
316 | 8f4efc55 | Igor V. Kovalenko | int64_t clock_offset; |
317 | 8f4efc55 | Igor V. Kovalenko | struct QEMUTimer *qtimer;
|
318 | 8f4efc55 | Igor V. Kovalenko | }; |
319 | 8f4efc55 | Igor V. Kovalenko | |
320 | 8f4efc55 | Igor V. Kovalenko | typedef struct CPUTimer CPUTimer; |
321 | 8f4efc55 | Igor V. Kovalenko | |
322 | 8f4efc55 | Igor V. Kovalenko | struct QEMUFile;
|
323 | 8f4efc55 | Igor V. Kovalenko | void cpu_put_timer(struct QEMUFile *f, CPUTimer *s); |
324 | 8f4efc55 | Igor V. Kovalenko | void cpu_get_timer(struct QEMUFile *f, CPUTimer *s); |
325 | 8f4efc55 | Igor V. Kovalenko | |
326 | 7a3f1944 | bellard | typedef struct CPUSPARCState { |
327 | af7bf89b | bellard | target_ulong gregs[8]; /* general registers */ |
328 | af7bf89b | bellard | target_ulong *regwptr; /* pointer to current register window */
|
329 | af7bf89b | bellard | target_ulong pc; /* program counter */
|
330 | af7bf89b | bellard | target_ulong npc; /* next program counter */
|
331 | af7bf89b | bellard | target_ulong y; /* multiply/divide register */
|
332 | dc99a3f2 | blueswir1 | |
333 | dc99a3f2 | blueswir1 | /* emulator internal flags handling */
|
334 | d9bdab86 | blueswir1 | target_ulong cc_src, cc_src2; |
335 | dc99a3f2 | blueswir1 | target_ulong cc_dst; |
336 | 8393617c | Blue Swirl | uint32_t cc_op; |
337 | dc99a3f2 | blueswir1 | |
338 | 7c60cc4b | bellard | target_ulong t0, t1; /* temporaries live across basic blocks */
|
339 | 7c60cc4b | bellard | target_ulong cond; /* conditional branch result (XXX: save it in a
|
340 | 7c60cc4b | bellard | temporary register when possible) */
|
341 | 7c60cc4b | bellard | |
342 | cf495bcf | bellard | uint32_t psr; /* processor state register */
|
343 | 3475187d | bellard | target_ulong fsr; /* FPU state register */
|
344 | 7c60cc4b | bellard | float32 fpr[TARGET_FPREGS]; /* floating point registers */
|
345 | cf495bcf | bellard | uint32_t cwp; /* index of current register window (extracted
|
346 | cf495bcf | bellard | from PSR) */
|
347 | 5210977a | Igor Kovalenko | #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
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348 | cf495bcf | bellard | uint32_t wim; /* window invalid mask */
|
349 | 5210977a | Igor Kovalenko | #endif
|
350 | 3475187d | bellard | target_ulong tbr; /* trap base register */
|
351 | 2aae2b8e | Igor V. Kovalenko | #if !defined(TARGET_SPARC64)
|
352 | e8af50a3 | bellard | int psrs; /* supervisor mode (extracted from PSR) */ |
353 | e8af50a3 | bellard | int psrps; /* previous supervisor mode */ |
354 | e8af50a3 | bellard | int psret; /* enable traps */ |
355 | 5210977a | Igor Kovalenko | #endif
|
356 | 327ac2e7 | blueswir1 | uint32_t psrpil; /* interrupt blocking level */
|
357 | 327ac2e7 | blueswir1 | uint32_t pil_in; /* incoming interrupt level bitmap */
|
358 | 2aae2b8e | Igor V. Kovalenko | #if !defined(TARGET_SPARC64)
|
359 | e80cfcfc | bellard | int psref; /* enable fpu */ |
360 | 2aae2b8e | Igor V. Kovalenko | #endif
|
361 | 62724a37 | blueswir1 | target_ulong version; |
362 | cf495bcf | bellard | int interrupt_index;
|
363 | 1a14026e | blueswir1 | uint32_t nwindows; |
364 | cf495bcf | bellard | /* NOTE: we allow 8 more registers to handle wrapping */
|
365 | 1a14026e | blueswir1 | target_ulong regbase[MAX_NWINDOWS * 16 + 8]; |
366 | d720b93d | bellard | |
367 | a316d335 | bellard | CPU_COMMON |
368 | a316d335 | bellard | |
369 | e8af50a3 | bellard | /* MMU regs */
|
370 | 3475187d | bellard | #if defined(TARGET_SPARC64)
|
371 | 3475187d | bellard | uint64_t lsu; |
372 | 3475187d | bellard | #define DMMU_E 0x8 |
373 | 3475187d | bellard | #define IMMU_E 0x4 |
374 | 6e8e7d4c | Igor Kovalenko | //typedef struct SparcMMU
|
375 | 6e8e7d4c | Igor Kovalenko | union {
|
376 | 6e8e7d4c | Igor Kovalenko | uint64_t immuregs[16];
|
377 | 6e8e7d4c | Igor Kovalenko | struct {
|
378 | 6e8e7d4c | Igor Kovalenko | uint64_t tsb_tag_target; |
379 | 6e8e7d4c | Igor Kovalenko | uint64_t unused_mmu_primary_context; // use DMMU
|
380 | 6e8e7d4c | Igor Kovalenko | uint64_t unused_mmu_secondary_context; // use DMMU
|
381 | 6e8e7d4c | Igor Kovalenko | uint64_t sfsr; |
382 | 6e8e7d4c | Igor Kovalenko | uint64_t sfar; |
383 | 6e8e7d4c | Igor Kovalenko | uint64_t tsb; |
384 | 6e8e7d4c | Igor Kovalenko | uint64_t tag_access; |
385 | 6e8e7d4c | Igor Kovalenko | } immu; |
386 | 6e8e7d4c | Igor Kovalenko | }; |
387 | 6e8e7d4c | Igor Kovalenko | union {
|
388 | 6e8e7d4c | Igor Kovalenko | uint64_t dmmuregs[16];
|
389 | 6e8e7d4c | Igor Kovalenko | struct {
|
390 | 6e8e7d4c | Igor Kovalenko | uint64_t tsb_tag_target; |
391 | 6e8e7d4c | Igor Kovalenko | uint64_t mmu_primary_context; |
392 | 6e8e7d4c | Igor Kovalenko | uint64_t mmu_secondary_context; |
393 | 6e8e7d4c | Igor Kovalenko | uint64_t sfsr; |
394 | 6e8e7d4c | Igor Kovalenko | uint64_t sfar; |
395 | 6e8e7d4c | Igor Kovalenko | uint64_t tsb; |
396 | 6e8e7d4c | Igor Kovalenko | uint64_t tag_access; |
397 | 6e8e7d4c | Igor Kovalenko | } dmmu; |
398 | 6e8e7d4c | Igor Kovalenko | }; |
399 | 6e8e7d4c | Igor Kovalenko | SparcTLBEntry itlb[64];
|
400 | 6e8e7d4c | Igor Kovalenko | SparcTLBEntry dtlb[64];
|
401 | fb79ceb9 | blueswir1 | uint32_t mmu_version; |
402 | 3475187d | bellard | #else
|
403 | 3dd9a152 | blueswir1 | uint32_t mmuregs[32];
|
404 | 952a328f | blueswir1 | uint64_t mxccdata[4];
|
405 | 952a328f | blueswir1 | uint64_t mxccregs[8];
|
406 | 4017190e | blueswir1 | uint64_t mmubpregs[4];
|
407 | 3ebf5aaf | blueswir1 | uint64_t prom_addr; |
408 | 3475187d | bellard | #endif
|
409 | e8af50a3 | bellard | /* temporary float registers */
|
410 | 65ce8c2f | bellard | float64 dt0, dt1; |
411 | 1f587329 | blueswir1 | float128 qt0, qt1; |
412 | 7a0e1f41 | bellard | float_status fp_status; |
413 | af7bf89b | bellard | #if defined(TARGET_SPARC64)
|
414 | c19148bd | blueswir1 | #define MAXTL_MAX 8 |
415 | c19148bd | blueswir1 | #define MAXTL_MASK (MAXTL_MAX - 1) |
416 | c19148bd | blueswir1 | trap_state ts[MAXTL_MAX]; |
417 | 0f8a249a | blueswir1 | uint32_t xcc; /* Extended integer condition codes */
|
418 | 3475187d | bellard | uint32_t asi; |
419 | 3475187d | bellard | uint32_t pstate; |
420 | 3475187d | bellard | uint32_t tl; |
421 | c19148bd | blueswir1 | uint32_t maxtl; |
422 | 3475187d | bellard | uint32_t cansave, canrestore, otherwin, wstate, cleanwin; |
423 | 83469015 | bellard | uint64_t agregs[8]; /* alternate general registers */ |
424 | 83469015 | bellard | uint64_t bgregs[8]; /* backup for normal global registers */ |
425 | 83469015 | bellard | uint64_t igregs[8]; /* interrupt general registers */ |
426 | 83469015 | bellard | uint64_t mgregs[8]; /* mmu general registers */ |
427 | 3475187d | bellard | uint64_t fprs; |
428 | 83469015 | bellard | uint64_t tick_cmpr, stick_cmpr; |
429 | 8f4efc55 | Igor V. Kovalenko | CPUTimer *tick, *stick; |
430 | 709f2c1b | Igor V. Kovalenko | #define TICK_NPT_MASK 0x8000000000000000ULL |
431 | 709f2c1b | Igor V. Kovalenko | #define TICK_INT_DIS 0x8000000000000000ULL |
432 | 725cb90b | bellard | uint64_t gsr; |
433 | e9ebed4d | blueswir1 | uint32_t gl; // UA2005
|
434 | e9ebed4d | blueswir1 | /* UA 2005 hyperprivileged registers */
|
435 | c19148bd | blueswir1 | uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; |
436 | 8f4efc55 | Igor V. Kovalenko | CPUTimer *hstick; // UA 2005
|
437 | 9d926598 | blueswir1 | uint32_t softint; |
438 | 8fa211e8 | blueswir1 | #define SOFTINT_TIMER 1 |
439 | 8fa211e8 | blueswir1 | #define SOFTINT_STIMER (1 << 16) |
440 | 709f2c1b | Igor V. Kovalenko | #define SOFTINT_INTRMASK (0xFFFE) |
441 | 709f2c1b | Igor V. Kovalenko | #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
|
442 | 3475187d | bellard | #endif
|
443 | 5578ceab | blueswir1 | sparc_def_t *def; |
444 | b04d9890 | Fabien Chouteau | |
445 | b04d9890 | Fabien Chouteau | void *irq_manager;
|
446 | b04d9890 | Fabien Chouteau | void (*qemu_irq_ack) (void *irq_manager, int intno); |
447 | b04d9890 | Fabien Chouteau | |
448 | b04d9890 | Fabien Chouteau | /* Leon3 cache control */
|
449 | b04d9890 | Fabien Chouteau | uint32_t cache_control; |
450 | 7a3f1944 | bellard | } CPUSPARCState; |
451 | 64a88d5d | blueswir1 | |
452 | 5a834bb4 | Blue Swirl | #ifndef NO_CPU_IO_DEFS
|
453 | 91736d37 | blueswir1 | /* helper.c */
|
454 | aaed909a | bellard | CPUSPARCState *cpu_sparc_init(const char *cpu_model); |
455 | 91736d37 | blueswir1 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); |
456 | 047b39e4 | Stefan Weil | void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
|
457 | 48585ec5 | blueswir1 | int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw, |
458 | 48585ec5 | blueswir1 | int mmu_idx, int is_softmmu); |
459 | 0b5c1ce8 | Nathan Froyd | #define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
|
460 | 48585ec5 | blueswir1 | target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
|
461 | d41160a3 | Blue Swirl | void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env);
|
462 | 91736d37 | blueswir1 | |
463 | 91736d37 | blueswir1 | /* translate.c */
|
464 | 91736d37 | blueswir1 | void gen_intermediate_code_init(CPUSPARCState *env);
|
465 | 91736d37 | blueswir1 | |
466 | 91736d37 | blueswir1 | /* cpu-exec.c */
|
467 | 91736d37 | blueswir1 | int cpu_sparc_exec(CPUSPARCState *s);
|
468 | 7a3f1944 | bellard | |
469 | 5a834bb4 | Blue Swirl | /* op_helper.c */
|
470 | 5a834bb4 | Blue Swirl | target_ulong cpu_get_psr(CPUState *env1); |
471 | 5a834bb4 | Blue Swirl | void cpu_put_psr(CPUState *env1, target_ulong val);
|
472 | 5a834bb4 | Blue Swirl | #ifdef TARGET_SPARC64
|
473 | 5a834bb4 | Blue Swirl | target_ulong cpu_get_ccr(CPUState *env1); |
474 | 5a834bb4 | Blue Swirl | void cpu_put_ccr(CPUState *env1, target_ulong val);
|
475 | 5a834bb4 | Blue Swirl | target_ulong cpu_get_cwp64(CPUState *env1); |
476 | 5a834bb4 | Blue Swirl | void cpu_put_cwp64(CPUState *env1, int cwp); |
477 | 4c6aa085 | Blue Swirl | #endif
|
478 | 5a834bb4 | Blue Swirl | int cpu_cwp_inc(CPUState *env1, int cwp); |
479 | 5a834bb4 | Blue Swirl | int cpu_cwp_dec(CPUState *env1, int cwp); |
480 | 5a834bb4 | Blue Swirl | void cpu_set_cwp(CPUState *env1, int new_cwp); |
481 | 60f356e8 | Fabien Chouteau | void leon3_irq_manager(void *irq_manager, int intno); |
482 | b04d9890 | Fabien Chouteau | |
483 | 4c6aa085 | Blue Swirl | /* sun4m.c, sun4u.c */
|
484 | 4c6aa085 | Blue Swirl | void cpu_check_irqs(CPUSPARCState *env);
|
485 | 1a14026e | blueswir1 | |
486 | 60f356e8 | Fabien Chouteau | /* leon3.c */
|
487 | 60f356e8 | Fabien Chouteau | void leon3_irq_ack(void *irq_manager, int intno); |
488 | 60f356e8 | Fabien Chouteau | |
489 | 299b520c | Igor V. Kovalenko | #if defined (TARGET_SPARC64)
|
490 | 299b520c | Igor V. Kovalenko | |
491 | 299b520c | Igor V. Kovalenko | static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) |
492 | 299b520c | Igor V. Kovalenko | { |
493 | 299b520c | Igor V. Kovalenko | return (x & mask) == (y & mask);
|
494 | 299b520c | Igor V. Kovalenko | } |
495 | 299b520c | Igor V. Kovalenko | |
496 | 299b520c | Igor V. Kovalenko | #define MMU_CONTEXT_BITS 13 |
497 | 299b520c | Igor V. Kovalenko | #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) |
498 | 299b520c | Igor V. Kovalenko | |
499 | 299b520c | Igor V. Kovalenko | static inline int tlb_compare_context(const SparcTLBEntry *tlb, |
500 | 299b520c | Igor V. Kovalenko | uint64_t context) |
501 | 299b520c | Igor V. Kovalenko | { |
502 | 299b520c | Igor V. Kovalenko | return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
|
503 | 299b520c | Igor V. Kovalenko | } |
504 | 299b520c | Igor V. Kovalenko | |
505 | 299b520c | Igor V. Kovalenko | #endif
|
506 | 3475187d | bellard | #endif
|
507 | 3475187d | bellard | |
508 | 91736d37 | blueswir1 | /* cpu-exec.c */
|
509 | 3c7b48b7 | Paul Brook | #if !defined(CONFIG_USER_ONLY)
|
510 | c227f099 | Anthony Liguori | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
511 | e18231a3 | blueswir1 | int is_asi, int size); |
512 | 2065061e | Igor V. Kovalenko | target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr, |
513 | 2065061e | Igor V. Kovalenko | int mmu_idx);
|
514 | 2065061e | Igor V. Kovalenko | |
515 | 3c7b48b7 | Paul Brook | #endif
|
516 | f0d5e471 | blueswir1 | int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); |
517 | 7a3f1944 | bellard | |
518 | 9467d44c | ths | #define cpu_init cpu_sparc_init
|
519 | 9467d44c | ths | #define cpu_exec cpu_sparc_exec
|
520 | 9467d44c | ths | #define cpu_gen_code cpu_sparc_gen_code
|
521 | 9467d44c | ths | #define cpu_signal_handler cpu_sparc_signal_handler
|
522 | c732abe2 | j_mayer | #define cpu_list sparc_cpu_list
|
523 | 9467d44c | ths | |
524 | 8f4efc55 | Igor V. Kovalenko | #define CPU_SAVE_VERSION 6 |
525 | b3c7724c | pbrook | |
526 | 6ebbf390 | j_mayer | /* MMU modes definitions */
|
527 | 2aae2b8e | Igor V. Kovalenko | #if defined (TARGET_SPARC64)
|
528 | 2aae2b8e | Igor V. Kovalenko | #define MMU_USER_IDX 0 |
529 | 6f27aba6 | blueswir1 | #define MMU_MODE0_SUFFIX _user
|
530 | 2aae2b8e | Igor V. Kovalenko | #define MMU_USER_SECONDARY_IDX 1 |
531 | 2aae2b8e | Igor V. Kovalenko | #define MMU_MODE1_SUFFIX _user_secondary
|
532 | 2aae2b8e | Igor V. Kovalenko | #define MMU_KERNEL_IDX 2 |
533 | 2aae2b8e | Igor V. Kovalenko | #define MMU_MODE2_SUFFIX _kernel
|
534 | 2aae2b8e | Igor V. Kovalenko | #define MMU_KERNEL_SECONDARY_IDX 3 |
535 | 2aae2b8e | Igor V. Kovalenko | #define MMU_MODE3_SUFFIX _kernel_secondary
|
536 | 2aae2b8e | Igor V. Kovalenko | #define MMU_NUCLEUS_IDX 4 |
537 | 2aae2b8e | Igor V. Kovalenko | #define MMU_MODE4_SUFFIX _nucleus
|
538 | 2aae2b8e | Igor V. Kovalenko | #define MMU_HYPV_IDX 5 |
539 | 2aae2b8e | Igor V. Kovalenko | #define MMU_MODE5_SUFFIX _hypv
|
540 | 2aae2b8e | Igor V. Kovalenko | #else
|
541 | 9e31b9e2 | blueswir1 | #define MMU_USER_IDX 0 |
542 | 2aae2b8e | Igor V. Kovalenko | #define MMU_MODE0_SUFFIX _user
|
543 | 9e31b9e2 | blueswir1 | #define MMU_KERNEL_IDX 1 |
544 | 2aae2b8e | Igor V. Kovalenko | #define MMU_MODE1_SUFFIX _kernel
|
545 | 2aae2b8e | Igor V. Kovalenko | #endif
|
546 | 2aae2b8e | Igor V. Kovalenko | |
547 | 2aae2b8e | Igor V. Kovalenko | #if defined (TARGET_SPARC64)
|
548 | 2aae2b8e | Igor V. Kovalenko | static inline int cpu_has_hypervisor(CPUState *env1) |
549 | 2aae2b8e | Igor V. Kovalenko | { |
550 | 2aae2b8e | Igor V. Kovalenko | return env1->def->features & CPU_FEATURE_HYPV;
|
551 | 2aae2b8e | Igor V. Kovalenko | } |
552 | 2aae2b8e | Igor V. Kovalenko | |
553 | 2aae2b8e | Igor V. Kovalenko | static inline int cpu_hypervisor_mode(CPUState *env1) |
554 | 2aae2b8e | Igor V. Kovalenko | { |
555 | 2aae2b8e | Igor V. Kovalenko | return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
|
556 | 2aae2b8e | Igor V. Kovalenko | } |
557 | 2aae2b8e | Igor V. Kovalenko | |
558 | 2aae2b8e | Igor V. Kovalenko | static inline int cpu_supervisor_mode(CPUState *env1) |
559 | 2aae2b8e | Igor V. Kovalenko | { |
560 | 2aae2b8e | Igor V. Kovalenko | return env1->pstate & PS_PRIV;
|
561 | 2aae2b8e | Igor V. Kovalenko | } |
562 | 2065061e | Igor V. Kovalenko | #endif
|
563 | 9e31b9e2 | blueswir1 | |
564 | 22548760 | blueswir1 | static inline int cpu_mmu_index(CPUState *env1) |
565 | 6ebbf390 | j_mayer | { |
566 | 6f27aba6 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
567 | 9e31b9e2 | blueswir1 | return MMU_USER_IDX;
|
568 | 6f27aba6 | blueswir1 | #elif !defined(TARGET_SPARC64)
|
569 | 22548760 | blueswir1 | return env1->psrs;
|
570 | 6f27aba6 | blueswir1 | #else
|
571 | 9fd1ae3a | Igor V. Kovalenko | if (env1->tl > 0) { |
572 | 9fd1ae3a | Igor V. Kovalenko | return MMU_NUCLEUS_IDX;
|
573 | 9fd1ae3a | Igor V. Kovalenko | } else if (cpu_hypervisor_mode(env1)) { |
574 | 9e31b9e2 | blueswir1 | return MMU_HYPV_IDX;
|
575 | 2aae2b8e | Igor V. Kovalenko | } else if (cpu_supervisor_mode(env1)) { |
576 | 2aae2b8e | Igor V. Kovalenko | return MMU_KERNEL_IDX;
|
577 | 2aae2b8e | Igor V. Kovalenko | } else {
|
578 | 2aae2b8e | Igor V. Kovalenko | return MMU_USER_IDX;
|
579 | 2aae2b8e | Igor V. Kovalenko | } |
580 | 6f27aba6 | blueswir1 | #endif
|
581 | 6f27aba6 | blueswir1 | } |
582 | 6f27aba6 | blueswir1 | |
583 | 2df6c2d0 | Igor V. Kovalenko | static inline int cpu_interrupts_enabled(CPUState *env1) |
584 | 2df6c2d0 | Igor V. Kovalenko | { |
585 | 2df6c2d0 | Igor V. Kovalenko | #if !defined (TARGET_SPARC64)
|
586 | 2df6c2d0 | Igor V. Kovalenko | if (env1->psret != 0) |
587 | 2df6c2d0 | Igor V. Kovalenko | return 1; |
588 | 2df6c2d0 | Igor V. Kovalenko | #else
|
589 | 2df6c2d0 | Igor V. Kovalenko | if (env1->pstate & PS_IE)
|
590 | 2df6c2d0 | Igor V. Kovalenko | return 1; |
591 | 2df6c2d0 | Igor V. Kovalenko | #endif
|
592 | 2df6c2d0 | Igor V. Kovalenko | |
593 | 2df6c2d0 | Igor V. Kovalenko | return 0; |
594 | 2df6c2d0 | Igor V. Kovalenko | } |
595 | 2df6c2d0 | Igor V. Kovalenko | |
596 | d532b26c | Igor V. Kovalenko | static inline int cpu_pil_allowed(CPUState *env1, int pil) |
597 | d532b26c | Igor V. Kovalenko | { |
598 | d532b26c | Igor V. Kovalenko | #if !defined(TARGET_SPARC64)
|
599 | d532b26c | Igor V. Kovalenko | /* level 15 is non-maskable on sparc v8 */
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600 | d532b26c | Igor V. Kovalenko | return pil == 15 || pil > env1->psrpil; |
601 | d532b26c | Igor V. Kovalenko | #else
|
602 | d532b26c | Igor V. Kovalenko | return pil > env1->psrpil;
|
603 | d532b26c | Igor V. Kovalenko | #endif
|
604 | d532b26c | Igor V. Kovalenko | } |
605 | d532b26c | Igor V. Kovalenko | |
606 | 22548760 | blueswir1 | static inline int cpu_fpu_enabled(CPUState *env1) |
607 | 6f27aba6 | blueswir1 | { |
608 | 6f27aba6 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
609 | 6f27aba6 | blueswir1 | return 1; |
610 | 6f27aba6 | blueswir1 | #elif !defined(TARGET_SPARC64)
|
611 | 22548760 | blueswir1 | return env1->psref;
|
612 | 6f27aba6 | blueswir1 | #else
|
613 | 22548760 | blueswir1 | return ((env1->pstate & PS_PEF) != 0) && ((env1->fprs & FPRS_FEF) != 0); |
614 | 6f27aba6 | blueswir1 | #endif
|
615 | 6ebbf390 | j_mayer | } |
616 | 6ebbf390 | j_mayer | |
617 | 6e68e076 | pbrook | #if defined(CONFIG_USER_ONLY)
|
618 | 6e68e076 | pbrook | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
619 | 6e68e076 | pbrook | { |
620 | f8ed7070 | pbrook | if (newsp)
|
621 | 6e68e076 | pbrook | env->regwptr[22] = newsp;
|
622 | 6e68e076 | pbrook | env->regwptr[0] = 0; |
623 | 6e68e076 | pbrook | /* FIXME: Do we also need to clear CF? */
|
624 | 6e68e076 | pbrook | /* XXXXX */
|
625 | 6e68e076 | pbrook | printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
|
626 | 6e68e076 | pbrook | } |
627 | 6e68e076 | pbrook | #endif
|
628 | 6e68e076 | pbrook | |
629 | 7a3f1944 | bellard | #include "cpu-all.h" |
630 | 7a3f1944 | bellard | |
631 | f4b1a842 | blueswir1 | #ifdef TARGET_SPARC64
|
632 | f4b1a842 | blueswir1 | /* sun4u.c */
|
633 | 8f4efc55 | Igor V. Kovalenko | void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
|
634 | 8f4efc55 | Igor V. Kovalenko | uint64_t cpu_tick_get_count(CPUTimer *timer); |
635 | 8f4efc55 | Igor V. Kovalenko | void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
|
636 | 8194f35a | Igor Kovalenko | trap_state* cpu_tsptr(CPUState* env); |
637 | f4b1a842 | blueswir1 | #endif
|
638 | f4b1a842 | blueswir1 | |
639 | 6b917547 | aliguori | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
640 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
|
641 | 6b917547 | aliguori | { |
642 | 6b917547 | aliguori | *pc = env->pc; |
643 | 6b917547 | aliguori | *cs_base = env->npc; |
644 | 6b917547 | aliguori | #ifdef TARGET_SPARC64
|
645 | 6b917547 | aliguori | // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
|
646 | 9fd1ae3a | Igor V. Kovalenko | *flags = ((env->pstate & PS_AM) << 2) /* 5 */ |
647 | 9fd1ae3a | Igor V. Kovalenko | | (((env->pstate & PS_PEF) >> 1) /* 3 */ |
648 | 9fd1ae3a | Igor V. Kovalenko | | ((env->fprs & FPRS_FEF) << 2)) /* 4 */ |
649 | 9fd1ae3a | Igor V. Kovalenko | | (env->pstate & PS_PRIV) /* 2 */
|
650 | 9fd1ae3a | Igor V. Kovalenko | | ((env->lsu & (DMMU_E | IMMU_E)) >> 2) /* 1, 0 */ |
651 | 9fd1ae3a | Igor V. Kovalenko | | ((env->tl & 0xff) << 8) |
652 | 9fd1ae3a | Igor V. Kovalenko | | (env->dmmu.mmu_primary_context << 16); /* 16... */ |
653 | 6b917547 | aliguori | #else
|
654 | 6b917547 | aliguori | // FPU enable . Supervisor
|
655 | 6b917547 | aliguori | *flags = (env->psref << 4) | env->psrs;
|
656 | 6b917547 | aliguori | #endif
|
657 | 6b917547 | aliguori | } |
658 | 6b917547 | aliguori | |
659 | 7a3f1944 | bellard | #endif |