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1 | 69b91039 | bellard | /*
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2 | 69b91039 | bellard | * QEMU PCI bus manager
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3 | 69b91039 | bellard | *
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4 | 69b91039 | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 69b91039 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 69b91039 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 69b91039 | bellard | * in the Software without restriction, including without limitation the rights
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9 | 69b91039 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 69b91039 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 69b91039 | bellard | * furnished to do so, subject to the following conditions:
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12 | 69b91039 | bellard | *
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13 | 69b91039 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 69b91039 | bellard | * all copies or substantial portions of the Software.
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15 | 69b91039 | bellard | *
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16 | 69b91039 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 69b91039 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 69b91039 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 69b91039 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 69b91039 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 69b91039 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 69b91039 | bellard | * THE SOFTWARE.
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23 | 69b91039 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pci.h" |
26 | 376253ec | aliguori | #include "monitor.h" |
27 | 87ecb68b | pbrook | #include "net.h" |
28 | 880345c4 | aliguori | #include "sysemu.h" |
29 | 69b91039 | bellard | |
30 | 69b91039 | bellard | //#define DEBUG_PCI
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31 | 69b91039 | bellard | |
32 | 30468f78 | bellard | struct PCIBus {
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33 | 30468f78 | bellard | int bus_num;
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34 | 30468f78 | bellard | int devfn_min;
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35 | 502a5395 | pbrook | pci_set_irq_fn set_irq; |
36 | d2b59317 | pbrook | pci_map_irq_fn map_irq; |
37 | 30468f78 | bellard | uint32_t config_reg; /* XXX: suppress */
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38 | 384d8876 | bellard | /* low level pic */
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39 | 384d8876 | bellard | SetIRQFunc *low_set_irq; |
40 | d537cf6c | pbrook | qemu_irq *irq_opaque; |
41 | 30468f78 | bellard | PCIDevice *devices[256];
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42 | 80b3ada7 | pbrook | PCIDevice *parent_dev; |
43 | 80b3ada7 | pbrook | PCIBus *next; |
44 | d2b59317 | pbrook | /* The bus IRQ state is the logical OR of the connected devices.
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45 | d2b59317 | pbrook | Keep a count of the number of devices with raised IRQs. */
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46 | 52fc1d83 | balrog | int nirq;
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47 | 80b3ada7 | pbrook | int irq_count[];
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48 | 30468f78 | bellard | }; |
49 | 69b91039 | bellard | |
50 | 1941d19c | bellard | static void pci_update_mappings(PCIDevice *d); |
51 | d537cf6c | pbrook | static void pci_set_irq(void *opaque, int irq_num, int level); |
52 | 1941d19c | bellard | |
53 | 69b91039 | bellard | target_phys_addr_t pci_mem_base; |
54 | d350d97d | aliguori | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
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55 | d350d97d | aliguori | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
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56 | 0ac32c83 | bellard | static int pci_irq_index; |
57 | 30468f78 | bellard | static PCIBus *first_bus;
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58 | 30468f78 | bellard | |
59 | 52fc1d83 | balrog | static void pcibus_save(QEMUFile *f, void *opaque) |
60 | 52fc1d83 | balrog | { |
61 | 52fc1d83 | balrog | PCIBus *bus = (PCIBus *)opaque; |
62 | 52fc1d83 | balrog | int i;
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63 | 52fc1d83 | balrog | |
64 | 52fc1d83 | balrog | qemu_put_be32(f, bus->nirq); |
65 | 52fc1d83 | balrog | for (i = 0; i < bus->nirq; i++) |
66 | 52fc1d83 | balrog | qemu_put_be32(f, bus->irq_count[i]); |
67 | 52fc1d83 | balrog | } |
68 | 52fc1d83 | balrog | |
69 | 52fc1d83 | balrog | static int pcibus_load(QEMUFile *f, void *opaque, int version_id) |
70 | 52fc1d83 | balrog | { |
71 | 52fc1d83 | balrog | PCIBus *bus = (PCIBus *)opaque; |
72 | 52fc1d83 | balrog | int i, nirq;
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73 | 52fc1d83 | balrog | |
74 | 52fc1d83 | balrog | if (version_id != 1) |
75 | 52fc1d83 | balrog | return -EINVAL;
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76 | 52fc1d83 | balrog | |
77 | 52fc1d83 | balrog | nirq = qemu_get_be32(f); |
78 | 52fc1d83 | balrog | if (bus->nirq != nirq) {
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79 | 52fc1d83 | balrog | fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
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80 | 52fc1d83 | balrog | nirq, bus->nirq); |
81 | 52fc1d83 | balrog | return -EINVAL;
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82 | 52fc1d83 | balrog | } |
83 | 52fc1d83 | balrog | |
84 | 52fc1d83 | balrog | for (i = 0; i < nirq; i++) |
85 | 52fc1d83 | balrog | bus->irq_count[i] = qemu_get_be32(f); |
86 | 52fc1d83 | balrog | |
87 | 52fc1d83 | balrog | return 0; |
88 | 52fc1d83 | balrog | } |
89 | 52fc1d83 | balrog | |
90 | d2b59317 | pbrook | PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
91 | d537cf6c | pbrook | qemu_irq *pic, int devfn_min, int nirq) |
92 | 30468f78 | bellard | { |
93 | 30468f78 | bellard | PCIBus *bus; |
94 | 52fc1d83 | balrog | static int nbus = 0; |
95 | 52fc1d83 | balrog | |
96 | 80b3ada7 | pbrook | bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int))); |
97 | 502a5395 | pbrook | bus->set_irq = set_irq; |
98 | d2b59317 | pbrook | bus->map_irq = map_irq; |
99 | 502a5395 | pbrook | bus->irq_opaque = pic; |
100 | 502a5395 | pbrook | bus->devfn_min = devfn_min; |
101 | 52fc1d83 | balrog | bus->nirq = nirq; |
102 | 425c608c | Isaku Yamahata | bus->next = first_bus; |
103 | 30468f78 | bellard | first_bus = bus; |
104 | 52fc1d83 | balrog | register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus); |
105 | 30468f78 | bellard | return bus;
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106 | 30468f78 | bellard | } |
107 | 69b91039 | bellard | |
108 | 9596ebb7 | pbrook | static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
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109 | 80b3ada7 | pbrook | { |
110 | 80b3ada7 | pbrook | PCIBus *bus; |
111 | 80b3ada7 | pbrook | bus = qemu_mallocz(sizeof(PCIBus));
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112 | 80b3ada7 | pbrook | bus->map_irq = map_irq; |
113 | 80b3ada7 | pbrook | bus->parent_dev = dev; |
114 | 80b3ada7 | pbrook | bus->next = dev->bus->next; |
115 | 80b3ada7 | pbrook | dev->bus->next = bus; |
116 | 80b3ada7 | pbrook | return bus;
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117 | 80b3ada7 | pbrook | } |
118 | 80b3ada7 | pbrook | |
119 | 502a5395 | pbrook | int pci_bus_num(PCIBus *s)
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120 | 502a5395 | pbrook | { |
121 | 502a5395 | pbrook | return s->bus_num;
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122 | 502a5395 | pbrook | } |
123 | 502a5395 | pbrook | |
124 | 1941d19c | bellard | void pci_device_save(PCIDevice *s, QEMUFile *f)
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125 | 30ca2aab | bellard | { |
126 | 52fc1d83 | balrog | int i;
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127 | 52fc1d83 | balrog | |
128 | 52fc1d83 | balrog | qemu_put_be32(f, 2); /* PCI device version */ |
129 | 30ca2aab | bellard | qemu_put_buffer(f, s->config, 256);
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130 | 52fc1d83 | balrog | for (i = 0; i < 4; i++) |
131 | 52fc1d83 | balrog | qemu_put_be32(f, s->irq_state[i]); |
132 | 30ca2aab | bellard | } |
133 | 30ca2aab | bellard | |
134 | 1941d19c | bellard | int pci_device_load(PCIDevice *s, QEMUFile *f)
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135 | 30ca2aab | bellard | { |
136 | 1941d19c | bellard | uint32_t version_id; |
137 | 52fc1d83 | balrog | int i;
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138 | 52fc1d83 | balrog | |
139 | 1941d19c | bellard | version_id = qemu_get_be32(f); |
140 | 52fc1d83 | balrog | if (version_id > 2) |
141 | 30ca2aab | bellard | return -EINVAL;
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142 | 30ca2aab | bellard | qemu_get_buffer(f, s->config, 256);
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143 | 1941d19c | bellard | pci_update_mappings(s); |
144 | 52fc1d83 | balrog | |
145 | 52fc1d83 | balrog | if (version_id >= 2) |
146 | 52fc1d83 | balrog | for (i = 0; i < 4; i ++) |
147 | 52fc1d83 | balrog | s->irq_state[i] = qemu_get_be32(f); |
148 | 52fc1d83 | balrog | |
149 | 30ca2aab | bellard | return 0; |
150 | 30ca2aab | bellard | } |
151 | 30ca2aab | bellard | |
152 | d350d97d | aliguori | static int pci_set_default_subsystem_id(PCIDevice *pci_dev) |
153 | d350d97d | aliguori | { |
154 | d350d97d | aliguori | uint16_t *id; |
155 | d350d97d | aliguori | |
156 | d350d97d | aliguori | id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
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157 | d350d97d | aliguori | id[0] = cpu_to_le16(pci_default_sub_vendor_id);
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158 | d350d97d | aliguori | id[1] = cpu_to_le16(pci_default_sub_device_id);
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159 | d350d97d | aliguori | return 0; |
160 | d350d97d | aliguori | } |
161 | d350d97d | aliguori | |
162 | 880345c4 | aliguori | /*
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163 | 880345c4 | aliguori | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
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164 | 880345c4 | aliguori | */
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165 | 880345c4 | aliguori | static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) |
166 | 880345c4 | aliguori | { |
167 | 880345c4 | aliguori | const char *p; |
168 | 880345c4 | aliguori | char *e;
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169 | 880345c4 | aliguori | unsigned long val; |
170 | 880345c4 | aliguori | unsigned long dom = 0, bus = 0; |
171 | 880345c4 | aliguori | unsigned slot = 0; |
172 | 880345c4 | aliguori | |
173 | 880345c4 | aliguori | p = addr; |
174 | 880345c4 | aliguori | val = strtoul(p, &e, 16);
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175 | 880345c4 | aliguori | if (e == p)
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176 | 880345c4 | aliguori | return -1; |
177 | 880345c4 | aliguori | if (*e == ':') { |
178 | 880345c4 | aliguori | bus = val; |
179 | 880345c4 | aliguori | p = e + 1;
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180 | 880345c4 | aliguori | val = strtoul(p, &e, 16);
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181 | 880345c4 | aliguori | if (e == p)
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182 | 880345c4 | aliguori | return -1; |
183 | 880345c4 | aliguori | if (*e == ':') { |
184 | 880345c4 | aliguori | dom = bus; |
185 | 880345c4 | aliguori | bus = val; |
186 | 880345c4 | aliguori | p = e + 1;
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187 | 880345c4 | aliguori | val = strtoul(p, &e, 16);
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188 | 880345c4 | aliguori | if (e == p)
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189 | 880345c4 | aliguori | return -1; |
190 | 880345c4 | aliguori | } |
191 | 880345c4 | aliguori | } |
192 | 880345c4 | aliguori | |
193 | 880345c4 | aliguori | if (dom > 0xffff || bus > 0xff || val > 0x1f) |
194 | 880345c4 | aliguori | return -1; |
195 | 880345c4 | aliguori | |
196 | 880345c4 | aliguori | slot = val; |
197 | 880345c4 | aliguori | |
198 | 880345c4 | aliguori | if (*e)
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199 | 880345c4 | aliguori | return -1; |
200 | 880345c4 | aliguori | |
201 | 880345c4 | aliguori | /* Note: QEMU doesn't implement domains other than 0 */
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202 | 880345c4 | aliguori | if (dom != 0 || pci_find_bus(bus) == NULL) |
203 | 880345c4 | aliguori | return -1; |
204 | 880345c4 | aliguori | |
205 | 880345c4 | aliguori | *domp = dom; |
206 | 880345c4 | aliguori | *busp = bus; |
207 | 880345c4 | aliguori | *slotp = slot; |
208 | 880345c4 | aliguori | return 0; |
209 | 880345c4 | aliguori | } |
210 | 880345c4 | aliguori | |
211 | 880345c4 | aliguori | int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) |
212 | 880345c4 | aliguori | { |
213 | 880345c4 | aliguori | char devaddr[32]; |
214 | 880345c4 | aliguori | |
215 | 880345c4 | aliguori | if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr)) |
216 | 880345c4 | aliguori | return -1; |
217 | 880345c4 | aliguori | |
218 | 880345c4 | aliguori | return pci_parse_devaddr(devaddr, domp, busp, slotp);
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219 | 880345c4 | aliguori | } |
220 | 880345c4 | aliguori | |
221 | 880345c4 | aliguori | int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp) |
222 | 880345c4 | aliguori | { |
223 | 880345c4 | aliguori | char devaddr[32]; |
224 | 880345c4 | aliguori | |
225 | 880345c4 | aliguori | if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr)) |
226 | 880345c4 | aliguori | return -1; |
227 | 880345c4 | aliguori | |
228 | 880345c4 | aliguori | if (!strcmp(devaddr, "auto")) { |
229 | 880345c4 | aliguori | *domp = *busp = 0;
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230 | 880345c4 | aliguori | *slotp = -1;
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231 | 880345c4 | aliguori | /* want to support dom/bus auto-assign at some point */
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232 | 880345c4 | aliguori | return 0; |
233 | 880345c4 | aliguori | } |
234 | 880345c4 | aliguori | |
235 | 880345c4 | aliguori | return pci_parse_devaddr(devaddr, domp, busp, slotp);
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236 | 880345c4 | aliguori | } |
237 | 880345c4 | aliguori | |
238 | 69b91039 | bellard | /* -1 for devfn means auto assign */
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239 | 6b1b92d3 | Paul Brook | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
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240 | 6b1b92d3 | Paul Brook | const char *name, int devfn, |
241 | 6b1b92d3 | Paul Brook | PCIConfigReadFunc *config_read, |
242 | 6b1b92d3 | Paul Brook | PCIConfigWriteFunc *config_write) |
243 | 69b91039 | bellard | { |
244 | 0ac32c83 | bellard | if (pci_irq_index >= PCI_DEVICES_MAX)
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245 | 0ac32c83 | bellard | return NULL; |
246 | 3b46e624 | ths | |
247 | 69b91039 | bellard | if (devfn < 0) { |
248 | 30468f78 | bellard | for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
249 | 30468f78 | bellard | if (!bus->devices[devfn])
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250 | 69b91039 | bellard | goto found;
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251 | 69b91039 | bellard | } |
252 | 69b91039 | bellard | return NULL; |
253 | 69b91039 | bellard | found: ;
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254 | 69b91039 | bellard | } |
255 | 30468f78 | bellard | pci_dev->bus = bus; |
256 | 69b91039 | bellard | pci_dev->devfn = devfn; |
257 | 69b91039 | bellard | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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258 | d2b59317 | pbrook | memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
259 | d350d97d | aliguori | pci_set_default_subsystem_id(pci_dev); |
260 | 0ac32c83 | bellard | |
261 | 0ac32c83 | bellard | if (!config_read)
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262 | 0ac32c83 | bellard | config_read = pci_default_read_config; |
263 | 0ac32c83 | bellard | if (!config_write)
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264 | 0ac32c83 | bellard | config_write = pci_default_write_config; |
265 | 69b91039 | bellard | pci_dev->config_read = config_read; |
266 | 69b91039 | bellard | pci_dev->config_write = config_write; |
267 | 0ac32c83 | bellard | pci_dev->irq_index = pci_irq_index++; |
268 | 30468f78 | bellard | bus->devices[devfn] = pci_dev; |
269 | d537cf6c | pbrook | pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
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270 | 69b91039 | bellard | return pci_dev;
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271 | 69b91039 | bellard | } |
272 | 69b91039 | bellard | |
273 | 6b1b92d3 | Paul Brook | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
274 | 6b1b92d3 | Paul Brook | int instance_size, int devfn, |
275 | 6b1b92d3 | Paul Brook | PCIConfigReadFunc *config_read, |
276 | 6b1b92d3 | Paul Brook | PCIConfigWriteFunc *config_write) |
277 | 6b1b92d3 | Paul Brook | { |
278 | 6b1b92d3 | Paul Brook | PCIDevice *pci_dev; |
279 | 6b1b92d3 | Paul Brook | |
280 | 6b1b92d3 | Paul Brook | pci_dev = qemu_mallocz(instance_size); |
281 | 6b1b92d3 | Paul Brook | pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, |
282 | 6b1b92d3 | Paul Brook | config_read, config_write); |
283 | 6b1b92d3 | Paul Brook | return pci_dev;
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284 | 6b1b92d3 | Paul Brook | } |
285 | 5851e08c | aliguori | static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
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286 | 5851e08c | aliguori | { |
287 | 5851e08c | aliguori | return addr + pci_mem_base;
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288 | 5851e08c | aliguori | } |
289 | 5851e08c | aliguori | |
290 | 5851e08c | aliguori | static void pci_unregister_io_regions(PCIDevice *pci_dev) |
291 | 5851e08c | aliguori | { |
292 | 5851e08c | aliguori | PCIIORegion *r; |
293 | 5851e08c | aliguori | int i;
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294 | 5851e08c | aliguori | |
295 | 5851e08c | aliguori | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
296 | 5851e08c | aliguori | r = &pci_dev->io_regions[i]; |
297 | 5851e08c | aliguori | if (!r->size || r->addr == -1) |
298 | 5851e08c | aliguori | continue;
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299 | 5851e08c | aliguori | if (r->type == PCI_ADDRESS_SPACE_IO) {
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300 | 5851e08c | aliguori | isa_unassign_ioport(r->addr, r->size); |
301 | 5851e08c | aliguori | } else {
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302 | 5851e08c | aliguori | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
303 | 5851e08c | aliguori | r->size, |
304 | 5851e08c | aliguori | IO_MEM_UNASSIGNED); |
305 | 5851e08c | aliguori | } |
306 | 5851e08c | aliguori | } |
307 | 5851e08c | aliguori | } |
308 | 5851e08c | aliguori | |
309 | 5851e08c | aliguori | int pci_unregister_device(PCIDevice *pci_dev)
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310 | 5851e08c | aliguori | { |
311 | 5851e08c | aliguori | int ret = 0; |
312 | 5851e08c | aliguori | |
313 | 5851e08c | aliguori | if (pci_dev->unregister)
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314 | 5851e08c | aliguori | ret = pci_dev->unregister(pci_dev); |
315 | 5851e08c | aliguori | if (ret)
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316 | 5851e08c | aliguori | return ret;
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317 | 5851e08c | aliguori | |
318 | 5851e08c | aliguori | pci_unregister_io_regions(pci_dev); |
319 | 5851e08c | aliguori | |
320 | 5851e08c | aliguori | qemu_free_irqs(pci_dev->irq); |
321 | 5851e08c | aliguori | pci_irq_index--; |
322 | 5851e08c | aliguori | pci_dev->bus->devices[pci_dev->devfn] = NULL;
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323 | 5851e08c | aliguori | qemu_free(pci_dev); |
324 | 5851e08c | aliguori | return 0; |
325 | 5851e08c | aliguori | } |
326 | 5851e08c | aliguori | |
327 | 5fafdf24 | ths | void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
328 | 5fafdf24 | ths | uint32_t size, int type,
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329 | 69b91039 | bellard | PCIMapIORegionFunc *map_func) |
330 | 69b91039 | bellard | { |
331 | 69b91039 | bellard | PCIIORegion *r; |
332 | d7ce493a | pbrook | uint32_t addr; |
333 | 69b91039 | bellard | |
334 | 8a8696a3 | bellard | if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
335 | 69b91039 | bellard | return;
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336 | a4c20c6a | aliguori | |
337 | a4c20c6a | aliguori | if (size & (size-1)) { |
338 | a4c20c6a | aliguori | fprintf(stderr, "ERROR: PCI region size must be pow2 "
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339 | a4c20c6a | aliguori | "type=0x%x, size=0x%x\n", type, size);
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340 | a4c20c6a | aliguori | exit(1);
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341 | a4c20c6a | aliguori | } |
342 | a4c20c6a | aliguori | |
343 | 69b91039 | bellard | r = &pci_dev->io_regions[region_num]; |
344 | 69b91039 | bellard | r->addr = -1;
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345 | 69b91039 | bellard | r->size = size; |
346 | 69b91039 | bellard | r->type = type; |
347 | 69b91039 | bellard | r->map_func = map_func; |
348 | d7ce493a | pbrook | if (region_num == PCI_ROM_SLOT) {
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349 | d7ce493a | pbrook | addr = 0x30;
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350 | d7ce493a | pbrook | } else {
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351 | d7ce493a | pbrook | addr = 0x10 + region_num * 4; |
352 | d7ce493a | pbrook | } |
353 | d7ce493a | pbrook | *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); |
354 | 69b91039 | bellard | } |
355 | 69b91039 | bellard | |
356 | 0ac32c83 | bellard | static void pci_update_mappings(PCIDevice *d) |
357 | 0ac32c83 | bellard | { |
358 | 0ac32c83 | bellard | PCIIORegion *r; |
359 | 0ac32c83 | bellard | int cmd, i;
|
360 | 8a8696a3 | bellard | uint32_t last_addr, new_addr, config_ofs; |
361 | 3b46e624 | ths | |
362 | 0ac32c83 | bellard | cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
363 | 8a8696a3 | bellard | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
364 | 0ac32c83 | bellard | r = &d->io_regions[i]; |
365 | 8a8696a3 | bellard | if (i == PCI_ROM_SLOT) {
|
366 | 8a8696a3 | bellard | config_ofs = 0x30;
|
367 | 8a8696a3 | bellard | } else {
|
368 | 8a8696a3 | bellard | config_ofs = 0x10 + i * 4; |
369 | 8a8696a3 | bellard | } |
370 | 0ac32c83 | bellard | if (r->size != 0) { |
371 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
|
372 | 0ac32c83 | bellard | if (cmd & PCI_COMMAND_IO) {
|
373 | 5fafdf24 | ths | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
374 | 8a8696a3 | bellard | config_ofs)); |
375 | 0ac32c83 | bellard | new_addr = new_addr & ~(r->size - 1);
|
376 | 0ac32c83 | bellard | last_addr = new_addr + r->size - 1;
|
377 | 0ac32c83 | bellard | /* NOTE: we have only 64K ioports on PC */
|
378 | 0ac32c83 | bellard | if (last_addr <= new_addr || new_addr == 0 || |
379 | 0ac32c83 | bellard | last_addr >= 0x10000) {
|
380 | 0ac32c83 | bellard | new_addr = -1;
|
381 | 0ac32c83 | bellard | } |
382 | 0ac32c83 | bellard | } else {
|
383 | 0ac32c83 | bellard | new_addr = -1;
|
384 | 0ac32c83 | bellard | } |
385 | 0ac32c83 | bellard | } else {
|
386 | 0ac32c83 | bellard | if (cmd & PCI_COMMAND_MEMORY) {
|
387 | 5fafdf24 | ths | new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
388 | 8a8696a3 | bellard | config_ofs)); |
389 | 8a8696a3 | bellard | /* the ROM slot has a specific enable bit */
|
390 | 8a8696a3 | bellard | if (i == PCI_ROM_SLOT && !(new_addr & 1)) |
391 | 8a8696a3 | bellard | goto no_mem_map;
|
392 | 0ac32c83 | bellard | new_addr = new_addr & ~(r->size - 1);
|
393 | 0ac32c83 | bellard | last_addr = new_addr + r->size - 1;
|
394 | 0ac32c83 | bellard | /* NOTE: we do not support wrapping */
|
395 | 0ac32c83 | bellard | /* XXX: as we cannot support really dynamic
|
396 | 0ac32c83 | bellard | mappings, we handle specific values as invalid
|
397 | 0ac32c83 | bellard | mappings. */
|
398 | 0ac32c83 | bellard | if (last_addr <= new_addr || new_addr == 0 || |
399 | 0ac32c83 | bellard | last_addr == -1) {
|
400 | 0ac32c83 | bellard | new_addr = -1;
|
401 | 0ac32c83 | bellard | } |
402 | 0ac32c83 | bellard | } else {
|
403 | 8a8696a3 | bellard | no_mem_map:
|
404 | 0ac32c83 | bellard | new_addr = -1;
|
405 | 0ac32c83 | bellard | } |
406 | 0ac32c83 | bellard | } |
407 | 0ac32c83 | bellard | /* now do the real mapping */
|
408 | 0ac32c83 | bellard | if (new_addr != r->addr) {
|
409 | 0ac32c83 | bellard | if (r->addr != -1) { |
410 | 0ac32c83 | bellard | if (r->type & PCI_ADDRESS_SPACE_IO) {
|
411 | 0ac32c83 | bellard | int class;
|
412 | 0ac32c83 | bellard | /* NOTE: specific hack for IDE in PC case:
|
413 | 0ac32c83 | bellard | only one byte must be mapped. */
|
414 | 0ac32c83 | bellard | class = d->config[0x0a] | (d->config[0x0b] << 8); |
415 | 0ac32c83 | bellard | if (class == 0x0101 && r->size == 4) { |
416 | 0ac32c83 | bellard | isa_unassign_ioport(r->addr + 2, 1); |
417 | 0ac32c83 | bellard | } else {
|
418 | 0ac32c83 | bellard | isa_unassign_ioport(r->addr, r->size); |
419 | 0ac32c83 | bellard | } |
420 | 0ac32c83 | bellard | } else {
|
421 | 502a5395 | pbrook | cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
422 | 5fafdf24 | ths | r->size, |
423 | 0ac32c83 | bellard | IO_MEM_UNASSIGNED); |
424 | f65ed4c1 | aliguori | qemu_unregister_coalesced_mmio(r->addr, r->size); |
425 | 0ac32c83 | bellard | } |
426 | 0ac32c83 | bellard | } |
427 | 0ac32c83 | bellard | r->addr = new_addr; |
428 | 0ac32c83 | bellard | if (r->addr != -1) { |
429 | 0ac32c83 | bellard | r->map_func(d, i, r->addr, r->size, r->type); |
430 | 0ac32c83 | bellard | } |
431 | 0ac32c83 | bellard | } |
432 | 0ac32c83 | bellard | } |
433 | 0ac32c83 | bellard | } |
434 | 0ac32c83 | bellard | } |
435 | 0ac32c83 | bellard | |
436 | 5fafdf24 | ths | uint32_t pci_default_read_config(PCIDevice *d, |
437 | 0ac32c83 | bellard | uint32_t address, int len)
|
438 | 69b91039 | bellard | { |
439 | 0ac32c83 | bellard | uint32_t val; |
440 | a2d4e44b | ths | |
441 | 0ac32c83 | bellard | switch(len) {
|
442 | 0ac32c83 | bellard | default:
|
443 | 0ac32c83 | bellard | case 4: |
444 | a2d4e44b | ths | if (address <= 0xfc) { |
445 | a2d4e44b | ths | val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
446 | a2d4e44b | ths | break;
|
447 | a2d4e44b | ths | } |
448 | a2d4e44b | ths | /* fall through */
|
449 | a2d4e44b | ths | case 2: |
450 | a2d4e44b | ths | if (address <= 0xfe) { |
451 | a2d4e44b | ths | val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
452 | a2d4e44b | ths | break;
|
453 | a2d4e44b | ths | } |
454 | a2d4e44b | ths | /* fall through */
|
455 | a2d4e44b | ths | case 1: |
456 | a2d4e44b | ths | val = d->config[address]; |
457 | 0ac32c83 | bellard | break;
|
458 | 0ac32c83 | bellard | } |
459 | 0ac32c83 | bellard | return val;
|
460 | 0ac32c83 | bellard | } |
461 | 0ac32c83 | bellard | |
462 | 5fafdf24 | ths | void pci_default_write_config(PCIDevice *d,
|
463 | 0ac32c83 | bellard | uint32_t address, uint32_t val, int len)
|
464 | 0ac32c83 | bellard | { |
465 | 0ac32c83 | bellard | int can_write, i;
|
466 | 7bf5be70 | bellard | uint32_t end, addr; |
467 | 0ac32c83 | bellard | |
468 | 5fafdf24 | ths | if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || |
469 | 8a8696a3 | bellard | (address >= 0x30 && address < 0x34))) { |
470 | 0ac32c83 | bellard | PCIIORegion *r; |
471 | 0ac32c83 | bellard | int reg;
|
472 | 0ac32c83 | bellard | |
473 | 8a8696a3 | bellard | if ( address >= 0x30 ) { |
474 | 8a8696a3 | bellard | reg = PCI_ROM_SLOT; |
475 | 8a8696a3 | bellard | }else{
|
476 | 8a8696a3 | bellard | reg = (address - 0x10) >> 2; |
477 | 8a8696a3 | bellard | } |
478 | 0ac32c83 | bellard | r = &d->io_regions[reg]; |
479 | 0ac32c83 | bellard | if (r->size == 0) |
480 | 0ac32c83 | bellard | goto default_config;
|
481 | 0ac32c83 | bellard | /* compute the stored value */
|
482 | 8a8696a3 | bellard | if (reg == PCI_ROM_SLOT) {
|
483 | 8a8696a3 | bellard | /* keep ROM enable bit */
|
484 | 8a8696a3 | bellard | val &= (~(r->size - 1)) | 1; |
485 | 8a8696a3 | bellard | } else {
|
486 | 8a8696a3 | bellard | val &= ~(r->size - 1);
|
487 | 8a8696a3 | bellard | val |= r->type; |
488 | 8a8696a3 | bellard | } |
489 | 8a8696a3 | bellard | *(uint32_t *)(d->config + address) = cpu_to_le32(val); |
490 | 0ac32c83 | bellard | pci_update_mappings(d); |
491 | 69b91039 | bellard | return;
|
492 | 0ac32c83 | bellard | } |
493 | 0ac32c83 | bellard | default_config:
|
494 | 0ac32c83 | bellard | /* not efficient, but simple */
|
495 | 7bf5be70 | bellard | addr = address; |
496 | 0ac32c83 | bellard | for(i = 0; i < len; i++) { |
497 | 0ac32c83 | bellard | /* default read/write accesses */
|
498 | 1f62d938 | bellard | switch(d->config[0x0e]) { |
499 | 0ac32c83 | bellard | case 0x00: |
500 | 1f62d938 | bellard | case 0x80: |
501 | 1f62d938 | bellard | switch(addr) {
|
502 | 1f62d938 | bellard | case 0x00: |
503 | 1f62d938 | bellard | case 0x01: |
504 | 1f62d938 | bellard | case 0x02: |
505 | 1f62d938 | bellard | case 0x03: |
506 | c2c5104b | aliguori | case 0x06: |
507 | c2c5104b | aliguori | case 0x07: |
508 | 1f62d938 | bellard | case 0x08: |
509 | 1f62d938 | bellard | case 0x09: |
510 | 1f62d938 | bellard | case 0x0a: |
511 | 1f62d938 | bellard | case 0x0b: |
512 | 1f62d938 | bellard | case 0x0e: |
513 | 1f62d938 | bellard | case 0x10 ... 0x27: /* base */ |
514 | 8098ed41 | aurel32 | case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ |
515 | 1f62d938 | bellard | case 0x30 ... 0x33: /* rom */ |
516 | 1f62d938 | bellard | case 0x3d: |
517 | 1f62d938 | bellard | can_write = 0;
|
518 | 1f62d938 | bellard | break;
|
519 | 1f62d938 | bellard | default:
|
520 | 1f62d938 | bellard | can_write = 1;
|
521 | 1f62d938 | bellard | break;
|
522 | 1f62d938 | bellard | } |
523 | 0ac32c83 | bellard | break;
|
524 | 0ac32c83 | bellard | default:
|
525 | 1f62d938 | bellard | case 0x01: |
526 | 1f62d938 | bellard | switch(addr) {
|
527 | 1f62d938 | bellard | case 0x00: |
528 | 1f62d938 | bellard | case 0x01: |
529 | 1f62d938 | bellard | case 0x02: |
530 | 1f62d938 | bellard | case 0x03: |
531 | c2c5104b | aliguori | case 0x06: |
532 | c2c5104b | aliguori | case 0x07: |
533 | 1f62d938 | bellard | case 0x08: |
534 | 1f62d938 | bellard | case 0x09: |
535 | 1f62d938 | bellard | case 0x0a: |
536 | 1f62d938 | bellard | case 0x0b: |
537 | 1f62d938 | bellard | case 0x0e: |
538 | 8098ed41 | aurel32 | case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ |
539 | 1f62d938 | bellard | case 0x38 ... 0x3b: /* rom */ |
540 | 1f62d938 | bellard | case 0x3d: |
541 | 1f62d938 | bellard | can_write = 0;
|
542 | 1f62d938 | bellard | break;
|
543 | 1f62d938 | bellard | default:
|
544 | 1f62d938 | bellard | can_write = 1;
|
545 | 1f62d938 | bellard | break;
|
546 | 1f62d938 | bellard | } |
547 | 0ac32c83 | bellard | break;
|
548 | 0ac32c83 | bellard | } |
549 | 0ac32c83 | bellard | if (can_write) {
|
550 | 8098ed41 | aurel32 | /* Mask out writes to reserved bits in registers */
|
551 | 8098ed41 | aurel32 | switch (addr) {
|
552 | 475dc65f | aurel32 | case 0x05: |
553 | 475dc65f | aurel32 | val &= ~PCI_COMMAND_RESERVED_MASK_HI; |
554 | 475dc65f | aurel32 | break;
|
555 | 8098ed41 | aurel32 | case 0x06: |
556 | 8098ed41 | aurel32 | val &= ~PCI_STATUS_RESERVED_MASK_LO; |
557 | 8098ed41 | aurel32 | break;
|
558 | 8098ed41 | aurel32 | case 0x07: |
559 | 8098ed41 | aurel32 | val &= ~PCI_STATUS_RESERVED_MASK_HI; |
560 | 8098ed41 | aurel32 | break;
|
561 | 8098ed41 | aurel32 | } |
562 | 7bf5be70 | bellard | d->config[addr] = val; |
563 | 0ac32c83 | bellard | } |
564 | a2d4e44b | ths | if (++addr > 0xff) |
565 | a2d4e44b | ths | break;
|
566 | 0ac32c83 | bellard | val >>= 8;
|
567 | 0ac32c83 | bellard | } |
568 | 0ac32c83 | bellard | |
569 | 0ac32c83 | bellard | end = address + len; |
570 | 0ac32c83 | bellard | if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { |
571 | 0ac32c83 | bellard | /* if the command register is modified, we must modify the mappings */
|
572 | 0ac32c83 | bellard | pci_update_mappings(d); |
573 | 69b91039 | bellard | } |
574 | 69b91039 | bellard | } |
575 | 69b91039 | bellard | |
576 | 502a5395 | pbrook | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
577 | 69b91039 | bellard | { |
578 | 30468f78 | bellard | PCIBus *s = opaque; |
579 | 30468f78 | bellard | PCIDevice *pci_dev; |
580 | 30468f78 | bellard | int config_addr, bus_num;
|
581 | 3b46e624 | ths | |
582 | 69b91039 | bellard | #if defined(DEBUG_PCI) && 0 |
583 | 69b91039 | bellard | printf("pci_data_write: addr=%08x val=%08x len=%d\n",
|
584 | 502a5395 | pbrook | addr, val, len); |
585 | 69b91039 | bellard | #endif
|
586 | 502a5395 | pbrook | bus_num = (addr >> 16) & 0xff; |
587 | 80b3ada7 | pbrook | while (s && s->bus_num != bus_num)
|
588 | 80b3ada7 | pbrook | s = s->next; |
589 | 80b3ada7 | pbrook | if (!s)
|
590 | 69b91039 | bellard | return;
|
591 | 502a5395 | pbrook | pci_dev = s->devices[(addr >> 8) & 0xff]; |
592 | 69b91039 | bellard | if (!pci_dev)
|
593 | 69b91039 | bellard | return;
|
594 | 502a5395 | pbrook | config_addr = addr & 0xff;
|
595 | 69b91039 | bellard | #if defined(DEBUG_PCI)
|
596 | 69b91039 | bellard | printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
|
597 | 69b91039 | bellard | pci_dev->name, config_addr, val, len); |
598 | 69b91039 | bellard | #endif
|
599 | 0ac32c83 | bellard | pci_dev->config_write(pci_dev, config_addr, val, len); |
600 | 69b91039 | bellard | } |
601 | 69b91039 | bellard | |
602 | 502a5395 | pbrook | uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
603 | 69b91039 | bellard | { |
604 | 30468f78 | bellard | PCIBus *s = opaque; |
605 | 30468f78 | bellard | PCIDevice *pci_dev; |
606 | 30468f78 | bellard | int config_addr, bus_num;
|
607 | 69b91039 | bellard | uint32_t val; |
608 | 69b91039 | bellard | |
609 | 502a5395 | pbrook | bus_num = (addr >> 16) & 0xff; |
610 | 80b3ada7 | pbrook | while (s && s->bus_num != bus_num)
|
611 | 80b3ada7 | pbrook | s= s->next; |
612 | 80b3ada7 | pbrook | if (!s)
|
613 | 69b91039 | bellard | goto fail;
|
614 | 502a5395 | pbrook | pci_dev = s->devices[(addr >> 8) & 0xff]; |
615 | 69b91039 | bellard | if (!pci_dev) {
|
616 | 69b91039 | bellard | fail:
|
617 | 63ce9e0a | bellard | switch(len) {
|
618 | 63ce9e0a | bellard | case 1: |
619 | 63ce9e0a | bellard | val = 0xff;
|
620 | 63ce9e0a | bellard | break;
|
621 | 63ce9e0a | bellard | case 2: |
622 | 63ce9e0a | bellard | val = 0xffff;
|
623 | 63ce9e0a | bellard | break;
|
624 | 63ce9e0a | bellard | default:
|
625 | 63ce9e0a | bellard | case 4: |
626 | 63ce9e0a | bellard | val = 0xffffffff;
|
627 | 63ce9e0a | bellard | break;
|
628 | 63ce9e0a | bellard | } |
629 | 69b91039 | bellard | goto the_end;
|
630 | 69b91039 | bellard | } |
631 | 502a5395 | pbrook | config_addr = addr & 0xff;
|
632 | 69b91039 | bellard | val = pci_dev->config_read(pci_dev, config_addr, len); |
633 | 69b91039 | bellard | #if defined(DEBUG_PCI)
|
634 | 69b91039 | bellard | printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
635 | 69b91039 | bellard | pci_dev->name, config_addr, val, len); |
636 | 69b91039 | bellard | #endif
|
637 | 69b91039 | bellard | the_end:
|
638 | 69b91039 | bellard | #if defined(DEBUG_PCI) && 0 |
639 | 69b91039 | bellard | printf("pci_data_read: addr=%08x val=%08x len=%d\n",
|
640 | 502a5395 | pbrook | addr, val, len); |
641 | 69b91039 | bellard | #endif
|
642 | 69b91039 | bellard | return val;
|
643 | 69b91039 | bellard | } |
644 | 69b91039 | bellard | |
645 | 502a5395 | pbrook | /***********************************************************/
|
646 | 502a5395 | pbrook | /* generic PCI irq support */
|
647 | 30468f78 | bellard | |
648 | 502a5395 | pbrook | /* 0 <= irq_num <= 3. level must be 0 or 1 */
|
649 | d537cf6c | pbrook | static void pci_set_irq(void *opaque, int irq_num, int level) |
650 | 69b91039 | bellard | { |
651 | d537cf6c | pbrook | PCIDevice *pci_dev = (PCIDevice *)opaque; |
652 | 80b3ada7 | pbrook | PCIBus *bus; |
653 | 80b3ada7 | pbrook | int change;
|
654 | 3b46e624 | ths | |
655 | 80b3ada7 | pbrook | change = level - pci_dev->irq_state[irq_num]; |
656 | 80b3ada7 | pbrook | if (!change)
|
657 | 80b3ada7 | pbrook | return;
|
658 | d2b59317 | pbrook | |
659 | d2b59317 | pbrook | pci_dev->irq_state[irq_num] = level; |
660 | 5e966ce6 | pbrook | for (;;) {
|
661 | 5e966ce6 | pbrook | bus = pci_dev->bus; |
662 | 80b3ada7 | pbrook | irq_num = bus->map_irq(pci_dev, irq_num); |
663 | 5e966ce6 | pbrook | if (bus->set_irq)
|
664 | 5e966ce6 | pbrook | break;
|
665 | 80b3ada7 | pbrook | pci_dev = bus->parent_dev; |
666 | 80b3ada7 | pbrook | } |
667 | 80b3ada7 | pbrook | bus->irq_count[irq_num] += change; |
668 | d2b59317 | pbrook | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
|
669 | 69b91039 | bellard | } |
670 | 69b91039 | bellard | |
671 | 502a5395 | pbrook | /***********************************************************/
|
672 | 502a5395 | pbrook | /* monitor info on PCI */
|
673 | 0ac32c83 | bellard | |
674 | 6650ee6d | pbrook | typedef struct { |
675 | 6650ee6d | pbrook | uint16_t class; |
676 | 6650ee6d | pbrook | const char *desc; |
677 | 6650ee6d | pbrook | } pci_class_desc; |
678 | 6650ee6d | pbrook | |
679 | 09bc878a | blueswir1 | static const pci_class_desc pci_class_descriptions[] = |
680 | 6650ee6d | pbrook | { |
681 | 4ca9c76f | pbrook | { 0x0100, "SCSI controller"}, |
682 | 6650ee6d | pbrook | { 0x0101, "IDE controller"}, |
683 | dcb5b19a | ths | { 0x0102, "Floppy controller"}, |
684 | dcb5b19a | ths | { 0x0103, "IPI controller"}, |
685 | dcb5b19a | ths | { 0x0104, "RAID controller"}, |
686 | dcb5b19a | ths | { 0x0106, "SATA controller"}, |
687 | dcb5b19a | ths | { 0x0107, "SAS controller"}, |
688 | dcb5b19a | ths | { 0x0180, "Storage controller"}, |
689 | 6650ee6d | pbrook | { 0x0200, "Ethernet controller"}, |
690 | dcb5b19a | ths | { 0x0201, "Token Ring controller"}, |
691 | dcb5b19a | ths | { 0x0202, "FDDI controller"}, |
692 | dcb5b19a | ths | { 0x0203, "ATM controller"}, |
693 | dcb5b19a | ths | { 0x0280, "Network controller"}, |
694 | 6650ee6d | pbrook | { 0x0300, "VGA controller"}, |
695 | dcb5b19a | ths | { 0x0301, "XGA controller"}, |
696 | dcb5b19a | ths | { 0x0302, "3D controller"}, |
697 | dcb5b19a | ths | { 0x0380, "Display controller"}, |
698 | dcb5b19a | ths | { 0x0400, "Video controller"}, |
699 | dcb5b19a | ths | { 0x0401, "Audio controller"}, |
700 | dcb5b19a | ths | { 0x0402, "Phone"}, |
701 | dcb5b19a | ths | { 0x0480, "Multimedia controller"}, |
702 | dcb5b19a | ths | { 0x0500, "RAM controller"}, |
703 | dcb5b19a | ths | { 0x0501, "Flash controller"}, |
704 | dcb5b19a | ths | { 0x0580, "Memory controller"}, |
705 | 6650ee6d | pbrook | { 0x0600, "Host bridge"}, |
706 | 6650ee6d | pbrook | { 0x0601, "ISA bridge"}, |
707 | dcb5b19a | ths | { 0x0602, "EISA bridge"}, |
708 | dcb5b19a | ths | { 0x0603, "MC bridge"}, |
709 | 6650ee6d | pbrook | { 0x0604, "PCI bridge"}, |
710 | dcb5b19a | ths | { 0x0605, "PCMCIA bridge"}, |
711 | dcb5b19a | ths | { 0x0606, "NUBUS bridge"}, |
712 | dcb5b19a | ths | { 0x0607, "CARDBUS bridge"}, |
713 | dcb5b19a | ths | { 0x0608, "RACEWAY bridge"}, |
714 | dcb5b19a | ths | { 0x0680, "Bridge"}, |
715 | 6650ee6d | pbrook | { 0x0c03, "USB controller"}, |
716 | 6650ee6d | pbrook | { 0, NULL} |
717 | 6650ee6d | pbrook | }; |
718 | 6650ee6d | pbrook | |
719 | 502a5395 | pbrook | static void pci_info_device(PCIDevice *d) |
720 | 30468f78 | bellard | { |
721 | 376253ec | aliguori | Monitor *mon = cur_mon; |
722 | 502a5395 | pbrook | int i, class;
|
723 | 502a5395 | pbrook | PCIIORegion *r; |
724 | 09bc878a | blueswir1 | const pci_class_desc *desc;
|
725 | 30468f78 | bellard | |
726 | 376253ec | aliguori | monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
|
727 | 376253ec | aliguori | d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
728 | 502a5395 | pbrook | class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
729 | 376253ec | aliguori | monitor_printf(mon, " ");
|
730 | 6650ee6d | pbrook | desc = pci_class_descriptions; |
731 | 6650ee6d | pbrook | while (desc->desc && class != desc->class)
|
732 | 6650ee6d | pbrook | desc++; |
733 | 6650ee6d | pbrook | if (desc->desc) {
|
734 | 376253ec | aliguori | monitor_printf(mon, "%s", desc->desc);
|
735 | 6650ee6d | pbrook | } else {
|
736 | 376253ec | aliguori | monitor_printf(mon, "Class %04x", class);
|
737 | 72cc6cfe | bellard | } |
738 | 376253ec | aliguori | monitor_printf(mon, ": PCI device %04x:%04x\n",
|
739 | 502a5395 | pbrook | le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
740 | 502a5395 | pbrook | le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
741 | 30468f78 | bellard | |
742 | 502a5395 | pbrook | if (d->config[PCI_INTERRUPT_PIN] != 0) { |
743 | 376253ec | aliguori | monitor_printf(mon, " IRQ %d.\n",
|
744 | 376253ec | aliguori | d->config[PCI_INTERRUPT_LINE]); |
745 | 30468f78 | bellard | } |
746 | 80b3ada7 | pbrook | if (class == 0x0604) { |
747 | 376253ec | aliguori | monitor_printf(mon, " BUS %d.\n", d->config[0x19]); |
748 | 80b3ada7 | pbrook | } |
749 | 502a5395 | pbrook | for(i = 0;i < PCI_NUM_REGIONS; i++) { |
750 | 502a5395 | pbrook | r = &d->io_regions[i]; |
751 | 502a5395 | pbrook | if (r->size != 0) { |
752 | 376253ec | aliguori | monitor_printf(mon, " BAR%d: ", i);
|
753 | 502a5395 | pbrook | if (r->type & PCI_ADDRESS_SPACE_IO) {
|
754 | 376253ec | aliguori | monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
|
755 | 376253ec | aliguori | r->addr, r->addr + r->size - 1);
|
756 | 502a5395 | pbrook | } else {
|
757 | 376253ec | aliguori | monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
|
758 | 376253ec | aliguori | r->addr, r->addr + r->size - 1);
|
759 | 502a5395 | pbrook | } |
760 | 502a5395 | pbrook | } |
761 | 77d4bc34 | bellard | } |
762 | 80b3ada7 | pbrook | if (class == 0x0604 && d->config[0x19] != 0) { |
763 | 80b3ada7 | pbrook | pci_for_each_device(d->config[0x19], pci_info_device);
|
764 | 80b3ada7 | pbrook | } |
765 | 384d8876 | bellard | } |
766 | 384d8876 | bellard | |
767 | 80b3ada7 | pbrook | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) |
768 | 384d8876 | bellard | { |
769 | 502a5395 | pbrook | PCIBus *bus = first_bus; |
770 | 384d8876 | bellard | PCIDevice *d; |
771 | 502a5395 | pbrook | int devfn;
|
772 | 3b46e624 | ths | |
773 | 80b3ada7 | pbrook | while (bus && bus->bus_num != bus_num)
|
774 | 80b3ada7 | pbrook | bus = bus->next; |
775 | 502a5395 | pbrook | if (bus) {
|
776 | 502a5395 | pbrook | for(devfn = 0; devfn < 256; devfn++) { |
777 | 502a5395 | pbrook | d = bus->devices[devfn]; |
778 | 502a5395 | pbrook | if (d)
|
779 | 502a5395 | pbrook | fn(d); |
780 | 502a5395 | pbrook | } |
781 | f2aa58c6 | bellard | } |
782 | f2aa58c6 | bellard | } |
783 | f2aa58c6 | bellard | |
784 | 376253ec | aliguori | void pci_info(Monitor *mon)
|
785 | f2aa58c6 | bellard | { |
786 | 80b3ada7 | pbrook | pci_for_each_device(0, pci_info_device);
|
787 | 77d4bc34 | bellard | } |
788 | a41b2ff2 | pbrook | |
789 | cb457d76 | aliguori | static const char * const pci_nic_models[] = { |
790 | cb457d76 | aliguori | "ne2k_pci",
|
791 | cb457d76 | aliguori | "i82551",
|
792 | cb457d76 | aliguori | "i82557b",
|
793 | cb457d76 | aliguori | "i82559er",
|
794 | cb457d76 | aliguori | "rtl8139",
|
795 | cb457d76 | aliguori | "e1000",
|
796 | cb457d76 | aliguori | "pcnet",
|
797 | cb457d76 | aliguori | "virtio",
|
798 | cb457d76 | aliguori | NULL
|
799 | cb457d76 | aliguori | }; |
800 | cb457d76 | aliguori | |
801 | 9d07d757 | Paul Brook | static const char * const pci_nic_names[] = { |
802 | 9d07d757 | Paul Brook | "ne2k_pci",
|
803 | 9d07d757 | Paul Brook | "i82551",
|
804 | 9d07d757 | Paul Brook | "i82557b",
|
805 | 9d07d757 | Paul Brook | "i82559er",
|
806 | 9d07d757 | Paul Brook | "rtl8139",
|
807 | 9d07d757 | Paul Brook | "e1000",
|
808 | 9d07d757 | Paul Brook | "pcnet",
|
809 | 53c25cea | Paul Brook | "virtio-net-pci",
|
810 | cb457d76 | aliguori | NULL
|
811 | cb457d76 | aliguori | }; |
812 | cb457d76 | aliguori | |
813 | a41b2ff2 | pbrook | /* Initialize a PCI NIC. */
|
814 | 72da4208 | aliguori | PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
|
815 | cb457d76 | aliguori | const char *default_model) |
816 | a41b2ff2 | pbrook | { |
817 | 9d07d757 | Paul Brook | DeviceState *dev; |
818 | cb457d76 | aliguori | int i;
|
819 | cb457d76 | aliguori | |
820 | cb457d76 | aliguori | qemu_check_nic_model_list(nd, pci_nic_models, default_model); |
821 | cb457d76 | aliguori | |
822 | 9d07d757 | Paul Brook | for (i = 0; pci_nic_models[i]; i++) { |
823 | 72da4208 | aliguori | if (strcmp(nd->model, pci_nic_models[i]) == 0) { |
824 | 9d07d757 | Paul Brook | dev = qdev_create(bus, pci_nic_names[i]); |
825 | 9d07d757 | Paul Brook | qdev_set_prop_int(dev, "devfn", devfn);
|
826 | 9d07d757 | Paul Brook | qdev_set_netdev(dev, nd); |
827 | 9d07d757 | Paul Brook | qdev_init(dev); |
828 | 9d07d757 | Paul Brook | nd->private = dev; |
829 | 9d07d757 | Paul Brook | return (PCIDevice *)dev;
|
830 | 72da4208 | aliguori | } |
831 | 9d07d757 | Paul Brook | } |
832 | 72da4208 | aliguori | |
833 | 72da4208 | aliguori | return NULL; |
834 | a41b2ff2 | pbrook | } |
835 | a41b2ff2 | pbrook | |
836 | 80b3ada7 | pbrook | typedef struct { |
837 | 80b3ada7 | pbrook | PCIDevice dev; |
838 | 80b3ada7 | pbrook | PCIBus *bus; |
839 | 80b3ada7 | pbrook | } PCIBridge; |
840 | 80b3ada7 | pbrook | |
841 | 9596ebb7 | pbrook | static void pci_bridge_write_config(PCIDevice *d, |
842 | 80b3ada7 | pbrook | uint32_t address, uint32_t val, int len)
|
843 | 80b3ada7 | pbrook | { |
844 | 80b3ada7 | pbrook | PCIBridge *s = (PCIBridge *)d; |
845 | 80b3ada7 | pbrook | |
846 | 80b3ada7 | pbrook | if (address == 0x19 || (address == 0x18 && len > 1)) { |
847 | 80b3ada7 | pbrook | if (address == 0x19) |
848 | 80b3ada7 | pbrook | s->bus->bus_num = val & 0xff;
|
849 | 80b3ada7 | pbrook | else
|
850 | 80b3ada7 | pbrook | s->bus->bus_num = (val >> 8) & 0xff; |
851 | 80b3ada7 | pbrook | #if defined(DEBUG_PCI)
|
852 | 80b3ada7 | pbrook | printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
|
853 | 80b3ada7 | pbrook | #endif
|
854 | 80b3ada7 | pbrook | } |
855 | 80b3ada7 | pbrook | pci_default_write_config(d, address, val, len); |
856 | 80b3ada7 | pbrook | } |
857 | 80b3ada7 | pbrook | |
858 | 3ae80618 | aliguori | PCIBus *pci_find_bus(int bus_num)
|
859 | 3ae80618 | aliguori | { |
860 | 3ae80618 | aliguori | PCIBus *bus = first_bus; |
861 | 3ae80618 | aliguori | |
862 | 3ae80618 | aliguori | while (bus && bus->bus_num != bus_num)
|
863 | 3ae80618 | aliguori | bus = bus->next; |
864 | 3ae80618 | aliguori | |
865 | 3ae80618 | aliguori | return bus;
|
866 | 3ae80618 | aliguori | } |
867 | 3ae80618 | aliguori | |
868 | 3ae80618 | aliguori | PCIDevice *pci_find_device(int bus_num, int slot, int function) |
869 | 3ae80618 | aliguori | { |
870 | 3ae80618 | aliguori | PCIBus *bus = pci_find_bus(bus_num); |
871 | 3ae80618 | aliguori | |
872 | 3ae80618 | aliguori | if (!bus)
|
873 | 3ae80618 | aliguori | return NULL; |
874 | 3ae80618 | aliguori | |
875 | 3ae80618 | aliguori | return bus->devices[PCI_DEVFN(slot, function)];
|
876 | 3ae80618 | aliguori | } |
877 | 3ae80618 | aliguori | |
878 | 480b9f24 | blueswir1 | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
|
879 | 80b3ada7 | pbrook | pci_map_irq_fn map_irq, const char *name) |
880 | 80b3ada7 | pbrook | { |
881 | 80b3ada7 | pbrook | PCIBridge *s; |
882 | 5fafdf24 | ths | s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
|
883 | 80b3ada7 | pbrook | devfn, NULL, pci_bridge_write_config);
|
884 | 480b9f24 | blueswir1 | |
885 | 480b9f24 | blueswir1 | pci_config_set_vendor_id(s->dev.config, vid); |
886 | 480b9f24 | blueswir1 | pci_config_set_device_id(s->dev.config, did); |
887 | 480b9f24 | blueswir1 | |
888 | 80b3ada7 | pbrook | s->dev.config[0x04] = 0x06; // command = bus master, pci mem |
889 | 80b3ada7 | pbrook | s->dev.config[0x05] = 0x00; |
890 | 80b3ada7 | pbrook | s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
891 | 80b3ada7 | pbrook | s->dev.config[0x07] = 0x00; // status = fast devsel |
892 | 80b3ada7 | pbrook | s->dev.config[0x08] = 0x00; // revision |
893 | 80b3ada7 | pbrook | s->dev.config[0x09] = 0x00; // programming i/f |
894 | 173a543b | blueswir1 | pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI); |
895 | 80b3ada7 | pbrook | s->dev.config[0x0D] = 0x10; // latency_timer |
896 | 6407f373 | Isaku Yamahata | s->dev.config[PCI_HEADER_TYPE] = |
897 | 6407f373 | Isaku Yamahata | PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
|
898 | 80b3ada7 | pbrook | s->dev.config[0x1E] = 0xa0; // secondary status |
899 | 80b3ada7 | pbrook | |
900 | 80b3ada7 | pbrook | s->bus = pci_register_secondary_bus(&s->dev, map_irq); |
901 | 80b3ada7 | pbrook | return s->bus;
|
902 | 80b3ada7 | pbrook | } |
903 | 6b1b92d3 | Paul Brook | |
904 | 6b1b92d3 | Paul Brook | static void pci_qdev_init(DeviceState *qdev, void *opaque) |
905 | 6b1b92d3 | Paul Brook | { |
906 | 6b1b92d3 | Paul Brook | PCIDevice *pci_dev = (PCIDevice *)qdev; |
907 | 6b1b92d3 | Paul Brook | pci_qdev_initfn init; |
908 | 6b1b92d3 | Paul Brook | PCIBus *bus; |
909 | 6b1b92d3 | Paul Brook | int devfn;
|
910 | 6b1b92d3 | Paul Brook | |
911 | 6b1b92d3 | Paul Brook | init = opaque; |
912 | 6b1b92d3 | Paul Brook | bus = qdev_get_bus(qdev); |
913 | 6b1b92d3 | Paul Brook | devfn = qdev_get_prop_int(qdev, "devfn", -1); |
914 | 6b1b92d3 | Paul Brook | pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn,
|
915 | 6b1b92d3 | Paul Brook | NULL, NULL);//FIXME:config_read, config_write); |
916 | 6b1b92d3 | Paul Brook | assert(pci_dev); |
917 | 6b1b92d3 | Paul Brook | init(pci_dev); |
918 | 6b1b92d3 | Paul Brook | } |
919 | 6b1b92d3 | Paul Brook | |
920 | 6b1b92d3 | Paul Brook | void pci_qdev_register(const char *name, int size, pci_qdev_initfn init) |
921 | 6b1b92d3 | Paul Brook | { |
922 | 6b1b92d3 | Paul Brook | qdev_register(name, size, pci_qdev_init, init); |
923 | 6b1b92d3 | Paul Brook | } |
924 | 6b1b92d3 | Paul Brook | |
925 | 6b1b92d3 | Paul Brook | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
926 | 6b1b92d3 | Paul Brook | { |
927 | 6b1b92d3 | Paul Brook | DeviceState *dev; |
928 | 6b1b92d3 | Paul Brook | |
929 | 6b1b92d3 | Paul Brook | dev = qdev_create(bus, name); |
930 | 6b1b92d3 | Paul Brook | qdev_set_prop_int(dev, "devfn", devfn);
|
931 | 6b1b92d3 | Paul Brook | qdev_init(dev); |
932 | 6b1b92d3 | Paul Brook | |
933 | 6b1b92d3 | Paul Brook | return (PCIDevice *)dev;
|
934 | 6b1b92d3 | Paul Brook | } |