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tcg: Change tcg_gen_exit_tb argument to uintptr_t
And update all users.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: Add muluh and mulsh opcodes
Use them in places where mulu2 and muls2 are used.Optimize mulx2 with dead low part to mulxh.
tcg: Split rem requirement from div requirement
There are several hosts with only a "div" insn. Remainder is computedmanually from the quotient and inputs. We can do this generically.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Richard Henderson <rth@twiddle.net>
tcg: fix deposit_i64 op on 32-bit targets
On 32-bit TCG targets, when emulating deposit_i64 with a mov_i32 +deposit_i32, care should be taken to not overwrite the low part ofthe second argument before the deposit when it is the same thedestination.
This fixes the shld instruction in qemu-system-x86_64, which in turns...
tcg: Implement muls2 with mulu2
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg: Implement a 64-bit to 32-bit extraction helper
We're going to have use for this shortly in implementing other helpers.
tcg: Implement multiword multiply helpers
tcg: Implement multiword addition helpers
tcg: Add TCGV_IS_UNUSED_*
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opparam_ptr from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
tcg: rework TCG helper flags
The current helper flags, TCG_CALL_CONST and TCG_CALL_PURE might beconfusing and doesn't provide enough granularity for some helpers (FPhelpers for example).
This patch changes them into the following helpers flags:- TCG_CALL_NO_READ_GLOBALS means that the helper does not read globals,...
tcg: Optimize mulu2
Like add2, do operand ordering, constant folding, and dead operandelimination. The latter happens about 15% of all mulu2 during anx86_64 bios boot.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Constant fold add2 and sub2
tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYS
There are several cases that can be handled easier inside bothtranslators and code generators if we have out-of-band valuesfor conditions. It's easy enough to handle ALWAYS and NEVER inthe natural way inside the tcg middle-end....
tcg: Sanity check goto_tb input
Checking that we don't try for idx != [01] is trivial. Checkingthat we don't issue more than one of any index requires a tadmore data and some ifdefs protecting that new variable.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
tcg: Streamline movcond_i64 using 32-bit arithmetic
Avoiding 64-bit arithmetic (outside of the compare) reduces thegenerated op count from 15 to 12, and the generated code size oni686 from 105 to 88 bytes.
tcg: Streamline movcond_i64 using movcond_i32
When movcond_i32 is available we can further reduce the generatedop count from 12 to 6, and the generated code size on i686 from88 to 74 bytes.
tcg: Emit ANDI as EXTU for appropriate constants
Note that andi_i64 failed to perform even the minimaloptimizations promised by the README.
tcg: Optimize initial inputs for ori_i64
Copy the same optimizations from ori_i32.
tcg: Emit XORI as NOT for appropriate constants
Note that xori_i64 failed to perform even the minimaloptimizations promised by the README.
tcg: Implement concat*_i64 with deposit_i64
For tcg_gen_concat_i32_i64 we only use deposit if the host supports it.For tcg_gen_concat32_i64 even if the host does not, as we get identicalcode before and after.
Note that this relies on the ANDI -> EXTU patch for the identity claim....
tcg: Sanity check deposit inputs
Given these are constants, checking once here means everythingafter can assume they're correct.
tcg: Introduce movcond
Implemented with setcond if the target does not providethe optional opcode.
tcg: make tcg_const_ptr actually accept a pointer argument
Make tcg_const_ptr() include a cast so that you can pass it apointer. This allows us to drop the casts we had in all the placesthat use this macro.
Acked-by: Andreas Färber <andreas.faerber@web.de>...
tcg: Fix whitespace in tcg-op.h.
Removing the only tabs in the file.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: malc <av1474@comtv.ru>
tcg: Fix regression in tcg_gen_deposit_i64.
The error being caused by the failure to copy the other half ofthe input to the output after having narrowed the deposit operation.
tcg: Optimize some forms of deposit.
If the deposit replaces the entire word, optimize to a move.
If we're inserting to the top of the word, avoid the mask of arg2as we'll be shifting out all of the garbage and shifting in zeros.
If the host is 32-bit, reduce a 64-bit deposit to a 32-bit deposit...
tcg-i386: Introduce limited deposit support
x86 cannot provide an optimized generic deposit implementation. But atleast for a few special cases, namely for writing bits 0..7, 8..15, and0..15, versions using only a single instruction are feasible.Introducing such limited support improves emulating 16-bit x86 code on...
tcg: Always define all of the TCGOpcode enum members.
By always defining these symbols, we can eliminate a lot of ifdefs.
To allow this to be checked reliably, the semantics of theTCG_TARGET_HAS_* macros must be changed from def/undef to true/false.This allows even more ifdefs to be removed, converting them into...
tcg: If DEBUG_TCGV, distinguish TCGv_ptr from TCGv_i32/TCGv_i64
When compiling with DEBUG_TCGV enabled, make the TCGv_ptr type distinctfrom TCGv_i32/TCGv_i64. This means that using an i32 or i64 TCG op tomanipulate a TCGv_ptr will always be detected at compile time, rather...
tcg/tcg-op.h: Fix prototypes for ld/st functions on 64 bit hosts
The prototypes for the ld/st functions on a 64 bit host declaredthe address parameter as a TCGv_i64 rather than a TCGv_ptr. Thisworked OK (since the two are aliases), but needs to be fixed to...
tcg: Define "deposit" as an optional operation.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
tcg: Fix default definition of divu_i32 and remu_i32.
The arguments to tcg_gen_helper32 for these functions were notupdated correctly in rev 2bece2c88331f024a46527634e3dd91c71d22141.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.
Some hosts (amd64, ia64) have an ABI that ignores the high bitsof the 64-bit register when passing 32-bit arguments. Othersrequire the value to be properly sign-extended for the type.I.e. "int32_t" must be sign-extended and "uint32_t" must be...
tcg: Use INDEX_op_qemu_ld32 for 32-bit results.
tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operandssign-extended in 64-bit registers (regardless of the "real" signof the operand). For that, we need to be able to distinguishbetween a 32-bit load with a 32-bit result and a 32-bit load with...
tcg: Allow target-specific implementation of NOR.
tcg: Allow target-specific implementation of NAND.
tcg: Allow target-specific implementation of EQV.
tcg: Use not_i32 to implement not_i64.
tcg: Change TCGType to an enumeration.
The TCGType name was already used consistently. Changing itto an enumeration instead of a set of defines aids debugging.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Use TCGCond where appropriate.
Use the TCGCond enumeration type in the brcond and setcondrelated prototypes in tcg-op.h and each code generator.
tcg: Name the opcode enumeration.
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.Use that enumeration type instead of "int" whereever appropriate.
tcg: declare internal helpers as const and pure
TCG internal helpers only access to the values passed in arguments, anddo not modify the CPU internal state. Thus they can be declared asconst and pure.
tcg: add div/rem 32-bit helpers
Some targets like ARM would benefit to use 32-bit helpers fordiv/rem/divu/remu.
Create a #define for div2 so that targets can select betweendiv, div2 and helper implementation. Use the helper version if noneof the #define are present....
tcg: Optional target implementation of ORC.
Previously ORC was always implemented by tcg-op.h withan explicit NOT opcode. Allow a target implementation.
tcg: Optional target implementation of ANDC.
Previously ANDC was always implemented by tcg-op.h withan explicit NOT opcode. Allow a target implementation.
tcg: move setcond* ops to non-optional section
setcond is not an optional op, move it to the non-optional section.
tcg: add setcondi pseudo-op
tcg: generic support for conditional set
Defines setcond_{i32,i64} and setcond2_i32 for 64-on-32-bit.
tcg: add ext{8,16,32}u_i{32,64} TCG ops
Currently zero extensions ops are implemented by a and op with aconstant. This is then catched in some backend, and replaced bya zero extension instruction. While this works well on RISCmachines, this adds a useless register move on non-RISC machines....
tcg: fix size of local variables in tcg_gen_bswap64_i64
t0, t1 must be 64 bit values, not 32 bit.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Fix tcg_gen_rotr_i64
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: fix _tl aliases for divu/remu
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6948 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: add _tl aliases for div/divu/rem/remu
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6939 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: add _tl aliases to bswap16/32/64 TCG ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6833 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: add bswap16_i64 and bswap32_i64 TCG ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6832 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: optimize tcg_gen_bswap16_i32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6831 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: fix commit r6805
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6810 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: optimize logical operations
Simplify nand/nor/eqv and move their optimizations to and/or/xor
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6805 c046a42c-6fe2-441c-8c8c-71466251a162
Fix tcg after commit 6800
The introduction of TCGV_EQUAL and not op is slightly broken.The definition of DEBUG_TCGV shows that.
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6802 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: use TCGV_EQUAL_I{32,64}
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6800 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: optimize nor(X, Y, Y), used on PPC for not(X, Y)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6798 c046a42c-6fe2-441c-8c8c-71466251a162
Implement TCG not ops for x86-64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6797 c046a42c-6fe2-441c-8c8c-71466251a162
Implement TCG rotation ops for x86-64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6795 c046a42c-6fe2-441c-8c8c-71466251a162
Fix DEBUG_TCGV compile error.
Don't call TCGV_LOW on arg2. This section of code falls under
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
tcg_temp_local_new should take no parameter
This patch removes useless type information in some calls totcg_temp_local_new. It also removes the parameter from themacro declaration; if a target has to use a specific non-defaultsize then it should use tcg_temp_local_new_{i32,i64}....
Remove unnecessary trailing newlines
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
Some cleanups after dyngen removal
this patch removes some now unused things after dyngen removal.
1. dyngen-exec.h: op_param, op _jmp and some associated macros are now unused;2. Makefile.target: tcg-dyngen is not needed anymore2. tcg/tcg-op.h, tcg/tcg-opc.h: gen-op.h is dead...
Some fixes for TCG debugging
This fixes a few things after Paul's improvements for TCG debugging:
- change TCGv_i64 field name to something different from TCGv_i32 - fix things in tcg that the above change made visible.
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>...
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
Fix rotri_i64 typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5609 c046a42c-6fe2-441c-8c8c-71466251a162
tcg-ops.h: add rotl/rotli and rotr/rotri TCG instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5607 c046a42c-6fe2-441c-8c8c-71466251a162
tcg-op.h: reorder _i64 instructions common to 32- and 64-bit targets
Use the same order as the _i32 version (pure code move). Suggested byLaurent Laurent Desnogues.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5606 c046a42c-6fe2-441c-8c8c-71466251a162
64-bit target subfi fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5602 c046a42c-6fe2-441c-8c8c-71466251a162
tcg-ops.h: add a subfi wrapper
Add a subfi (subtract from immediate) wrapper, useful for the PPC target.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5599 c046a42c-6fe2-441c-8c8c-71466251a162
tcg-ops.h: _i64 TCG immediate instructions cleanup
Move addi_i64, muli_i64 and subi_i64 out of #if TCG_TARGET_REG_BITSas both implementations are strictly identical. Use the sameoptimisation (ie when imm == 0) for addi_i64 and subi_64 than the32-bit version....
TCG: add tcg_const_local_tl()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5504 c046a42c-6fe2-441c-8c8c-71466251a162
TCG: add logical operations found on alpha and powerpc processors
- andc_i32/i64 t0, t1, t2- eqv_i32/i64 t0, t1, t2- nand_i32/i64 t0, t1, t2- nor_i32/i64 t0, t1, t2- orc_i32/i64 t0, t1, t2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5501 c046a42c-6fe2-441c-8c8c-71466251a162
Fix tcg_gen_concat32_i64 on 64-bit hosts.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5306 c046a42c-6fe2-441c-8c8c-71466251a162
Add concat32_i64 and concat_tl_i64 ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5282 c046a42c-6fe2-441c-8c8c-71466251a162
Add concat_i32_i64 op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
suppressed unused macro handling
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4580 c046a42c-6fe2-441c-8c8c-71466251a162
More TCGv type fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4553 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARM conditional branch bug.Add tcg_gen_brcondi.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4552 c046a42c-6fe2-441c-8c8c-71466251a162
added tcg_temp_free() and improved the handling of constants
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4544 c046a42c-6fe2-441c-8c8c-71466251a162
added debug_insn_start debug instruction
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4531 c046a42c-6fe2-441c-8c8c-71466251a162
small shift opts
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4525 c046a42c-6fe2-441c-8c8c-71466251a162
Switch most MIPS logical and arithmetic instructions to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4496 c046a42c-6fe2-441c-8c8c-71466251a162
added not pseudo op - more _tl macros
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4468 c046a42c-6fe2-441c-8c8c-71466251a162
Add TCG native negation op.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4426 c046a42c-6fe2-441c-8c8c-71466251a162
Add zero extension (pseudo-)ops.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4424 c046a42c-6fe2-441c-8c8c-71466251a162
Fix DEBUG_TCGV.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4415 c046a42c-6fe2-441c-8c8c-71466251a162
Rename CONFIG_NO_DYNGEN_OP to CONFIG_DYNGEN_OP to avoid double negatives
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4412 c046a42c-6fe2-441c-8c8c-71466251a162
Add helpers and shorthands for mul and muli operations.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4319 c046a42c-6fe2-441c-8c8c-71466251a162
Skip register moves when the target and the source are the same
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4312 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 9/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4146 c046a42c-6fe2-441c-8c8c-71466251a162
ARM TCG conversion 7/16.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4144 c046a42c-6fe2-441c-8c8c-71466251a162