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1 | e6e5906b | pbrook | /*
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2 | e6e5906b | pbrook | * m68k virtual CPU header
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3 | 5fafdf24 | ths | *
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4 | 0633879f | pbrook | * Copyright (c) 2005-2007 CodeSourcery
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5 | e6e5906b | pbrook | * Written by Paul Brook
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6 | e6e5906b | pbrook | *
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7 | e6e5906b | pbrook | * This library is free software; you can redistribute it and/or
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8 | e6e5906b | pbrook | * modify it under the terms of the GNU Lesser General Public
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9 | e6e5906b | pbrook | * License as published by the Free Software Foundation; either
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10 | e6e5906b | pbrook | * version 2 of the License, or (at your option) any later version.
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11 | e6e5906b | pbrook | *
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12 | e6e5906b | pbrook | * This library is distributed in the hope that it will be useful,
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13 | e6e5906b | pbrook | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | e6e5906b | pbrook | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | e6e5906b | pbrook | * General Public License for more details.
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16 | e6e5906b | pbrook | *
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17 | e6e5906b | pbrook | * You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | e6e5906b | pbrook | */
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20 | e6e5906b | pbrook | #ifndef CPU_M68K_H
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21 | e6e5906b | pbrook | #define CPU_M68K_H
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22 | e6e5906b | pbrook | |
23 | e6e5906b | pbrook | #define TARGET_LONG_BITS 32 |
24 | e6e5906b | pbrook | |
25 | c2764719 | pbrook | #define CPUState struct CPUM68KState |
26 | c2764719 | pbrook | |
27 | e6e5906b | pbrook | #include "cpu-defs.h" |
28 | e6e5906b | pbrook | |
29 | e6e5906b | pbrook | #include "softfloat.h" |
30 | e6e5906b | pbrook | |
31 | e6e5906b | pbrook | #define MAX_QREGS 32 |
32 | e6e5906b | pbrook | |
33 | e6e5906b | pbrook | #define TARGET_HAS_ICE 1 |
34 | e6e5906b | pbrook | |
35 | 9042c0e2 | ths | #define ELF_MACHINE EM_68K
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36 | 9042c0e2 | ths | |
37 | e6e5906b | pbrook | #define EXCP_ACCESS 2 /* Access (MMU) error. */ |
38 | e6e5906b | pbrook | #define EXCP_ADDRESS 3 /* Address error. */ |
39 | e6e5906b | pbrook | #define EXCP_ILLEGAL 4 /* Illegal instruction. */ |
40 | e6e5906b | pbrook | #define EXCP_DIV0 5 /* Divide by zero */ |
41 | e6e5906b | pbrook | #define EXCP_PRIVILEGE 8 /* Privilege violation. */ |
42 | e6e5906b | pbrook | #define EXCP_TRACE 9 |
43 | e6e5906b | pbrook | #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ |
44 | e6e5906b | pbrook | #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ |
45 | e6e5906b | pbrook | #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ |
46 | e6e5906b | pbrook | #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ |
47 | e6e5906b | pbrook | #define EXCP_FORMAT 14 /* RTE format error. */ |
48 | e6e5906b | pbrook | #define EXCP_UNINITIALIZED 15 |
49 | e6e5906b | pbrook | #define EXCP_TRAP0 32 /* User trap #0. */ |
50 | e6e5906b | pbrook | #define EXCP_TRAP15 47 /* User trap #15. */ |
51 | e6e5906b | pbrook | #define EXCP_UNSUPPORTED 61 |
52 | e6e5906b | pbrook | #define EXCP_ICE 13 |
53 | e6e5906b | pbrook | |
54 | 0633879f | pbrook | #define EXCP_RTE 0x100 |
55 | a87295e8 | pbrook | #define EXCP_HALT_INSN 0x101 |
56 | 0633879f | pbrook | |
57 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 2 |
58 | 6ebbf390 | j_mayer | |
59 | e6e5906b | pbrook | typedef struct CPUM68KState { |
60 | e6e5906b | pbrook | uint32_t dregs[8];
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61 | e6e5906b | pbrook | uint32_t aregs[8];
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62 | e6e5906b | pbrook | uint32_t pc; |
63 | e6e5906b | pbrook | uint32_t sr; |
64 | e6e5906b | pbrook | |
65 | 20dcee94 | pbrook | /* SSP and USP. The current_sp is stored in aregs[7], the other here. */
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66 | 20dcee94 | pbrook | int current_sp;
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67 | 20dcee94 | pbrook | uint32_t sp[2];
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68 | 20dcee94 | pbrook | |
69 | e6e5906b | pbrook | /* Condition flags. */
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70 | e6e5906b | pbrook | uint32_t cc_op; |
71 | e6e5906b | pbrook | uint32_t cc_dest; |
72 | e6e5906b | pbrook | uint32_t cc_src; |
73 | e6e5906b | pbrook | uint32_t cc_x; |
74 | e6e5906b | pbrook | |
75 | e6e5906b | pbrook | float64 fregs[8];
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76 | e6e5906b | pbrook | float64 fp_result; |
77 | e6e5906b | pbrook | uint32_t fpcr; |
78 | e6e5906b | pbrook | uint32_t fpsr; |
79 | e6e5906b | pbrook | float_status fp_status; |
80 | e6e5906b | pbrook | |
81 | acf930aa | pbrook | uint64_t mactmp; |
82 | acf930aa | pbrook | /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
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83 | acf930aa | pbrook | two 8-bit parts. We store a single 64-bit value and
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84 | acf930aa | pbrook | rearrange/extend this when changing modes. */
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85 | acf930aa | pbrook | uint64_t macc[4];
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86 | acf930aa | pbrook | uint32_t macsr; |
87 | acf930aa | pbrook | uint32_t mac_mask; |
88 | acf930aa | pbrook | |
89 | e6e5906b | pbrook | /* Temporary storage for DIV helpers. */
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90 | e6e5906b | pbrook | uint32_t div1; |
91 | e6e5906b | pbrook | uint32_t div2; |
92 | 3b46e624 | ths | |
93 | e6e5906b | pbrook | /* MMU status. */
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94 | e6e5906b | pbrook | struct {
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95 | e6e5906b | pbrook | uint32_t ar; |
96 | e6e5906b | pbrook | } mmu; |
97 | 0633879f | pbrook | |
98 | 0633879f | pbrook | /* Control registers. */
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99 | 0633879f | pbrook | uint32_t vbr; |
100 | 0633879f | pbrook | uint32_t mbar; |
101 | 0633879f | pbrook | uint32_t rambar0; |
102 | 20dcee94 | pbrook | uint32_t cacr; |
103 | 0633879f | pbrook | |
104 | e6e5906b | pbrook | /* ??? remove this. */
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105 | e6e5906b | pbrook | uint32_t t1; |
106 | e6e5906b | pbrook | |
107 | 0633879f | pbrook | int pending_vector;
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108 | 0633879f | pbrook | int pending_level;
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109 | e6e5906b | pbrook | |
110 | e6e5906b | pbrook | uint32_t qregs[MAX_QREGS]; |
111 | e6e5906b | pbrook | |
112 | e6e5906b | pbrook | CPU_COMMON |
113 | aaed909a | bellard | |
114 | aaed909a | bellard | uint32_t features; |
115 | e6e5906b | pbrook | } CPUM68KState; |
116 | e6e5906b | pbrook | |
117 | e1f3808e | pbrook | void m68k_tcg_init(void); |
118 | aaed909a | bellard | CPUM68KState *cpu_m68k_init(const char *cpu_model); |
119 | e6e5906b | pbrook | int cpu_m68k_exec(CPUM68KState *s);
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120 | e6e5906b | pbrook | void cpu_m68k_close(CPUM68KState *s);
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121 | 0633879f | pbrook | void do_interrupt(int is_hw); |
122 | e6e5906b | pbrook | /* you can call this signal handler from your SIGBUS and SIGSEGV
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123 | e6e5906b | pbrook | signal handlers to inform the virtual CPU of exceptions. non zero
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124 | e6e5906b | pbrook | is returned if the signal was handled by the virtual CPU. */
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125 | 5fafdf24 | ths | int cpu_m68k_signal_handler(int host_signum, void *pinfo, |
126 | e6e5906b | pbrook | void *puc);
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127 | e6e5906b | pbrook | void cpu_m68k_flush_flags(CPUM68KState *, int); |
128 | e6e5906b | pbrook | |
129 | e6e5906b | pbrook | enum {
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130 | e6e5906b | pbrook | CC_OP_DYNAMIC, /* Use env->cc_op */
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131 | e6e5906b | pbrook | CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
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132 | e6e5906b | pbrook | CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */
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133 | e6e5906b | pbrook | CC_OP_ADD, /* CC_DEST = result, CC_SRC = source */
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134 | e6e5906b | pbrook | CC_OP_SUB, /* CC_DEST = result, CC_SRC = source */
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135 | e6e5906b | pbrook | CC_OP_CMPB, /* CC_DEST = result, CC_SRC = source */
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136 | e6e5906b | pbrook | CC_OP_CMPW, /* CC_DEST = result, CC_SRC = source */
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137 | e6e5906b | pbrook | CC_OP_ADDX, /* CC_DEST = result, CC_SRC = source */
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138 | e6e5906b | pbrook | CC_OP_SUBX, /* CC_DEST = result, CC_SRC = source */
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139 | e1f3808e | pbrook | CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
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140 | e6e5906b | pbrook | }; |
141 | e6e5906b | pbrook | |
142 | e6e5906b | pbrook | #define CCF_C 0x01 |
143 | e6e5906b | pbrook | #define CCF_V 0x02 |
144 | e6e5906b | pbrook | #define CCF_Z 0x04 |
145 | e6e5906b | pbrook | #define CCF_N 0x08 |
146 | 0633879f | pbrook | #define CCF_X 0x10 |
147 | 0633879f | pbrook | |
148 | 0633879f | pbrook | #define SR_I_SHIFT 8 |
149 | 0633879f | pbrook | #define SR_I 0x0700 |
150 | 0633879f | pbrook | #define SR_M 0x1000 |
151 | 0633879f | pbrook | #define SR_S 0x2000 |
152 | 0633879f | pbrook | #define SR_T 0x8000 |
153 | e6e5906b | pbrook | |
154 | 20dcee94 | pbrook | #define M68K_SSP 0 |
155 | 20dcee94 | pbrook | #define M68K_USP 1 |
156 | 20dcee94 | pbrook | |
157 | 20dcee94 | pbrook | /* CACR fields are implementation defined, but some bits are common. */
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158 | 20dcee94 | pbrook | #define M68K_CACR_EUSP 0x10 |
159 | 20dcee94 | pbrook | |
160 | acf930aa | pbrook | #define MACSR_PAV0 0x100 |
161 | acf930aa | pbrook | #define MACSR_OMC 0x080 |
162 | acf930aa | pbrook | #define MACSR_SU 0x040 |
163 | acf930aa | pbrook | #define MACSR_FI 0x020 |
164 | acf930aa | pbrook | #define MACSR_RT 0x010 |
165 | acf930aa | pbrook | #define MACSR_N 0x008 |
166 | acf930aa | pbrook | #define MACSR_Z 0x004 |
167 | acf930aa | pbrook | #define MACSR_V 0x002 |
168 | acf930aa | pbrook | #define MACSR_EV 0x001 |
169 | acf930aa | pbrook | |
170 | 0633879f | pbrook | void m68k_set_irq_level(CPUM68KState *env, int level, uint8_t vector); |
171 | acf930aa | pbrook | void m68k_set_macsr(CPUM68KState *env, uint32_t val);
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172 | 20dcee94 | pbrook | void m68k_switch_sp(CPUM68KState *env);
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173 | e6e5906b | pbrook | |
174 | e6e5906b | pbrook | #define M68K_FPCR_PREC (1 << 6) |
175 | e6e5906b | pbrook | |
176 | a87295e8 | pbrook | void do_m68k_semihosting(CPUM68KState *env, int nr); |
177 | a87295e8 | pbrook | |
178 | d315c888 | pbrook | /* There are 4 ColdFire core ISA revisions: A, A+, B and C.
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179 | d315c888 | pbrook | Each feature covers the subset of instructions common to the
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180 | d315c888 | pbrook | ISA revisions mentioned. */
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181 | d315c888 | pbrook | |
182 | 0402f767 | pbrook | enum m68k_features {
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183 | 0402f767 | pbrook | M68K_FEATURE_CF_ISA_A, |
184 | d315c888 | pbrook | M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
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185 | d315c888 | pbrook | M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
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186 | d315c888 | pbrook | M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
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187 | 0402f767 | pbrook | M68K_FEATURE_CF_FPU, |
188 | 0402f767 | pbrook | M68K_FEATURE_CF_MAC, |
189 | 0402f767 | pbrook | M68K_FEATURE_CF_EMAC, |
190 | d315c888 | pbrook | M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
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191 | d315c888 | pbrook | M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
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192 | e6dbd3b3 | pbrook | M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
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193 | e6dbd3b3 | pbrook | M68K_FEATURE_WORD_INDEX /* word sized address index registers. */
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194 | 0402f767 | pbrook | }; |
195 | 0402f767 | pbrook | |
196 | 0402f767 | pbrook | static inline int m68k_feature(CPUM68KState *env, int feature) |
197 | 0402f767 | pbrook | { |
198 | 0402f767 | pbrook | return (env->features & (1u << feature)) != 0; |
199 | 0402f767 | pbrook | } |
200 | 0402f767 | pbrook | |
201 | 009a4356 | Laurent Vivier | void m68k_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
202 | 009a4356 | Laurent Vivier | |
203 | 0402f767 | pbrook | void register_m68k_insns (CPUM68KState *env);
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204 | 0402f767 | pbrook | |
205 | e6e5906b | pbrook | #ifdef CONFIG_USER_ONLY
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206 | e6e5906b | pbrook | /* Linux uses 8k pages. */
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207 | e6e5906b | pbrook | #define TARGET_PAGE_BITS 13 |
208 | e6e5906b | pbrook | #else
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209 | 5fafdf24 | ths | /* Smallest TLB entry size is 1k. */
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210 | e6e5906b | pbrook | #define TARGET_PAGE_BITS 10 |
211 | e6e5906b | pbrook | #endif
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212 | 9467d44c | ths | |
213 | 9467d44c | ths | #define cpu_init cpu_m68k_init
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214 | 9467d44c | ths | #define cpu_exec cpu_m68k_exec
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215 | 9467d44c | ths | #define cpu_gen_code cpu_m68k_gen_code
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216 | 9467d44c | ths | #define cpu_signal_handler cpu_m68k_signal_handler
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217 | 009a4356 | Laurent Vivier | #define cpu_list m68k_cpu_list
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218 | 9467d44c | ths | |
219 | 6ebbf390 | j_mayer | /* MMU modes definitions */
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220 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
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221 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _user
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222 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 1 |
223 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
224 | 6ebbf390 | j_mayer | { |
225 | 6ebbf390 | j_mayer | return (env->sr & SR_S) == 0 ? 1 : 0; |
226 | 6ebbf390 | j_mayer | } |
227 | 6ebbf390 | j_mayer | |
228 | aaedd1f9 | aurel32 | int cpu_m68k_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
229 | aaedd1f9 | aurel32 | int mmu_idx, int is_softmmu); |
230 | 0b5c1ce8 | Nathan Froyd | #define cpu_handle_mmu_fault cpu_m68k_handle_mmu_fault
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231 | aaedd1f9 | aurel32 | |
232 | 6e68e076 | pbrook | #if defined(CONFIG_USER_ONLY)
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233 | 6e68e076 | pbrook | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
234 | 6e68e076 | pbrook | { |
235 | f8ed7070 | pbrook | if (newsp)
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236 | 6e68e076 | pbrook | env->aregs[7] = newsp;
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237 | 6e68e076 | pbrook | env->dregs[0] = 0; |
238 | 6e68e076 | pbrook | } |
239 | 6e68e076 | pbrook | #endif
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240 | 6e68e076 | pbrook | |
241 | e6e5906b | pbrook | #include "cpu-all.h" |
242 | 622ed360 | aliguori | #include "exec-all.h" |
243 | 622ed360 | aliguori | |
244 | 622ed360 | aliguori | static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
245 | 622ed360 | aliguori | { |
246 | 622ed360 | aliguori | env->pc = tb->pc; |
247 | 622ed360 | aliguori | } |
248 | e6e5906b | pbrook | |
249 | 6b917547 | aliguori | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
250 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
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251 | 6b917547 | aliguori | { |
252 | 6b917547 | aliguori | *pc = env->pc; |
253 | 6b917547 | aliguori | *cs_base = 0;
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254 | 6b917547 | aliguori | *flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
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255 | 6b917547 | aliguori | | (env->sr & SR_S) /* Bit 13 */
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256 | 6b917547 | aliguori | | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ |
257 | 6b917547 | aliguori | } |
258 | 6b917547 | aliguori | |
259 | e6e5906b | pbrook | #endif |