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/*
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* m68k virtual CPU header
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*
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* Copyright (c) 2005-2007 CodeSourcery
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* Written by Paul Brook
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_M68K_H
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#define CPU_M68K_H
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#define TARGET_LONG_BITS 32 |
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#define CPUState struct CPUM68KState |
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#include "cpu-defs.h" |
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#include "softfloat.h" |
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#define MAX_QREGS 32 |
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#define TARGET_HAS_ICE 1 |
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#define ELF_MACHINE EM_68K
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#define EXCP_ACCESS 2 /* Access (MMU) error. */ |
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#define EXCP_ADDRESS 3 /* Address error. */ |
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#define EXCP_ILLEGAL 4 /* Illegal instruction. */ |
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#define EXCP_DIV0 5 /* Divide by zero */ |
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#define EXCP_PRIVILEGE 8 /* Privilege violation. */ |
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#define EXCP_TRACE 9 |
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#define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ |
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#define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ |
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#define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ |
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#define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ |
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#define EXCP_FORMAT 14 /* RTE format error. */ |
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#define EXCP_UNINITIALIZED 15 |
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#define EXCP_TRAP0 32 /* User trap #0. */ |
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#define EXCP_TRAP15 47 /* User trap #15. */ |
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#define EXCP_UNSUPPORTED 61 |
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#define EXCP_ICE 13 |
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#define EXCP_RTE 0x100 |
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#define EXCP_HALT_INSN 0x101 |
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#define NB_MMU_MODES 2 |
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typedef struct CPUM68KState { |
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uint32_t dregs[8];
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uint32_t aregs[8];
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uint32_t pc; |
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uint32_t sr; |
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/* SSP and USP. The current_sp is stored in aregs[7], the other here. */
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int current_sp;
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uint32_t sp[2];
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/* Condition flags. */
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uint32_t cc_op; |
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uint32_t cc_dest; |
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uint32_t cc_src; |
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uint32_t cc_x; |
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float64 fregs[8];
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float64 fp_result; |
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uint32_t fpcr; |
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uint32_t fpsr; |
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float_status fp_status; |
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uint64_t mactmp; |
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/* EMAC Hardware deals with 48-bit values composed of one 32-bit and
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two 8-bit parts. We store a single 64-bit value and
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rearrange/extend this when changing modes. */
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uint64_t macc[4];
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uint32_t macsr; |
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uint32_t mac_mask; |
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/* Temporary storage for DIV helpers. */
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uint32_t div1; |
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uint32_t div2; |
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/* MMU status. */
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struct {
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uint32_t ar; |
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} mmu; |
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/* Control registers. */
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uint32_t vbr; |
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uint32_t mbar; |
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uint32_t rambar0; |
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uint32_t cacr; |
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/* ??? remove this. */
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uint32_t t1; |
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int pending_vector;
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int pending_level;
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uint32_t qregs[MAX_QREGS]; |
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CPU_COMMON |
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uint32_t features; |
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} CPUM68KState; |
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void m68k_tcg_init(void); |
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CPUM68KState *cpu_m68k_init(const char *cpu_model); |
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int cpu_m68k_exec(CPUM68KState *s);
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void cpu_m68k_close(CPUM68KState *s);
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void do_interrupt(int is_hw); |
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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int cpu_m68k_signal_handler(int host_signum, void *pinfo, |
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void *puc);
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void cpu_m68k_flush_flags(CPUM68KState *, int); |
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enum {
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CC_OP_DYNAMIC, /* Use env->cc_op */
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CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
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CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */
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CC_OP_ADD, /* CC_DEST = result, CC_SRC = source */
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CC_OP_SUB, /* CC_DEST = result, CC_SRC = source */
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CC_OP_CMPB, /* CC_DEST = result, CC_SRC = source */
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CC_OP_CMPW, /* CC_DEST = result, CC_SRC = source */
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CC_OP_ADDX, /* CC_DEST = result, CC_SRC = source */
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CC_OP_SUBX, /* CC_DEST = result, CC_SRC = source */
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CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
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}; |
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#define CCF_C 0x01 |
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#define CCF_V 0x02 |
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#define CCF_Z 0x04 |
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#define CCF_N 0x08 |
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#define CCF_X 0x10 |
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#define SR_I_SHIFT 8 |
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#define SR_I 0x0700 |
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#define SR_M 0x1000 |
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#define SR_S 0x2000 |
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#define SR_T 0x8000 |
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#define M68K_SSP 0 |
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#define M68K_USP 1 |
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/* CACR fields are implementation defined, but some bits are common. */
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#define M68K_CACR_EUSP 0x10 |
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#define MACSR_PAV0 0x100 |
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#define MACSR_OMC 0x080 |
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#define MACSR_SU 0x040 |
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#define MACSR_FI 0x020 |
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#define MACSR_RT 0x010 |
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#define MACSR_N 0x008 |
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#define MACSR_Z 0x004 |
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#define MACSR_V 0x002 |
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#define MACSR_EV 0x001 |
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void m68k_set_irq_level(CPUM68KState *env, int level, uint8_t vector); |
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void m68k_set_macsr(CPUM68KState *env, uint32_t val);
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void m68k_switch_sp(CPUM68KState *env);
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#define M68K_FPCR_PREC (1 << 6) |
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void do_m68k_semihosting(CPUM68KState *env, int nr); |
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/* There are 4 ColdFire core ISA revisions: A, A+, B and C.
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Each feature covers the subset of instructions common to the
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ISA revisions mentioned. */
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enum m68k_features {
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M68K_FEATURE_CF_ISA_A, |
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M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
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M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
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M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
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M68K_FEATURE_CF_FPU, |
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M68K_FEATURE_CF_MAC, |
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M68K_FEATURE_CF_EMAC, |
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M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
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M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
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M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
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M68K_FEATURE_WORD_INDEX /* word sized address index registers. */
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}; |
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static inline int m68k_feature(CPUM68KState *env, int feature) |
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{ |
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return (env->features & (1u << feature)) != 0; |
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} |
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void m68k_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
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void register_m68k_insns (CPUM68KState *env);
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#ifdef CONFIG_USER_ONLY
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/* Linux uses 8k pages. */
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#define TARGET_PAGE_BITS 13 |
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#else
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/* Smallest TLB entry size is 1k. */
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#define TARGET_PAGE_BITS 10 |
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#endif
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#define cpu_init cpu_m68k_init
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#define cpu_exec cpu_m68k_exec
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#define cpu_gen_code cpu_m68k_gen_code
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#define cpu_signal_handler cpu_m68k_signal_handler
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#define cpu_list m68k_cpu_list
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _user
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#define MMU_USER_IDX 1 |
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static inline int cpu_mmu_index (CPUState *env) |
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{ |
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return (env->sr & SR_S) == 0 ? 1 : 0; |
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} |
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int cpu_m68k_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu); |
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#define cpu_handle_mmu_fault cpu_m68k_handle_mmu_fault
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#if defined(CONFIG_USER_ONLY)
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static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
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{ |
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if (newsp)
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env->aregs[7] = newsp;
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env->dregs[0] = 0; |
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} |
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#endif
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#include "cpu-all.h" |
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#include "exec-all.h" |
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static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
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{ |
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env->pc = tb->pc; |
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} |
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static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
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target_ulong *cs_base, int *flags)
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{ |
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*pc = env->pc; |
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*cs_base = 0;
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*flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
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| (env->sr & SR_S) /* Bit 13 */
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| ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ |
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} |
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#endif
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