Statistics
| Branch: | Revision:

root / hw / ppc_prep.c @ 9077f01b

History | View | Annotate | Download (20.7 kB)

1 9a64fbe4 bellard
/*
2 a541f297 bellard
 * QEMU PPC PREP hardware System Emulator
3 5fafdf24 ths
 *
4 47103572 j_mayer
 * Copyright (c) 2003-2007 Jocelyn Mayer
5 5fafdf24 ths
 *
6 a541f297 bellard
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 a541f297 bellard
 * of this software and associated documentation files (the "Software"), to deal
8 a541f297 bellard
 * in the Software without restriction, including without limitation the rights
9 a541f297 bellard
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 a541f297 bellard
 * copies of the Software, and to permit persons to whom the Software is
11 a541f297 bellard
 * furnished to do so, subject to the following conditions:
12 a541f297 bellard
 *
13 a541f297 bellard
 * The above copyright notice and this permission notice shall be included in
14 a541f297 bellard
 * all copies or substantial portions of the Software.
15 a541f297 bellard
 *
16 a541f297 bellard
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 a541f297 bellard
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 a541f297 bellard
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 a541f297 bellard
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 a541f297 bellard
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 a541f297 bellard
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 a541f297 bellard
 * THE SOFTWARE.
23 9a64fbe4 bellard
 */
24 87ecb68b pbrook
#include "hw.h"
25 87ecb68b pbrook
#include "nvram.h"
26 87ecb68b pbrook
#include "pc.h"
27 87ecb68b pbrook
#include "fdc.h"
28 87ecb68b pbrook
#include "net.h"
29 87ecb68b pbrook
#include "sysemu.h"
30 87ecb68b pbrook
#include "isa.h"
31 87ecb68b pbrook
#include "pci.h"
32 8ca8c7bc Andreas Färber
#include "pci_host.h"
33 87ecb68b pbrook
#include "ppc.h"
34 87ecb68b pbrook
#include "boards.h"
35 3b3fb322 blueswir1
#include "qemu-log.h"
36 ec82026c Gerd Hoffmann
#include "ide.h"
37 ca20cf32 Blue Swirl
#include "loader.h"
38 1d914fa0 Isaku Yamahata
#include "mc146818rtc.h"
39 2446333c Blue Swirl
#include "blockdev.h"
40 9357b144 Hervé Poussineau
#include "arch_init.h"
41 1e39101c Avi Kivity
#include "exec-memory.h"
42 9fddaa0c bellard
43 9a64fbe4 bellard
//#define HARD_DEBUG_PPC_IO
44 a541f297 bellard
//#define DEBUG_PPC_IO
45 9a64fbe4 bellard
46 fe33cc71 j_mayer
/* SMP is not enabled, for now */
47 fe33cc71 j_mayer
#define MAX_CPUS 1
48 fe33cc71 j_mayer
49 e4bcb14c ths
#define MAX_IDE_BUS 2
50 e4bcb14c ths
51 bba831e8 Paul Brook
#define BIOS_SIZE (1024 * 1024)
52 b6b8bd18 bellard
#define BIOS_FILENAME "ppc_rom.bin"
53 b6b8bd18 bellard
#define KERNEL_LOAD_ADDR 0x01000000
54 b6b8bd18 bellard
#define INITRD_LOAD_ADDR 0x01800000
55 64201201 bellard
56 9a64fbe4 bellard
#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
57 9a64fbe4 bellard
#define DEBUG_PPC_IO
58 9a64fbe4 bellard
#endif
59 9a64fbe4 bellard
60 9a64fbe4 bellard
#if defined (HARD_DEBUG_PPC_IO)
61 001faf32 Blue Swirl
#define PPC_IO_DPRINTF(fmt, ...)                         \
62 9a64fbe4 bellard
do {                                                     \
63 8fec2b8c aliguori
    if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
64 001faf32 Blue Swirl
        qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
65 9a64fbe4 bellard
    } else {                                             \
66 001faf32 Blue Swirl
        printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
67 9a64fbe4 bellard
    }                                                    \
68 9a64fbe4 bellard
} while (0)
69 9a64fbe4 bellard
#elif defined (DEBUG_PPC_IO)
70 0bf9e31a Blue Swirl
#define PPC_IO_DPRINTF(fmt, ...) \
71 0bf9e31a Blue Swirl
qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
72 9a64fbe4 bellard
#else
73 001faf32 Blue Swirl
#define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
74 9a64fbe4 bellard
#endif
75 9a64fbe4 bellard
76 64201201 bellard
/* Constants for devices init */
77 a541f297 bellard
static const int ide_iobase[2] = { 0x1f0, 0x170 };
78 a541f297 bellard
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
79 a541f297 bellard
static const int ide_irq[2] = { 13, 13 };
80 a541f297 bellard
81 a541f297 bellard
#define NE2000_NB_MAX 6
82 a541f297 bellard
83 a541f297 bellard
static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
84 a541f297 bellard
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
85 9a64fbe4 bellard
86 64201201 bellard
/* ISA IO ports bridge */
87 9a64fbe4 bellard
#define PPC_IO_BASE 0x80000000
88 9a64fbe4 bellard
89 64201201 bellard
/* PowerPC control and status registers */
90 64201201 bellard
#if 0 // Not used
91 64201201 bellard
static struct {
92 64201201 bellard
    /* IDs */
93 64201201 bellard
    uint32_t veni_devi;
94 64201201 bellard
    uint32_t revi;
95 64201201 bellard
    /* Control and status */
96 64201201 bellard
    uint32_t gcsr;
97 64201201 bellard
    uint32_t xcfr;
98 64201201 bellard
    uint32_t ct32;
99 64201201 bellard
    uint32_t mcsr;
100 64201201 bellard
    /* General purpose registers */
101 64201201 bellard
    uint32_t gprg[6];
102 64201201 bellard
    /* Exceptions */
103 64201201 bellard
    uint32_t feen;
104 64201201 bellard
    uint32_t fest;
105 64201201 bellard
    uint32_t fema;
106 64201201 bellard
    uint32_t fecl;
107 64201201 bellard
    uint32_t eeen;
108 64201201 bellard
    uint32_t eest;
109 64201201 bellard
    uint32_t eecl;
110 64201201 bellard
    uint32_t eeint;
111 64201201 bellard
    uint32_t eemck0;
112 64201201 bellard
    uint32_t eemck1;
113 64201201 bellard
    /* Error diagnostic */
114 64201201 bellard
} XCSR;
115 64201201 bellard

116 36081602 j_mayer
static void PPC_XCSR_writeb (void *opaque,
117 c227f099 Anthony Liguori
                             target_phys_addr_t addr, uint32_t value)
118 64201201 bellard
{
119 90e189ec Blue Swirl
    printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
120 90e189ec Blue Swirl
           value);
121 64201201 bellard
}
122 64201201 bellard

123 36081602 j_mayer
static void PPC_XCSR_writew (void *opaque,
124 c227f099 Anthony Liguori
                             target_phys_addr_t addr, uint32_t value)
125 9a64fbe4 bellard
{
126 90e189ec Blue Swirl
    printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
127 90e189ec Blue Swirl
           value);
128 9a64fbe4 bellard
}
129 9a64fbe4 bellard

130 36081602 j_mayer
static void PPC_XCSR_writel (void *opaque,
131 c227f099 Anthony Liguori
                             target_phys_addr_t addr, uint32_t value)
132 9a64fbe4 bellard
{
133 90e189ec Blue Swirl
    printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
134 90e189ec Blue Swirl
           value);
135 9a64fbe4 bellard
}
136 9a64fbe4 bellard

137 c227f099 Anthony Liguori
static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
138 64201201 bellard
{
139 64201201 bellard
    uint32_t retval = 0;
140 9a64fbe4 bellard

141 90e189ec Blue Swirl
    printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
142 90e189ec Blue Swirl
           retval);
143 9a64fbe4 bellard

144 64201201 bellard
    return retval;
145 64201201 bellard
}
146 64201201 bellard

147 c227f099 Anthony Liguori
static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
148 9a64fbe4 bellard
{
149 64201201 bellard
    uint32_t retval = 0;
150 64201201 bellard

151 90e189ec Blue Swirl
    printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
152 90e189ec Blue Swirl
           retval);
153 64201201 bellard

154 64201201 bellard
    return retval;
155 9a64fbe4 bellard
}
156 9a64fbe4 bellard

157 c227f099 Anthony Liguori
static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
158 9a64fbe4 bellard
{
159 9a64fbe4 bellard
    uint32_t retval = 0;
160 9a64fbe4 bellard

161 90e189ec Blue Swirl
    printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
162 90e189ec Blue Swirl
           retval);
163 9a64fbe4 bellard

164 9a64fbe4 bellard
    return retval;
165 9a64fbe4 bellard
}
166 9a64fbe4 bellard

167 0c90c52f Avi Kivity
static const MemoryRegionOps PPC_XCSR_ops = {
168 0c90c52f Avi Kivity
    .old_mmio = {
169 0c90c52f Avi Kivity
        .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
170 0c90c52f Avi Kivity
        .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
171 0c90c52f Avi Kivity
    },
172 0c90c52f Avi Kivity
    .endianness = DEVICE_LITTLE_ENDIAN,
173 9a64fbe4 bellard
};
174 9a64fbe4 bellard

175 b6b8bd18 bellard
#endif
176 9a64fbe4 bellard
177 64201201 bellard
/* Fake super-io ports for PREP platform (Intel 82378ZB) */
178 c227f099 Anthony Liguori
typedef struct sysctrl_t {
179 c4781a51 j_mayer
    qemu_irq reset_irq;
180 43a34704 Blue Swirl
    M48t59State *nvram;
181 64201201 bellard
    uint8_t state;
182 64201201 bellard
    uint8_t syscontrol;
183 64201201 bellard
    uint8_t fake_io[2];
184 da9b266b bellard
    int contiguous_map;
185 fb3444b8 bellard
    int endian;
186 c227f099 Anthony Liguori
} sysctrl_t;
187 9a64fbe4 bellard
188 64201201 bellard
enum {
189 64201201 bellard
    STATE_HARDFILE = 0x01,
190 9a64fbe4 bellard
};
191 9a64fbe4 bellard
192 c227f099 Anthony Liguori
static sysctrl_t *sysctrl;
193 9a64fbe4 bellard
194 a541f297 bellard
static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
195 9a64fbe4 bellard
{
196 c227f099 Anthony Liguori
    sysctrl_t *sysctrl = opaque;
197 64201201 bellard
198 aae9366a j_mayer
    PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
199 aae9366a j_mayer
                   val);
200 64201201 bellard
    sysctrl->fake_io[addr - 0x0398] = val;
201 9a64fbe4 bellard
}
202 9a64fbe4 bellard
203 a541f297 bellard
static uint32_t PREP_io_read (void *opaque, uint32_t addr)
204 9a64fbe4 bellard
{
205 c227f099 Anthony Liguori
    sysctrl_t *sysctrl = opaque;
206 9a64fbe4 bellard
207 aae9366a j_mayer
    PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
208 64201201 bellard
                   sysctrl->fake_io[addr - 0x0398]);
209 64201201 bellard
    return sysctrl->fake_io[addr - 0x0398];
210 64201201 bellard
}
211 9a64fbe4 bellard
212 a541f297 bellard
static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
213 9a64fbe4 bellard
{
214 c227f099 Anthony Liguori
    sysctrl_t *sysctrl = opaque;
215 64201201 bellard
216 aae9366a j_mayer
    PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
217 aae9366a j_mayer
                   addr - PPC_IO_BASE, val);
218 9a64fbe4 bellard
    switch (addr) {
219 9a64fbe4 bellard
    case 0x0092:
220 9a64fbe4 bellard
        /* Special port 92 */
221 9a64fbe4 bellard
        /* Check soft reset asked */
222 64201201 bellard
        if (val & 0x01) {
223 c4781a51 j_mayer
            qemu_irq_raise(sysctrl->reset_irq);
224 c4781a51 j_mayer
        } else {
225 c4781a51 j_mayer
            qemu_irq_lower(sysctrl->reset_irq);
226 9a64fbe4 bellard
        }
227 9a64fbe4 bellard
        /* Check LE mode */
228 64201201 bellard
        if (val & 0x02) {
229 fb3444b8 bellard
            sysctrl->endian = 1;
230 fb3444b8 bellard
        } else {
231 fb3444b8 bellard
            sysctrl->endian = 0;
232 9a64fbe4 bellard
        }
233 9a64fbe4 bellard
        break;
234 64201201 bellard
    case 0x0800:
235 64201201 bellard
        /* Motorola CPU configuration register : read-only */
236 64201201 bellard
        break;
237 64201201 bellard
    case 0x0802:
238 64201201 bellard
        /* Motorola base module feature register : read-only */
239 64201201 bellard
        break;
240 64201201 bellard
    case 0x0803:
241 64201201 bellard
        /* Motorola base module status register : read-only */
242 64201201 bellard
        break;
243 9a64fbe4 bellard
    case 0x0808:
244 64201201 bellard
        /* Hardfile light register */
245 64201201 bellard
        if (val & 1)
246 64201201 bellard
            sysctrl->state |= STATE_HARDFILE;
247 64201201 bellard
        else
248 64201201 bellard
            sysctrl->state &= ~STATE_HARDFILE;
249 9a64fbe4 bellard
        break;
250 9a64fbe4 bellard
    case 0x0810:
251 9a64fbe4 bellard
        /* Password protect 1 register */
252 64201201 bellard
        if (sysctrl->nvram != NULL)
253 64201201 bellard
            m48t59_toggle_lock(sysctrl->nvram, 1);
254 9a64fbe4 bellard
        break;
255 9a64fbe4 bellard
    case 0x0812:
256 9a64fbe4 bellard
        /* Password protect 2 register */
257 64201201 bellard
        if (sysctrl->nvram != NULL)
258 64201201 bellard
            m48t59_toggle_lock(sysctrl->nvram, 2);
259 9a64fbe4 bellard
        break;
260 9a64fbe4 bellard
    case 0x0814:
261 64201201 bellard
        /* L2 invalidate register */
262 c68ea704 bellard
        //        tlb_flush(first_cpu, 1);
263 9a64fbe4 bellard
        break;
264 9a64fbe4 bellard
    case 0x081C:
265 9a64fbe4 bellard
        /* system control register */
266 64201201 bellard
        sysctrl->syscontrol = val & 0x0F;
267 9a64fbe4 bellard
        break;
268 9a64fbe4 bellard
    case 0x0850:
269 9a64fbe4 bellard
        /* I/O map type register */
270 da9b266b bellard
        sysctrl->contiguous_map = val & 0x01;
271 9a64fbe4 bellard
        break;
272 9a64fbe4 bellard
    default:
273 aae9366a j_mayer
        printf("ERROR: unaffected IO port write: %04" PRIx32
274 aae9366a j_mayer
               " => %02" PRIx32"\n", addr, val);
275 9a64fbe4 bellard
        break;
276 9a64fbe4 bellard
    }
277 9a64fbe4 bellard
}
278 9a64fbe4 bellard
279 a541f297 bellard
static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
280 9a64fbe4 bellard
{
281 c227f099 Anthony Liguori
    sysctrl_t *sysctrl = opaque;
282 9a64fbe4 bellard
    uint32_t retval = 0xFF;
283 9a64fbe4 bellard
284 9a64fbe4 bellard
    switch (addr) {
285 9a64fbe4 bellard
    case 0x0092:
286 9a64fbe4 bellard
        /* Special port 92 */
287 64201201 bellard
        retval = 0x00;
288 64201201 bellard
        break;
289 64201201 bellard
    case 0x0800:
290 64201201 bellard
        /* Motorola CPU configuration register */
291 64201201 bellard
        retval = 0xEF; /* MPC750 */
292 64201201 bellard
        break;
293 64201201 bellard
    case 0x0802:
294 64201201 bellard
        /* Motorola Base module feature register */
295 64201201 bellard
        retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
296 64201201 bellard
        break;
297 64201201 bellard
    case 0x0803:
298 64201201 bellard
        /* Motorola base module status register */
299 64201201 bellard
        retval = 0xE0; /* Standard MPC750 */
300 9a64fbe4 bellard
        break;
301 9a64fbe4 bellard
    case 0x080C:
302 9a64fbe4 bellard
        /* Equipment present register:
303 9a64fbe4 bellard
         *  no L2 cache
304 9a64fbe4 bellard
         *  no upgrade processor
305 9a64fbe4 bellard
         *  no cards in PCI slots
306 9a64fbe4 bellard
         *  SCSI fuse is bad
307 9a64fbe4 bellard
         */
308 64201201 bellard
        retval = 0x3C;
309 64201201 bellard
        break;
310 64201201 bellard
    case 0x0810:
311 64201201 bellard
        /* Motorola base module extended feature register */
312 64201201 bellard
        retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
313 9a64fbe4 bellard
        break;
314 da9b266b bellard
    case 0x0814:
315 da9b266b bellard
        /* L2 invalidate: don't care */
316 da9b266b bellard
        break;
317 9a64fbe4 bellard
    case 0x0818:
318 9a64fbe4 bellard
        /* Keylock */
319 9a64fbe4 bellard
        retval = 0x00;
320 9a64fbe4 bellard
        break;
321 9a64fbe4 bellard
    case 0x081C:
322 9a64fbe4 bellard
        /* system control register
323 9a64fbe4 bellard
         * 7 - 6 / 1 - 0: L2 cache enable
324 9a64fbe4 bellard
         */
325 64201201 bellard
        retval = sysctrl->syscontrol;
326 9a64fbe4 bellard
        break;
327 9a64fbe4 bellard
    case 0x0823:
328 9a64fbe4 bellard
        /* */
329 9a64fbe4 bellard
        retval = 0x03; /* no L2 cache */
330 9a64fbe4 bellard
        break;
331 9a64fbe4 bellard
    case 0x0850:
332 9a64fbe4 bellard
        /* I/O map type register */
333 da9b266b bellard
        retval = sysctrl->contiguous_map;
334 9a64fbe4 bellard
        break;
335 9a64fbe4 bellard
    default:
336 aae9366a j_mayer
        printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
337 9a64fbe4 bellard
        break;
338 9a64fbe4 bellard
    }
339 aae9366a j_mayer
    PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
340 aae9366a j_mayer
                   addr - PPC_IO_BASE, retval);
341 9a64fbe4 bellard
342 9a64fbe4 bellard
    return retval;
343 9a64fbe4 bellard
}
344 9a64fbe4 bellard
345 c227f099 Anthony Liguori
static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
346 c227f099 Anthony Liguori
                                                 target_phys_addr_t addr)
347 da9b266b bellard
{
348 da9b266b bellard
    if (sysctrl->contiguous_map == 0) {
349 da9b266b bellard
        /* 64 KB contiguous space for IOs */
350 da9b266b bellard
        addr &= 0xFFFF;
351 da9b266b bellard
    } else {
352 da9b266b bellard
        /* 8 MB non-contiguous space for IOs */
353 da9b266b bellard
        addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
354 da9b266b bellard
    }
355 da9b266b bellard
356 da9b266b bellard
    return addr;
357 da9b266b bellard
}
358 da9b266b bellard
359 c227f099 Anthony Liguori
static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
360 da9b266b bellard
                                uint32_t value)
361 da9b266b bellard
{
362 c227f099 Anthony Liguori
    sysctrl_t *sysctrl = opaque;
363 da9b266b bellard
364 da9b266b bellard
    addr = prep_IO_address(sysctrl, addr);
365 afcea8cb Blue Swirl
    cpu_outb(addr, value);
366 da9b266b bellard
}
367 da9b266b bellard
368 c227f099 Anthony Liguori
static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
369 da9b266b bellard
{
370 c227f099 Anthony Liguori
    sysctrl_t *sysctrl = opaque;
371 da9b266b bellard
    uint32_t ret;
372 da9b266b bellard
373 da9b266b bellard
    addr = prep_IO_address(sysctrl, addr);
374 afcea8cb Blue Swirl
    ret = cpu_inb(addr);
375 da9b266b bellard
376 da9b266b bellard
    return ret;
377 da9b266b bellard
}
378 da9b266b bellard
379 c227f099 Anthony Liguori
static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
380 da9b266b bellard
                                uint32_t value)
381 da9b266b bellard
{
382 c227f099 Anthony Liguori
    sysctrl_t *sysctrl = opaque;
383 da9b266b bellard
384 da9b266b bellard
    addr = prep_IO_address(sysctrl, addr);
385 90e189ec Blue Swirl
    PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
386 afcea8cb Blue Swirl
    cpu_outw(addr, value);
387 da9b266b bellard
}
388 da9b266b bellard
389 c227f099 Anthony Liguori
static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
390 da9b266b bellard
{
391 c227f099 Anthony Liguori
    sysctrl_t *sysctrl = opaque;
392 da9b266b bellard
    uint32_t ret;
393 da9b266b bellard
394 da9b266b bellard
    addr = prep_IO_address(sysctrl, addr);
395 afcea8cb Blue Swirl
    ret = cpu_inw(addr);
396 90e189ec Blue Swirl
    PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
397 da9b266b bellard
398 da9b266b bellard
    return ret;
399 da9b266b bellard
}
400 da9b266b bellard
401 c227f099 Anthony Liguori
static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
402 da9b266b bellard
                                uint32_t value)
403 da9b266b bellard
{
404 c227f099 Anthony Liguori
    sysctrl_t *sysctrl = opaque;
405 da9b266b bellard
406 da9b266b bellard
    addr = prep_IO_address(sysctrl, addr);
407 90e189ec Blue Swirl
    PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
408 afcea8cb Blue Swirl
    cpu_outl(addr, value);
409 da9b266b bellard
}
410 da9b266b bellard
411 c227f099 Anthony Liguori
static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
412 da9b266b bellard
{
413 c227f099 Anthony Liguori
    sysctrl_t *sysctrl = opaque;
414 da9b266b bellard
    uint32_t ret;
415 da9b266b bellard
416 da9b266b bellard
    addr = prep_IO_address(sysctrl, addr);
417 afcea8cb Blue Swirl
    ret = cpu_inl(addr);
418 90e189ec Blue Swirl
    PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
419 da9b266b bellard
420 da9b266b bellard
    return ret;
421 da9b266b bellard
}
422 da9b266b bellard
423 0c90c52f Avi Kivity
static const MemoryRegionOps PPC_prep_io_ops = {
424 0c90c52f Avi Kivity
    .old_mmio = {
425 0c90c52f Avi Kivity
        .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },
426 0c90c52f Avi Kivity
        .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },
427 0c90c52f Avi Kivity
    },
428 0c90c52f Avi Kivity
    .endianness = DEVICE_LITTLE_ENDIAN,
429 da9b266b bellard
};
430 da9b266b bellard
431 64201201 bellard
#define NVRAM_SIZE        0x2000
432 a541f297 bellard
433 4556bd8b Blue Swirl
static void cpu_request_exit(void *opaque, int irq, int level)
434 4556bd8b Blue Swirl
{
435 e2684c0b Andreas Färber
    CPUPPCState *env = cpu_single_env;
436 4556bd8b Blue Swirl
437 4556bd8b Blue Swirl
    if (env && level) {
438 4556bd8b Blue Swirl
        cpu_exit(env);
439 4556bd8b Blue Swirl
    }
440 4556bd8b Blue Swirl
}
441 4556bd8b Blue Swirl
442 1bba0dc9 Andreas Färber
static void ppc_prep_reset(void *opaque)
443 1bba0dc9 Andreas Färber
{
444 5c3e735f Andreas Färber
    PowerPCCPU *cpu = opaque;
445 1bba0dc9 Andreas Färber
446 5c3e735f Andreas Färber
    cpu_reset(CPU(cpu));
447 1bba0dc9 Andreas Färber
}
448 1bba0dc9 Andreas Färber
449 26aa7d72 bellard
/* PowerPC PREP hardware initialisation */
450 c227f099 Anthony Liguori
static void ppc_prep_init (ram_addr_t ram_size,
451 3023f332 aliguori
                           const char *boot_device,
452 b881c2c6 blueswir1
                           const char *kernel_filename,
453 94fc95cd j_mayer
                           const char *kernel_cmdline,
454 94fc95cd j_mayer
                           const char *initrd_filename,
455 94fc95cd j_mayer
                           const char *cpu_model)
456 a541f297 bellard
{
457 0c90c52f Avi Kivity
    MemoryRegion *sysmem = get_system_memory();
458 a9bf3df0 Andreas Färber
    PowerPCCPU *cpu = NULL;
459 e2684c0b Andreas Färber
    CPUPPCState *env = NULL;
460 5cea8590 Paul Brook
    char *filename;
461 c227f099 Anthony Liguori
    nvram_t nvram;
462 43a34704 Blue Swirl
    M48t59State *m48t59;
463 0c90c52f Avi Kivity
    MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);
464 0c90c52f Avi Kivity
#if 0
465 0c90c52f Avi Kivity
    MemoryRegion *xcsr = g_new(MemoryRegion, 1);
466 0c90c52f Avi Kivity
#endif
467 4157a662 bellard
    int linux_boot, i, nb_nics1, bios_size;
468 0c90c52f Avi Kivity
    MemoryRegion *ram = g_new(MemoryRegion, 1);
469 0c90c52f Avi Kivity
    MemoryRegion *bios = g_new(MemoryRegion, 1);
470 093209cd Blue Swirl
    uint32_t kernel_base, initrd_base;
471 093209cd Blue Swirl
    long kernel_size, initrd_size;
472 8ca8c7bc Andreas Färber
    DeviceState *dev;
473 8ca8c7bc Andreas Färber
    SysBusDevice *sys;
474 8ca8c7bc Andreas Färber
    PCIHostState *pcihost;
475 46e50e9d bellard
    PCIBus *pci_bus;
476 506b7ddf Andreas Färber
    PCIDevice *pci;
477 48a18b3c Hervé Poussineau
    ISABus *isa_bus;
478 4556bd8b Blue Swirl
    qemu_irq *cpu_exit_irq;
479 28c5af54 j_mayer
    int ppc_boot_device;
480 f455e98c Gerd Hoffmann
    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
481 fd8014e1 Gerd Hoffmann
    DriveInfo *fd[MAX_FD];
482 64201201 bellard
483 7267c094 Anthony Liguori
    sysctrl = g_malloc0(sizeof(sysctrl_t));
484 a541f297 bellard
485 a541f297 bellard
    linux_boot = (kernel_filename != NULL);
486 0a032cbe j_mayer
487 c68ea704 bellard
    /* init CPUs */
488 94fc95cd j_mayer
    if (cpu_model == NULL)
489 b37fc148 Gerd Hoffmann
        cpu_model = "602";
490 fe33cc71 j_mayer
    for (i = 0; i < smp_cpus; i++) {
491 a9bf3df0 Andreas Färber
        cpu = cpu_ppc_init(cpu_model);
492 a9bf3df0 Andreas Färber
        if (cpu == NULL) {
493 aaed909a bellard
            fprintf(stderr, "Unable to find PowerPC CPU definition\n");
494 aaed909a bellard
            exit(1);
495 aaed909a bellard
        }
496 a9bf3df0 Andreas Färber
        env = &cpu->env;
497 a9bf3df0 Andreas Färber
498 4018bae9 j_mayer
        if (env->flags & POWERPC_FLAG_RTC_CLK) {
499 4018bae9 j_mayer
            /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
500 4018bae9 j_mayer
            cpu_ppc_tb_init(env, 7812500UL);
501 4018bae9 j_mayer
        } else {
502 4018bae9 j_mayer
            /* Set time-base frequency to 100 Mhz */
503 4018bae9 j_mayer
            cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
504 4018bae9 j_mayer
        }
505 5c3e735f Andreas Färber
        qemu_register_reset(ppc_prep_reset, cpu);
506 fe33cc71 j_mayer
    }
507 a541f297 bellard
508 a541f297 bellard
    /* allocate RAM */
509 c5705a77 Avi Kivity
    memory_region_init_ram(ram, "ppc_prep.ram", ram_size);
510 c5705a77 Avi Kivity
    vmstate_register_ram_global(ram);
511 0c90c52f Avi Kivity
    memory_region_add_subregion(sysmem, 0, ram);
512 cf9c147c blueswir1
513 64201201 bellard
    /* allocate and load BIOS */
514 c5705a77 Avi Kivity
    memory_region_init_ram(bios, "ppc_prep.bios", BIOS_SIZE);
515 809680c0 Andreas Färber
    memory_region_set_readonly(bios, true);
516 809680c0 Andreas Färber
    memory_region_add_subregion(sysmem, (uint32_t)(-BIOS_SIZE), bios);
517 c5705a77 Avi Kivity
    vmstate_register_ram_global(bios);
518 1192dad8 j_mayer
    if (bios_name == NULL)
519 1192dad8 j_mayer
        bios_name = BIOS_FILENAME;
520 5cea8590 Paul Brook
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
521 5cea8590 Paul Brook
    if (filename) {
522 5cea8590 Paul Brook
        bios_size = get_image_size(filename);
523 5cea8590 Paul Brook
    } else {
524 5cea8590 Paul Brook
        bios_size = -1;
525 5cea8590 Paul Brook
    }
526 dcac9679 pbrook
    if (bios_size > 0 && bios_size <= BIOS_SIZE) {
527 c227f099 Anthony Liguori
        target_phys_addr_t bios_addr;
528 dcac9679 pbrook
        bios_size = (bios_size + 0xfff) & ~0xfff;
529 dcac9679 pbrook
        bios_addr = (uint32_t)(-bios_size);
530 5cea8590 Paul Brook
        bios_size = load_image_targphys(filename, bios_addr, bios_size);
531 dcac9679 pbrook
    }
532 4157a662 bellard
    if (bios_size < 0 || bios_size > BIOS_SIZE) {
533 5cea8590 Paul Brook
        hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
534 5cea8590 Paul Brook
    }
535 5cea8590 Paul Brook
    if (filename) {
536 7267c094 Anthony Liguori
        g_free(filename);
537 64201201 bellard
    }
538 26aa7d72 bellard
539 a541f297 bellard
    if (linux_boot) {
540 64201201 bellard
        kernel_base = KERNEL_LOAD_ADDR;
541 a541f297 bellard
        /* now we can load the kernel */
542 dcac9679 pbrook
        kernel_size = load_image_targphys(kernel_filename, kernel_base,
543 dcac9679 pbrook
                                          ram_size - kernel_base);
544 64201201 bellard
        if (kernel_size < 0) {
545 2ac71179 Paul Brook
            hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
546 a541f297 bellard
            exit(1);
547 a541f297 bellard
        }
548 a541f297 bellard
        /* load initrd */
549 a541f297 bellard
        if (initrd_filename) {
550 64201201 bellard
            initrd_base = INITRD_LOAD_ADDR;
551 dcac9679 pbrook
            initrd_size = load_image_targphys(initrd_filename, initrd_base,
552 dcac9679 pbrook
                                              ram_size - initrd_base);
553 a541f297 bellard
            if (initrd_size < 0) {
554 2ac71179 Paul Brook
                hw_error("qemu: could not load initial ram disk '%s'\n",
555 4a057712 j_mayer
                          initrd_filename);
556 a541f297 bellard
            }
557 64201201 bellard
        } else {
558 64201201 bellard
            initrd_base = 0;
559 64201201 bellard
            initrd_size = 0;
560 a541f297 bellard
        }
561 6ac0e82d balrog
        ppc_boot_device = 'm';
562 a541f297 bellard
    } else {
563 64201201 bellard
        kernel_base = 0;
564 64201201 bellard
        kernel_size = 0;
565 64201201 bellard
        initrd_base = 0;
566 64201201 bellard
        initrd_size = 0;
567 28c5af54 j_mayer
        ppc_boot_device = '\0';
568 28c5af54 j_mayer
        /* For now, OHW cannot boot from the network. */
569 0d913fdb j_mayer
        for (i = 0; boot_device[i] != '\0'; i++) {
570 0d913fdb j_mayer
            if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
571 0d913fdb j_mayer
                ppc_boot_device = boot_device[i];
572 28c5af54 j_mayer
                break;
573 0d913fdb j_mayer
            }
574 28c5af54 j_mayer
        }
575 28c5af54 j_mayer
        if (ppc_boot_device == '\0') {
576 28c5af54 j_mayer
            fprintf(stderr, "No valid boot device for Mac99 machine\n");
577 28c5af54 j_mayer
            exit(1);
578 28c5af54 j_mayer
        }
579 a541f297 bellard
    }
580 a541f297 bellard
581 dd37a5e4 j_mayer
    if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
582 2ac71179 Paul Brook
        hw_error("Only 6xx bus is supported on PREP machine\n");
583 dd37a5e4 j_mayer
    }
584 8ca8c7bc Andreas Färber
585 8ca8c7bc Andreas Färber
    dev = qdev_create(NULL, "raven-pcihost");
586 8ca8c7bc Andreas Färber
    sys = sysbus_from_qdev(dev);
587 8ca8c7bc Andreas Färber
    pcihost = DO_UPCAST(PCIHostState, busdev, sys);
588 8ca8c7bc Andreas Färber
    pcihost->address_space = get_system_memory();
589 f05f6b4a Paolo Bonzini
    object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
590 f424d5c4 Paolo Bonzini
    qdev_init_nofail(dev);
591 8ca8c7bc Andreas Färber
    pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
592 8ca8c7bc Andreas Färber
    if (pci_bus == NULL) {
593 8ca8c7bc Andreas Färber
        fprintf(stderr, "Couldn't create PCI host controller.\n");
594 8ca8c7bc Andreas Färber
        exit(1);
595 8ca8c7bc Andreas Färber
    }
596 8ca8c7bc Andreas Färber
597 506b7ddf Andreas Färber
    /* PCI -> ISA bridge */
598 506b7ddf Andreas Färber
    pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
599 506b7ddf Andreas Färber
    cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
600 506b7ddf Andreas Färber
    qdev_connect_gpio_out(&pci->qdev, 0,
601 506b7ddf Andreas Färber
                          first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
602 506b7ddf Andreas Färber
    qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
603 506b7ddf Andreas Färber
    sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
604 506b7ddf Andreas Färber
    sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
605 506b7ddf Andreas Färber
    sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
606 506b7ddf Andreas Färber
    sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
607 506b7ddf Andreas Färber
    isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
608 506b7ddf Andreas Färber
609 da9b266b bellard
    /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
610 0c90c52f Avi Kivity
    memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl,
611 0c90c52f Avi Kivity
                          "ppc-io", 0x00800000);
612 0c90c52f Avi Kivity
    memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);
613 64201201 bellard
614 a541f297 bellard
    /* init basic PC hardware */
615 78895427 Gerd Hoffmann
    pci_vga_init(pci_bus);
616 a541f297 bellard
617 ac0be998 Gerd Hoffmann
    if (serial_hds[0])
618 48a18b3c Hervé Poussineau
        serial_isa_init(isa_bus, 0, serial_hds[0]);
619 a541f297 bellard
    nb_nics1 = nb_nics;
620 a541f297 bellard
    if (nb_nics1 > NE2000_NB_MAX)
621 a541f297 bellard
        nb_nics1 = NE2000_NB_MAX;
622 a541f297 bellard
    for(i = 0; i < nb_nics1; i++) {
623 5652ef78 aurel32
        if (nd_table[i].model == NULL) {
624 7267c094 Anthony Liguori
            nd_table[i].model = g_strdup("ne2k_isa");
625 5652ef78 aurel32
        }
626 5652ef78 aurel32
        if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
627 48a18b3c Hervé Poussineau
            isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
628 48a18b3c Hervé Poussineau
                            &nd_table[i]);
629 a41b2ff2 pbrook
        } else {
630 07caea31 Markus Armbruster
            pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
631 a41b2ff2 pbrook
        }
632 a541f297 bellard
    }
633 a541f297 bellard
634 75717903 Isaku Yamahata
    ide_drive_get(hd, MAX_IDE_BUS);
635 81aa0647 Aurelien Jarno
    for(i = 0; i < MAX_IDE_BUS; i++) {
636 48a18b3c Hervé Poussineau
        isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
637 e4bcb14c ths
                     hd[2 * i],
638 e4bcb14c ths
                     hd[2 * i + 1]);
639 a541f297 bellard
    }
640 48a18b3c Hervé Poussineau
    isa_create_simple(isa_bus, "i8042");
641 4556bd8b Blue Swirl
642 a541f297 bellard
    //    SB16_init();
643 a541f297 bellard
644 e4bcb14c ths
    for(i = 0; i < MAX_FD; i++) {
645 fd8014e1 Gerd Hoffmann
        fd[i] = drive_get(IF_FLOPPY, 0, i);
646 e4bcb14c ths
    }
647 48a18b3c Hervé Poussineau
    fdctrl_init_isa(isa_bus, fd);
648 a541f297 bellard
649 a541f297 bellard
    /* Register fake IO ports for PREP */
650 c4781a51 j_mayer
    sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
651 64201201 bellard
    register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
652 64201201 bellard
    register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
653 a541f297 bellard
    /* System control ports */
654 64201201 bellard
    register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
655 64201201 bellard
    register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
656 64201201 bellard
    register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
657 64201201 bellard
    register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
658 64201201 bellard
    /* PowerPC control and status register group */
659 b6b8bd18 bellard
#if 0
660 0c90c52f Avi Kivity
    memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
661 0c90c52f Avi Kivity
    memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
662 b6b8bd18 bellard
#endif
663 a541f297 bellard
664 0d92ed30 pbrook
    if (usb_enabled) {
665 afb9a60e Gerd Hoffmann
        pci_create_simple(pci_bus, -1, "pci-ohci");
666 0d92ed30 pbrook
    }
667 0d92ed30 pbrook
668 48e93728 Andreas Färber
    m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
669 3cbee15b j_mayer
    if (m48t59 == NULL)
670 64201201 bellard
        return;
671 3cbee15b j_mayer
    sysctrl->nvram = m48t59;
672 64201201 bellard
673 64201201 bellard
    /* Initialise NVRAM */
674 3cbee15b j_mayer
    nvram.opaque = m48t59;
675 3cbee15b j_mayer
    nvram.read_fn = &m48t59_read;
676 3cbee15b j_mayer
    nvram.write_fn = &m48t59_write;
677 6ac0e82d balrog
    PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
678 64201201 bellard
                         kernel_base, kernel_size,
679 b6b8bd18 bellard
                         kernel_cmdline,
680 64201201 bellard
                         initrd_base, initrd_size,
681 64201201 bellard
                         /* XXX: need an option to load a NVRAM image */
682 b6b8bd18 bellard
                         0,
683 b6b8bd18 bellard
                         graphic_width, graphic_height, graphic_depth);
684 c0e564d5 bellard
685 c0e564d5 bellard
    /* Special port to get debug messages from Open-Firmware */
686 c0e564d5 bellard
    register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
687 9357b144 Hervé Poussineau
688 9357b144 Hervé Poussineau
    /* Initialize audio subsystem */
689 9357b144 Hervé Poussineau
    audio_init(isa_bus, pci_bus);
690 a541f297 bellard
}
691 c0e564d5 bellard
692 f80f9ec9 Anthony Liguori
static QEMUMachine prep_machine = {
693 4b32e168 aliguori
    .name = "prep",
694 4b32e168 aliguori
    .desc = "PowerPC PREP platform",
695 4b32e168 aliguori
    .init = ppc_prep_init,
696 3d878caa balrog
    .max_cpus = MAX_CPUS,
697 c0e564d5 bellard
};
698 f80f9ec9 Anthony Liguori
699 f80f9ec9 Anthony Liguori
static void prep_machine_init(void)
700 f80f9ec9 Anthony Liguori
{
701 f80f9ec9 Anthony Liguori
    qemu_register_machine(&prep_machine);
702 f80f9ec9 Anthony Liguori
}
703 f80f9ec9 Anthony Liguori
704 f80f9ec9 Anthony Liguori
machine_init(prep_machine_init);