root / exec-all.h @ 90cb786c
History | View | Annotate | Download (17.3 kB)
1 | d4e8164f | bellard | /*
|
---|---|---|---|
2 | d4e8164f | bellard | * internal execution defines for qemu
|
3 | 5fafdf24 | ths | *
|
4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | d4e8164f | bellard | *
|
6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
|
7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
|
9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | d4e8164f | bellard | *
|
11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
|
12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | d4e8164f | bellard | * Lesser General Public License for more details.
|
15 | d4e8164f | bellard | *
|
16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
|
18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | d4e8164f | bellard | */
|
20 | d4e8164f | bellard | |
21 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
|
22 | cb7cca1a | aurel32 | #define DEBUG_DISAS
|
23 | b346ff46 | bellard | |
24 | b346ff46 | bellard | /* is_jmp field values */
|
25 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
26 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
27 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
28 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
29 | b346ff46 | bellard | |
30 | b346ff46 | bellard | struct TranslationBlock;
|
31 | b346ff46 | bellard | |
32 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
|
33 | e83a8673 | edgar_igl | #define MAX_OP_PER_INSTR 64 |
34 | 0115be31 | pbrook | /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
|
35 | 0115be31 | pbrook | #define MAX_OPC_PARAM 10 |
36 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
37 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
|
38 | b346ff46 | bellard | |
39 | a208e54a | pbrook | /* Maximum size a TCG op can expand to. This is complicated because a
|
40 | a208e54a | pbrook | single op may require several host instructions and regirster reloads.
|
41 | a208e54a | pbrook | For now take a wild guess at 128 bytes, which should allow at least
|
42 | a208e54a | pbrook | a couple of fixup instructions per argument. */
|
43 | a208e54a | pbrook | #define TCG_MAX_OP_SIZE 128 |
44 | a208e54a | pbrook | |
45 | 0115be31 | pbrook | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
|
46 | b346ff46 | bellard | |
47 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
|
48 | c27004ec | bellard | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
|
49 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
|
50 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
|
51 | c3278b7b | bellard | extern target_ulong gen_opc_jump_pc[2]; |
52 | 30d6cb84 | bellard | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
|
53 | b346ff46 | bellard | |
54 | 9886cc16 | bellard | typedef void (GenOpFunc)(void); |
55 | 9886cc16 | bellard | typedef void (GenOpFunc1)(long); |
56 | 9886cc16 | bellard | typedef void (GenOpFunc2)(long, long); |
57 | 9886cc16 | bellard | typedef void (GenOpFunc3)(long, long, long); |
58 | 3b46e624 | ths | |
59 | b346ff46 | bellard | extern FILE *logfile;
|
60 | b346ff46 | bellard | extern int loglevel; |
61 | b346ff46 | bellard | |
62 | 4c3a88a2 | bellard | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
63 | 4c3a88a2 | bellard | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
64 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, struct TranslationBlock *tb, |
65 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc); |
66 | d2856f1a | aurel32 | |
67 | d07bde88 | blueswir1 | unsigned long code_gen_max_block_size(void); |
68 | 57fec1fe | bellard | void cpu_gen_init(void); |
69 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
70 | d07bde88 | blueswir1 | int *gen_code_size_ptr);
|
71 | 5fafdf24 | ths | int cpu_restore_state(struct TranslationBlock *tb, |
72 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
73 | 58fe2f10 | bellard | void *puc);
|
74 | 5fafdf24 | ths | int cpu_restore_state_copy(struct TranslationBlock *tb, |
75 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
76 | 58fe2f10 | bellard | void *puc);
|
77 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
78 | 6a00d601 | bellard | void cpu_exec_init(CPUState *env);
|
79 | 53a5960a | pbrook | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
80 | 00f82b8a | aurel32 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
|
81 | 2e12669a | bellard | int is_cpu_write_access);
|
82 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
|
83 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
|
84 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
85 | 5fafdf24 | ths | int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
|
86 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
|
87 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu); |
88 | 4d7a0880 | blueswir1 | static inline int tlb_set_page(CPUState *env1, target_ulong vaddr, |
89 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
|
90 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
91 | 84b7b8e7 | bellard | { |
92 | 84b7b8e7 | bellard | if (prot & PAGE_READ)
|
93 | 84b7b8e7 | bellard | prot |= PAGE_EXEC; |
94 | 4d7a0880 | blueswir1 | return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
|
95 | 84b7b8e7 | bellard | } |
96 | d4e8164f | bellard | |
97 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
98 | d4e8164f | bellard | |
99 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
100 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
101 | 4390df51 | bellard | |
102 | 26a5f13b | bellard | #define MIN_CODE_GEN_BUFFER_SIZE (1024 * 1024) |
103 | d4e8164f | bellard | |
104 | 4390df51 | bellard | /* estimated block size for TB allocation */
|
105 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
|
106 | 4390df51 | bellard | according to the host CPU */
|
107 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
|
108 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
109 | 4390df51 | bellard | #else
|
110 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
111 | 4390df51 | bellard | #endif
|
112 | 4390df51 | bellard | |
113 | 811d4cf4 | balrog | #if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
|
114 | 4390df51 | bellard | #define USE_DIRECT_JUMP
|
115 | 4390df51 | bellard | #endif
|
116 | 67b915a5 | bellard | #if defined(__i386__) && !defined(_WIN32)
|
117 | d4e8164f | bellard | #define USE_DIRECT_JUMP
|
118 | d4e8164f | bellard | #endif
|
119 | d4e8164f | bellard | |
120 | d4e8164f | bellard | typedef struct TranslationBlock { |
121 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
|
122 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
|
123 | c068688b | j_mayer | uint64_t flags; /* flags defining in which context the code was generated */
|
124 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
|
125 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
|
126 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
|
127 | bf088061 | bellard | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ |
128 | bf088061 | bellard | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ |
129 | 2e12669a | bellard | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
130 | 58fe2f10 | bellard | |
131 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
|
132 | 4390df51 | bellard | /* next matching tb for physical address. */
|
133 | 5fafdf24 | ths | struct TranslationBlock *phys_hash_next;
|
134 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
|
135 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
|
136 | 5fafdf24 | ths | struct TranslationBlock *page_next[2]; |
137 | 5fafdf24 | ths | target_ulong page_addr[2];
|
138 | 4390df51 | bellard | |
139 | d4e8164f | bellard | /* the following data are used to directly call another TB from
|
140 | d4e8164f | bellard | the code of this one. */
|
141 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
142 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
|
143 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
144 | d4e8164f | bellard | #else
|
145 | 57fec1fe | bellard | unsigned long tb_next[2]; /* address of jump generated code */ |
146 | d4e8164f | bellard | #endif
|
147 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
|
148 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
|
149 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
|
150 | d4e8164f | bellard | jmp_first */
|
151 | 5fafdf24 | ths | struct TranslationBlock *jmp_next[2]; |
152 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
|
153 | d4e8164f | bellard | } TranslationBlock; |
154 | d4e8164f | bellard | |
155 | b362e5e0 | pbrook | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
156 | b362e5e0 | pbrook | { |
157 | b362e5e0 | pbrook | target_ulong tmp; |
158 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
159 | b5e19d4c | edgar_igl | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
|
160 | b362e5e0 | pbrook | } |
161 | b362e5e0 | pbrook | |
162 | 8a40a180 | bellard | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
163 | d4e8164f | bellard | { |
164 | b362e5e0 | pbrook | target_ulong tmp; |
165 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
166 | b5e19d4c | edgar_igl | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
|
167 | b5e19d4c | edgar_igl | | (tmp & TB_JMP_ADDR_MASK)); |
168 | d4e8164f | bellard | } |
169 | d4e8164f | bellard | |
170 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
171 | 4390df51 | bellard | { |
172 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
173 | 4390df51 | bellard | } |
174 | 4390df51 | bellard | |
175 | c27004ec | bellard | TranslationBlock *tb_alloc(target_ulong pc); |
176 | 0124311e | bellard | void tb_flush(CPUState *env);
|
177 | 5fafdf24 | ths | void tb_link_phys(TranslationBlock *tb,
|
178 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
179 | d4e8164f | bellard | |
180 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
|
181 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
|
182 | 26a5f13b | bellard | extern int code_gen_max_blocks; |
183 | d4e8164f | bellard | |
184 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
|
185 | 4390df51 | bellard | |
186 | 4390df51 | bellard | #if defined(__powerpc__)
|
187 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
188 | d4e8164f | bellard | { |
189 | d4e8164f | bellard | uint32_t val, *ptr; |
190 | d4e8164f | bellard | |
191 | d4e8164f | bellard | /* patch the branch destination */
|
192 | 4cbb86e1 | bellard | ptr = (uint32_t *)jmp_addr; |
193 | d4e8164f | bellard | val = *ptr; |
194 | 4cbb86e1 | bellard | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
195 | d4e8164f | bellard | *ptr = val; |
196 | d4e8164f | bellard | /* flush icache */
|
197 | d4e8164f | bellard | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
198 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
199 | d4e8164f | bellard | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
200 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
201 | d4e8164f | bellard | asm volatile ("isync" : : : "memory"); |
202 | d4e8164f | bellard | } |
203 | 57fec1fe | bellard | #elif defined(__i386__) || defined(__x86_64__)
|
204 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
205 | 4390df51 | bellard | { |
206 | 4390df51 | bellard | /* patch the branch destination */
|
207 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
|
208 | 4390df51 | bellard | /* no need to flush icache explicitely */
|
209 | 4390df51 | bellard | } |
210 | 811d4cf4 | balrog | #elif defined(__arm__)
|
211 | 811d4cf4 | balrog | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
212 | 811d4cf4 | balrog | { |
213 | 811d4cf4 | balrog | register unsigned long _beg __asm ("a1"); |
214 | 811d4cf4 | balrog | register unsigned long _end __asm ("a2"); |
215 | 811d4cf4 | balrog | register unsigned long _flg __asm ("a3"); |
216 | 811d4cf4 | balrog | |
217 | 811d4cf4 | balrog | /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
|
218 | 811d4cf4 | balrog | *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff; |
219 | 811d4cf4 | balrog | |
220 | 811d4cf4 | balrog | /* flush icache */
|
221 | 811d4cf4 | balrog | _beg = jmp_addr; |
222 | 811d4cf4 | balrog | _end = jmp_addr + 4;
|
223 | 811d4cf4 | balrog | _flg = 0;
|
224 | 811d4cf4 | balrog | __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); |
225 | 811d4cf4 | balrog | } |
226 | 4390df51 | bellard | #endif
|
227 | d4e8164f | bellard | |
228 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
229 | 4cbb86e1 | bellard | int n, unsigned long addr) |
230 | 4cbb86e1 | bellard | { |
231 | 4cbb86e1 | bellard | unsigned long offset; |
232 | 4cbb86e1 | bellard | |
233 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
234 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
235 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
|
236 | 4cbb86e1 | bellard | if (offset != 0xffff) |
237 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
238 | 4cbb86e1 | bellard | } |
239 | 4cbb86e1 | bellard | |
240 | d4e8164f | bellard | #else
|
241 | d4e8164f | bellard | |
242 | d4e8164f | bellard | /* set the jump target */
|
243 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
244 | d4e8164f | bellard | int n, unsigned long addr) |
245 | d4e8164f | bellard | { |
246 | 95f7652d | bellard | tb->tb_next[n] = addr; |
247 | d4e8164f | bellard | } |
248 | d4e8164f | bellard | |
249 | d4e8164f | bellard | #endif
|
250 | d4e8164f | bellard | |
251 | 5fafdf24 | ths | static inline void tb_add_jump(TranslationBlock *tb, int n, |
252 | d4e8164f | bellard | TranslationBlock *tb_next) |
253 | d4e8164f | bellard | { |
254 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
|
255 | cf25629d | bellard | if (!tb->jmp_next[n]) {
|
256 | cf25629d | bellard | /* patch the native jump address */
|
257 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
258 | 3b46e624 | ths | |
259 | cf25629d | bellard | /* add in TB jmp circular list */
|
260 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
261 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
|
262 | cf25629d | bellard | } |
263 | d4e8164f | bellard | } |
264 | d4e8164f | bellard | |
265 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
266 | a513fe19 | bellard | |
267 | d4e8164f | bellard | #ifndef offsetof
|
268 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
269 | d4e8164f | bellard | #endif
|
270 | d4e8164f | bellard | |
271 | d549f7d9 | bellard | #if defined(_WIN32)
|
272 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
273 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".section .text\n" |
274 | d549f7d9 | bellard | #elif defined(__APPLE__)
|
275 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".data\n" |
276 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".text\n" |
277 | d549f7d9 | bellard | #else
|
278 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
279 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".previous\n" |
280 | d549f7d9 | bellard | #endif
|
281 | d549f7d9 | bellard | |
282 | 75913b72 | bellard | #define ASM_OP_LABEL_NAME(n, opname) \
|
283 | 75913b72 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) |
284 | 75913b72 | bellard | |
285 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
286 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
287 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
288 | 33417e70 | bellard | |
289 | 15a51156 | aurel32 | #if defined(__hppa__)
|
290 | 15a51156 | aurel32 | |
291 | 15a51156 | aurel32 | typedef int spinlock_t[4]; |
292 | 15a51156 | aurel32 | |
293 | 15a51156 | aurel32 | #define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 } |
294 | 15a51156 | aurel32 | |
295 | 15a51156 | aurel32 | static inline void resetlock (spinlock_t *p) |
296 | 15a51156 | aurel32 | { |
297 | 15a51156 | aurel32 | (*p)[0] = (*p)[1] = (*p)[2] = (*p)[3] = 1; |
298 | 15a51156 | aurel32 | } |
299 | 15a51156 | aurel32 | |
300 | 15a51156 | aurel32 | #else
|
301 | 15a51156 | aurel32 | |
302 | 15a51156 | aurel32 | typedef int spinlock_t; |
303 | 15a51156 | aurel32 | |
304 | 15a51156 | aurel32 | #define SPIN_LOCK_UNLOCKED 0 |
305 | 15a51156 | aurel32 | |
306 | 15a51156 | aurel32 | static inline void resetlock (spinlock_t *p) |
307 | 15a51156 | aurel32 | { |
308 | 15a51156 | aurel32 | *p = SPIN_LOCK_UNLOCKED; |
309 | 15a51156 | aurel32 | } |
310 | 15a51156 | aurel32 | |
311 | 15a51156 | aurel32 | #endif
|
312 | 15a51156 | aurel32 | |
313 | 204a1b8d | ths | #if defined(__powerpc__)
|
314 | d4e8164f | bellard | static inline int testandset (int *p) |
315 | d4e8164f | bellard | { |
316 | d4e8164f | bellard | int ret;
|
317 | d4e8164f | bellard | __asm__ __volatile__ ( |
318 | 02e1ec9b | bellard | "0: lwarx %0,0,%1\n"
|
319 | 02e1ec9b | bellard | " xor. %0,%3,%0\n"
|
320 | 02e1ec9b | bellard | " bne 1f\n"
|
321 | 02e1ec9b | bellard | " stwcx. %2,0,%1\n"
|
322 | 02e1ec9b | bellard | " bne- 0b\n"
|
323 | d4e8164f | bellard | "1: "
|
324 | d4e8164f | bellard | : "=&r" (ret)
|
325 | d4e8164f | bellard | : "r" (p), "r" (1), "r" (0) |
326 | d4e8164f | bellard | : "cr0", "memory"); |
327 | d4e8164f | bellard | return ret;
|
328 | d4e8164f | bellard | } |
329 | 204a1b8d | ths | #elif defined(__i386__)
|
330 | d4e8164f | bellard | static inline int testandset (int *p) |
331 | d4e8164f | bellard | { |
332 | 4955a2cd | bellard | long int readval = 0; |
333 | 3b46e624 | ths | |
334 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
|
335 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
336 | 4955a2cd | bellard | : "r" (1) |
337 | 4955a2cd | bellard | : "cc");
|
338 | 4955a2cd | bellard | return readval;
|
339 | d4e8164f | bellard | } |
340 | 204a1b8d | ths | #elif defined(__x86_64__)
|
341 | bc51c5c9 | bellard | static inline int testandset (int *p) |
342 | bc51c5c9 | bellard | { |
343 | 4955a2cd | bellard | long int readval = 0; |
344 | 3b46e624 | ths | |
345 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
|
346 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
347 | 4955a2cd | bellard | : "r" (1) |
348 | 4955a2cd | bellard | : "cc");
|
349 | 4955a2cd | bellard | return readval;
|
350 | bc51c5c9 | bellard | } |
351 | 204a1b8d | ths | #elif defined(__s390__)
|
352 | d4e8164f | bellard | static inline int testandset (int *p) |
353 | d4e8164f | bellard | { |
354 | d4e8164f | bellard | int ret;
|
355 | d4e8164f | bellard | |
356 | d4e8164f | bellard | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
|
357 | d4e8164f | bellard | " jl 0b"
|
358 | d4e8164f | bellard | : "=&d" (ret)
|
359 | 5fafdf24 | ths | : "r" (1), "a" (p), "0" (*p) |
360 | d4e8164f | bellard | : "cc", "memory" ); |
361 | d4e8164f | bellard | return ret;
|
362 | d4e8164f | bellard | } |
363 | 204a1b8d | ths | #elif defined(__alpha__)
|
364 | 2f87c607 | bellard | static inline int testandset (int *p) |
365 | d4e8164f | bellard | { |
366 | d4e8164f | bellard | int ret;
|
367 | d4e8164f | bellard | unsigned long one; |
368 | d4e8164f | bellard | |
369 | d4e8164f | bellard | __asm__ __volatile__ ("0: mov 1,%2\n"
|
370 | d4e8164f | bellard | " ldl_l %0,%1\n"
|
371 | d4e8164f | bellard | " stl_c %2,%1\n"
|
372 | d4e8164f | bellard | " beq %2,1f\n"
|
373 | d4e8164f | bellard | ".subsection 2\n"
|
374 | d4e8164f | bellard | "1: br 0b\n"
|
375 | d4e8164f | bellard | ".previous"
|
376 | d4e8164f | bellard | : "=r" (ret), "=m" (*p), "=r" (one) |
377 | d4e8164f | bellard | : "m" (*p));
|
378 | d4e8164f | bellard | return ret;
|
379 | d4e8164f | bellard | } |
380 | 204a1b8d | ths | #elif defined(__sparc__)
|
381 | d4e8164f | bellard | static inline int testandset (int *p) |
382 | d4e8164f | bellard | { |
383 | d4e8164f | bellard | int ret;
|
384 | d4e8164f | bellard | |
385 | d4e8164f | bellard | __asm__ __volatile__("ldstub [%1], %0"
|
386 | d4e8164f | bellard | : "=r" (ret)
|
387 | d4e8164f | bellard | : "r" (p)
|
388 | d4e8164f | bellard | : "memory");
|
389 | d4e8164f | bellard | |
390 | d4e8164f | bellard | return (ret ? 1 : 0); |
391 | d4e8164f | bellard | } |
392 | 204a1b8d | ths | #elif defined(__arm__)
|
393 | a95c6790 | bellard | static inline int testandset (int *spinlock) |
394 | a95c6790 | bellard | { |
395 | a95c6790 | bellard | register unsigned int ret; |
396 | a95c6790 | bellard | __asm__ __volatile__("swp %0, %1, [%2]"
|
397 | a95c6790 | bellard | : "=r"(ret)
|
398 | a95c6790 | bellard | : "0"(1), "r"(spinlock)); |
399 | 3b46e624 | ths | |
400 | a95c6790 | bellard | return ret;
|
401 | a95c6790 | bellard | } |
402 | 204a1b8d | ths | #elif defined(__mc68000)
|
403 | 38e584a0 | bellard | static inline int testandset (int *p) |
404 | 38e584a0 | bellard | { |
405 | 38e584a0 | bellard | char ret;
|
406 | 38e584a0 | bellard | __asm__ __volatile__("tas %1; sne %0"
|
407 | 38e584a0 | bellard | : "=r" (ret)
|
408 | 38e584a0 | bellard | : "m" (p)
|
409 | 38e584a0 | bellard | : "cc","memory"); |
410 | 4955a2cd | bellard | return ret;
|
411 | 38e584a0 | bellard | } |
412 | 15a51156 | aurel32 | #elif defined(__hppa__)
|
413 | 15a51156 | aurel32 | |
414 | 15a51156 | aurel32 | /* Because malloc only guarantees 8-byte alignment for malloc'd data,
|
415 | 15a51156 | aurel32 | and GCC only guarantees 8-byte alignment for stack locals, we can't
|
416 | 15a51156 | aurel32 | be assured of 16-byte alignment for atomic lock data even if we
|
417 | 15a51156 | aurel32 | specify "__attribute ((aligned(16)))" in the type declaration. So,
|
418 | 15a51156 | aurel32 | we use a struct containing an array of four ints for the atomic lock
|
419 | 15a51156 | aurel32 | type and dynamically select the 16-byte aligned int from the array
|
420 | 15a51156 | aurel32 | for the semaphore. */
|
421 | 15a51156 | aurel32 | #define __PA_LDCW_ALIGNMENT 16 |
422 | 15a51156 | aurel32 | static inline void *ldcw_align (void *p) { |
423 | 15a51156 | aurel32 | unsigned long a = (unsigned long)p; |
424 | 15a51156 | aurel32 | a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1); |
425 | 15a51156 | aurel32 | return (void *)a; |
426 | 15a51156 | aurel32 | } |
427 | 15a51156 | aurel32 | |
428 | 15a51156 | aurel32 | static inline int testandset (spinlock_t *p) |
429 | 15a51156 | aurel32 | { |
430 | 15a51156 | aurel32 | unsigned int ret; |
431 | 15a51156 | aurel32 | p = ldcw_align(p); |
432 | 15a51156 | aurel32 | __asm__ __volatile__("ldcw 0(%1),%0"
|
433 | 15a51156 | aurel32 | : "=r" (ret)
|
434 | 15a51156 | aurel32 | : "r" (p)
|
435 | 15a51156 | aurel32 | : "memory" );
|
436 | 15a51156 | aurel32 | return !ret;
|
437 | 15a51156 | aurel32 | } |
438 | 15a51156 | aurel32 | |
439 | 204a1b8d | ths | #elif defined(__ia64)
|
440 | 38e584a0 | bellard | |
441 | b8076a74 | bellard | #include <ia64intrin.h> |
442 | b8076a74 | bellard | |
443 | b8076a74 | bellard | static inline int testandset (int *p) |
444 | b8076a74 | bellard | { |
445 | b8076a74 | bellard | return __sync_lock_test_and_set (p, 1); |
446 | b8076a74 | bellard | } |
447 | 204a1b8d | ths | #elif defined(__mips__)
|
448 | c4b89d18 | ths | static inline int testandset (int *p) |
449 | c4b89d18 | ths | { |
450 | c4b89d18 | ths | int ret;
|
451 | c4b89d18 | ths | |
452 | c4b89d18 | ths | __asm__ __volatile__ ( |
453 | c4b89d18 | ths | " .set push \n"
|
454 | c4b89d18 | ths | " .set noat \n"
|
455 | c4b89d18 | ths | " .set mips2 \n"
|
456 | c4b89d18 | ths | "1: li $1, 1 \n"
|
457 | c4b89d18 | ths | " ll %0, %1 \n"
|
458 | c4b89d18 | ths | " sc $1, %1 \n"
|
459 | 976a0d0d | ths | " beqz $1, 1b \n"
|
460 | c4b89d18 | ths | " .set pop "
|
461 | c4b89d18 | ths | : "=r" (ret), "+R" (*p) |
462 | c4b89d18 | ths | : |
463 | c4b89d18 | ths | : "memory");
|
464 | c4b89d18 | ths | |
465 | c4b89d18 | ths | return ret;
|
466 | c4b89d18 | ths | } |
467 | 204a1b8d | ths | #else
|
468 | 204a1b8d | ths | #error unimplemented CPU support
|
469 | c4b89d18 | ths | #endif
|
470 | c4b89d18 | ths | |
471 | aebcb60e | bellard | #if defined(CONFIG_USER_ONLY)
|
472 | d4e8164f | bellard | static inline void spin_lock(spinlock_t *lock) |
473 | d4e8164f | bellard | { |
474 | d4e8164f | bellard | while (testandset(lock));
|
475 | d4e8164f | bellard | } |
476 | d4e8164f | bellard | |
477 | d4e8164f | bellard | static inline void spin_unlock(spinlock_t *lock) |
478 | d4e8164f | bellard | { |
479 | 15a51156 | aurel32 | resetlock(lock); |
480 | d4e8164f | bellard | } |
481 | d4e8164f | bellard | |
482 | d4e8164f | bellard | static inline int spin_trylock(spinlock_t *lock) |
483 | d4e8164f | bellard | { |
484 | d4e8164f | bellard | return !testandset(lock);
|
485 | d4e8164f | bellard | } |
486 | 3c1cf9fa | bellard | #else
|
487 | 3c1cf9fa | bellard | static inline void spin_lock(spinlock_t *lock) |
488 | 3c1cf9fa | bellard | { |
489 | 3c1cf9fa | bellard | } |
490 | 3c1cf9fa | bellard | |
491 | 3c1cf9fa | bellard | static inline void spin_unlock(spinlock_t *lock) |
492 | 3c1cf9fa | bellard | { |
493 | 3c1cf9fa | bellard | } |
494 | 3c1cf9fa | bellard | |
495 | 3c1cf9fa | bellard | static inline int spin_trylock(spinlock_t *lock) |
496 | 3c1cf9fa | bellard | { |
497 | 3c1cf9fa | bellard | return 1; |
498 | 3c1cf9fa | bellard | } |
499 | 3c1cf9fa | bellard | #endif
|
500 | d4e8164f | bellard | |
501 | d4e8164f | bellard | extern spinlock_t tb_lock;
|
502 | d4e8164f | bellard | |
503 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
504 | 6e59c1db | bellard | |
505 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
|
506 | 6e59c1db | bellard | |
507 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
508 | 6e59c1db | bellard | void *retaddr);
|
509 | 6e59c1db | bellard | |
510 | 6ebbf390 | j_mayer | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
511 | 6e59c1db | bellard | #define MEMSUFFIX _code
|
512 | 6e59c1db | bellard | #define env cpu_single_env
|
513 | 6e59c1db | bellard | |
514 | 6e59c1db | bellard | #define DATA_SIZE 1 |
515 | 6e59c1db | bellard | #include "softmmu_header.h" |
516 | 6e59c1db | bellard | |
517 | 6e59c1db | bellard | #define DATA_SIZE 2 |
518 | 6e59c1db | bellard | #include "softmmu_header.h" |
519 | 6e59c1db | bellard | |
520 | 6e59c1db | bellard | #define DATA_SIZE 4 |
521 | 6e59c1db | bellard | #include "softmmu_header.h" |
522 | 6e59c1db | bellard | |
523 | c27004ec | bellard | #define DATA_SIZE 8 |
524 | c27004ec | bellard | #include "softmmu_header.h" |
525 | c27004ec | bellard | |
526 | 6e59c1db | bellard | #undef ACCESS_TYPE
|
527 | 6e59c1db | bellard | #undef MEMSUFFIX
|
528 | 6e59c1db | bellard | #undef env
|
529 | 6e59c1db | bellard | |
530 | 6e59c1db | bellard | #endif
|
531 | 4390df51 | bellard | |
532 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
|
533 | 4d7a0880 | blueswir1 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
534 | 4390df51 | bellard | { |
535 | 4390df51 | bellard | return addr;
|
536 | 4390df51 | bellard | } |
537 | 4390df51 | bellard | #else
|
538 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
|
539 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
|
540 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
|
541 | 4d7a0880 | blueswir1 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
542 | 4390df51 | bellard | { |
543 | 4d7a0880 | blueswir1 | int mmu_idx, page_index, pd;
|
544 | 4390df51 | bellard | |
545 | 4d7a0880 | blueswir1 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
546 | 4d7a0880 | blueswir1 | mmu_idx = cpu_mmu_index(env1); |
547 | 4d7a0880 | blueswir1 | if (__builtin_expect(env1->tlb_table[mmu_idx][page_index].addr_code !=
|
548 | 4390df51 | bellard | (addr & TARGET_PAGE_MASK), 0)) {
|
549 | c27004ec | bellard | ldub_code(addr); |
550 | c27004ec | bellard | } |
551 | 4d7a0880 | blueswir1 | pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; |
552 | 2a4188a3 | bellard | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
|
553 | 647de6ca | ths | #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
|
554 | 6c36d3fa | blueswir1 | do_unassigned_access(addr, 0, 1, 0); |
555 | 6c36d3fa | blueswir1 | #else
|
556 | 4d7a0880 | blueswir1 | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
557 | 6c36d3fa | blueswir1 | #endif
|
558 | 4390df51 | bellard | } |
559 | 4d7a0880 | blueswir1 | return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base; |
560 | 4390df51 | bellard | } |
561 | 4390df51 | bellard | #endif
|
562 | 9df217a3 | bellard | |
563 | 9df217a3 | bellard | #ifdef USE_KQEMU
|
564 | f32fc648 | bellard | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
565 | f32fc648 | bellard | |
566 | 9df217a3 | bellard | int kqemu_init(CPUState *env);
|
567 | 9df217a3 | bellard | int kqemu_cpu_exec(CPUState *env);
|
568 | 9df217a3 | bellard | void kqemu_flush_page(CPUState *env, target_ulong addr);
|
569 | 9df217a3 | bellard | void kqemu_flush(CPUState *env, int global); |
570 | 4b7df22f | bellard | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
|
571 | f32fc648 | bellard | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
|
572 | a332e112 | bellard | void kqemu_cpu_interrupt(CPUState *env);
|
573 | f32fc648 | bellard | void kqemu_record_dump(void); |
574 | 9df217a3 | bellard | |
575 | 9df217a3 | bellard | static inline int kqemu_is_ok(CPUState *env) |
576 | 9df217a3 | bellard | { |
577 | 9df217a3 | bellard | return(env->kqemu_enabled &&
|
578 | 5fafdf24 | ths | (env->cr[0] & CR0_PE_MASK) &&
|
579 | f32fc648 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
580 | 9df217a3 | bellard | (env->eflags & IF_MASK) && |
581 | f32fc648 | bellard | !(env->eflags & VM_MASK) && |
582 | 5fafdf24 | ths | (env->kqemu_enabled == 2 ||
|
583 | f32fc648 | bellard | ((env->hflags & HF_CPL_MASK) == 3 &&
|
584 | f32fc648 | bellard | (env->eflags & IOPL_MASK) != IOPL_MASK))); |
585 | 9df217a3 | bellard | } |
586 | 9df217a3 | bellard | |
587 | 9df217a3 | bellard | #endif |