tcg/ppc64: Fix zero extension code generation bug for ppc64 host
The ppc64 code generation backend uses an rldicr (Rotate Left DoubleImmediate and Clear Right) instruction to implement zero extension ofa 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64). However...
tcg/ppc64: fix 16/32 mixup
Signed-off-by: malc <av1474@comtv.ru>
tcg/ppc64: implement not_i32/64 and ext32u_i64
tcg: Always define all of the TCGOpcode enum members.
By always defining these symbols, we can eliminate a lot of ifdefs.
To allow this to be checked reliably, the semantics of theTCG_TARGET_HAS_* macros must be changed from def/undef to true/false.This allows even more ifdefs to be removed, converting them into...
TCG/PPC: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCG temps.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: malc <av1474@comtv.ru>
tcg/ppc64: Remove tcg_out_addi
The only user (within tcg.c) was removed
Delegate setup of TCG temporaries to targets
Delegate TCG temp_buf setup to targets, so that they can use a stackframe later instead.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
cpu-exec.c: avoid AREG0 use
Make functions take a parameter for CPUState instead of relyingon global env. Pass CPUState pointer to TCG prologue, which movesit to AREG0.
Thanks to Peter Maydell and Laurent Desnogues for the ARM prologuechange.
Revert the hacks to avoid AREG0 use on Sparc hosts....
TCG: Revert ppc64 tcg_out_movi32 change
3b6dac34161bc0a342336072643c2f6d17e0ec45 apparently broke the ppc64 TCG targetcompilation in the code path without guest base.
Reverting this line fixes the build.
Signed-off-by: Andreas F?rber <andreas.faerber@web.de>...
tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.
We need not reserve the register unless we're going to use it.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: malc <av1474@comtv.ru>
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