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Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
target-ppc: log instructions start in TCG code
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
static and inline should came before the type of the functions
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-ppc: optimize slw/srw/sld/srd
Remove a temp local variable and a jump by computing a mask with shifts.
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
Replace REGX with PRIx64
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Replace always_inline with inline
We define inline as always_inline.
target-ppc: retain l{w,d}arx loaded value
We do this so we can check on the corresponding stc{w,d}x. whether thevalue has changed. It's a poor man's form of implementing atomicoperations and is valid only for NPTL usermode Linux emulation.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
target-ppc: add exceptions for conditional stores
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: malc <av1474@comtv.ru>
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Update to a hopefully more future proof FSF address
ppc tcg: fix wrong bit/mask of wrteei
Signed-off-by: Baojun Wang <wangbj@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: fix evmergelo and evmergelohi
For 32-bit PPC targets, we translated:
evmergelo rX, rX, rY
as:
rX-lo = rY-lorX-hi = rX-lo
which is wrong, because we should be transferring rX-lo first. Thisproblem is fixed by swapping the order in which we write the parts of...
Apply TCGV_UNUSED on variables that GCC mistakenly thinks can be useduninitialized
Replace ELF section hack with normal table
Concentrate rest of table entries to top
Concentrate most table entries to top
Clean up GEN_HANDLER2
Clean up GEN_HANDLER
target-ppc: expose cpu capability flags
Do this so other pieces of code can make decisions based on thecapabilities of the CPU we're emulating.
Fix ppc-softmmu warnings on OpenBSD host
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7099 c046a42c-6fe2-441c-8c8c-71466251a162
Add new command line option -singlestep for tcg single stepping.
This replaces a compile time option for some targets and addsthis feature to targets which did not have a compile time option.
Add monitor command to enable or disable single step mode.
Modify monitor command "info status" to display single step mode....
target-ppc: avoid nop to override next instruction
While searching PC, always store the pc of a new instruction.Instructions that didn't generate tcg code (such as nop) prevented thenext one to be referenced.
Based on patch for target-alpha, r6930.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-ppc: use the new bswap* TCG ops
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6835 c046a42c-6fe2-441c-8c8c-71466251a162
tcg: rename bswap_i32/i64 functions
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
targe-ppc: optimize mfcr and mtcrf
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162
Fix mfcr on ppc64-softmmu
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6758 c046a42c-6fe2-441c-8c8c-71466251a162
Implement mtfsf.L encoding
Mtfsf can have the L bit set, so all the register contents get storedin FPSCR. Linux uses it, so let's implement it.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6753 c046a42c-6fe2-441c-8c8c-71466251a162
Implment tlbiel
Linux uses tlbiel to flush TLB entries in PPC64 mode. This special TLBflush opcode only flushes an entry for the CPU it runs on, not acrossall CPUs in the system.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6749 c046a42c-6fe2-441c-8c8c-71466251a162
Implement slbmte
In order to modify SLB entries on recent PPC64 machines, the slbmteinstruction is used.
This patch implements the slbmte instruction and makes the "bridge" mode code use the slb set functions, so we can move the SLB intothe CPU struct later....
Sparse fixes: add extern to ELF opcode tables to avoid warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6740 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: improve mfcr/mtcrf
- use ctz32 instead of ffs - 1- small optimisation of mtcrf- add the name of both opcodes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6669 c046a42c-6fe2-441c-8c8c-71466251a162
Fix mtcrf/mfcr
Noticed by Alexander Graf
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6667 c046a42c-6fe2-441c-8c8c-71466251a162
Fix typo in gen_qemu_ld32s
When the CPU is in little endian mode, it should load values from RAMin byte swapped manner. This check is in all the ld and st functions,but misspelled in gen_qemu_ld32s.
This patch fixes the misspelling and makes ppc64 Linux happier....
Fix branch debugging
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6629 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Model SPE floating-point instructions more accurately
Single-precision and double-precision floating-point instructions shouldbe separated into their own categories, since some chips only supportsingle-precision instructions.
target-ppc: Add vrsqrtefp instruction
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6574 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add vrefp instruction
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6573 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add vct{u,s}xs instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6572 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add vcmp{eq, ge, gt, b}fp{, .} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6571 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add vmaddfp and vnmsubfp instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6570 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add v{add,sub}fp instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6569 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add v{max,min}fp instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6568 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: change instruction name vrlogefp into vlogefp
Thanks to Nathan Froyd for noticing that.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6532 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: add vrlogefp instruction
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6519 c046a42c-6fe2-441c-8c8c-71466251a162
Add vcf{u,s}x instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6513 c046a42c-6fe2-441c-8c8c-71466251a162
Add vrfi{m,n,p,z} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6512 c046a42c-6fe2-441c-8c8c-71466251a162
Make mtvscr use a helper
Do this so we can set float statuses once per mtvscr, rather than onceper Altivec instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6508 c046a42c-6fe2-441c-8c8c-71466251a162
Fix compilation of PPC64 targets with DEBUG_TCGV enabled
The attached patch fixes compilation of PPC64 targets with DEBUG_TCGVenabled.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6502 c046a42c-6fe2-441c-8c8c-71466251a162
global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &X) qemu_log()' statement.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
Clean up debugging code #ifdefs (Eduardo Habkost)
Use macros to avoid #ifdefs on debugging code.
This patch doesn't try to merge logging macros from different files,but just unify the debugging code #ifdefs onto a macro on each file. Afurther cleanup can unify the debugging macros on a common header, later...
target-ppc: fix wrteei instruction
Patch by Andrew May
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6308 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: add altivec cache instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6275 c046a42c-6fe2-441c-8c8c-71466251a162
Add v{add, sub}{s, u}{b, h, w}s instructions
Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6254 c046a42c-6fe2-441c-8c8c-71466251a162
Add vspltis{b,h,w} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6238 c046a42c-6fe2-441c-8c8c-71466251a162
Add vs{l,r} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6237 c046a42c-6fe2-441c-8c8c-71466251a162
Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6236 c046a42c-6fe2-441c-8c8c-71466251a162
Add GEN_VXRFORM{,1} macros for subsequent instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6235 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add m{f,t}vscr instructions.
Based on a patch by Nathan Froyd <froydnj@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6190 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsumsws, vsum2sws, and vsum4{sbs, shs,ubs} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6189 c046a42c-6fe2-441c-8c8c-71466251a162
Add {l,st}ve{b,h,w}x instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6188 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmladduhm instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6187 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmsumsh{m,s} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6186 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmsumuh{m,s} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6185 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmh{,r}addshs instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6184 c046a42c-6fe2-441c-8c8c-71466251a162
Add vpkpx instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6183 c046a42c-6fe2-441c-8c8c-71466251a162
Add vpks{h, w}{s, u}s, vpku{h, w}us, and vpku{h, w}um instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6182 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsel and vperm instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6180 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmsum{u,m}bm instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6179 c046a42c-6fe2-441c-8c8c-71466251a162
Add GEN_VAFORM_PAIRED macro for subsequent instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6178 c046a42c-6fe2-441c-8c8c-71466251a162
Add vupk{h,l}s{b,h} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6177 c046a42c-6fe2-441c-8c8c-71466251a162
Add vupk{h,l}px instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6176 c046a42c-6fe2-441c-8c8c-71466251a162
Add GEN_VXFORM_NOA macro for subsequent instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6175 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsplt{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6174 c046a42c-6fe2-441c-8c8c-71466251a162
Add GEN_VXFORM_UIMM macro for subsequent instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6173 c046a42c-6fe2-441c-8c8c-71466251a162
Add GEN_VXFORM_SIMM macro for subsequent instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6172 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsldoi instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6171 c046a42c-6fe2-441c-8c8c-71466251a162
Add vrl{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6170 c046a42c-6fe2-441c-8c8c-71466251a162
Add lvs{l,r} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6169 c046a42c-6fe2-441c-8c8c-71466251a162
Add v{add,sub}cuw instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6168 c046a42c-6fe2-441c-8c8c-71466251a162
Add vs{l,r}o instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6167 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsl{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6166 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsr{,a}{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6165 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmul{e,o}{s,u}{b,h} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6164 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmrg{l,h}{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6163 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Add v{min, max}{s, u}{b, h, w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6157 c046a42c-6fe2-441c-8c8c-71466251a162
Add vavg{s,u}{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6156 c046a42c-6fe2-441c-8c8c-71466251a162
Add v{add,sub}u{b,h,w}m instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6155 c046a42c-6fe2-441c-8c8c-71466251a162
Add GEN_VXFORM macro for subsequent instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6154 c046a42c-6fe2-441c-8c8c-71466251a162
Fix TCG error in gen_avr_ptr.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6152 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix TGC type mismatch introduced by r6146
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6147 c046a42c-6fe2-441c-8c8c-71466251a162
tcg_temp_local_new should take no parameter
This patch removes useless type information in some calls totcg_temp_local_new. It also removes the parameter from themacro declaration; if a target has to use a specific non-defaultsize then it should use tcg_temp_local_new_{i32,i64}....
target-ppc: add gen_avr_ptr function.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6098 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: add Altivec logical operations
Use opc2/opc3 instead of one big xo field. Do this consistency with therest of translate.c
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6087 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: update nip before calling an helper in FP instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6045 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix TCGv type in fcmpu/fcmpo
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6044 c046a42c-6fe2-441c-8c8c-71466251a162