root / target-sh4 / helper.c @ 94909d9f
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1 | fdf9b3e8 | bellard | /*
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2 | fdf9b3e8 | bellard | * SH4 emulation
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3 | 5fafdf24 | ths | *
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4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
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5 | fdf9b3e8 | bellard | *
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6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
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7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
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9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | fdf9b3e8 | bellard | *
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11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
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12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
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15 | fdf9b3e8 | bellard | *
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16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | fdf9b3e8 | bellard | * License along with this library; if not, write to the Free Software
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18 | fad6cb1a | aurel32 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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19 | fdf9b3e8 | bellard | */
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20 | fdf9b3e8 | bellard | #include <stdarg.h> |
21 | fdf9b3e8 | bellard | #include <stdlib.h> |
22 | fdf9b3e8 | bellard | #include <stdio.h> |
23 | fdf9b3e8 | bellard | #include <string.h> |
24 | fdf9b3e8 | bellard | #include <inttypes.h> |
25 | fdf9b3e8 | bellard | #include <signal.h> |
26 | fdf9b3e8 | bellard | #include <assert.h> |
27 | fdf9b3e8 | bellard | |
28 | fdf9b3e8 | bellard | #include "cpu.h" |
29 | fdf9b3e8 | bellard | #include "exec-all.h" |
30 | e96e2044 | ths | #include "hw/sh_intc.h" |
31 | fdf9b3e8 | bellard | |
32 | 355fb23d | pbrook | #if defined(CONFIG_USER_ONLY)
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33 | 355fb23d | pbrook | |
34 | 355fb23d | pbrook | void do_interrupt (CPUState *env)
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35 | 355fb23d | pbrook | { |
36 | 355fb23d | pbrook | env->exception_index = -1;
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37 | 355fb23d | pbrook | } |
38 | 355fb23d | pbrook | |
39 | 355fb23d | pbrook | int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
40 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
41 | 355fb23d | pbrook | { |
42 | 355fb23d | pbrook | env->tea = address; |
43 | c3b5bc8a | ths | env->exception_index = 0;
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44 | 355fb23d | pbrook | switch (rw) {
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45 | 355fb23d | pbrook | case 0: |
46 | 355fb23d | pbrook | env->exception_index = 0x0a0;
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47 | 355fb23d | pbrook | break;
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48 | 355fb23d | pbrook | case 1: |
49 | 355fb23d | pbrook | env->exception_index = 0x0c0;
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50 | 355fb23d | pbrook | break;
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51 | cf7055bd | aurel32 | case 2: |
52 | cf7055bd | aurel32 | env->exception_index = 0x0a0;
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53 | cf7055bd | aurel32 | break;
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54 | 355fb23d | pbrook | } |
55 | 355fb23d | pbrook | return 1; |
56 | 355fb23d | pbrook | } |
57 | 355fb23d | pbrook | |
58 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
59 | 355fb23d | pbrook | { |
60 | 355fb23d | pbrook | return addr;
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61 | 355fb23d | pbrook | } |
62 | 355fb23d | pbrook | |
63 | 3c1adf12 | edgar_igl | int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
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64 | 3c1adf12 | edgar_igl | { |
65 | 3c1adf12 | edgar_igl | /* For user mode, only U0 area is cachable. */
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66 | 679dee3c | edgar_igl | return !(addr & 0x80000000); |
67 | 3c1adf12 | edgar_igl | } |
68 | 3c1adf12 | edgar_igl | |
69 | 355fb23d | pbrook | #else /* !CONFIG_USER_ONLY */ |
70 | 355fb23d | pbrook | |
71 | fdf9b3e8 | bellard | #define MMU_OK 0 |
72 | fdf9b3e8 | bellard | #define MMU_ITLB_MISS (-1) |
73 | fdf9b3e8 | bellard | #define MMU_ITLB_MULTIPLE (-2) |
74 | fdf9b3e8 | bellard | #define MMU_ITLB_VIOLATION (-3) |
75 | fdf9b3e8 | bellard | #define MMU_DTLB_MISS_READ (-4) |
76 | fdf9b3e8 | bellard | #define MMU_DTLB_MISS_WRITE (-5) |
77 | fdf9b3e8 | bellard | #define MMU_DTLB_INITIAL_WRITE (-6) |
78 | fdf9b3e8 | bellard | #define MMU_DTLB_VIOLATION_READ (-7) |
79 | fdf9b3e8 | bellard | #define MMU_DTLB_VIOLATION_WRITE (-8) |
80 | fdf9b3e8 | bellard | #define MMU_DTLB_MULTIPLE (-9) |
81 | fdf9b3e8 | bellard | #define MMU_DTLB_MISS (-10) |
82 | cf7055bd | aurel32 | #define MMU_IADDR_ERROR (-11) |
83 | cf7055bd | aurel32 | #define MMU_DADDR_ERROR_READ (-12) |
84 | cf7055bd | aurel32 | #define MMU_DADDR_ERROR_WRITE (-13) |
85 | fdf9b3e8 | bellard | |
86 | fdf9b3e8 | bellard | void do_interrupt(CPUState * env)
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87 | fdf9b3e8 | bellard | { |
88 | e96e2044 | ths | int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
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89 | e96e2044 | ths | int do_exp, irq_vector = env->exception_index;
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90 | e96e2044 | ths | |
91 | e96e2044 | ths | /* prioritize exceptions over interrupts */
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92 | e96e2044 | ths | |
93 | e96e2044 | ths | do_exp = env->exception_index != -1;
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94 | e96e2044 | ths | do_irq = do_irq && (env->exception_index == -1);
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95 | e96e2044 | ths | |
96 | e96e2044 | ths | if (env->sr & SR_BL) {
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97 | e96e2044 | ths | if (do_exp && env->exception_index != 0x1e0) { |
98 | e96e2044 | ths | env->exception_index = 0x000; /* masked exception -> reset */ |
99 | e96e2044 | ths | } |
100 | 833ed386 | aurel32 | if (do_irq && !env->intr_at_halt) {
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101 | e96e2044 | ths | return; /* masked */ |
102 | e96e2044 | ths | } |
103 | 833ed386 | aurel32 | env->intr_at_halt = 0;
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104 | e96e2044 | ths | } |
105 | e96e2044 | ths | |
106 | e96e2044 | ths | if (do_irq) {
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107 | e96e2044 | ths | irq_vector = sh_intc_get_pending_vector(env->intc_handle, |
108 | e96e2044 | ths | (env->sr >> 4) & 0xf); |
109 | e96e2044 | ths | if (irq_vector == -1) { |
110 | e96e2044 | ths | return; /* masked */ |
111 | e96e2044 | ths | } |
112 | e96e2044 | ths | } |
113 | e96e2044 | ths | |
114 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_INT)) {
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115 | fdf9b3e8 | bellard | const char *expname; |
116 | fdf9b3e8 | bellard | switch (env->exception_index) {
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117 | fdf9b3e8 | bellard | case 0x0e0: |
118 | fdf9b3e8 | bellard | expname = "addr_error";
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119 | fdf9b3e8 | bellard | break;
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120 | fdf9b3e8 | bellard | case 0x040: |
121 | fdf9b3e8 | bellard | expname = "tlb_miss";
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122 | fdf9b3e8 | bellard | break;
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123 | fdf9b3e8 | bellard | case 0x0a0: |
124 | fdf9b3e8 | bellard | expname = "tlb_violation";
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125 | fdf9b3e8 | bellard | break;
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126 | fdf9b3e8 | bellard | case 0x180: |
127 | fdf9b3e8 | bellard | expname = "illegal_instruction";
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128 | fdf9b3e8 | bellard | break;
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129 | fdf9b3e8 | bellard | case 0x1a0: |
130 | fdf9b3e8 | bellard | expname = "slot_illegal_instruction";
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131 | fdf9b3e8 | bellard | break;
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132 | fdf9b3e8 | bellard | case 0x800: |
133 | fdf9b3e8 | bellard | expname = "fpu_disable";
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134 | fdf9b3e8 | bellard | break;
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135 | fdf9b3e8 | bellard | case 0x820: |
136 | fdf9b3e8 | bellard | expname = "slot_fpu";
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137 | fdf9b3e8 | bellard | break;
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138 | fdf9b3e8 | bellard | case 0x100: |
139 | fdf9b3e8 | bellard | expname = "data_write";
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140 | fdf9b3e8 | bellard | break;
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141 | fdf9b3e8 | bellard | case 0x060: |
142 | fdf9b3e8 | bellard | expname = "dtlb_miss_write";
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143 | fdf9b3e8 | bellard | break;
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144 | fdf9b3e8 | bellard | case 0x0c0: |
145 | fdf9b3e8 | bellard | expname = "dtlb_violation_write";
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146 | fdf9b3e8 | bellard | break;
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147 | fdf9b3e8 | bellard | case 0x120: |
148 | fdf9b3e8 | bellard | expname = "fpu_exception";
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149 | fdf9b3e8 | bellard | break;
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150 | fdf9b3e8 | bellard | case 0x080: |
151 | fdf9b3e8 | bellard | expname = "initial_page_write";
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152 | fdf9b3e8 | bellard | break;
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153 | fdf9b3e8 | bellard | case 0x160: |
154 | fdf9b3e8 | bellard | expname = "trapa";
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155 | fdf9b3e8 | bellard | break;
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156 | fdf9b3e8 | bellard | default:
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157 | e96e2044 | ths | expname = do_irq ? "interrupt" : "???"; |
158 | e96e2044 | ths | break;
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159 | fdf9b3e8 | bellard | } |
160 | 93fcfe39 | aliguori | qemu_log("exception 0x%03x [%s] raised\n",
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161 | 93fcfe39 | aliguori | irq_vector, expname); |
162 | 93fcfe39 | aliguori | log_cpu_state(env, 0);
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163 | fdf9b3e8 | bellard | } |
164 | fdf9b3e8 | bellard | |
165 | fdf9b3e8 | bellard | env->ssr = env->sr; |
166 | e96e2044 | ths | env->spc = env->pc; |
167 | fdf9b3e8 | bellard | env->sgr = env->gregs[15];
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168 | fdf9b3e8 | bellard | env->sr |= SR_BL | SR_MD | SR_RB; |
169 | fdf9b3e8 | bellard | |
170 | 274a9e70 | aurel32 | if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
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171 | 274a9e70 | aurel32 | /* Branch instruction should be executed again before delay slot. */
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172 | 274a9e70 | aurel32 | env->spc -= 2;
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173 | 274a9e70 | aurel32 | /* Clear flags for exception/interrupt routine. */
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174 | 274a9e70 | aurel32 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE); |
175 | 274a9e70 | aurel32 | } |
176 | 274a9e70 | aurel32 | if (env->flags & DELAY_SLOT_CLEARME)
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177 | 274a9e70 | aurel32 | env->flags = 0;
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178 | 274a9e70 | aurel32 | |
179 | e96e2044 | ths | if (do_exp) {
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180 | e96e2044 | ths | env->expevt = env->exception_index; |
181 | e96e2044 | ths | switch (env->exception_index) {
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182 | e96e2044 | ths | case 0x000: |
183 | e96e2044 | ths | case 0x020: |
184 | e96e2044 | ths | case 0x140: |
185 | e96e2044 | ths | env->sr &= ~SR_FD; |
186 | e96e2044 | ths | env->sr |= 0xf << 4; /* IMASK */ |
187 | e96e2044 | ths | env->pc = 0xa0000000;
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188 | e96e2044 | ths | break;
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189 | e96e2044 | ths | case 0x040: |
190 | e96e2044 | ths | case 0x060: |
191 | e96e2044 | ths | env->pc = env->vbr + 0x400;
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192 | e96e2044 | ths | break;
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193 | e96e2044 | ths | case 0x160: |
194 | e96e2044 | ths | env->spc += 2; /* special case for TRAPA */ |
195 | e96e2044 | ths | /* fall through */
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196 | e96e2044 | ths | default:
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197 | e96e2044 | ths | env->pc = env->vbr + 0x100;
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198 | e96e2044 | ths | break;
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199 | e96e2044 | ths | } |
200 | e96e2044 | ths | return;
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201 | e96e2044 | ths | } |
202 | e96e2044 | ths | |
203 | e96e2044 | ths | if (do_irq) {
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204 | e96e2044 | ths | env->intevt = irq_vector; |
205 | e96e2044 | ths | env->pc = env->vbr + 0x600;
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206 | e96e2044 | ths | return;
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207 | fdf9b3e8 | bellard | } |
208 | fdf9b3e8 | bellard | } |
209 | fdf9b3e8 | bellard | |
210 | fdf9b3e8 | bellard | static void update_itlb_use(CPUState * env, int itlbnb) |
211 | fdf9b3e8 | bellard | { |
212 | fdf9b3e8 | bellard | uint8_t or_mask = 0, and_mask = (uint8_t) - 1; |
213 | fdf9b3e8 | bellard | |
214 | fdf9b3e8 | bellard | switch (itlbnb) {
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215 | fdf9b3e8 | bellard | case 0: |
216 | ea2b542a | aurel32 | and_mask = 0x1f;
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217 | fdf9b3e8 | bellard | break;
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218 | fdf9b3e8 | bellard | case 1: |
219 | fdf9b3e8 | bellard | and_mask = 0xe7;
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220 | fdf9b3e8 | bellard | or_mask = 0x80;
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221 | fdf9b3e8 | bellard | break;
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222 | fdf9b3e8 | bellard | case 2: |
223 | fdf9b3e8 | bellard | and_mask = 0xfb;
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224 | fdf9b3e8 | bellard | or_mask = 0x50;
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225 | fdf9b3e8 | bellard | break;
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226 | fdf9b3e8 | bellard | case 3: |
227 | fdf9b3e8 | bellard | or_mask = 0x2c;
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228 | fdf9b3e8 | bellard | break;
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229 | fdf9b3e8 | bellard | } |
230 | fdf9b3e8 | bellard | |
231 | ea2b542a | aurel32 | env->mmucr &= (and_mask << 24) | 0x00ffffff; |
232 | fdf9b3e8 | bellard | env->mmucr |= (or_mask << 24);
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233 | fdf9b3e8 | bellard | } |
234 | fdf9b3e8 | bellard | |
235 | fdf9b3e8 | bellard | static int itlb_replacement(CPUState * env) |
236 | fdf9b3e8 | bellard | { |
237 | fdf9b3e8 | bellard | if ((env->mmucr & 0xe0000000) == 0xe0000000) |
238 | fdf9b3e8 | bellard | return 0; |
239 | ea2b542a | aurel32 | if ((env->mmucr & 0x98000000) == 0x18000000) |
240 | fdf9b3e8 | bellard | return 1; |
241 | fdf9b3e8 | bellard | if ((env->mmucr & 0x54000000) == 0x04000000) |
242 | fdf9b3e8 | bellard | return 2; |
243 | fdf9b3e8 | bellard | if ((env->mmucr & 0x2c000000) == 0x00000000) |
244 | fdf9b3e8 | bellard | return 3; |
245 | fdf9b3e8 | bellard | assert(0);
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246 | fdf9b3e8 | bellard | } |
247 | fdf9b3e8 | bellard | |
248 | fdf9b3e8 | bellard | /* Find the corresponding entry in the right TLB
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249 | fdf9b3e8 | bellard | Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
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250 | fdf9b3e8 | bellard | */
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251 | fdf9b3e8 | bellard | static int find_tlb_entry(CPUState * env, target_ulong address, |
252 | fdf9b3e8 | bellard | tlb_t * entries, uint8_t nbtlb, int use_asid)
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253 | fdf9b3e8 | bellard | { |
254 | fdf9b3e8 | bellard | int match = MMU_DTLB_MISS;
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255 | fdf9b3e8 | bellard | uint32_t start, end; |
256 | fdf9b3e8 | bellard | uint8_t asid; |
257 | fdf9b3e8 | bellard | int i;
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258 | fdf9b3e8 | bellard | |
259 | fdf9b3e8 | bellard | asid = env->pteh & 0xff;
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260 | fdf9b3e8 | bellard | |
261 | fdf9b3e8 | bellard | for (i = 0; i < nbtlb; i++) { |
262 | fdf9b3e8 | bellard | if (!entries[i].v)
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263 | fdf9b3e8 | bellard | continue; /* Invalid entry */ |
264 | eeda6778 | aurel32 | if (!entries[i].sh && use_asid && entries[i].asid != asid)
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265 | fdf9b3e8 | bellard | continue; /* Bad ASID */ |
266 | fdf9b3e8 | bellard | #if 0
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267 | fdf9b3e8 | bellard | switch (entries[i].sz) {
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268 | fdf9b3e8 | bellard | case 0:
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269 | fdf9b3e8 | bellard | size = 1024; /* 1kB */
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270 | fdf9b3e8 | bellard | break;
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271 | fdf9b3e8 | bellard | case 1:
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272 | fdf9b3e8 | bellard | size = 4 * 1024; /* 4kB */
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273 | fdf9b3e8 | bellard | break;
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274 | fdf9b3e8 | bellard | case 2:
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275 | fdf9b3e8 | bellard | size = 64 * 1024; /* 64kB */
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276 | fdf9b3e8 | bellard | break;
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277 | fdf9b3e8 | bellard | case 3:
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278 | fdf9b3e8 | bellard | size = 1024 * 1024; /* 1MB */
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279 | fdf9b3e8 | bellard | break;
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280 | fdf9b3e8 | bellard | default:
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281 | fdf9b3e8 | bellard | assert(0);
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282 | fdf9b3e8 | bellard | }
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283 | fdf9b3e8 | bellard | #endif
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284 | fdf9b3e8 | bellard | start = (entries[i].vpn << 10) & ~(entries[i].size - 1); |
285 | fdf9b3e8 | bellard | end = start + entries[i].size - 1;
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286 | fdf9b3e8 | bellard | if (address >= start && address <= end) { /* Match */ |
287 | ea2b542a | aurel32 | if (match != MMU_DTLB_MISS)
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288 | fdf9b3e8 | bellard | return MMU_DTLB_MULTIPLE; /* Multiple match */ |
289 | fdf9b3e8 | bellard | match = i; |
290 | fdf9b3e8 | bellard | } |
291 | fdf9b3e8 | bellard | } |
292 | fdf9b3e8 | bellard | return match;
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293 | fdf9b3e8 | bellard | } |
294 | fdf9b3e8 | bellard | |
295 | 29e179bc | aurel32 | static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb, |
296 | 29e179bc | aurel32 | const tlb_t * needle)
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297 | 29e179bc | aurel32 | { |
298 | 29e179bc | aurel32 | int i;
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299 | 29e179bc | aurel32 | for (i = 0; i < nbtlb; i++) |
300 | 29e179bc | aurel32 | if (!memcmp(&haystack[i], needle, sizeof(tlb_t))) |
301 | 29e179bc | aurel32 | return 1; |
302 | 29e179bc | aurel32 | return 0; |
303 | 29e179bc | aurel32 | } |
304 | 29e179bc | aurel32 | |
305 | 29e179bc | aurel32 | static void increment_urc(CPUState * env) |
306 | 29e179bc | aurel32 | { |
307 | 29e179bc | aurel32 | uint8_t urb, urc; |
308 | 29e179bc | aurel32 | |
309 | 29e179bc | aurel32 | /* Increment URC */
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310 | 29e179bc | aurel32 | urb = ((env->mmucr) >> 18) & 0x3f; |
311 | 29e179bc | aurel32 | urc = ((env->mmucr) >> 10) & 0x3f; |
312 | 29e179bc | aurel32 | urc++; |
313 | 927e3a4e | aurel32 | if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1)) |
314 | 29e179bc | aurel32 | urc = 0;
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315 | 29e179bc | aurel32 | env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10); |
316 | 29e179bc | aurel32 | } |
317 | 29e179bc | aurel32 | |
318 | fdf9b3e8 | bellard | /* Find itlb entry - update itlb from utlb if necessary and asked for
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319 | fdf9b3e8 | bellard | Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
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320 | fdf9b3e8 | bellard | Update the itlb from utlb if update is not 0
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321 | fdf9b3e8 | bellard | */
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322 | ef7ec1c1 | aurel32 | static int find_itlb_entry(CPUState * env, target_ulong address, |
323 | ef7ec1c1 | aurel32 | int use_asid, int update) |
324 | fdf9b3e8 | bellard | { |
325 | fdf9b3e8 | bellard | int e, n;
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326 | fdf9b3e8 | bellard | |
327 | fdf9b3e8 | bellard | e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid); |
328 | fdf9b3e8 | bellard | if (e == MMU_DTLB_MULTIPLE)
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329 | fdf9b3e8 | bellard | e = MMU_ITLB_MULTIPLE; |
330 | fdf9b3e8 | bellard | else if (e == MMU_DTLB_MISS && update) { |
331 | fdf9b3e8 | bellard | e = find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid); |
332 | fdf9b3e8 | bellard | if (e >= 0) { |
333 | 06afe2c8 | aurel32 | tlb_t * ientry; |
334 | fdf9b3e8 | bellard | n = itlb_replacement(env); |
335 | 06afe2c8 | aurel32 | ientry = &env->itlb[n]; |
336 | 06afe2c8 | aurel32 | if (ientry->v) {
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337 | 06afe2c8 | aurel32 | if (!same_tlb_entry_exists(env->utlb, UTLB_SIZE, ientry))
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338 | 06afe2c8 | aurel32 | tlb_flush_page(env, ientry->vpn << 10);
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339 | 06afe2c8 | aurel32 | } |
340 | 06afe2c8 | aurel32 | *ientry = env->utlb[e]; |
341 | fdf9b3e8 | bellard | e = n; |
342 | ea2b542a | aurel32 | } else if (e == MMU_DTLB_MISS) |
343 | ea2b542a | aurel32 | e = MMU_ITLB_MISS; |
344 | ea2b542a | aurel32 | } else if (e == MMU_DTLB_MISS) |
345 | ea2b542a | aurel32 | e = MMU_ITLB_MISS; |
346 | fdf9b3e8 | bellard | if (e >= 0) |
347 | fdf9b3e8 | bellard | update_itlb_use(env, e); |
348 | fdf9b3e8 | bellard | return e;
|
349 | fdf9b3e8 | bellard | } |
350 | fdf9b3e8 | bellard | |
351 | fdf9b3e8 | bellard | /* Find utlb entry
|
352 | fdf9b3e8 | bellard | Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
|
353 | ef7ec1c1 | aurel32 | static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid) |
354 | fdf9b3e8 | bellard | { |
355 | 29e179bc | aurel32 | /* per utlb access */
|
356 | 29e179bc | aurel32 | increment_urc(env); |
357 | fdf9b3e8 | bellard | |
358 | fdf9b3e8 | bellard | /* Return entry */
|
359 | fdf9b3e8 | bellard | return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
|
360 | fdf9b3e8 | bellard | } |
361 | fdf9b3e8 | bellard | |
362 | fdf9b3e8 | bellard | /* Match address against MMU
|
363 | fdf9b3e8 | bellard | Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
|
364 | fdf9b3e8 | bellard | MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
|
365 | fdf9b3e8 | bellard | MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
|
366 | cf7055bd | aurel32 | MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
|
367 | cf7055bd | aurel32 | MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
|
368 | fdf9b3e8 | bellard | */
|
369 | fdf9b3e8 | bellard | static int get_mmu_address(CPUState * env, target_ulong * physical, |
370 | fdf9b3e8 | bellard | int *prot, target_ulong address,
|
371 | fdf9b3e8 | bellard | int rw, int access_type) |
372 | fdf9b3e8 | bellard | { |
373 | cf7055bd | aurel32 | int use_asid, n;
|
374 | fdf9b3e8 | bellard | tlb_t *matching = NULL;
|
375 | fdf9b3e8 | bellard | |
376 | 06afe2c8 | aurel32 | use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0; |
377 | fdf9b3e8 | bellard | |
378 | cf7055bd | aurel32 | if (rw == 2) { |
379 | fdf9b3e8 | bellard | n = find_itlb_entry(env, address, use_asid, 1);
|
380 | fdf9b3e8 | bellard | if (n >= 0) { |
381 | fdf9b3e8 | bellard | matching = &env->itlb[n]; |
382 | fdf9b3e8 | bellard | if ((env->sr & SR_MD) & !(matching->pr & 2)) |
383 | fdf9b3e8 | bellard | n = MMU_ITLB_VIOLATION; |
384 | fdf9b3e8 | bellard | else
|
385 | fdf9b3e8 | bellard | *prot = PAGE_READ; |
386 | fdf9b3e8 | bellard | } |
387 | fdf9b3e8 | bellard | } else {
|
388 | fdf9b3e8 | bellard | n = find_utlb_entry(env, address, use_asid); |
389 | fdf9b3e8 | bellard | if (n >= 0) { |
390 | fdf9b3e8 | bellard | matching = &env->utlb[n]; |
391 | fdf9b3e8 | bellard | switch ((matching->pr << 1) | ((env->sr & SR_MD) ? 1 : 0)) { |
392 | fdf9b3e8 | bellard | case 0: /* 000 */ |
393 | fdf9b3e8 | bellard | case 2: /* 010 */ |
394 | cf7055bd | aurel32 | n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
|
395 | fdf9b3e8 | bellard | MMU_DTLB_VIOLATION_READ; |
396 | fdf9b3e8 | bellard | break;
|
397 | fdf9b3e8 | bellard | case 1: /* 001 */ |
398 | fdf9b3e8 | bellard | case 4: /* 100 */ |
399 | fdf9b3e8 | bellard | case 5: /* 101 */ |
400 | cf7055bd | aurel32 | if (rw == 1) |
401 | fdf9b3e8 | bellard | n = MMU_DTLB_VIOLATION_WRITE; |
402 | fdf9b3e8 | bellard | else
|
403 | fdf9b3e8 | bellard | *prot = PAGE_READ; |
404 | fdf9b3e8 | bellard | break;
|
405 | fdf9b3e8 | bellard | case 3: /* 011 */ |
406 | fdf9b3e8 | bellard | case 6: /* 110 */ |
407 | fdf9b3e8 | bellard | case 7: /* 111 */ |
408 | cf7055bd | aurel32 | *prot = (rw == 1)? PAGE_WRITE : PAGE_READ;
|
409 | fdf9b3e8 | bellard | break;
|
410 | fdf9b3e8 | bellard | } |
411 | fdf9b3e8 | bellard | } else if (n == MMU_DTLB_MISS) { |
412 | cf7055bd | aurel32 | n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
|
413 | fdf9b3e8 | bellard | MMU_DTLB_MISS_READ; |
414 | fdf9b3e8 | bellard | } |
415 | fdf9b3e8 | bellard | } |
416 | fdf9b3e8 | bellard | if (n >= 0) { |
417 | fdf9b3e8 | bellard | *physical = ((matching->ppn << 10) & ~(matching->size - 1)) | |
418 | fdf9b3e8 | bellard | (address & (matching->size - 1));
|
419 | cf7055bd | aurel32 | if ((rw == 1) & !matching->d) |
420 | fdf9b3e8 | bellard | n = MMU_DTLB_INITIAL_WRITE; |
421 | fdf9b3e8 | bellard | else
|
422 | fdf9b3e8 | bellard | n = MMU_OK; |
423 | fdf9b3e8 | bellard | } |
424 | fdf9b3e8 | bellard | return n;
|
425 | fdf9b3e8 | bellard | } |
426 | fdf9b3e8 | bellard | |
427 | ef7ec1c1 | aurel32 | static int get_physical_address(CPUState * env, target_ulong * physical, |
428 | ef7ec1c1 | aurel32 | int *prot, target_ulong address,
|
429 | ef7ec1c1 | aurel32 | int rw, int access_type) |
430 | fdf9b3e8 | bellard | { |
431 | fdf9b3e8 | bellard | /* P1, P2 and P4 areas do not use translation */
|
432 | fdf9b3e8 | bellard | if ((address >= 0x80000000 && address < 0xc0000000) || |
433 | fdf9b3e8 | bellard | address >= 0xe0000000) {
|
434 | fdf9b3e8 | bellard | if (!(env->sr & SR_MD)
|
435 | fdf9b3e8 | bellard | && (address < 0xe0000000 || address > 0xe4000000)) { |
436 | fdf9b3e8 | bellard | /* Unauthorized access in user mode (only store queues are available) */
|
437 | fdf9b3e8 | bellard | fprintf(stderr, "Unauthorized access\n");
|
438 | cf7055bd | aurel32 | if (rw == 0) |
439 | cf7055bd | aurel32 | return MMU_DADDR_ERROR_READ;
|
440 | cf7055bd | aurel32 | else if (rw == 1) |
441 | cf7055bd | aurel32 | return MMU_DADDR_ERROR_WRITE;
|
442 | cf7055bd | aurel32 | else
|
443 | cf7055bd | aurel32 | return MMU_IADDR_ERROR;
|
444 | fdf9b3e8 | bellard | } |
445 | 29e179bc | aurel32 | if (address >= 0x80000000 && address < 0xc0000000) { |
446 | 29e179bc | aurel32 | /* Mask upper 3 bits for P1 and P2 areas */
|
447 | 29e179bc | aurel32 | *physical = address & 0x1fffffff;
|
448 | 29e179bc | aurel32 | } else {
|
449 | 29e179bc | aurel32 | *physical = address; |
450 | 29e179bc | aurel32 | } |
451 | fdf9b3e8 | bellard | *prot = PAGE_READ | PAGE_WRITE; |
452 | fdf9b3e8 | bellard | return MMU_OK;
|
453 | fdf9b3e8 | bellard | } |
454 | fdf9b3e8 | bellard | |
455 | fdf9b3e8 | bellard | /* If MMU is disabled, return the corresponding physical page */
|
456 | fdf9b3e8 | bellard | if (!env->mmucr & MMUCR_AT) {
|
457 | fdf9b3e8 | bellard | *physical = address & 0x1FFFFFFF;
|
458 | fdf9b3e8 | bellard | *prot = PAGE_READ | PAGE_WRITE; |
459 | fdf9b3e8 | bellard | return MMU_OK;
|
460 | fdf9b3e8 | bellard | } |
461 | fdf9b3e8 | bellard | |
462 | fdf9b3e8 | bellard | /* We need to resort to the MMU */
|
463 | fdf9b3e8 | bellard | return get_mmu_address(env, physical, prot, address, rw, access_type);
|
464 | fdf9b3e8 | bellard | } |
465 | fdf9b3e8 | bellard | |
466 | fdf9b3e8 | bellard | int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw, |
467 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
468 | fdf9b3e8 | bellard | { |
469 | fdf9b3e8 | bellard | target_ulong physical, page_offset, page_size; |
470 | fdf9b3e8 | bellard | int prot, ret, access_type;
|
471 | fdf9b3e8 | bellard | |
472 | fdf9b3e8 | bellard | access_type = ACCESS_INT; |
473 | fdf9b3e8 | bellard | ret = |
474 | fdf9b3e8 | bellard | get_physical_address(env, &physical, &prot, address, rw, |
475 | fdf9b3e8 | bellard | access_type); |
476 | fdf9b3e8 | bellard | |
477 | fdf9b3e8 | bellard | if (ret != MMU_OK) {
|
478 | fdf9b3e8 | bellard | env->tea = address; |
479 | fdf9b3e8 | bellard | switch (ret) {
|
480 | fdf9b3e8 | bellard | case MMU_ITLB_MISS:
|
481 | fdf9b3e8 | bellard | case MMU_DTLB_MISS_READ:
|
482 | fdf9b3e8 | bellard | env->exception_index = 0x040;
|
483 | fdf9b3e8 | bellard | break;
|
484 | fdf9b3e8 | bellard | case MMU_DTLB_MULTIPLE:
|
485 | fdf9b3e8 | bellard | case MMU_ITLB_MULTIPLE:
|
486 | fdf9b3e8 | bellard | env->exception_index = 0x140;
|
487 | fdf9b3e8 | bellard | break;
|
488 | fdf9b3e8 | bellard | case MMU_ITLB_VIOLATION:
|
489 | fdf9b3e8 | bellard | env->exception_index = 0x0a0;
|
490 | fdf9b3e8 | bellard | break;
|
491 | fdf9b3e8 | bellard | case MMU_DTLB_MISS_WRITE:
|
492 | fdf9b3e8 | bellard | env->exception_index = 0x060;
|
493 | fdf9b3e8 | bellard | break;
|
494 | fdf9b3e8 | bellard | case MMU_DTLB_INITIAL_WRITE:
|
495 | fdf9b3e8 | bellard | env->exception_index = 0x080;
|
496 | fdf9b3e8 | bellard | break;
|
497 | fdf9b3e8 | bellard | case MMU_DTLB_VIOLATION_READ:
|
498 | fdf9b3e8 | bellard | env->exception_index = 0x0a0;
|
499 | fdf9b3e8 | bellard | break;
|
500 | fdf9b3e8 | bellard | case MMU_DTLB_VIOLATION_WRITE:
|
501 | fdf9b3e8 | bellard | env->exception_index = 0x0c0;
|
502 | fdf9b3e8 | bellard | break;
|
503 | cf7055bd | aurel32 | case MMU_IADDR_ERROR:
|
504 | cf7055bd | aurel32 | case MMU_DADDR_ERROR_READ:
|
505 | cf7055bd | aurel32 | env->exception_index = 0x0c0;
|
506 | cf7055bd | aurel32 | break;
|
507 | cf7055bd | aurel32 | case MMU_DADDR_ERROR_WRITE:
|
508 | cf7055bd | aurel32 | env->exception_index = 0x100;
|
509 | cf7055bd | aurel32 | break;
|
510 | fdf9b3e8 | bellard | default:
|
511 | fdf9b3e8 | bellard | assert(0);
|
512 | fdf9b3e8 | bellard | } |
513 | fdf9b3e8 | bellard | return 1; |
514 | fdf9b3e8 | bellard | } |
515 | fdf9b3e8 | bellard | |
516 | fdf9b3e8 | bellard | page_size = TARGET_PAGE_SIZE; |
517 | fdf9b3e8 | bellard | page_offset = |
518 | fdf9b3e8 | bellard | (address - (address & TARGET_PAGE_MASK)) & ~(page_size - 1);
|
519 | fdf9b3e8 | bellard | address = (address & TARGET_PAGE_MASK) + page_offset; |
520 | fdf9b3e8 | bellard | physical = (physical & TARGET_PAGE_MASK) + page_offset; |
521 | fdf9b3e8 | bellard | |
522 | 6ebbf390 | j_mayer | return tlb_set_page(env, address, physical, prot, mmu_idx, is_softmmu);
|
523 | fdf9b3e8 | bellard | } |
524 | 355fb23d | pbrook | |
525 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr) |
526 | 355fb23d | pbrook | { |
527 | 355fb23d | pbrook | target_ulong physical; |
528 | 355fb23d | pbrook | int prot;
|
529 | 355fb23d | pbrook | |
530 | cf7055bd | aurel32 | get_physical_address(env, &physical, &prot, addr, 0, 0); |
531 | 355fb23d | pbrook | return physical;
|
532 | 355fb23d | pbrook | } |
533 | 355fb23d | pbrook | |
534 | ef7ec1c1 | aurel32 | void cpu_load_tlb(CPUSH4State * env)
|
535 | ea2b542a | aurel32 | { |
536 | ea2b542a | aurel32 | int n = cpu_mmucr_urc(env->mmucr);
|
537 | ea2b542a | aurel32 | tlb_t * entry = &env->utlb[n]; |
538 | ea2b542a | aurel32 | |
539 | 06afe2c8 | aurel32 | if (entry->v) {
|
540 | 06afe2c8 | aurel32 | /* Overwriting valid entry in utlb. */
|
541 | 06afe2c8 | aurel32 | target_ulong address = entry->vpn << 10;
|
542 | 06afe2c8 | aurel32 | if (!same_tlb_entry_exists(env->itlb, ITLB_SIZE, entry)) {
|
543 | 06afe2c8 | aurel32 | tlb_flush_page(env, address); |
544 | 06afe2c8 | aurel32 | } |
545 | 06afe2c8 | aurel32 | } |
546 | 06afe2c8 | aurel32 | |
547 | ea2b542a | aurel32 | /* Take values into cpu status from registers. */
|
548 | ea2b542a | aurel32 | entry->asid = (uint8_t)cpu_pteh_asid(env->pteh); |
549 | ea2b542a | aurel32 | entry->vpn = cpu_pteh_vpn(env->pteh); |
550 | ea2b542a | aurel32 | entry->v = (uint8_t)cpu_ptel_v(env->ptel); |
551 | ea2b542a | aurel32 | entry->ppn = cpu_ptel_ppn(env->ptel); |
552 | ea2b542a | aurel32 | entry->sz = (uint8_t)cpu_ptel_sz(env->ptel); |
553 | ea2b542a | aurel32 | switch (entry->sz) {
|
554 | ea2b542a | aurel32 | case 0: /* 00 */ |
555 | ea2b542a | aurel32 | entry->size = 1024; /* 1K */ |
556 | ea2b542a | aurel32 | break;
|
557 | ea2b542a | aurel32 | case 1: /* 01 */ |
558 | ea2b542a | aurel32 | entry->size = 1024 * 4; /* 4K */ |
559 | ea2b542a | aurel32 | break;
|
560 | ea2b542a | aurel32 | case 2: /* 10 */ |
561 | ea2b542a | aurel32 | entry->size = 1024 * 64; /* 64K */ |
562 | ea2b542a | aurel32 | break;
|
563 | ea2b542a | aurel32 | case 3: /* 11 */ |
564 | ea2b542a | aurel32 | entry->size = 1024 * 1024; /* 1M */ |
565 | ea2b542a | aurel32 | break;
|
566 | ea2b542a | aurel32 | default:
|
567 | ea2b542a | aurel32 | assert(0);
|
568 | ea2b542a | aurel32 | break;
|
569 | ea2b542a | aurel32 | } |
570 | ea2b542a | aurel32 | entry->sh = (uint8_t)cpu_ptel_sh(env->ptel); |
571 | ea2b542a | aurel32 | entry->c = (uint8_t)cpu_ptel_c(env->ptel); |
572 | ea2b542a | aurel32 | entry->pr = (uint8_t)cpu_ptel_pr(env->ptel); |
573 | ea2b542a | aurel32 | entry->d = (uint8_t)cpu_ptel_d(env->ptel); |
574 | ea2b542a | aurel32 | entry->wt = (uint8_t)cpu_ptel_wt(env->ptel); |
575 | ea2b542a | aurel32 | entry->sa = (uint8_t)cpu_ptea_sa(env->ptea); |
576 | ea2b542a | aurel32 | entry->tc = (uint8_t)cpu_ptea_tc(env->ptea); |
577 | ea2b542a | aurel32 | } |
578 | ea2b542a | aurel32 | |
579 | 29e179bc | aurel32 | void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
|
580 | 29e179bc | aurel32 | uint32_t mem_value) |
581 | 29e179bc | aurel32 | { |
582 | 29e179bc | aurel32 | int associate = addr & 0x0000080; |
583 | 29e179bc | aurel32 | uint32_t vpn = (mem_value & 0xfffffc00) >> 10; |
584 | 29e179bc | aurel32 | uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9); |
585 | 29e179bc | aurel32 | uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8); |
586 | 29e179bc | aurel32 | uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
|
587 | eeda6778 | aurel32 | int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0; |
588 | 29e179bc | aurel32 | |
589 | 29e179bc | aurel32 | if (associate) {
|
590 | 29e179bc | aurel32 | int i;
|
591 | 29e179bc | aurel32 | tlb_t * utlb_match_entry = NULL;
|
592 | 29e179bc | aurel32 | int needs_tlb_flush = 0; |
593 | 29e179bc | aurel32 | |
594 | 29e179bc | aurel32 | /* search UTLB */
|
595 | 29e179bc | aurel32 | for (i = 0; i < UTLB_SIZE; i++) { |
596 | 29e179bc | aurel32 | tlb_t * entry = &s->utlb[i]; |
597 | 29e179bc | aurel32 | if (!entry->v)
|
598 | 29e179bc | aurel32 | continue;
|
599 | 29e179bc | aurel32 | |
600 | eeda6778 | aurel32 | if (entry->vpn == vpn
|
601 | eeda6778 | aurel32 | && (!use_asid || entry->asid == asid || entry->sh)) { |
602 | 29e179bc | aurel32 | if (utlb_match_entry) {
|
603 | 29e179bc | aurel32 | /* Multiple TLB Exception */
|
604 | 29e179bc | aurel32 | s->exception_index = 0x140;
|
605 | 29e179bc | aurel32 | s->tea = addr; |
606 | 29e179bc | aurel32 | break;
|
607 | 29e179bc | aurel32 | } |
608 | 29e179bc | aurel32 | if (entry->v && !v)
|
609 | 29e179bc | aurel32 | needs_tlb_flush = 1;
|
610 | 29e179bc | aurel32 | entry->v = v; |
611 | 29e179bc | aurel32 | entry->d = d; |
612 | 29e179bc | aurel32 | utlb_match_entry = entry; |
613 | 29e179bc | aurel32 | } |
614 | 29e179bc | aurel32 | increment_urc(s); /* per utlb access */
|
615 | 29e179bc | aurel32 | } |
616 | 29e179bc | aurel32 | |
617 | 29e179bc | aurel32 | /* search ITLB */
|
618 | 29e179bc | aurel32 | for (i = 0; i < ITLB_SIZE; i++) { |
619 | 29e179bc | aurel32 | tlb_t * entry = &s->itlb[i]; |
620 | eeda6778 | aurel32 | if (entry->vpn == vpn
|
621 | eeda6778 | aurel32 | && (!use_asid || entry->asid == asid || entry->sh)) { |
622 | 29e179bc | aurel32 | if (entry->v && !v)
|
623 | 29e179bc | aurel32 | needs_tlb_flush = 1;
|
624 | 29e179bc | aurel32 | if (utlb_match_entry)
|
625 | 29e179bc | aurel32 | *entry = *utlb_match_entry; |
626 | 29e179bc | aurel32 | else
|
627 | 29e179bc | aurel32 | entry->v = v; |
628 | 29e179bc | aurel32 | break;
|
629 | 29e179bc | aurel32 | } |
630 | 29e179bc | aurel32 | } |
631 | 29e179bc | aurel32 | |
632 | 29e179bc | aurel32 | if (needs_tlb_flush)
|
633 | 29e179bc | aurel32 | tlb_flush_page(s, vpn << 10);
|
634 | 29e179bc | aurel32 | |
635 | 29e179bc | aurel32 | } else {
|
636 | 29e179bc | aurel32 | int index = (addr & 0x00003f00) >> 8; |
637 | 29e179bc | aurel32 | tlb_t * entry = &s->utlb[index]; |
638 | 29e179bc | aurel32 | if (entry->v) {
|
639 | 29e179bc | aurel32 | /* Overwriting valid entry in utlb. */
|
640 | 29e179bc | aurel32 | target_ulong address = entry->vpn << 10;
|
641 | 29e179bc | aurel32 | if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
|
642 | 29e179bc | aurel32 | tlb_flush_page(s, address); |
643 | 29e179bc | aurel32 | } |
644 | 29e179bc | aurel32 | } |
645 | 29e179bc | aurel32 | entry->asid = asid; |
646 | 29e179bc | aurel32 | entry->vpn = vpn; |
647 | 29e179bc | aurel32 | entry->d = d; |
648 | 29e179bc | aurel32 | entry->v = v; |
649 | 29e179bc | aurel32 | increment_urc(s); |
650 | 29e179bc | aurel32 | } |
651 | 29e179bc | aurel32 | } |
652 | 29e179bc | aurel32 | |
653 | 852d481f | edgar_igl | int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
|
654 | 852d481f | edgar_igl | { |
655 | 852d481f | edgar_igl | int n;
|
656 | 852d481f | edgar_igl | int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0; |
657 | 852d481f | edgar_igl | |
658 | 852d481f | edgar_igl | /* check area */
|
659 | 852d481f | edgar_igl | if (env->sr & SR_MD) {
|
660 | 852d481f | edgar_igl | /* For previledged mode, P2 and P4 area is not cachable. */
|
661 | 852d481f | edgar_igl | if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr) |
662 | 852d481f | edgar_igl | return 0; |
663 | 852d481f | edgar_igl | } else {
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664 | 852d481f | edgar_igl | /* For user mode, only U0 area is cachable. */
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665 | 852d481f | edgar_igl | if (0x80000000 <= addr) |
666 | 852d481f | edgar_igl | return 0; |
667 | 852d481f | edgar_igl | } |
668 | 852d481f | edgar_igl | |
669 | 852d481f | edgar_igl | /*
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670 | 852d481f | edgar_igl | * TODO : Evaluate CCR and check if the cache is on or off.
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671 | 852d481f | edgar_igl | * Now CCR is not in CPUSH4State, but in SH7750State.
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672 | 852d481f | edgar_igl | * When you move the ccr inot CPUSH4State, the code will be
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673 | 852d481f | edgar_igl | * as follows.
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674 | 852d481f | edgar_igl | */
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675 | 852d481f | edgar_igl | #if 0
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676 | 852d481f | edgar_igl | /* check if operand cache is enabled or not. */
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677 | 852d481f | edgar_igl | if (!(env->ccr & 1))
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678 | 852d481f | edgar_igl | return 0;
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679 | 852d481f | edgar_igl | #endif
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680 | 852d481f | edgar_igl | |
681 | 852d481f | edgar_igl | /* if MMU is off, no check for TLB. */
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682 | 852d481f | edgar_igl | if (env->mmucr & MMUCR_AT)
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683 | 852d481f | edgar_igl | return 1; |
684 | 852d481f | edgar_igl | |
685 | 852d481f | edgar_igl | /* check TLB */
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686 | 852d481f | edgar_igl | n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid); |
687 | 852d481f | edgar_igl | if (n >= 0) |
688 | 852d481f | edgar_igl | return env->itlb[n].c;
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689 | 852d481f | edgar_igl | |
690 | 852d481f | edgar_igl | n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid); |
691 | 852d481f | edgar_igl | if (n >= 0) |
692 | 852d481f | edgar_igl | return env->utlb[n].c;
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693 | 852d481f | edgar_igl | |
694 | 852d481f | edgar_igl | return 0; |
695 | 852d481f | edgar_igl | } |
696 | 852d481f | edgar_igl | |
697 | 355fb23d | pbrook | #endif |