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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * ARM micro operations
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 2c0262af | bellard | *
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6 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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7 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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9 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 2c0262af | bellard | *
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11 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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12 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 2c0262af | bellard | * Lesser General Public License for more details.
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15 | 2c0262af | bellard | *
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16 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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18 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 2c0262af | bellard | */
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20 | 2c0262af | bellard | #include "exec.h" |
21 | 2c0262af | bellard | |
22 | 2c0262af | bellard | #define REGNAME r0
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23 | 2c0262af | bellard | #define REG (env->regs[0]) |
24 | 2c0262af | bellard | #include "op_template.h" |
25 | 2c0262af | bellard | |
26 | 2c0262af | bellard | #define REGNAME r1
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27 | 2c0262af | bellard | #define REG (env->regs[1]) |
28 | 2c0262af | bellard | #include "op_template.h" |
29 | 2c0262af | bellard | |
30 | 2c0262af | bellard | #define REGNAME r2
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31 | 2c0262af | bellard | #define REG (env->regs[2]) |
32 | 2c0262af | bellard | #include "op_template.h" |
33 | 2c0262af | bellard | |
34 | 2c0262af | bellard | #define REGNAME r3
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35 | 2c0262af | bellard | #define REG (env->regs[3]) |
36 | 2c0262af | bellard | #include "op_template.h" |
37 | 2c0262af | bellard | |
38 | 2c0262af | bellard | #define REGNAME r4
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39 | 2c0262af | bellard | #define REG (env->regs[4]) |
40 | 2c0262af | bellard | #include "op_template.h" |
41 | 2c0262af | bellard | |
42 | 2c0262af | bellard | #define REGNAME r5
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43 | 2c0262af | bellard | #define REG (env->regs[5]) |
44 | 2c0262af | bellard | #include "op_template.h" |
45 | 2c0262af | bellard | |
46 | 2c0262af | bellard | #define REGNAME r6
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47 | 2c0262af | bellard | #define REG (env->regs[6]) |
48 | 2c0262af | bellard | #include "op_template.h" |
49 | 2c0262af | bellard | |
50 | 2c0262af | bellard | #define REGNAME r7
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51 | 2c0262af | bellard | #define REG (env->regs[7]) |
52 | 2c0262af | bellard | #include "op_template.h" |
53 | 2c0262af | bellard | |
54 | 2c0262af | bellard | #define REGNAME r8
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55 | 2c0262af | bellard | #define REG (env->regs[8]) |
56 | 2c0262af | bellard | #include "op_template.h" |
57 | 2c0262af | bellard | |
58 | 2c0262af | bellard | #define REGNAME r9
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59 | 2c0262af | bellard | #define REG (env->regs[9]) |
60 | 2c0262af | bellard | #include "op_template.h" |
61 | 2c0262af | bellard | |
62 | 2c0262af | bellard | #define REGNAME r10
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63 | 2c0262af | bellard | #define REG (env->regs[10]) |
64 | 2c0262af | bellard | #include "op_template.h" |
65 | 2c0262af | bellard | |
66 | 2c0262af | bellard | #define REGNAME r11
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67 | 2c0262af | bellard | #define REG (env->regs[11]) |
68 | 2c0262af | bellard | #include "op_template.h" |
69 | 2c0262af | bellard | |
70 | 2c0262af | bellard | #define REGNAME r12
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71 | 2c0262af | bellard | #define REG (env->regs[12]) |
72 | 2c0262af | bellard | #include "op_template.h" |
73 | 2c0262af | bellard | |
74 | 2c0262af | bellard | #define REGNAME r13
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75 | 2c0262af | bellard | #define REG (env->regs[13]) |
76 | 2c0262af | bellard | #include "op_template.h" |
77 | 2c0262af | bellard | |
78 | 2c0262af | bellard | #define REGNAME r14
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79 | 2c0262af | bellard | #define REG (env->regs[14]) |
80 | 2c0262af | bellard | #include "op_template.h" |
81 | 2c0262af | bellard | |
82 | 2c0262af | bellard | #define REGNAME r15
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83 | 2c0262af | bellard | #define REG (env->regs[15]) |
84 | 2c0262af | bellard | #include "op_template.h" |
85 | 2c0262af | bellard | |
86 | 2c0262af | bellard | void OPPROTO op_movl_T0_0(void) |
87 | 2c0262af | bellard | { |
88 | 2c0262af | bellard | T0 = 0;
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89 | 2c0262af | bellard | } |
90 | 2c0262af | bellard | |
91 | 2c0262af | bellard | void OPPROTO op_movl_T0_im(void) |
92 | 2c0262af | bellard | { |
93 | 2c0262af | bellard | T0 = PARAM1; |
94 | 2c0262af | bellard | } |
95 | 2c0262af | bellard | |
96 | 2c0262af | bellard | void OPPROTO op_movl_T1_im(void) |
97 | 2c0262af | bellard | { |
98 | 2c0262af | bellard | T1 = PARAM1; |
99 | 2c0262af | bellard | } |
100 | 2c0262af | bellard | |
101 | 2c0262af | bellard | void OPPROTO op_movl_T2_im(void) |
102 | 2c0262af | bellard | { |
103 | 2c0262af | bellard | T2 = PARAM1; |
104 | 2c0262af | bellard | } |
105 | 2c0262af | bellard | |
106 | 2c0262af | bellard | void OPPROTO op_addl_T1_im(void) |
107 | 2c0262af | bellard | { |
108 | 2c0262af | bellard | T1 += PARAM1; |
109 | 2c0262af | bellard | } |
110 | 2c0262af | bellard | |
111 | 2c0262af | bellard | void OPPROTO op_addl_T1_T2(void) |
112 | 2c0262af | bellard | { |
113 | 2c0262af | bellard | T1 += T2; |
114 | 2c0262af | bellard | } |
115 | 2c0262af | bellard | |
116 | 2c0262af | bellard | void OPPROTO op_subl_T1_T2(void) |
117 | 2c0262af | bellard | { |
118 | 2c0262af | bellard | T1 -= T2; |
119 | 2c0262af | bellard | } |
120 | 2c0262af | bellard | |
121 | 2c0262af | bellard | void OPPROTO op_addl_T0_T1(void) |
122 | 2c0262af | bellard | { |
123 | 2c0262af | bellard | T0 += T1; |
124 | 2c0262af | bellard | } |
125 | 2c0262af | bellard | |
126 | 2c0262af | bellard | void OPPROTO op_addl_T0_T1_cc(void) |
127 | 2c0262af | bellard | { |
128 | 2c0262af | bellard | unsigned int src1; |
129 | 2c0262af | bellard | src1 = T0; |
130 | 2c0262af | bellard | T0 += T1; |
131 | 2c0262af | bellard | env->NZF = T0; |
132 | 2c0262af | bellard | env->CF = T0 < src1; |
133 | 2c0262af | bellard | env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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134 | 2c0262af | bellard | } |
135 | 2c0262af | bellard | |
136 | 2c0262af | bellard | void OPPROTO op_adcl_T0_T1(void) |
137 | 2c0262af | bellard | { |
138 | 2c0262af | bellard | T0 += T1 + env->CF; |
139 | 2c0262af | bellard | } |
140 | 2c0262af | bellard | |
141 | 2c0262af | bellard | void OPPROTO op_adcl_T0_T1_cc(void) |
142 | 2c0262af | bellard | { |
143 | 2c0262af | bellard | unsigned int src1; |
144 | 2c0262af | bellard | src1 = T0; |
145 | 2c0262af | bellard | if (!env->CF) {
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146 | 2c0262af | bellard | T0 += T1; |
147 | 2c0262af | bellard | env->CF = T0 < src1; |
148 | 2c0262af | bellard | } else {
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149 | 2c0262af | bellard | T0 += T1 + 1;
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150 | 2c0262af | bellard | env->CF = T0 <= src1; |
151 | 2c0262af | bellard | } |
152 | 2c0262af | bellard | env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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153 | 2c0262af | bellard | env->NZF = T0; |
154 | 2c0262af | bellard | FORCE_RET(); |
155 | 2c0262af | bellard | } |
156 | 2c0262af | bellard | |
157 | 2c0262af | bellard | #define OPSUB(sub, sbc, res, T0, T1) \
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158 | 2c0262af | bellard | \ |
159 | 2c0262af | bellard | void OPPROTO op_ ## sub ## l_T0_T1(void) \ |
160 | 2c0262af | bellard | { \ |
161 | 2c0262af | bellard | res = T0 - T1; \ |
162 | 2c0262af | bellard | } \ |
163 | 2c0262af | bellard | \ |
164 | 2c0262af | bellard | void OPPROTO op_ ## sub ## l_T0_T1_cc(void) \ |
165 | 2c0262af | bellard | { \ |
166 | 2c0262af | bellard | unsigned int src1; \ |
167 | 2c0262af | bellard | src1 = T0; \ |
168 | 2c0262af | bellard | T0 -= T1; \ |
169 | 2c0262af | bellard | env->NZF = T0; \ |
170 | 2c0262af | bellard | env->CF = src1 >= T1; \ |
171 | 2c0262af | bellard | env->VF = (src1 ^ T1) & (src1 ^ T0); \ |
172 | 2c0262af | bellard | res = T0; \ |
173 | 2c0262af | bellard | } \ |
174 | 2c0262af | bellard | \ |
175 | 2c0262af | bellard | void OPPROTO op_ ## sbc ## l_T0_T1(void) \ |
176 | 2c0262af | bellard | { \ |
177 | 2c0262af | bellard | res = T0 - T1 + env->CF - 1; \
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178 | 2c0262af | bellard | } \ |
179 | 2c0262af | bellard | \ |
180 | 2c0262af | bellard | void OPPROTO op_ ## sbc ## l_T0_T1_cc(void) \ |
181 | 2c0262af | bellard | { \ |
182 | 2c0262af | bellard | unsigned int src1; \ |
183 | 2c0262af | bellard | src1 = T0; \ |
184 | 2c0262af | bellard | if (!env->CF) { \
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185 | 2c0262af | bellard | T0 = T0 - T1 - 1; \
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186 | 2c0262af | bellard | env->CF = src1 >= T1; \ |
187 | 2c0262af | bellard | } else { \
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188 | 2c0262af | bellard | T0 = T0 - T1; \ |
189 | 2c0262af | bellard | env->CF = src1 > T1; \ |
190 | 2c0262af | bellard | } \ |
191 | 2c0262af | bellard | env->VF = (src1 ^ T1) & (src1 ^ T0); \ |
192 | 2c0262af | bellard | env->NZF = T0; \ |
193 | 2c0262af | bellard | res = T0; \ |
194 | 2c0262af | bellard | FORCE_RET(); \ |
195 | 2c0262af | bellard | } |
196 | 2c0262af | bellard | |
197 | 2c0262af | bellard | OPSUB(sub, sbc, T0, T0, T1) |
198 | 2c0262af | bellard | |
199 | 2c0262af | bellard | OPSUB(rsb, rsc, T0, T1, T0) |
200 | 2c0262af | bellard | |
201 | 2c0262af | bellard | void OPPROTO op_andl_T0_T1(void) |
202 | 2c0262af | bellard | { |
203 | 2c0262af | bellard | T0 &= T1; |
204 | 2c0262af | bellard | } |
205 | 2c0262af | bellard | |
206 | 2c0262af | bellard | void OPPROTO op_xorl_T0_T1(void) |
207 | 2c0262af | bellard | { |
208 | 2c0262af | bellard | T0 ^= T1; |
209 | 2c0262af | bellard | } |
210 | 2c0262af | bellard | |
211 | 2c0262af | bellard | void OPPROTO op_orl_T0_T1(void) |
212 | 2c0262af | bellard | { |
213 | 2c0262af | bellard | T0 |= T1; |
214 | 2c0262af | bellard | } |
215 | 2c0262af | bellard | |
216 | 2c0262af | bellard | void OPPROTO op_bicl_T0_T1(void) |
217 | 2c0262af | bellard | { |
218 | 2c0262af | bellard | T0 &= ~T1; |
219 | 2c0262af | bellard | } |
220 | 2c0262af | bellard | |
221 | 2c0262af | bellard | void OPPROTO op_notl_T1(void) |
222 | 2c0262af | bellard | { |
223 | 2c0262af | bellard | T1 = ~T1; |
224 | 2c0262af | bellard | } |
225 | 2c0262af | bellard | |
226 | 2c0262af | bellard | void OPPROTO op_logic_T0_cc(void) |
227 | 2c0262af | bellard | { |
228 | 2c0262af | bellard | env->NZF = T0; |
229 | 2c0262af | bellard | } |
230 | 2c0262af | bellard | |
231 | 2c0262af | bellard | void OPPROTO op_logic_T1_cc(void) |
232 | 2c0262af | bellard | { |
233 | 2c0262af | bellard | env->NZF = T1; |
234 | 2c0262af | bellard | } |
235 | 2c0262af | bellard | |
236 | 2c0262af | bellard | #define EIP (env->regs[15]) |
237 | 2c0262af | bellard | |
238 | 2c0262af | bellard | void OPPROTO op_test_eq(void) |
239 | 2c0262af | bellard | { |
240 | 2c0262af | bellard | if (env->NZF == 0) |
241 | 2c0262af | bellard | JUMP_TB(op_test_eq, PARAM1, 0, PARAM2);
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242 | 2c0262af | bellard | FORCE_RET(); |
243 | 2c0262af | bellard | } |
244 | 2c0262af | bellard | |
245 | 2c0262af | bellard | void OPPROTO op_test_ne(void) |
246 | 2c0262af | bellard | { |
247 | 2c0262af | bellard | if (env->NZF != 0) |
248 | 2c0262af | bellard | JUMP_TB(op_test_ne, PARAM1, 0, PARAM2);
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249 | 2c0262af | bellard | FORCE_RET(); |
250 | 2c0262af | bellard | } |
251 | 2c0262af | bellard | |
252 | 2c0262af | bellard | void OPPROTO op_test_cs(void) |
253 | 2c0262af | bellard | { |
254 | 2c0262af | bellard | if (env->CF != 0) |
255 | 2c0262af | bellard | JUMP_TB(op_test_cs, PARAM1, 0, PARAM2);
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256 | 2c0262af | bellard | FORCE_RET(); |
257 | 2c0262af | bellard | } |
258 | 2c0262af | bellard | |
259 | 2c0262af | bellard | void OPPROTO op_test_cc(void) |
260 | 2c0262af | bellard | { |
261 | 2c0262af | bellard | if (env->CF == 0) |
262 | 2c0262af | bellard | JUMP_TB(op_test_cc, PARAM1, 0, PARAM2);
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263 | 2c0262af | bellard | FORCE_RET(); |
264 | 2c0262af | bellard | } |
265 | 2c0262af | bellard | |
266 | 2c0262af | bellard | void OPPROTO op_test_mi(void) |
267 | 2c0262af | bellard | { |
268 | 2c0262af | bellard | if ((env->NZF & 0x80000000) != 0) |
269 | 2c0262af | bellard | JUMP_TB(op_test_mi, PARAM1, 0, PARAM2);
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270 | 2c0262af | bellard | FORCE_RET(); |
271 | 2c0262af | bellard | } |
272 | 2c0262af | bellard | |
273 | 2c0262af | bellard | void OPPROTO op_test_pl(void) |
274 | 2c0262af | bellard | { |
275 | 2c0262af | bellard | if ((env->NZF & 0x80000000) == 0) |
276 | 2c0262af | bellard | JUMP_TB(op_test_pl, PARAM1, 0, PARAM2);
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277 | 2c0262af | bellard | FORCE_RET(); |
278 | 2c0262af | bellard | } |
279 | 2c0262af | bellard | |
280 | 2c0262af | bellard | void OPPROTO op_test_vs(void) |
281 | 2c0262af | bellard | { |
282 | 2c0262af | bellard | if ((env->VF & 0x80000000) != 0) |
283 | 2c0262af | bellard | JUMP_TB(op_test_vs, PARAM1, 0, PARAM2);
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284 | 2c0262af | bellard | FORCE_RET(); |
285 | 2c0262af | bellard | } |
286 | 2c0262af | bellard | |
287 | 2c0262af | bellard | void OPPROTO op_test_vc(void) |
288 | 2c0262af | bellard | { |
289 | 2c0262af | bellard | if ((env->VF & 0x80000000) == 0) |
290 | 2c0262af | bellard | JUMP_TB(op_test_vc, PARAM1, 0, PARAM2);
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291 | 2c0262af | bellard | FORCE_RET(); |
292 | 2c0262af | bellard | } |
293 | 2c0262af | bellard | |
294 | 2c0262af | bellard | void OPPROTO op_test_hi(void) |
295 | 2c0262af | bellard | { |
296 | 2c0262af | bellard | if (env->CF != 0 && env->NZF != 0) |
297 | 2c0262af | bellard | JUMP_TB(op_test_hi, PARAM1, 0, PARAM2);
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298 | 2c0262af | bellard | FORCE_RET(); |
299 | 2c0262af | bellard | } |
300 | 2c0262af | bellard | |
301 | 2c0262af | bellard | void OPPROTO op_test_ls(void) |
302 | 2c0262af | bellard | { |
303 | 2c0262af | bellard | if (env->CF == 0 || env->NZF == 0) |
304 | 2c0262af | bellard | JUMP_TB(op_test_ls, PARAM1, 0, PARAM2);
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305 | 2c0262af | bellard | FORCE_RET(); |
306 | 2c0262af | bellard | } |
307 | 2c0262af | bellard | |
308 | 2c0262af | bellard | void OPPROTO op_test_ge(void) |
309 | 2c0262af | bellard | { |
310 | 2c0262af | bellard | if (((env->VF ^ env->NZF) & 0x80000000) == 0) |
311 | 2c0262af | bellard | JUMP_TB(op_test_ge, PARAM1, 0, PARAM2);
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312 | 2c0262af | bellard | FORCE_RET(); |
313 | 2c0262af | bellard | } |
314 | 2c0262af | bellard | |
315 | 2c0262af | bellard | void OPPROTO op_test_lt(void) |
316 | 2c0262af | bellard | { |
317 | 2c0262af | bellard | if (((env->VF ^ env->NZF) & 0x80000000) != 0) |
318 | 2c0262af | bellard | JUMP_TB(op_test_lt, PARAM1, 0, PARAM2);
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319 | 2c0262af | bellard | FORCE_RET(); |
320 | 2c0262af | bellard | } |
321 | 2c0262af | bellard | |
322 | 2c0262af | bellard | void OPPROTO op_test_gt(void) |
323 | 2c0262af | bellard | { |
324 | 2c0262af | bellard | if (env->NZF != 0 && ((env->VF ^ env->NZF) & 0x80000000) == 0) |
325 | 2c0262af | bellard | JUMP_TB(op_test_gt, PARAM1, 0, PARAM2);
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326 | 2c0262af | bellard | FORCE_RET(); |
327 | 2c0262af | bellard | } |
328 | 2c0262af | bellard | |
329 | 2c0262af | bellard | void OPPROTO op_test_le(void) |
330 | 2c0262af | bellard | { |
331 | 2c0262af | bellard | if (env->NZF == 0 || ((env->VF ^ env->NZF) & 0x80000000) != 0) |
332 | 2c0262af | bellard | JUMP_TB(op_test_le, PARAM1, 0, PARAM2);
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333 | 2c0262af | bellard | FORCE_RET(); |
334 | 2c0262af | bellard | } |
335 | 2c0262af | bellard | |
336 | 2c0262af | bellard | void OPPROTO op_jmp(void) |
337 | 2c0262af | bellard | { |
338 | 2c0262af | bellard | JUMP_TB(op_jmp, PARAM1, 1, PARAM2);
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339 | 2c0262af | bellard | } |
340 | 2c0262af | bellard | |
341 | 2c0262af | bellard | void OPPROTO op_exit_tb(void) |
342 | 2c0262af | bellard | { |
343 | 2c0262af | bellard | EXIT_TB(); |
344 | 2c0262af | bellard | } |
345 | 2c0262af | bellard | |
346 | 2c0262af | bellard | void OPPROTO op_movl_T0_psr(void) |
347 | 2c0262af | bellard | { |
348 | 2c0262af | bellard | T0 = compute_cpsr(); |
349 | 2c0262af | bellard | } |
350 | 2c0262af | bellard | |
351 | 2c0262af | bellard | /* NOTE: N = 1 and Z = 1 cannot be stored currently */
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352 | 2c0262af | bellard | void OPPROTO op_movl_psr_T0(void) |
353 | 2c0262af | bellard | { |
354 | 2c0262af | bellard | unsigned int psr; |
355 | 2c0262af | bellard | psr = T0; |
356 | 2c0262af | bellard | env->CF = (psr >> 29) & 1; |
357 | 2c0262af | bellard | env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
358 | 2c0262af | bellard | env->VF = (psr << 3) & 0x80000000; |
359 | 2c0262af | bellard | /* for user mode we do not update other state info */
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360 | 2c0262af | bellard | } |
361 | 2c0262af | bellard | |
362 | 2c0262af | bellard | void OPPROTO op_mul_T0_T1(void) |
363 | 2c0262af | bellard | { |
364 | 2c0262af | bellard | T0 = T0 * T1; |
365 | 2c0262af | bellard | } |
366 | 2c0262af | bellard | |
367 | 2c0262af | bellard | /* 64 bit unsigned mul */
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368 | 2c0262af | bellard | void OPPROTO op_mull_T0_T1(void) |
369 | 2c0262af | bellard | { |
370 | 2c0262af | bellard | uint64_t res; |
371 | 2e134c9c | bellard | res = (uint64_t)T0 * (uint64_t)T1; |
372 | 2c0262af | bellard | T1 = res >> 32;
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373 | 2c0262af | bellard | T0 = res; |
374 | 2c0262af | bellard | } |
375 | 2c0262af | bellard | |
376 | 2c0262af | bellard | /* 64 bit signed mul */
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377 | 2c0262af | bellard | void OPPROTO op_imull_T0_T1(void) |
378 | 2c0262af | bellard | { |
379 | 2c0262af | bellard | uint64_t res; |
380 | 163a7cb6 | bellard | res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1); |
381 | 2c0262af | bellard | T1 = res >> 32;
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382 | 2c0262af | bellard | T0 = res; |
383 | 2c0262af | bellard | } |
384 | 2c0262af | bellard | |
385 | 2c0262af | bellard | void OPPROTO op_addq_T0_T1(void) |
386 | 2c0262af | bellard | { |
387 | 2c0262af | bellard | uint64_t res; |
388 | 2c0262af | bellard | res = ((uint64_t)T1 << 32) | T0;
|
389 | 2c0262af | bellard | res += ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
|
390 | 2c0262af | bellard | T1 = res >> 32;
|
391 | 2c0262af | bellard | T0 = res; |
392 | 2c0262af | bellard | } |
393 | 2c0262af | bellard | |
394 | 2c0262af | bellard | void OPPROTO op_logicq_cc(void) |
395 | 2c0262af | bellard | { |
396 | 2c0262af | bellard | env->NZF = (T1 & 0x80000000) | ((T0 | T1) != 0); |
397 | 2c0262af | bellard | } |
398 | 2c0262af | bellard | |
399 | 2c0262af | bellard | /* memory access */
|
400 | 2c0262af | bellard | |
401 | 2c0262af | bellard | void OPPROTO op_ldub_T0_T1(void) |
402 | 2c0262af | bellard | { |
403 | 2c0262af | bellard | T0 = ldub((void *)T1);
|
404 | 2c0262af | bellard | } |
405 | 2c0262af | bellard | |
406 | 2c0262af | bellard | void OPPROTO op_ldsb_T0_T1(void) |
407 | 2c0262af | bellard | { |
408 | 2c0262af | bellard | T0 = ldsb((void *)T1);
|
409 | 2c0262af | bellard | } |
410 | 2c0262af | bellard | |
411 | 2c0262af | bellard | void OPPROTO op_lduw_T0_T1(void) |
412 | 2c0262af | bellard | { |
413 | 2c0262af | bellard | T0 = lduw((void *)T1);
|
414 | 2c0262af | bellard | } |
415 | 2c0262af | bellard | |
416 | 2c0262af | bellard | void OPPROTO op_ldsw_T0_T1(void) |
417 | 2c0262af | bellard | { |
418 | 2c0262af | bellard | T0 = ldsw((void *)T1);
|
419 | 2c0262af | bellard | } |
420 | 2c0262af | bellard | |
421 | 2c0262af | bellard | void OPPROTO op_ldl_T0_T1(void) |
422 | 2c0262af | bellard | { |
423 | 2c0262af | bellard | T0 = ldl((void *)T1);
|
424 | 2c0262af | bellard | } |
425 | 2c0262af | bellard | |
426 | 2c0262af | bellard | void OPPROTO op_stb_T0_T1(void) |
427 | 2c0262af | bellard | { |
428 | 2c0262af | bellard | stb((void *)T1, T0);
|
429 | 2c0262af | bellard | } |
430 | 2c0262af | bellard | |
431 | 2c0262af | bellard | void OPPROTO op_stw_T0_T1(void) |
432 | 2c0262af | bellard | { |
433 | 2c0262af | bellard | stw((void *)T1, T0);
|
434 | 2c0262af | bellard | } |
435 | 2c0262af | bellard | |
436 | 2c0262af | bellard | void OPPROTO op_stl_T0_T1(void) |
437 | 2c0262af | bellard | { |
438 | 2c0262af | bellard | stl((void *)T1, T0);
|
439 | 2c0262af | bellard | } |
440 | 2c0262af | bellard | |
441 | 2c0262af | bellard | void OPPROTO op_swpb_T0_T1(void) |
442 | 2c0262af | bellard | { |
443 | 2c0262af | bellard | int tmp;
|
444 | 2c0262af | bellard | |
445 | 2c0262af | bellard | cpu_lock(); |
446 | 2c0262af | bellard | tmp = ldub((void *)T1);
|
447 | 2c0262af | bellard | stb((void *)T1, T0);
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448 | 2c0262af | bellard | T0 = tmp; |
449 | 2c0262af | bellard | cpu_unlock(); |
450 | 2c0262af | bellard | } |
451 | 2c0262af | bellard | |
452 | 2c0262af | bellard | void OPPROTO op_swpl_T0_T1(void) |
453 | 2c0262af | bellard | { |
454 | 2c0262af | bellard | int tmp;
|
455 | 2c0262af | bellard | |
456 | 2c0262af | bellard | cpu_lock(); |
457 | 2c0262af | bellard | tmp = ldl((void *)T1);
|
458 | 2c0262af | bellard | stl((void *)T1, T0);
|
459 | 2c0262af | bellard | T0 = tmp; |
460 | 2c0262af | bellard | cpu_unlock(); |
461 | 2c0262af | bellard | } |
462 | 2c0262af | bellard | |
463 | 2c0262af | bellard | /* shifts */
|
464 | 2c0262af | bellard | |
465 | 2c0262af | bellard | /* T1 based */
|
466 | 1e8d4eec | bellard | |
467 | 2c0262af | bellard | void OPPROTO op_shll_T1_im(void) |
468 | 2c0262af | bellard | { |
469 | 2c0262af | bellard | T1 = T1 << PARAM1; |
470 | 2c0262af | bellard | } |
471 | 2c0262af | bellard | |
472 | 2c0262af | bellard | void OPPROTO op_shrl_T1_im(void) |
473 | 2c0262af | bellard | { |
474 | 2c0262af | bellard | T1 = (uint32_t)T1 >> PARAM1; |
475 | 2c0262af | bellard | } |
476 | 2c0262af | bellard | |
477 | 1e8d4eec | bellard | void OPPROTO op_shrl_T1_0(void) |
478 | 1e8d4eec | bellard | { |
479 | 1e8d4eec | bellard | T1 = 0;
|
480 | 1e8d4eec | bellard | } |
481 | 1e8d4eec | bellard | |
482 | 2c0262af | bellard | void OPPROTO op_sarl_T1_im(void) |
483 | 2c0262af | bellard | { |
484 | 2c0262af | bellard | T1 = (int32_t)T1 >> PARAM1; |
485 | 2c0262af | bellard | } |
486 | 2c0262af | bellard | |
487 | 1e8d4eec | bellard | void OPPROTO op_sarl_T1_0(void) |
488 | 1e8d4eec | bellard | { |
489 | 1e8d4eec | bellard | T1 = (int32_t)T1 >> 31;
|
490 | 1e8d4eec | bellard | } |
491 | 1e8d4eec | bellard | |
492 | 2c0262af | bellard | void OPPROTO op_rorl_T1_im(void) |
493 | 2c0262af | bellard | { |
494 | 2c0262af | bellard | int shift;
|
495 | 2c0262af | bellard | shift = PARAM1; |
496 | 2c0262af | bellard | T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
497 | 2c0262af | bellard | } |
498 | 2c0262af | bellard | |
499 | 88920f34 | bellard | void OPPROTO op_rrxl_T1(void) |
500 | 88920f34 | bellard | { |
501 | 88920f34 | bellard | T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31); |
502 | 88920f34 | bellard | } |
503 | 88920f34 | bellard | |
504 | 2c0262af | bellard | /* T1 based, set C flag */
|
505 | 2c0262af | bellard | void OPPROTO op_shll_T1_im_cc(void) |
506 | 2c0262af | bellard | { |
507 | 2c0262af | bellard | env->CF = (T1 >> (32 - PARAM1)) & 1; |
508 | 2c0262af | bellard | T1 = T1 << PARAM1; |
509 | 2c0262af | bellard | } |
510 | 2c0262af | bellard | |
511 | 2c0262af | bellard | void OPPROTO op_shrl_T1_im_cc(void) |
512 | 2c0262af | bellard | { |
513 | 2c0262af | bellard | env->CF = (T1 >> (PARAM1 - 1)) & 1; |
514 | 2c0262af | bellard | T1 = (uint32_t)T1 >> PARAM1; |
515 | 2c0262af | bellard | } |
516 | 2c0262af | bellard | |
517 | 1e8d4eec | bellard | void OPPROTO op_shrl_T1_0_cc(void) |
518 | 1e8d4eec | bellard | { |
519 | 1e8d4eec | bellard | env->CF = (T1 >> 31) & 1; |
520 | 1e8d4eec | bellard | T1 = 0;
|
521 | 1e8d4eec | bellard | } |
522 | 1e8d4eec | bellard | |
523 | 2c0262af | bellard | void OPPROTO op_sarl_T1_im_cc(void) |
524 | 2c0262af | bellard | { |
525 | 2c0262af | bellard | env->CF = (T1 >> (PARAM1 - 1)) & 1; |
526 | 2c0262af | bellard | T1 = (int32_t)T1 >> PARAM1; |
527 | 2c0262af | bellard | } |
528 | 2c0262af | bellard | |
529 | 1e8d4eec | bellard | void OPPROTO op_sarl_T1_0_cc(void) |
530 | 1e8d4eec | bellard | { |
531 | 1e8d4eec | bellard | env->CF = (T1 >> 31) & 1; |
532 | 1e8d4eec | bellard | T1 = (int32_t)T1 >> 31;
|
533 | 1e8d4eec | bellard | } |
534 | 1e8d4eec | bellard | |
535 | 2c0262af | bellard | void OPPROTO op_rorl_T1_im_cc(void) |
536 | 2c0262af | bellard | { |
537 | 2c0262af | bellard | int shift;
|
538 | 2c0262af | bellard | shift = PARAM1; |
539 | 2c0262af | bellard | env->CF = (T1 >> (shift - 1)) & 1; |
540 | 2c0262af | bellard | T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
541 | 2c0262af | bellard | } |
542 | 2c0262af | bellard | |
543 | 88920f34 | bellard | void OPPROTO op_rrxl_T1_cc(void) |
544 | 88920f34 | bellard | { |
545 | 88920f34 | bellard | uint32_t c; |
546 | 88920f34 | bellard | c = T1 & 1;
|
547 | 88920f34 | bellard | T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31); |
548 | 88920f34 | bellard | env->CF = c; |
549 | 88920f34 | bellard | } |
550 | 88920f34 | bellard | |
551 | 2c0262af | bellard | /* T2 based */
|
552 | 2c0262af | bellard | void OPPROTO op_shll_T2_im(void) |
553 | 2c0262af | bellard | { |
554 | 2c0262af | bellard | T2 = T2 << PARAM1; |
555 | 2c0262af | bellard | } |
556 | 2c0262af | bellard | |
557 | 2c0262af | bellard | void OPPROTO op_shrl_T2_im(void) |
558 | 2c0262af | bellard | { |
559 | 2c0262af | bellard | T2 = (uint32_t)T2 >> PARAM1; |
560 | 2c0262af | bellard | } |
561 | 2c0262af | bellard | |
562 | 1e8d4eec | bellard | void OPPROTO op_shrl_T2_0(void) |
563 | 1e8d4eec | bellard | { |
564 | 1e8d4eec | bellard | T2 = 0;
|
565 | 1e8d4eec | bellard | } |
566 | 1e8d4eec | bellard | |
567 | 2c0262af | bellard | void OPPROTO op_sarl_T2_im(void) |
568 | 2c0262af | bellard | { |
569 | 2c0262af | bellard | T2 = (int32_t)T2 >> PARAM1; |
570 | 2c0262af | bellard | } |
571 | 2c0262af | bellard | |
572 | 1e8d4eec | bellard | void OPPROTO op_sarl_T2_0(void) |
573 | 1e8d4eec | bellard | { |
574 | 1e8d4eec | bellard | T2 = (int32_t)T2 >> 31;
|
575 | 1e8d4eec | bellard | } |
576 | 1e8d4eec | bellard | |
577 | 2c0262af | bellard | void OPPROTO op_rorl_T2_im(void) |
578 | 2c0262af | bellard | { |
579 | 2c0262af | bellard | int shift;
|
580 | 2c0262af | bellard | shift = PARAM1; |
581 | 2c0262af | bellard | T2 = ((uint32_t)T2 >> shift) | (T2 << (32 - shift));
|
582 | 2c0262af | bellard | } |
583 | 2c0262af | bellard | |
584 | 1e8d4eec | bellard | void OPPROTO op_rrxl_T2(void) |
585 | 1e8d4eec | bellard | { |
586 | 1e8d4eec | bellard | T2 = ((uint32_t)T2 >> 1) | ((uint32_t)env->CF << 31); |
587 | 1e8d4eec | bellard | } |
588 | 1e8d4eec | bellard | |
589 | 2c0262af | bellard | /* T1 based, use T0 as shift count */
|
590 | 2c0262af | bellard | |
591 | 2c0262af | bellard | void OPPROTO op_shll_T1_T0(void) |
592 | 2c0262af | bellard | { |
593 | 2c0262af | bellard | int shift;
|
594 | 2c0262af | bellard | shift = T0 & 0xff;
|
595 | 2c0262af | bellard | if (shift >= 32) |
596 | 2c0262af | bellard | T1 = 0;
|
597 | 2c0262af | bellard | else
|
598 | 2c0262af | bellard | T1 = T1 << shift; |
599 | 2c0262af | bellard | FORCE_RET(); |
600 | 2c0262af | bellard | } |
601 | 2c0262af | bellard | |
602 | 2c0262af | bellard | void OPPROTO op_shrl_T1_T0(void) |
603 | 2c0262af | bellard | { |
604 | 2c0262af | bellard | int shift;
|
605 | 2c0262af | bellard | shift = T0 & 0xff;
|
606 | 2c0262af | bellard | if (shift >= 32) |
607 | 2c0262af | bellard | T1 = 0;
|
608 | 2c0262af | bellard | else
|
609 | 2c0262af | bellard | T1 = (uint32_t)T1 >> shift; |
610 | 2c0262af | bellard | FORCE_RET(); |
611 | 2c0262af | bellard | } |
612 | 2c0262af | bellard | |
613 | 2c0262af | bellard | void OPPROTO op_sarl_T1_T0(void) |
614 | 2c0262af | bellard | { |
615 | 2c0262af | bellard | int shift;
|
616 | 2c0262af | bellard | shift = T0 & 0xff;
|
617 | 2c0262af | bellard | if (shift >= 32) |
618 | 2c0262af | bellard | shift = 31;
|
619 | 2c0262af | bellard | T1 = (int32_t)T1 >> shift; |
620 | 2c0262af | bellard | } |
621 | 2c0262af | bellard | |
622 | 2c0262af | bellard | void OPPROTO op_rorl_T1_T0(void) |
623 | 2c0262af | bellard | { |
624 | 2c0262af | bellard | int shift;
|
625 | 2c0262af | bellard | shift = T0 & 0x1f;
|
626 | 2c0262af | bellard | if (shift) {
|
627 | 2c0262af | bellard | T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
628 | 2c0262af | bellard | } |
629 | 2c0262af | bellard | FORCE_RET(); |
630 | 2c0262af | bellard | } |
631 | 2c0262af | bellard | |
632 | 2c0262af | bellard | /* T1 based, use T0 as shift count and compute CF */
|
633 | 2c0262af | bellard | |
634 | 2c0262af | bellard | void OPPROTO op_shll_T1_T0_cc(void) |
635 | 2c0262af | bellard | { |
636 | 2c0262af | bellard | int shift;
|
637 | 2c0262af | bellard | shift = T0 & 0xff;
|
638 | 2c0262af | bellard | if (shift >= 32) { |
639 | 2c0262af | bellard | if (shift == 32) |
640 | 2c0262af | bellard | env->CF = T1 & 1;
|
641 | 2c0262af | bellard | else
|
642 | 2c0262af | bellard | env->CF = 0;
|
643 | 2c0262af | bellard | T1 = 0;
|
644 | 2c0262af | bellard | } else if (shift != 0) { |
645 | 2c0262af | bellard | env->CF = (T1 >> (32 - shift)) & 1; |
646 | 2c0262af | bellard | T1 = T1 << shift; |
647 | 2c0262af | bellard | } |
648 | 2c0262af | bellard | FORCE_RET(); |
649 | 2c0262af | bellard | } |
650 | 2c0262af | bellard | |
651 | 2c0262af | bellard | void OPPROTO op_shrl_T1_T0_cc(void) |
652 | 2c0262af | bellard | { |
653 | 2c0262af | bellard | int shift;
|
654 | 2c0262af | bellard | shift = T0 & 0xff;
|
655 | 2c0262af | bellard | if (shift >= 32) { |
656 | 2c0262af | bellard | if (shift == 32) |
657 | 2c0262af | bellard | env->CF = (T1 >> 31) & 1; |
658 | 2c0262af | bellard | else
|
659 | 2c0262af | bellard | env->CF = 0;
|
660 | 2c0262af | bellard | T1 = 0;
|
661 | 2c0262af | bellard | } else if (shift != 0) { |
662 | 2c0262af | bellard | env->CF = (T1 >> (shift - 1)) & 1; |
663 | 2c0262af | bellard | T1 = (uint32_t)T1 >> shift; |
664 | 2c0262af | bellard | } |
665 | 2c0262af | bellard | FORCE_RET(); |
666 | 2c0262af | bellard | } |
667 | 2c0262af | bellard | |
668 | 2c0262af | bellard | void OPPROTO op_sarl_T1_T0_cc(void) |
669 | 2c0262af | bellard | { |
670 | 2c0262af | bellard | int shift;
|
671 | 2c0262af | bellard | shift = T0 & 0xff;
|
672 | 2c0262af | bellard | if (shift >= 32) { |
673 | 2c0262af | bellard | env->CF = (T1 >> 31) & 1; |
674 | 2c0262af | bellard | T1 = (int32_t)T1 >> 31;
|
675 | 2c0262af | bellard | } else {
|
676 | 2c0262af | bellard | env->CF = (T1 >> (shift - 1)) & 1; |
677 | 2c0262af | bellard | T1 = (int32_t)T1 >> shift; |
678 | 2c0262af | bellard | } |
679 | 2c0262af | bellard | FORCE_RET(); |
680 | 2c0262af | bellard | } |
681 | 2c0262af | bellard | |
682 | 2c0262af | bellard | void OPPROTO op_rorl_T1_T0_cc(void) |
683 | 2c0262af | bellard | { |
684 | 2c0262af | bellard | int shift1, shift;
|
685 | 2c0262af | bellard | shift1 = T0 & 0xff;
|
686 | 2c0262af | bellard | shift = shift1 & 0x1f;
|
687 | 2c0262af | bellard | if (shift == 0) { |
688 | 2c0262af | bellard | if (shift1 != 0) |
689 | 2c0262af | bellard | env->CF = (T1 >> 31) & 1; |
690 | 2c0262af | bellard | } else {
|
691 | 2c0262af | bellard | env->CF = (T1 >> (shift - 1)) & 1; |
692 | 2c0262af | bellard | T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
693 | 2c0262af | bellard | } |
694 | 2c0262af | bellard | FORCE_RET(); |
695 | 2c0262af | bellard | } |
696 | 2c0262af | bellard | |
697 | 2c0262af | bellard | /* exceptions */
|
698 | 2c0262af | bellard | |
699 | 2c0262af | bellard | void OPPROTO op_swi(void) |
700 | 2c0262af | bellard | { |
701 | 2c0262af | bellard | env->exception_index = EXCP_SWI; |
702 | 2c0262af | bellard | cpu_loop_exit(); |
703 | 2c0262af | bellard | } |
704 | 2c0262af | bellard | |
705 | 2c0262af | bellard | void OPPROTO op_undef_insn(void) |
706 | 2c0262af | bellard | { |
707 | 2c0262af | bellard | env->exception_index = EXCP_UDEF; |
708 | 2c0262af | bellard | cpu_loop_exit(); |
709 | 2c0262af | bellard | } |
710 | 2c0262af | bellard | |
711 | 2c0262af | bellard | /* thread support */
|
712 | 2c0262af | bellard | |
713 | 2c0262af | bellard | spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
714 | 2c0262af | bellard | |
715 | 2c0262af | bellard | void cpu_lock(void) |
716 | 2c0262af | bellard | { |
717 | 2c0262af | bellard | spin_lock(&global_cpu_lock); |
718 | 2c0262af | bellard | } |
719 | 2c0262af | bellard | |
720 | 2c0262af | bellard | void cpu_unlock(void) |
721 | 2c0262af | bellard | { |
722 | 2c0262af | bellard | spin_unlock(&global_cpu_lock); |
723 | 2c0262af | bellard | } |