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/*
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* ARM micro operations
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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#define REGNAME r0
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#define REG (env->regs[0]) |
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#include "op_template.h" |
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#define REGNAME r1
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#define REG (env->regs[1]) |
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#include "op_template.h" |
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#define REGNAME r2
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#define REG (env->regs[2]) |
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#include "op_template.h" |
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#define REGNAME r3
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#define REG (env->regs[3]) |
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#include "op_template.h" |
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|
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#define REGNAME r4
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#define REG (env->regs[4]) |
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#include "op_template.h" |
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#define REGNAME r5
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#define REG (env->regs[5]) |
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#include "op_template.h" |
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#define REGNAME r6
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#define REG (env->regs[6]) |
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#include "op_template.h" |
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#define REGNAME r7
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#define REG (env->regs[7]) |
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#include "op_template.h" |
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#define REGNAME r8
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#define REG (env->regs[8]) |
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#include "op_template.h" |
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#define REGNAME r9
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#define REG (env->regs[9]) |
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#include "op_template.h" |
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#define REGNAME r10
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#define REG (env->regs[10]) |
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#include "op_template.h" |
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#define REGNAME r11
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#define REG (env->regs[11]) |
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#include "op_template.h" |
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#define REGNAME r12
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#define REG (env->regs[12]) |
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#include "op_template.h" |
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#define REGNAME r13
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#define REG (env->regs[13]) |
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#include "op_template.h" |
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#define REGNAME r14
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#define REG (env->regs[14]) |
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#include "op_template.h" |
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#define REGNAME r15
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#define REG (env->regs[15]) |
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#include "op_template.h" |
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|
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void OPPROTO op_movl_T0_0(void) |
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{
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T0 = 0;
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} |
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void OPPROTO op_movl_T0_im(void) |
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{
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T0 = PARAM1; |
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} |
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void OPPROTO op_movl_T1_im(void) |
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{
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T1 = PARAM1; |
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} |
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void OPPROTO op_movl_T2_im(void) |
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{
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T2 = PARAM1; |
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} |
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void OPPROTO op_addl_T1_im(void) |
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{
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T1 += PARAM1; |
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} |
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void OPPROTO op_addl_T1_T2(void) |
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{
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T1 += T2; |
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} |
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void OPPROTO op_subl_T1_T2(void) |
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{
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T1 -= T2; |
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} |
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void OPPROTO op_addl_T0_T1(void) |
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{
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T0 += T1; |
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} |
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void OPPROTO op_addl_T0_T1_cc(void) |
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{
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unsigned int src1; |
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src1 = T0; |
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T0 += T1; |
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env->NZF = T0; |
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env->CF = T0 < src1; |
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env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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} |
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void OPPROTO op_adcl_T0_T1(void) |
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{
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T0 += T1 + env->CF; |
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} |
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void OPPROTO op_adcl_T0_T1_cc(void) |
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{
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unsigned int src1; |
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src1 = T0; |
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if (!env->CF) {
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T0 += T1; |
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env->CF = T0 < src1; |
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} else {
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T0 += T1 + 1;
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env->CF = T0 <= src1; |
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} |
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env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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env->NZF = T0; |
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FORCE_RET(); |
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} |
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#define OPSUB(sub, sbc, res, T0, T1) \
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\ |
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void OPPROTO op_ ## sub ## l_T0_T1(void) \ |
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{ \
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res = T0 - T1; \ |
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} \ |
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\ |
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void OPPROTO op_ ## sub ## l_T0_T1_cc(void) \ |
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{ \
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unsigned int src1; \ |
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src1 = T0; \ |
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T0 -= T1; \ |
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env->NZF = T0; \ |
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env->CF = src1 >= T1; \ |
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env->VF = (src1 ^ T1) & (src1 ^ T0); \ |
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res = T0; \ |
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} \ |
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\ |
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void OPPROTO op_ ## sbc ## l_T0_T1(void) \ |
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{ \
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res = T0 - T1 + env->CF - 1; \
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} \ |
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\ |
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void OPPROTO op_ ## sbc ## l_T0_T1_cc(void) \ |
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{ \
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unsigned int src1; \ |
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src1 = T0; \ |
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if (!env->CF) { \
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T0 = T0 - T1 - 1; \
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env->CF = src1 >= T1; \ |
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} else { \
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T0 = T0 - T1; \ |
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env->CF = src1 > T1; \ |
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} \ |
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env->VF = (src1 ^ T1) & (src1 ^ T0); \ |
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env->NZF = T0; \ |
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res = T0; \ |
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FORCE_RET(); \ |
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} |
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OPSUB(sub, sbc, T0, T0, T1) |
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OPSUB(rsb, rsc, T0, T1, T0) |
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void OPPROTO op_andl_T0_T1(void) |
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{
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T0 &= T1; |
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} |
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void OPPROTO op_xorl_T0_T1(void) |
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{
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T0 ^= T1; |
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} |
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void OPPROTO op_orl_T0_T1(void) |
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{
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T0 |= T1; |
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} |
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void OPPROTO op_bicl_T0_T1(void) |
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{
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T0 &= ~T1; |
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} |
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void OPPROTO op_notl_T1(void) |
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{
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T1 = ~T1; |
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} |
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void OPPROTO op_logic_T0_cc(void) |
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{
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env->NZF = T0; |
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} |
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void OPPROTO op_logic_T1_cc(void) |
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{
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env->NZF = T1; |
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} |
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#define EIP (env->regs[15]) |
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void OPPROTO op_test_eq(void) |
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{
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if (env->NZF == 0) |
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JUMP_TB(op_test_eq, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_ne(void) |
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{
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if (env->NZF != 0) |
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JUMP_TB(op_test_ne, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_cs(void) |
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{
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if (env->CF != 0) |
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JUMP_TB(op_test_cs, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_cc(void) |
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{
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if (env->CF == 0) |
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JUMP_TB(op_test_cc, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_mi(void) |
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{
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if ((env->NZF & 0x80000000) != 0) |
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JUMP_TB(op_test_mi, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_pl(void) |
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{
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if ((env->NZF & 0x80000000) == 0) |
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JUMP_TB(op_test_pl, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_vs(void) |
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{
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if ((env->VF & 0x80000000) != 0) |
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JUMP_TB(op_test_vs, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_vc(void) |
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{
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if ((env->VF & 0x80000000) == 0) |
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JUMP_TB(op_test_vc, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_hi(void) |
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{
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if (env->CF != 0 && env->NZF != 0) |
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JUMP_TB(op_test_hi, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_ls(void) |
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{
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if (env->CF == 0 || env->NZF == 0) |
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JUMP_TB(op_test_ls, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_ge(void) |
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{
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if (((env->VF ^ env->NZF) & 0x80000000) == 0) |
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JUMP_TB(op_test_ge, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_lt(void) |
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{
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if (((env->VF ^ env->NZF) & 0x80000000) != 0) |
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JUMP_TB(op_test_lt, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_gt(void) |
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{
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if (env->NZF != 0 && ((env->VF ^ env->NZF) & 0x80000000) == 0) |
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JUMP_TB(op_test_gt, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_test_le(void) |
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{
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if (env->NZF == 0 || ((env->VF ^ env->NZF) & 0x80000000) != 0) |
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JUMP_TB(op_test_le, PARAM1, 0, PARAM2);
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FORCE_RET(); |
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} |
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void OPPROTO op_jmp(void) |
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{
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JUMP_TB(op_jmp, PARAM1, 1, PARAM2);
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} |
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|
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void OPPROTO op_exit_tb(void) |
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{
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EXIT_TB(); |
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} |
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|
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void OPPROTO op_movl_T0_psr(void) |
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{
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T0 = compute_cpsr(); |
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} |
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/* NOTE: N = 1 and Z = 1 cannot be stored currently */
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void OPPROTO op_movl_psr_T0(void) |
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{
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unsigned int psr; |
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psr = T0; |
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env->CF = (psr >> 29) & 1; |
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env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
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env->VF = (psr << 3) & 0x80000000; |
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/* for user mode we do not update other state info */
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} |
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|
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void OPPROTO op_mul_T0_T1(void) |
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{
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T0 = T0 * T1; |
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} |
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/* 64 bit unsigned mul */
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void OPPROTO op_mull_T0_T1(void) |
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{
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uint64_t res; |
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res = (uint64_t)T0 * (uint64_t)T1; |
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T1 = res >> 32;
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T0 = res; |
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} |
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/* 64 bit signed mul */
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void OPPROTO op_imull_T0_T1(void) |
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{
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uint64_t res; |
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res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1); |
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T1 = res >> 32;
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T0 = res; |
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} |
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void OPPROTO op_addq_T0_T1(void) |
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{
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uint64_t res; |
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res = ((uint64_t)T1 << 32) | T0;
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res += ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
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T1 = res >> 32;
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T0 = res; |
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} |
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void OPPROTO op_logicq_cc(void) |
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{
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env->NZF = (T1 & 0x80000000) | ((T0 | T1) != 0); |
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} |
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|
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/* memory access */
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|
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void OPPROTO op_ldub_T0_T1(void) |
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{
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T0 = ldub((void *)T1);
|
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} |
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|
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void OPPROTO op_ldsb_T0_T1(void) |
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{
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T0 = ldsb((void *)T1);
|
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} |
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|
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void OPPROTO op_lduw_T0_T1(void) |
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{
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T0 = lduw((void *)T1);
|
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} |
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|
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void OPPROTO op_ldsw_T0_T1(void) |
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{
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T0 = ldsw((void *)T1);
|
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} |
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|
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void OPPROTO op_ldl_T0_T1(void) |
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{
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T0 = ldl((void *)T1);
|
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} |
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|
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void OPPROTO op_stb_T0_T1(void) |
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{
|
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stb((void *)T1, T0);
|
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} |
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|
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void OPPROTO op_stw_T0_T1(void) |
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{
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stw((void *)T1, T0);
|
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} |
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|
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void OPPROTO op_stl_T0_T1(void) |
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{
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stl((void *)T1, T0);
|
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} |
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|
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void OPPROTO op_swpb_T0_T1(void) |
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{
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int tmp;
|
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|
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cpu_lock(); |
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tmp = ldub((void *)T1);
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stb((void *)T1, T0);
|
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T0 = tmp; |
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cpu_unlock(); |
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} |
| 451 |
|
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void OPPROTO op_swpl_T0_T1(void) |
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{
|
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int tmp;
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|
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cpu_lock(); |
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tmp = ldl((void *)T1);
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stl((void *)T1, T0);
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T0 = tmp; |
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cpu_unlock(); |
| 461 |
} |
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|
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/* shifts */
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|
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/* T1 based */
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|
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void OPPROTO op_shll_T1_im(void) |
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{
|
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T1 = T1 << PARAM1; |
| 470 |
} |
| 471 |
|
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void OPPROTO op_shrl_T1_im(void) |
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{
|
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T1 = (uint32_t)T1 >> PARAM1; |
| 475 |
} |
| 476 |
|
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void OPPROTO op_shrl_T1_0(void) |
| 478 |
{
|
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T1 = 0;
|
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} |
| 481 |
|
| 482 |
void OPPROTO op_sarl_T1_im(void) |
| 483 |
{
|
| 484 |
T1 = (int32_t)T1 >> PARAM1; |
| 485 |
} |
| 486 |
|
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void OPPROTO op_sarl_T1_0(void) |
| 488 |
{
|
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T1 = (int32_t)T1 >> 31;
|
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} |
| 491 |
|
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void OPPROTO op_rorl_T1_im(void) |
| 493 |
{
|
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int shift;
|
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shift = PARAM1; |
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T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
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} |
| 498 |
|
| 499 |
void OPPROTO op_rrxl_T1(void) |
| 500 |
{
|
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T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31); |
| 502 |
} |
| 503 |
|
| 504 |
/* T1 based, set C flag */
|
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void OPPROTO op_shll_T1_im_cc(void) |
| 506 |
{
|
| 507 |
env->CF = (T1 >> (32 - PARAM1)) & 1; |
| 508 |
T1 = T1 << PARAM1; |
| 509 |
} |
| 510 |
|
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void OPPROTO op_shrl_T1_im_cc(void) |
| 512 |
{
|
| 513 |
env->CF = (T1 >> (PARAM1 - 1)) & 1; |
| 514 |
T1 = (uint32_t)T1 >> PARAM1; |
| 515 |
} |
| 516 |
|
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void OPPROTO op_shrl_T1_0_cc(void) |
| 518 |
{
|
| 519 |
env->CF = (T1 >> 31) & 1; |
| 520 |
T1 = 0;
|
| 521 |
} |
| 522 |
|
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void OPPROTO op_sarl_T1_im_cc(void) |
| 524 |
{
|
| 525 |
env->CF = (T1 >> (PARAM1 - 1)) & 1; |
| 526 |
T1 = (int32_t)T1 >> PARAM1; |
| 527 |
} |
| 528 |
|
| 529 |
void OPPROTO op_sarl_T1_0_cc(void) |
| 530 |
{
|
| 531 |
env->CF = (T1 >> 31) & 1; |
| 532 |
T1 = (int32_t)T1 >> 31;
|
| 533 |
} |
| 534 |
|
| 535 |
void OPPROTO op_rorl_T1_im_cc(void) |
| 536 |
{
|
| 537 |
int shift;
|
| 538 |
shift = PARAM1; |
| 539 |
env->CF = (T1 >> (shift - 1)) & 1; |
| 540 |
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
| 541 |
} |
| 542 |
|
| 543 |
void OPPROTO op_rrxl_T1_cc(void) |
| 544 |
{
|
| 545 |
uint32_t c; |
| 546 |
c = T1 & 1;
|
| 547 |
T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31); |
| 548 |
env->CF = c; |
| 549 |
} |
| 550 |
|
| 551 |
/* T2 based */
|
| 552 |
void OPPROTO op_shll_T2_im(void) |
| 553 |
{
|
| 554 |
T2 = T2 << PARAM1; |
| 555 |
} |
| 556 |
|
| 557 |
void OPPROTO op_shrl_T2_im(void) |
| 558 |
{
|
| 559 |
T2 = (uint32_t)T2 >> PARAM1; |
| 560 |
} |
| 561 |
|
| 562 |
void OPPROTO op_shrl_T2_0(void) |
| 563 |
{
|
| 564 |
T2 = 0;
|
| 565 |
} |
| 566 |
|
| 567 |
void OPPROTO op_sarl_T2_im(void) |
| 568 |
{
|
| 569 |
T2 = (int32_t)T2 >> PARAM1; |
| 570 |
} |
| 571 |
|
| 572 |
void OPPROTO op_sarl_T2_0(void) |
| 573 |
{
|
| 574 |
T2 = (int32_t)T2 >> 31;
|
| 575 |
} |
| 576 |
|
| 577 |
void OPPROTO op_rorl_T2_im(void) |
| 578 |
{
|
| 579 |
int shift;
|
| 580 |
shift = PARAM1; |
| 581 |
T2 = ((uint32_t)T2 >> shift) | (T2 << (32 - shift));
|
| 582 |
} |
| 583 |
|
| 584 |
void OPPROTO op_rrxl_T2(void) |
| 585 |
{
|
| 586 |
T2 = ((uint32_t)T2 >> 1) | ((uint32_t)env->CF << 31); |
| 587 |
} |
| 588 |
|
| 589 |
/* T1 based, use T0 as shift count */
|
| 590 |
|
| 591 |
void OPPROTO op_shll_T1_T0(void) |
| 592 |
{
|
| 593 |
int shift;
|
| 594 |
shift = T0 & 0xff;
|
| 595 |
if (shift >= 32) |
| 596 |
T1 = 0;
|
| 597 |
else
|
| 598 |
T1 = T1 << shift; |
| 599 |
FORCE_RET(); |
| 600 |
} |
| 601 |
|
| 602 |
void OPPROTO op_shrl_T1_T0(void) |
| 603 |
{
|
| 604 |
int shift;
|
| 605 |
shift = T0 & 0xff;
|
| 606 |
if (shift >= 32) |
| 607 |
T1 = 0;
|
| 608 |
else
|
| 609 |
T1 = (uint32_t)T1 >> shift; |
| 610 |
FORCE_RET(); |
| 611 |
} |
| 612 |
|
| 613 |
void OPPROTO op_sarl_T1_T0(void) |
| 614 |
{
|
| 615 |
int shift;
|
| 616 |
shift = T0 & 0xff;
|
| 617 |
if (shift >= 32) |
| 618 |
shift = 31;
|
| 619 |
T1 = (int32_t)T1 >> shift; |
| 620 |
} |
| 621 |
|
| 622 |
void OPPROTO op_rorl_T1_T0(void) |
| 623 |
{
|
| 624 |
int shift;
|
| 625 |
shift = T0 & 0x1f;
|
| 626 |
if (shift) {
|
| 627 |
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
| 628 |
} |
| 629 |
FORCE_RET(); |
| 630 |
} |
| 631 |
|
| 632 |
/* T1 based, use T0 as shift count and compute CF */
|
| 633 |
|
| 634 |
void OPPROTO op_shll_T1_T0_cc(void) |
| 635 |
{
|
| 636 |
int shift;
|
| 637 |
shift = T0 & 0xff;
|
| 638 |
if (shift >= 32) { |
| 639 |
if (shift == 32) |
| 640 |
env->CF = T1 & 1;
|
| 641 |
else
|
| 642 |
env->CF = 0;
|
| 643 |
T1 = 0;
|
| 644 |
} else if (shift != 0) { |
| 645 |
env->CF = (T1 >> (32 - shift)) & 1; |
| 646 |
T1 = T1 << shift; |
| 647 |
} |
| 648 |
FORCE_RET(); |
| 649 |
} |
| 650 |
|
| 651 |
void OPPROTO op_shrl_T1_T0_cc(void) |
| 652 |
{
|
| 653 |
int shift;
|
| 654 |
shift = T0 & 0xff;
|
| 655 |
if (shift >= 32) { |
| 656 |
if (shift == 32) |
| 657 |
env->CF = (T1 >> 31) & 1; |
| 658 |
else
|
| 659 |
env->CF = 0;
|
| 660 |
T1 = 0;
|
| 661 |
} else if (shift != 0) { |
| 662 |
env->CF = (T1 >> (shift - 1)) & 1; |
| 663 |
T1 = (uint32_t)T1 >> shift; |
| 664 |
} |
| 665 |
FORCE_RET(); |
| 666 |
} |
| 667 |
|
| 668 |
void OPPROTO op_sarl_T1_T0_cc(void) |
| 669 |
{
|
| 670 |
int shift;
|
| 671 |
shift = T0 & 0xff;
|
| 672 |
if (shift >= 32) { |
| 673 |
env->CF = (T1 >> 31) & 1; |
| 674 |
T1 = (int32_t)T1 >> 31;
|
| 675 |
} else {
|
| 676 |
env->CF = (T1 >> (shift - 1)) & 1; |
| 677 |
T1 = (int32_t)T1 >> shift; |
| 678 |
} |
| 679 |
FORCE_RET(); |
| 680 |
} |
| 681 |
|
| 682 |
void OPPROTO op_rorl_T1_T0_cc(void) |
| 683 |
{
|
| 684 |
int shift1, shift;
|
| 685 |
shift1 = T0 & 0xff;
|
| 686 |
shift = shift1 & 0x1f;
|
| 687 |
if (shift == 0) { |
| 688 |
if (shift1 != 0) |
| 689 |
env->CF = (T1 >> 31) & 1; |
| 690 |
} else {
|
| 691 |
env->CF = (T1 >> (shift - 1)) & 1; |
| 692 |
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
| 693 |
} |
| 694 |
FORCE_RET(); |
| 695 |
} |
| 696 |
|
| 697 |
/* exceptions */
|
| 698 |
|
| 699 |
void OPPROTO op_swi(void) |
| 700 |
{
|
| 701 |
env->exception_index = EXCP_SWI; |
| 702 |
cpu_loop_exit(); |
| 703 |
} |
| 704 |
|
| 705 |
void OPPROTO op_undef_insn(void) |
| 706 |
{
|
| 707 |
env->exception_index = EXCP_UDEF; |
| 708 |
cpu_loop_exit(); |
| 709 |
} |
| 710 |
|
| 711 |
/* thread support */
|
| 712 |
|
| 713 |
spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
| 714 |
|
| 715 |
void cpu_lock(void) |
| 716 |
{
|
| 717 |
spin_lock(&global_cpu_lock); |
| 718 |
} |
| 719 |
|
| 720 |
void cpu_unlock(void) |
| 721 |
{
|
| 722 |
spin_unlock(&global_cpu_lock); |
| 723 |
} |
| 724 |
|