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1 | a541f297 | bellard | /*
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2 | e9df014c | j_mayer | * QEMU generic PowerPC hardware System Emulator
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "ppc.h" |
26 | 87ecb68b | pbrook | #include "qemu-timer.h" |
27 | 87ecb68b | pbrook | #include "sysemu.h" |
28 | 87ecb68b | pbrook | #include "nvram.h" |
29 | a541f297 | bellard | |
30 | e9df014c | j_mayer | //#define PPC_DEBUG_IRQ
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31 | 4b6d0a4c | j_mayer | //#define PPC_DEBUG_TB
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32 | e9df014c | j_mayer | |
33 | 47103572 | j_mayer | extern FILE *logfile;
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34 | 47103572 | j_mayer | extern int loglevel; |
35 | 47103572 | j_mayer | |
36 | dbdd2506 | j_mayer | static void cpu_ppc_tb_stop (CPUState *env); |
37 | dbdd2506 | j_mayer | static void cpu_ppc_tb_start (CPUState *env); |
38 | dbdd2506 | j_mayer | |
39 | 00af685f | j_mayer | static void ppc_set_irq (CPUState *env, int n_IRQ, int level) |
40 | 47103572 | j_mayer | { |
41 | 47103572 | j_mayer | if (level) {
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42 | 47103572 | j_mayer | env->pending_interrupts |= 1 << n_IRQ;
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43 | 47103572 | j_mayer | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
44 | 47103572 | j_mayer | } else {
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45 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << n_IRQ);
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46 | 47103572 | j_mayer | if (env->pending_interrupts == 0) |
47 | 47103572 | j_mayer | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
48 | 47103572 | j_mayer | } |
49 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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50 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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51 | aae9366a | j_mayer | fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08" PRIx32
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52 | aae9366a | j_mayer | "req %08x\n", __func__, env, n_IRQ, level,
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53 | a496775f | j_mayer | env->pending_interrupts, env->interrupt_request); |
54 | a496775f | j_mayer | } |
55 | 47103572 | j_mayer | #endif
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56 | 47103572 | j_mayer | } |
57 | 47103572 | j_mayer | |
58 | e9df014c | j_mayer | /* PowerPC 6xx / 7xx internal IRQ controller */
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59 | e9df014c | j_mayer | static void ppc6xx_set_irq (void *opaque, int pin, int level) |
60 | d537cf6c | pbrook | { |
61 | e9df014c | j_mayer | CPUState *env = opaque; |
62 | e9df014c | j_mayer | int cur_level;
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63 | d537cf6c | pbrook | |
64 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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65 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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66 | a496775f | j_mayer | fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
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67 | a496775f | j_mayer | env, pin, level); |
68 | a496775f | j_mayer | } |
69 | e9df014c | j_mayer | #endif
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70 | e9df014c | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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71 | e9df014c | j_mayer | /* Don't generate spurious events */
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72 | 24be5ae3 | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
73 | e9df014c | j_mayer | switch (pin) {
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74 | dbdd2506 | j_mayer | case PPC6xx_INPUT_TBEN:
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75 | dbdd2506 | j_mayer | /* Level sensitive - active high */
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76 | dbdd2506 | j_mayer | #if defined(PPC_DEBUG_IRQ)
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77 | dbdd2506 | j_mayer | if (loglevel & CPU_LOG_INT) {
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78 | dbdd2506 | j_mayer | fprintf(logfile, "%s: %s the time base\n",
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79 | dbdd2506 | j_mayer | __func__, level ? "start" : "stop"); |
80 | dbdd2506 | j_mayer | } |
81 | dbdd2506 | j_mayer | #endif
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82 | dbdd2506 | j_mayer | if (level) {
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83 | dbdd2506 | j_mayer | cpu_ppc_tb_start(env); |
84 | dbdd2506 | j_mayer | } else {
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85 | dbdd2506 | j_mayer | cpu_ppc_tb_stop(env); |
86 | dbdd2506 | j_mayer | } |
87 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_INT:
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88 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
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89 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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90 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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91 | a496775f | j_mayer | fprintf(logfile, "%s: set the external IRQ state to %d\n",
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92 | a496775f | j_mayer | __func__, level); |
93 | a496775f | j_mayer | } |
94 | e9df014c | j_mayer | #endif
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95 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
96 | e9df014c | j_mayer | break;
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97 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_SMI:
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98 | e9df014c | j_mayer | /* Level sensitive - active high */
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99 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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100 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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101 | a496775f | j_mayer | fprintf(logfile, "%s: set the SMI IRQ state to %d\n",
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102 | a496775f | j_mayer | __func__, level); |
103 | a496775f | j_mayer | } |
104 | e9df014c | j_mayer | #endif
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105 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_SMI, level); |
106 | e9df014c | j_mayer | break;
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107 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_MCP:
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108 | e9df014c | j_mayer | /* Negative edge sensitive */
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109 | e9df014c | j_mayer | /* XXX: TODO: actual reaction may depends on HID0 status
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110 | e9df014c | j_mayer | * 603/604/740/750: check HID0[EMCP]
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111 | e9df014c | j_mayer | */
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112 | e9df014c | j_mayer | if (cur_level == 1 && level == 0) { |
113 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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114 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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115 | a496775f | j_mayer | fprintf(logfile, "%s: raise machine check state\n",
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116 | a496775f | j_mayer | __func__); |
117 | a496775f | j_mayer | } |
118 | e9df014c | j_mayer | #endif
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119 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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120 | e9df014c | j_mayer | } |
121 | e9df014c | j_mayer | break;
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122 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_CKSTP_IN:
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123 | e9df014c | j_mayer | /* Level sensitive - active low */
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124 | e9df014c | j_mayer | /* XXX: TODO: relay the signal to CKSTP_OUT pin */
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125 | e63ecc6f | j_mayer | /* XXX: Note that the only way to restart the CPU is to reset it */
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126 | e9df014c | j_mayer | if (level) {
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127 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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128 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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129 | a496775f | j_mayer | fprintf(logfile, "%s: stop the CPU\n", __func__);
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130 | a496775f | j_mayer | } |
131 | e9df014c | j_mayer | #endif
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132 | e9df014c | j_mayer | env->halted = 1;
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133 | e9df014c | j_mayer | } |
134 | e9df014c | j_mayer | break;
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135 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_HRESET:
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136 | e9df014c | j_mayer | /* Level sensitive - active low */
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137 | e9df014c | j_mayer | if (level) {
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138 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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139 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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140 | a496775f | j_mayer | fprintf(logfile, "%s: reset the CPU\n", __func__);
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141 | a496775f | j_mayer | } |
142 | e9df014c | j_mayer | #endif
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143 | ef397e88 | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
144 | ef397e88 | j_mayer | /* XXX: TOFIX */
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145 | ef397e88 | j_mayer | #if 0
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146 | ef397e88 | j_mayer | cpu_ppc_reset(env);
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147 | ef397e88 | j_mayer | #else
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148 | ef397e88 | j_mayer | qemu_system_reset_request(); |
149 | e9df014c | j_mayer | #endif
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150 | e9df014c | j_mayer | } |
151 | e9df014c | j_mayer | break;
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152 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_SRESET:
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153 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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154 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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155 | a496775f | j_mayer | fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
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156 | a496775f | j_mayer | __func__, level); |
157 | a496775f | j_mayer | } |
158 | e9df014c | j_mayer | #endif
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159 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
160 | e9df014c | j_mayer | break;
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161 | e9df014c | j_mayer | default:
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162 | e9df014c | j_mayer | /* Unknown pin - do nothing */
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163 | e9df014c | j_mayer | #if defined(PPC_DEBUG_IRQ)
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164 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
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165 | a496775f | j_mayer | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
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166 | a496775f | j_mayer | } |
167 | e9df014c | j_mayer | #endif
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168 | e9df014c | j_mayer | return;
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169 | e9df014c | j_mayer | } |
170 | e9df014c | j_mayer | if (level)
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171 | e9df014c | j_mayer | env->irq_input_state |= 1 << pin;
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172 | e9df014c | j_mayer | else
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173 | e9df014c | j_mayer | env->irq_input_state &= ~(1 << pin);
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174 | d537cf6c | pbrook | } |
175 | d537cf6c | pbrook | } |
176 | d537cf6c | pbrook | |
177 | e9df014c | j_mayer | void ppc6xx_irq_init (CPUState *env)
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178 | 47103572 | j_mayer | { |
179 | 7b62a955 | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env,
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180 | 7b62a955 | j_mayer | PPC6xx_INPUT_NB); |
181 | 47103572 | j_mayer | } |
182 | 47103572 | j_mayer | |
183 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
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184 | d0dfae6e | j_mayer | /* PowerPC 970 internal IRQ controller */
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185 | d0dfae6e | j_mayer | static void ppc970_set_irq (void *opaque, int pin, int level) |
186 | d0dfae6e | j_mayer | { |
187 | d0dfae6e | j_mayer | CPUState *env = opaque; |
188 | d0dfae6e | j_mayer | int cur_level;
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189 | d0dfae6e | j_mayer | |
190 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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191 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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192 | d0dfae6e | j_mayer | fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
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193 | d0dfae6e | j_mayer | env, pin, level); |
194 | d0dfae6e | j_mayer | } |
195 | d0dfae6e | j_mayer | #endif
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196 | d0dfae6e | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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197 | d0dfae6e | j_mayer | /* Don't generate spurious events */
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198 | d0dfae6e | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
199 | d0dfae6e | j_mayer | switch (pin) {
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200 | d0dfae6e | j_mayer | case PPC970_INPUT_INT:
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201 | d0dfae6e | j_mayer | /* Level sensitive - active high */
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202 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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203 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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204 | d0dfae6e | j_mayer | fprintf(logfile, "%s: set the external IRQ state to %d\n",
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205 | d0dfae6e | j_mayer | __func__, level); |
206 | d0dfae6e | j_mayer | } |
207 | d0dfae6e | j_mayer | #endif
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208 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
209 | d0dfae6e | j_mayer | break;
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210 | d0dfae6e | j_mayer | case PPC970_INPUT_THINT:
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211 | d0dfae6e | j_mayer | /* Level sensitive - active high */
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212 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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213 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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214 | d0dfae6e | j_mayer | fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__,
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215 | d0dfae6e | j_mayer | level); |
216 | d0dfae6e | j_mayer | } |
217 | d0dfae6e | j_mayer | #endif
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218 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_THERM, level); |
219 | d0dfae6e | j_mayer | break;
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220 | d0dfae6e | j_mayer | case PPC970_INPUT_MCP:
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221 | d0dfae6e | j_mayer | /* Negative edge sensitive */
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222 | d0dfae6e | j_mayer | /* XXX: TODO: actual reaction may depends on HID0 status
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223 | d0dfae6e | j_mayer | * 603/604/740/750: check HID0[EMCP]
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224 | d0dfae6e | j_mayer | */
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225 | d0dfae6e | j_mayer | if (cur_level == 1 && level == 0) { |
226 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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227 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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228 | d0dfae6e | j_mayer | fprintf(logfile, "%s: raise machine check state\n",
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229 | d0dfae6e | j_mayer | __func__); |
230 | d0dfae6e | j_mayer | } |
231 | d0dfae6e | j_mayer | #endif
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232 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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233 | d0dfae6e | j_mayer | } |
234 | d0dfae6e | j_mayer | break;
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235 | d0dfae6e | j_mayer | case PPC970_INPUT_CKSTP:
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236 | d0dfae6e | j_mayer | /* Level sensitive - active low */
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237 | d0dfae6e | j_mayer | /* XXX: TODO: relay the signal to CKSTP_OUT pin */
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238 | d0dfae6e | j_mayer | if (level) {
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239 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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240 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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241 | d0dfae6e | j_mayer | fprintf(logfile, "%s: stop the CPU\n", __func__);
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242 | d0dfae6e | j_mayer | } |
243 | d0dfae6e | j_mayer | #endif
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244 | d0dfae6e | j_mayer | env->halted = 1;
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245 | d0dfae6e | j_mayer | } else {
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246 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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247 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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248 | d0dfae6e | j_mayer | fprintf(logfile, "%s: restart the CPU\n", __func__);
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249 | d0dfae6e | j_mayer | } |
250 | d0dfae6e | j_mayer | #endif
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251 | d0dfae6e | j_mayer | env->halted = 0;
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252 | d0dfae6e | j_mayer | } |
253 | d0dfae6e | j_mayer | break;
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254 | d0dfae6e | j_mayer | case PPC970_INPUT_HRESET:
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255 | d0dfae6e | j_mayer | /* Level sensitive - active low */
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256 | d0dfae6e | j_mayer | if (level) {
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257 | d0dfae6e | j_mayer | #if 0 // XXX: TOFIX
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258 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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259 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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260 | d0dfae6e | j_mayer | fprintf(logfile, "%s: reset the CPU\n", __func__);
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261 | d0dfae6e | j_mayer | }
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262 | d0dfae6e | j_mayer | #endif
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263 | d0dfae6e | j_mayer | cpu_reset(env); |
264 | d0dfae6e | j_mayer | #endif
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265 | d0dfae6e | j_mayer | } |
266 | d0dfae6e | j_mayer | break;
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267 | d0dfae6e | j_mayer | case PPC970_INPUT_SRESET:
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268 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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269 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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270 | d0dfae6e | j_mayer | fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
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271 | d0dfae6e | j_mayer | __func__, level); |
272 | d0dfae6e | j_mayer | } |
273 | d0dfae6e | j_mayer | #endif
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274 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
275 | d0dfae6e | j_mayer | break;
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276 | d0dfae6e | j_mayer | case PPC970_INPUT_TBEN:
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277 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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278 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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279 | d0dfae6e | j_mayer | fprintf(logfile, "%s: set the TBEN state to %d\n", __func__,
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280 | d0dfae6e | j_mayer | level); |
281 | d0dfae6e | j_mayer | } |
282 | d0dfae6e | j_mayer | #endif
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283 | d0dfae6e | j_mayer | /* XXX: TODO */
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284 | d0dfae6e | j_mayer | break;
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285 | d0dfae6e | j_mayer | default:
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286 | d0dfae6e | j_mayer | /* Unknown pin - do nothing */
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287 | d0dfae6e | j_mayer | #if defined(PPC_DEBUG_IRQ)
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288 | d0dfae6e | j_mayer | if (loglevel & CPU_LOG_INT) {
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289 | d0dfae6e | j_mayer | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
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290 | d0dfae6e | j_mayer | } |
291 | d0dfae6e | j_mayer | #endif
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292 | d0dfae6e | j_mayer | return;
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293 | d0dfae6e | j_mayer | } |
294 | d0dfae6e | j_mayer | if (level)
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295 | d0dfae6e | j_mayer | env->irq_input_state |= 1 << pin;
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296 | d0dfae6e | j_mayer | else
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297 | d0dfae6e | j_mayer | env->irq_input_state &= ~(1 << pin);
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298 | d0dfae6e | j_mayer | } |
299 | d0dfae6e | j_mayer | } |
300 | d0dfae6e | j_mayer | |
301 | d0dfae6e | j_mayer | void ppc970_irq_init (CPUState *env)
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302 | d0dfae6e | j_mayer | { |
303 | 7b62a955 | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env,
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304 | 7b62a955 | j_mayer | PPC970_INPUT_NB); |
305 | d0dfae6e | j_mayer | } |
306 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
307 | d0dfae6e | j_mayer | |
308 | 4e290a0b | j_mayer | /* PowerPC 40x internal IRQ controller */
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309 | 4e290a0b | j_mayer | static void ppc40x_set_irq (void *opaque, int pin, int level) |
310 | 24be5ae3 | j_mayer | { |
311 | 24be5ae3 | j_mayer | CPUState *env = opaque; |
312 | 24be5ae3 | j_mayer | int cur_level;
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313 | 24be5ae3 | j_mayer | |
314 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
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315 | 8ecc7913 | j_mayer | if (loglevel & CPU_LOG_INT) {
|
316 | 8ecc7913 | j_mayer | fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
|
317 | 8ecc7913 | j_mayer | env, pin, level); |
318 | 8ecc7913 | j_mayer | } |
319 | 24be5ae3 | j_mayer | #endif
|
320 | 24be5ae3 | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
|
321 | 24be5ae3 | j_mayer | /* Don't generate spurious events */
|
322 | 24be5ae3 | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
323 | 24be5ae3 | j_mayer | switch (pin) {
|
324 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_SYS:
|
325 | 8ecc7913 | j_mayer | if (level) {
|
326 | 8ecc7913 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
327 | 8ecc7913 | j_mayer | if (loglevel & CPU_LOG_INT) {
|
328 | 8ecc7913 | j_mayer | fprintf(logfile, "%s: reset the PowerPC system\n",
|
329 | 8ecc7913 | j_mayer | __func__); |
330 | 8ecc7913 | j_mayer | } |
331 | 8ecc7913 | j_mayer | #endif
|
332 | 8ecc7913 | j_mayer | ppc40x_system_reset(env); |
333 | 8ecc7913 | j_mayer | } |
334 | 8ecc7913 | j_mayer | break;
|
335 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_CHIP:
|
336 | 8ecc7913 | j_mayer | if (level) {
|
337 | 8ecc7913 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
338 | 8ecc7913 | j_mayer | if (loglevel & CPU_LOG_INT) {
|
339 | 8ecc7913 | j_mayer | fprintf(logfile, "%s: reset the PowerPC chip\n", __func__);
|
340 | 8ecc7913 | j_mayer | } |
341 | 8ecc7913 | j_mayer | #endif
|
342 | 8ecc7913 | j_mayer | ppc40x_chip_reset(env); |
343 | 8ecc7913 | j_mayer | } |
344 | 8ecc7913 | j_mayer | break;
|
345 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_CORE:
|
346 | 24be5ae3 | j_mayer | /* XXX: TODO: update DBSR[MRR] */
|
347 | 24be5ae3 | j_mayer | if (level) {
|
348 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
349 | 8ecc7913 | j_mayer | if (loglevel & CPU_LOG_INT) {
|
350 | 8ecc7913 | j_mayer | fprintf(logfile, "%s: reset the PowerPC core\n", __func__);
|
351 | 8ecc7913 | j_mayer | } |
352 | 24be5ae3 | j_mayer | #endif
|
353 | 8ecc7913 | j_mayer | ppc40x_core_reset(env); |
354 | 24be5ae3 | j_mayer | } |
355 | 24be5ae3 | j_mayer | break;
|
356 | 4e290a0b | j_mayer | case PPC40x_INPUT_CINT:
|
357 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
358 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
359 | 8ecc7913 | j_mayer | if (loglevel & CPU_LOG_INT) {
|
360 | 8ecc7913 | j_mayer | fprintf(logfile, "%s: set the critical IRQ state to %d\n",
|
361 | 8ecc7913 | j_mayer | __func__, level); |
362 | 8ecc7913 | j_mayer | } |
363 | 24be5ae3 | j_mayer | #endif
|
364 | 4e290a0b | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); |
365 | 24be5ae3 | j_mayer | break;
|
366 | 4e290a0b | j_mayer | case PPC40x_INPUT_INT:
|
367 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
368 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
369 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
370 | a496775f | j_mayer | fprintf(logfile, "%s: set the external IRQ state to %d\n",
|
371 | a496775f | j_mayer | __func__, level); |
372 | a496775f | j_mayer | } |
373 | 24be5ae3 | j_mayer | #endif
|
374 | 24be5ae3 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
375 | 24be5ae3 | j_mayer | break;
|
376 | 4e290a0b | j_mayer | case PPC40x_INPUT_HALT:
|
377 | 24be5ae3 | j_mayer | /* Level sensitive - active low */
|
378 | 24be5ae3 | j_mayer | if (level) {
|
379 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
380 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
381 | a496775f | j_mayer | fprintf(logfile, "%s: stop the CPU\n", __func__);
|
382 | a496775f | j_mayer | } |
383 | 24be5ae3 | j_mayer | #endif
|
384 | 24be5ae3 | j_mayer | env->halted = 1;
|
385 | 24be5ae3 | j_mayer | } else {
|
386 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
387 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
388 | a496775f | j_mayer | fprintf(logfile, "%s: restart the CPU\n", __func__);
|
389 | a496775f | j_mayer | } |
390 | 24be5ae3 | j_mayer | #endif
|
391 | 24be5ae3 | j_mayer | env->halted = 0;
|
392 | 24be5ae3 | j_mayer | } |
393 | 24be5ae3 | j_mayer | break;
|
394 | 4e290a0b | j_mayer | case PPC40x_INPUT_DEBUG:
|
395 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
396 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
397 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
398 | a750fc0b | j_mayer | fprintf(logfile, "%s: set the debug pin state to %d\n",
|
399 | a496775f | j_mayer | __func__, level); |
400 | a496775f | j_mayer | } |
401 | 24be5ae3 | j_mayer | #endif
|
402 | a750fc0b | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); |
403 | 24be5ae3 | j_mayer | break;
|
404 | 24be5ae3 | j_mayer | default:
|
405 | 24be5ae3 | j_mayer | /* Unknown pin - do nothing */
|
406 | 24be5ae3 | j_mayer | #if defined(PPC_DEBUG_IRQ)
|
407 | a496775f | j_mayer | if (loglevel & CPU_LOG_INT) {
|
408 | a496775f | j_mayer | fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
|
409 | a496775f | j_mayer | } |
410 | 24be5ae3 | j_mayer | #endif
|
411 | 24be5ae3 | j_mayer | return;
|
412 | 24be5ae3 | j_mayer | } |
413 | 24be5ae3 | j_mayer | if (level)
|
414 | 24be5ae3 | j_mayer | env->irq_input_state |= 1 << pin;
|
415 | 24be5ae3 | j_mayer | else
|
416 | 24be5ae3 | j_mayer | env->irq_input_state &= ~(1 << pin);
|
417 | 24be5ae3 | j_mayer | } |
418 | 24be5ae3 | j_mayer | } |
419 | 24be5ae3 | j_mayer | |
420 | 4e290a0b | j_mayer | void ppc40x_irq_init (CPUState *env)
|
421 | 24be5ae3 | j_mayer | { |
422 | 4e290a0b | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
|
423 | 4e290a0b | j_mayer | env, PPC40x_INPUT_NB); |
424 | 24be5ae3 | j_mayer | } |
425 | 24be5ae3 | j_mayer | |
426 | 9fddaa0c | bellard | /*****************************************************************************/
|
427 | e9df014c | j_mayer | /* PowerPC time base and decrementer emulation */
|
428 | 9fddaa0c | bellard | struct ppc_tb_t {
|
429 | 9fddaa0c | bellard | /* Time base management */
|
430 | dbdd2506 | j_mayer | int64_t tb_offset; /* Compensation */
|
431 | dbdd2506 | j_mayer | int64_t atb_offset; /* Compensation */
|
432 | dbdd2506 | j_mayer | uint32_t tb_freq; /* TB frequency */
|
433 | 9fddaa0c | bellard | /* Decrementer management */
|
434 | dbdd2506 | j_mayer | uint64_t decr_next; /* Tick for next decr interrupt */
|
435 | dbdd2506 | j_mayer | uint32_t decr_freq; /* decrementer frequency */
|
436 | 9fddaa0c | bellard | struct QEMUTimer *decr_timer;
|
437 | 58a7d328 | j_mayer | /* Hypervisor decrementer management */
|
438 | 58a7d328 | j_mayer | uint64_t hdecr_next; /* Tick for next hdecr interrupt */
|
439 | 58a7d328 | j_mayer | struct QEMUTimer *hdecr_timer;
|
440 | 58a7d328 | j_mayer | uint64_t purr_load; |
441 | 58a7d328 | j_mayer | uint64_t purr_start; |
442 | 47103572 | j_mayer | void *opaque;
|
443 | 9fddaa0c | bellard | }; |
444 | 9fddaa0c | bellard | |
445 | dbdd2506 | j_mayer | static always_inline uint64_t cpu_ppc_get_tb (ppc_tb_t *tb_env, uint64_t vmclk,
|
446 | b068d6a7 | j_mayer | int64_t tb_offset) |
447 | 9fddaa0c | bellard | { |
448 | 9fddaa0c | bellard | /* TB time in tb periods */
|
449 | dbdd2506 | j_mayer | return muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec) + tb_offset;
|
450 | 9fddaa0c | bellard | } |
451 | 9fddaa0c | bellard | |
452 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbl (CPUState *env) |
453 | 9fddaa0c | bellard | { |
454 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
455 | 9fddaa0c | bellard | uint64_t tb; |
456 | 9fddaa0c | bellard | |
457 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
458 | a062e36c | j_mayer | #if defined(PPC_DEBUG_TB)
|
459 | a062e36c | j_mayer | if (loglevel != 0) { |
460 | aae9366a | j_mayer | fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb); |
461 | 9fddaa0c | bellard | } |
462 | 9fddaa0c | bellard | #endif
|
463 | 9fddaa0c | bellard | |
464 | 9fddaa0c | bellard | return tb & 0xFFFFFFFF; |
465 | 9fddaa0c | bellard | } |
466 | 9fddaa0c | bellard | |
467 | b068d6a7 | j_mayer | static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env)
|
468 | 9fddaa0c | bellard | { |
469 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
470 | 9fddaa0c | bellard | uint64_t tb; |
471 | 9fddaa0c | bellard | |
472 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
473 | 4b6d0a4c | j_mayer | #if defined(PPC_DEBUG_TB)
|
474 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
475 | aae9366a | j_mayer | fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb); |
476 | a496775f | j_mayer | } |
477 | 9fddaa0c | bellard | #endif
|
478 | 76a66253 | j_mayer | |
479 | 9fddaa0c | bellard | return tb >> 32; |
480 | 9fddaa0c | bellard | } |
481 | 9fddaa0c | bellard | |
482 | 8a84de23 | j_mayer | uint32_t cpu_ppc_load_tbu (CPUState *env) |
483 | 8a84de23 | j_mayer | { |
484 | 8a84de23 | j_mayer | return _cpu_ppc_load_tbu(env);
|
485 | 8a84de23 | j_mayer | } |
486 | 8a84de23 | j_mayer | |
487 | dbdd2506 | j_mayer | static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk, |
488 | b068d6a7 | j_mayer | int64_t *tb_offsetp, |
489 | b068d6a7 | j_mayer | uint64_t value) |
490 | 9fddaa0c | bellard | { |
491 | dbdd2506 | j_mayer | *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec); |
492 | 4b6d0a4c | j_mayer | #ifdef PPC_DEBUG_TB
|
493 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
494 | aae9366a | j_mayer | fprintf(logfile, "%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", |
495 | aae9366a | j_mayer | __func__, value, *tb_offsetp); |
496 | a496775f | j_mayer | } |
497 | 9fddaa0c | bellard | #endif
|
498 | 9fddaa0c | bellard | } |
499 | 9fddaa0c | bellard | |
500 | a062e36c | j_mayer | void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
|
501 | a062e36c | j_mayer | { |
502 | a062e36c | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
503 | a062e36c | j_mayer | uint64_t tb; |
504 | a062e36c | j_mayer | |
505 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
506 | a062e36c | j_mayer | tb &= 0xFFFFFFFF00000000ULL;
|
507 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
508 | dbdd2506 | j_mayer | &tb_env->tb_offset, tb | (uint64_t)value); |
509 | a062e36c | j_mayer | } |
510 | a062e36c | j_mayer | |
511 | b068d6a7 | j_mayer | static always_inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value) |
512 | 9fddaa0c | bellard | { |
513 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
514 | a062e36c | j_mayer | uint64_t tb; |
515 | 9fddaa0c | bellard | |
516 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
517 | a062e36c | j_mayer | tb &= 0x00000000FFFFFFFFULL;
|
518 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
519 | dbdd2506 | j_mayer | &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
|
520 | 9fddaa0c | bellard | } |
521 | 9fddaa0c | bellard | |
522 | 8a84de23 | j_mayer | void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
|
523 | 8a84de23 | j_mayer | { |
524 | 8a84de23 | j_mayer | _cpu_ppc_store_tbu(env, value); |
525 | 8a84de23 | j_mayer | } |
526 | 8a84de23 | j_mayer | |
527 | a062e36c | j_mayer | uint32_t cpu_ppc_load_atbl (CPUState *env) |
528 | a062e36c | j_mayer | { |
529 | a062e36c | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
530 | a062e36c | j_mayer | uint64_t tb; |
531 | a062e36c | j_mayer | |
532 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
533 | a062e36c | j_mayer | #if defined(PPC_DEBUG_TB)
|
534 | a062e36c | j_mayer | if (loglevel != 0) { |
535 | aae9366a | j_mayer | fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb); |
536 | a062e36c | j_mayer | } |
537 | a062e36c | j_mayer | #endif
|
538 | a062e36c | j_mayer | |
539 | a062e36c | j_mayer | return tb & 0xFFFFFFFF; |
540 | a062e36c | j_mayer | } |
541 | a062e36c | j_mayer | |
542 | a062e36c | j_mayer | uint32_t cpu_ppc_load_atbu (CPUState *env) |
543 | a062e36c | j_mayer | { |
544 | a062e36c | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
545 | a062e36c | j_mayer | uint64_t tb; |
546 | a062e36c | j_mayer | |
547 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
548 | a062e36c | j_mayer | #if defined(PPC_DEBUG_TB)
|
549 | a062e36c | j_mayer | if (loglevel != 0) { |
550 | aae9366a | j_mayer | fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb); |
551 | a062e36c | j_mayer | } |
552 | a062e36c | j_mayer | #endif
|
553 | a062e36c | j_mayer | |
554 | a062e36c | j_mayer | return tb >> 32; |
555 | a062e36c | j_mayer | } |
556 | a062e36c | j_mayer | |
557 | a062e36c | j_mayer | void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
|
558 | a062e36c | j_mayer | { |
559 | a062e36c | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
560 | a062e36c | j_mayer | uint64_t tb; |
561 | a062e36c | j_mayer | |
562 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
563 | a062e36c | j_mayer | tb &= 0xFFFFFFFF00000000ULL;
|
564 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
565 | dbdd2506 | j_mayer | &tb_env->atb_offset, tb | (uint64_t)value); |
566 | a062e36c | j_mayer | } |
567 | a062e36c | j_mayer | |
568 | a062e36c | j_mayer | void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
|
569 | 9fddaa0c | bellard | { |
570 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
571 | a062e36c | j_mayer | uint64_t tb; |
572 | 9fddaa0c | bellard | |
573 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
574 | a062e36c | j_mayer | tb &= 0x00000000FFFFFFFFULL;
|
575 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
576 | dbdd2506 | j_mayer | &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
|
577 | dbdd2506 | j_mayer | } |
578 | dbdd2506 | j_mayer | |
579 | dbdd2506 | j_mayer | static void cpu_ppc_tb_stop (CPUState *env) |
580 | dbdd2506 | j_mayer | { |
581 | dbdd2506 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
582 | dbdd2506 | j_mayer | uint64_t tb, atb, vmclk; |
583 | dbdd2506 | j_mayer | |
584 | dbdd2506 | j_mayer | /* If the time base is already frozen, do nothing */
|
585 | dbdd2506 | j_mayer | if (tb_env->tb_freq != 0) { |
586 | dbdd2506 | j_mayer | vmclk = qemu_get_clock(vm_clock); |
587 | dbdd2506 | j_mayer | /* Get the time base */
|
588 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); |
589 | dbdd2506 | j_mayer | /* Get the alternate time base */
|
590 | dbdd2506 | j_mayer | atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); |
591 | dbdd2506 | j_mayer | /* Store the time base value (ie compute the current offset) */
|
592 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
593 | dbdd2506 | j_mayer | /* Store the alternate time base value (compute the current offset) */
|
594 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
595 | dbdd2506 | j_mayer | /* Set the time base frequency to zero */
|
596 | dbdd2506 | j_mayer | tb_env->tb_freq = 0;
|
597 | dbdd2506 | j_mayer | /* Now, the time bases are frozen to tb_offset / atb_offset value */
|
598 | dbdd2506 | j_mayer | } |
599 | dbdd2506 | j_mayer | } |
600 | dbdd2506 | j_mayer | |
601 | dbdd2506 | j_mayer | static void cpu_ppc_tb_start (CPUState *env) |
602 | dbdd2506 | j_mayer | { |
603 | dbdd2506 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
604 | dbdd2506 | j_mayer | uint64_t tb, atb, vmclk; |
605 | aae9366a | j_mayer | |
606 | dbdd2506 | j_mayer | /* If the time base is not frozen, do nothing */
|
607 | dbdd2506 | j_mayer | if (tb_env->tb_freq == 0) { |
608 | dbdd2506 | j_mayer | vmclk = qemu_get_clock(vm_clock); |
609 | dbdd2506 | j_mayer | /* Get the time base from tb_offset */
|
610 | dbdd2506 | j_mayer | tb = tb_env->tb_offset; |
611 | dbdd2506 | j_mayer | /* Get the alternate time base from atb_offset */
|
612 | dbdd2506 | j_mayer | atb = tb_env->atb_offset; |
613 | dbdd2506 | j_mayer | /* Restore the tb frequency from the decrementer frequency */
|
614 | dbdd2506 | j_mayer | tb_env->tb_freq = tb_env->decr_freq; |
615 | dbdd2506 | j_mayer | /* Store the time base value */
|
616 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
617 | dbdd2506 | j_mayer | /* Store the alternate time base value */
|
618 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
619 | dbdd2506 | j_mayer | } |
620 | 9fddaa0c | bellard | } |
621 | 9fddaa0c | bellard | |
622 | b068d6a7 | j_mayer | static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env,
|
623 | b068d6a7 | j_mayer | uint64_t *next) |
624 | 9fddaa0c | bellard | { |
625 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
626 | 9fddaa0c | bellard | uint32_t decr; |
627 | 4e588a4d | bellard | int64_t diff; |
628 | 9fddaa0c | bellard | |
629 | 4e588a4d | bellard | diff = tb_env->decr_next - qemu_get_clock(vm_clock); |
630 | 4e588a4d | bellard | if (diff >= 0) |
631 | dbdd2506 | j_mayer | decr = muldiv64(diff, tb_env->decr_freq, ticks_per_sec); |
632 | 4e588a4d | bellard | else
|
633 | dbdd2506 | j_mayer | decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec); |
634 | 4b6d0a4c | j_mayer | #if defined(PPC_DEBUG_TB)
|
635 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
636 | aae9366a | j_mayer | fprintf(logfile, "%s: %08" PRIx32 "\n", __func__, decr); |
637 | a496775f | j_mayer | } |
638 | 9fddaa0c | bellard | #endif
|
639 | 76a66253 | j_mayer | |
640 | 9fddaa0c | bellard | return decr;
|
641 | 9fddaa0c | bellard | } |
642 | 9fddaa0c | bellard | |
643 | 58a7d328 | j_mayer | uint32_t cpu_ppc_load_decr (CPUState *env) |
644 | 58a7d328 | j_mayer | { |
645 | 58a7d328 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
646 | 58a7d328 | j_mayer | |
647 | 58a7d328 | j_mayer | return _cpu_ppc_load_decr(env, &tb_env->decr_next);
|
648 | 58a7d328 | j_mayer | } |
649 | 58a7d328 | j_mayer | |
650 | 58a7d328 | j_mayer | uint32_t cpu_ppc_load_hdecr (CPUState *env) |
651 | 58a7d328 | j_mayer | { |
652 | 58a7d328 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
653 | 58a7d328 | j_mayer | |
654 | 58a7d328 | j_mayer | return _cpu_ppc_load_decr(env, &tb_env->hdecr_next);
|
655 | 58a7d328 | j_mayer | } |
656 | 58a7d328 | j_mayer | |
657 | 58a7d328 | j_mayer | uint64_t cpu_ppc_load_purr (CPUState *env) |
658 | 58a7d328 | j_mayer | { |
659 | 58a7d328 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
660 | 58a7d328 | j_mayer | uint64_t diff; |
661 | 58a7d328 | j_mayer | |
662 | 58a7d328 | j_mayer | diff = qemu_get_clock(vm_clock) - tb_env->purr_start; |
663 | b33c17e1 | j_mayer | |
664 | 58a7d328 | j_mayer | return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
|
665 | 58a7d328 | j_mayer | } |
666 | 58a7d328 | j_mayer | |
667 | 9fddaa0c | bellard | /* When decrementer expires,
|
668 | 9fddaa0c | bellard | * all we need to do is generate or queue a CPU exception
|
669 | 9fddaa0c | bellard | */
|
670 | b068d6a7 | j_mayer | static always_inline void cpu_ppc_decr_excp (CPUState *env) |
671 | 9fddaa0c | bellard | { |
672 | 9fddaa0c | bellard | /* Raise it */
|
673 | 4b6d0a4c | j_mayer | #ifdef PPC_DEBUG_TB
|
674 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
675 | a496775f | j_mayer | fprintf(logfile, "raise decrementer exception\n");
|
676 | a496775f | j_mayer | } |
677 | 9fddaa0c | bellard | #endif
|
678 | 47103572 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
|
679 | 9fddaa0c | bellard | } |
680 | 9fddaa0c | bellard | |
681 | b068d6a7 | j_mayer | static always_inline void cpu_ppc_hdecr_excp (CPUState *env) |
682 | 58a7d328 | j_mayer | { |
683 | 58a7d328 | j_mayer | /* Raise it */
|
684 | 58a7d328 | j_mayer | #ifdef PPC_DEBUG_TB
|
685 | 58a7d328 | j_mayer | if (loglevel != 0) { |
686 | 58a7d328 | j_mayer | fprintf(logfile, "raise decrementer exception\n");
|
687 | 58a7d328 | j_mayer | } |
688 | 58a7d328 | j_mayer | #endif
|
689 | 58a7d328 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
|
690 | 58a7d328 | j_mayer | } |
691 | 58a7d328 | j_mayer | |
692 | 58a7d328 | j_mayer | static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, |
693 | b33c17e1 | j_mayer | struct QEMUTimer *timer,
|
694 | b33c17e1 | j_mayer | void (*raise_excp)(CPUState *),
|
695 | b33c17e1 | j_mayer | uint32_t decr, uint32_t value, |
696 | b33c17e1 | j_mayer | int is_excp)
|
697 | 9fddaa0c | bellard | { |
698 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
699 | 9fddaa0c | bellard | uint64_t now, next; |
700 | 9fddaa0c | bellard | |
701 | 4b6d0a4c | j_mayer | #ifdef PPC_DEBUG_TB
|
702 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
703 | aae9366a | j_mayer | fprintf(logfile, "%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, |
704 | aae9366a | j_mayer | decr, value); |
705 | a496775f | j_mayer | } |
706 | 9fddaa0c | bellard | #endif
|
707 | 9fddaa0c | bellard | now = qemu_get_clock(vm_clock); |
708 | dbdd2506 | j_mayer | next = now + muldiv64(value, ticks_per_sec, tb_env->decr_freq); |
709 | 9fddaa0c | bellard | if (is_excp)
|
710 | 58a7d328 | j_mayer | next += *nextp - now; |
711 | 9fddaa0c | bellard | if (next == now)
|
712 | 76a66253 | j_mayer | next++; |
713 | 58a7d328 | j_mayer | *nextp = next; |
714 | 9fddaa0c | bellard | /* Adjust timer */
|
715 | 58a7d328 | j_mayer | qemu_mod_timer(timer, next); |
716 | 9fddaa0c | bellard | /* If we set a negative value and the decrementer was positive,
|
717 | 9fddaa0c | bellard | * raise an exception.
|
718 | 9fddaa0c | bellard | */
|
719 | 9fddaa0c | bellard | if ((value & 0x80000000) && !(decr & 0x80000000)) |
720 | 58a7d328 | j_mayer | (*raise_excp)(env); |
721 | 58a7d328 | j_mayer | } |
722 | 58a7d328 | j_mayer | |
723 | b068d6a7 | j_mayer | static always_inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr, |
724 | b068d6a7 | j_mayer | uint32_t value, int is_excp)
|
725 | 58a7d328 | j_mayer | { |
726 | 58a7d328 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
727 | 58a7d328 | j_mayer | |
728 | 58a7d328 | j_mayer | __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer, |
729 | 58a7d328 | j_mayer | &cpu_ppc_decr_excp, decr, value, is_excp); |
730 | 9fddaa0c | bellard | } |
731 | 9fddaa0c | bellard | |
732 | 9fddaa0c | bellard | void cpu_ppc_store_decr (CPUState *env, uint32_t value)
|
733 | 9fddaa0c | bellard | { |
734 | 9fddaa0c | bellard | _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
|
735 | 9fddaa0c | bellard | } |
736 | 9fddaa0c | bellard | |
737 | 9fddaa0c | bellard | static void cpu_ppc_decr_cb (void *opaque) |
738 | 9fddaa0c | bellard | { |
739 | 9fddaa0c | bellard | _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
740 | 9fddaa0c | bellard | } |
741 | 9fddaa0c | bellard | |
742 | b068d6a7 | j_mayer | static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr, |
743 | b068d6a7 | j_mayer | uint32_t value, int is_excp)
|
744 | 58a7d328 | j_mayer | { |
745 | 58a7d328 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
746 | 58a7d328 | j_mayer | |
747 | b172c56a | j_mayer | if (tb_env->hdecr_timer != NULL) { |
748 | b172c56a | j_mayer | __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer, |
749 | b172c56a | j_mayer | &cpu_ppc_hdecr_excp, hdecr, value, is_excp); |
750 | b172c56a | j_mayer | } |
751 | 58a7d328 | j_mayer | } |
752 | 58a7d328 | j_mayer | |
753 | 58a7d328 | j_mayer | void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
|
754 | 58a7d328 | j_mayer | { |
755 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
|
756 | 58a7d328 | j_mayer | } |
757 | 58a7d328 | j_mayer | |
758 | 58a7d328 | j_mayer | static void cpu_ppc_hdecr_cb (void *opaque) |
759 | 58a7d328 | j_mayer | { |
760 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
761 | 58a7d328 | j_mayer | } |
762 | 58a7d328 | j_mayer | |
763 | 58a7d328 | j_mayer | void cpu_ppc_store_purr (CPUState *env, uint64_t value)
|
764 | 58a7d328 | j_mayer | { |
765 | 58a7d328 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
766 | 58a7d328 | j_mayer | |
767 | 58a7d328 | j_mayer | tb_env->purr_load = value; |
768 | 58a7d328 | j_mayer | tb_env->purr_start = qemu_get_clock(vm_clock); |
769 | 58a7d328 | j_mayer | } |
770 | 58a7d328 | j_mayer | |
771 | 8ecc7913 | j_mayer | static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) |
772 | 8ecc7913 | j_mayer | { |
773 | 8ecc7913 | j_mayer | CPUState *env = opaque; |
774 | 8ecc7913 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
775 | 8ecc7913 | j_mayer | |
776 | 8ecc7913 | j_mayer | tb_env->tb_freq = freq; |
777 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
778 | 8ecc7913 | j_mayer | /* There is a bug in Linux 2.4 kernels:
|
779 | 8ecc7913 | j_mayer | * if a decrementer exception is pending when it enables msr_ee at startup,
|
780 | 8ecc7913 | j_mayer | * it's not ready to handle it...
|
781 | 8ecc7913 | j_mayer | */
|
782 | 8ecc7913 | j_mayer | _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
783 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
784 | 58a7d328 | j_mayer | cpu_ppc_store_purr(env, 0x0000000000000000ULL);
|
785 | 8ecc7913 | j_mayer | } |
786 | 8ecc7913 | j_mayer | |
787 | 9fddaa0c | bellard | /* Set up (once) timebase frequency (in Hz) */
|
788 | 8ecc7913 | j_mayer | clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) |
789 | 9fddaa0c | bellard | { |
790 | 9fddaa0c | bellard | ppc_tb_t *tb_env; |
791 | 9fddaa0c | bellard | |
792 | 9fddaa0c | bellard | tb_env = qemu_mallocz(sizeof(ppc_tb_t));
|
793 | 9fddaa0c | bellard | if (tb_env == NULL) |
794 | 9fddaa0c | bellard | return NULL; |
795 | 9fddaa0c | bellard | env->tb_env = tb_env; |
796 | 8ecc7913 | j_mayer | /* Create new timer */
|
797 | 8ecc7913 | j_mayer | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); |
798 | b172c56a | j_mayer | if (0) { |
799 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor decrementer
|
800 | b172c56a | j_mayer | */
|
801 | b172c56a | j_mayer | tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env); |
802 | b172c56a | j_mayer | } else {
|
803 | b172c56a | j_mayer | tb_env->hdecr_timer = NULL;
|
804 | b172c56a | j_mayer | } |
805 | 8ecc7913 | j_mayer | cpu_ppc_set_tb_clk(env, freq); |
806 | 9fddaa0c | bellard | |
807 | 8ecc7913 | j_mayer | return &cpu_ppc_set_tb_clk;
|
808 | 9fddaa0c | bellard | } |
809 | 9fddaa0c | bellard | |
810 | 76a66253 | j_mayer | /* Specific helpers for POWER & PowerPC 601 RTC */
|
811 | 8ecc7913 | j_mayer | clk_setup_cb cpu_ppc601_rtc_init (CPUState *env) |
812 | 76a66253 | j_mayer | { |
813 | 76a66253 | j_mayer | return cpu_ppc_tb_init(env, 7812500); |
814 | 76a66253 | j_mayer | } |
815 | 76a66253 | j_mayer | |
816 | 76a66253 | j_mayer | void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
|
817 | 8a84de23 | j_mayer | { |
818 | 8a84de23 | j_mayer | _cpu_ppc_store_tbu(env, value); |
819 | 8a84de23 | j_mayer | } |
820 | 76a66253 | j_mayer | |
821 | 76a66253 | j_mayer | uint32_t cpu_ppc601_load_rtcu (CPUState *env) |
822 | 8a84de23 | j_mayer | { |
823 | 8a84de23 | j_mayer | return _cpu_ppc_load_tbu(env);
|
824 | 8a84de23 | j_mayer | } |
825 | 76a66253 | j_mayer | |
826 | 76a66253 | j_mayer | void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
|
827 | 76a66253 | j_mayer | { |
828 | 76a66253 | j_mayer | cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
|
829 | 76a66253 | j_mayer | } |
830 | 76a66253 | j_mayer | |
831 | 76a66253 | j_mayer | uint32_t cpu_ppc601_load_rtcl (CPUState *env) |
832 | 76a66253 | j_mayer | { |
833 | 76a66253 | j_mayer | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
834 | 76a66253 | j_mayer | } |
835 | 76a66253 | j_mayer | |
836 | 636aaad7 | j_mayer | /*****************************************************************************/
|
837 | 76a66253 | j_mayer | /* Embedded PowerPC timers */
|
838 | 636aaad7 | j_mayer | |
839 | 636aaad7 | j_mayer | /* PIT, FIT & WDT */
|
840 | 636aaad7 | j_mayer | typedef struct ppcemb_timer_t ppcemb_timer_t; |
841 | 636aaad7 | j_mayer | struct ppcemb_timer_t {
|
842 | 636aaad7 | j_mayer | uint64_t pit_reload; /* PIT auto-reload value */
|
843 | 636aaad7 | j_mayer | uint64_t fit_next; /* Tick for next FIT interrupt */
|
844 | 636aaad7 | j_mayer | struct QEMUTimer *fit_timer;
|
845 | 636aaad7 | j_mayer | uint64_t wdt_next; /* Tick for next WDT interrupt */
|
846 | 636aaad7 | j_mayer | struct QEMUTimer *wdt_timer;
|
847 | 636aaad7 | j_mayer | }; |
848 | 3b46e624 | ths | |
849 | 636aaad7 | j_mayer | /* Fixed interval timer */
|
850 | 636aaad7 | j_mayer | static void cpu_4xx_fit_cb (void *opaque) |
851 | 636aaad7 | j_mayer | { |
852 | 636aaad7 | j_mayer | CPUState *env; |
853 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
854 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
855 | 636aaad7 | j_mayer | uint64_t now, next; |
856 | 636aaad7 | j_mayer | |
857 | 636aaad7 | j_mayer | env = opaque; |
858 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
859 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
860 | 636aaad7 | j_mayer | now = qemu_get_clock(vm_clock); |
861 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { |
862 | 636aaad7 | j_mayer | case 0: |
863 | 636aaad7 | j_mayer | next = 1 << 9; |
864 | 636aaad7 | j_mayer | break;
|
865 | 636aaad7 | j_mayer | case 1: |
866 | 636aaad7 | j_mayer | next = 1 << 13; |
867 | 636aaad7 | j_mayer | break;
|
868 | 636aaad7 | j_mayer | case 2: |
869 | 636aaad7 | j_mayer | next = 1 << 17; |
870 | 636aaad7 | j_mayer | break;
|
871 | 636aaad7 | j_mayer | case 3: |
872 | 636aaad7 | j_mayer | next = 1 << 21; |
873 | 636aaad7 | j_mayer | break;
|
874 | 636aaad7 | j_mayer | default:
|
875 | 636aaad7 | j_mayer | /* Cannot occur, but makes gcc happy */
|
876 | 636aaad7 | j_mayer | return;
|
877 | 636aaad7 | j_mayer | } |
878 | 636aaad7 | j_mayer | next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); |
879 | 636aaad7 | j_mayer | if (next == now)
|
880 | 636aaad7 | j_mayer | next++; |
881 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->fit_timer, next); |
882 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 26; |
883 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) |
884 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
|
885 | 4b6d0a4c | j_mayer | #ifdef PPC_DEBUG_TB
|
886 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
887 | e96efcfc | j_mayer | fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__, |
888 | e96efcfc | j_mayer | (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), |
889 | 636aaad7 | j_mayer | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
890 | 636aaad7 | j_mayer | } |
891 | 4b6d0a4c | j_mayer | #endif
|
892 | 636aaad7 | j_mayer | } |
893 | 636aaad7 | j_mayer | |
894 | 636aaad7 | j_mayer | /* Programmable interval timer */
|
895 | 4b6d0a4c | j_mayer | static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) |
896 | 76a66253 | j_mayer | { |
897 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
898 | 636aaad7 | j_mayer | uint64_t now, next; |
899 | 636aaad7 | j_mayer | |
900 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
901 | 4b6d0a4c | j_mayer | if (ppcemb_timer->pit_reload <= 1 || |
902 | 4b6d0a4c | j_mayer | !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || |
903 | 4b6d0a4c | j_mayer | (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { |
904 | 4b6d0a4c | j_mayer | /* Stop PIT */
|
905 | 4b6d0a4c | j_mayer | #ifdef PPC_DEBUG_TB
|
906 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
907 | 4b6d0a4c | j_mayer | fprintf(logfile, "%s: stop PIT\n", __func__);
|
908 | 4b6d0a4c | j_mayer | } |
909 | 4b6d0a4c | j_mayer | #endif
|
910 | 4b6d0a4c | j_mayer | qemu_del_timer(tb_env->decr_timer); |
911 | 4b6d0a4c | j_mayer | } else {
|
912 | 4b6d0a4c | j_mayer | #ifdef PPC_DEBUG_TB
|
913 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
914 | aae9366a | j_mayer | fprintf(logfile, "%s: start PIT %016" PRIx64 "\n", |
915 | 4b6d0a4c | j_mayer | __func__, ppcemb_timer->pit_reload); |
916 | 4b6d0a4c | j_mayer | } |
917 | 4b6d0a4c | j_mayer | #endif
|
918 | 4b6d0a4c | j_mayer | now = qemu_get_clock(vm_clock); |
919 | 636aaad7 | j_mayer | next = now + muldiv64(ppcemb_timer->pit_reload, |
920 | dbdd2506 | j_mayer | ticks_per_sec, tb_env->decr_freq); |
921 | 4b6d0a4c | j_mayer | if (is_excp)
|
922 | 4b6d0a4c | j_mayer | next += tb_env->decr_next - now; |
923 | 636aaad7 | j_mayer | if (next == now)
|
924 | 636aaad7 | j_mayer | next++; |
925 | 636aaad7 | j_mayer | qemu_mod_timer(tb_env->decr_timer, next); |
926 | 636aaad7 | j_mayer | tb_env->decr_next = next; |
927 | 636aaad7 | j_mayer | } |
928 | 4b6d0a4c | j_mayer | } |
929 | 4b6d0a4c | j_mayer | |
930 | 4b6d0a4c | j_mayer | static void cpu_4xx_pit_cb (void *opaque) |
931 | 4b6d0a4c | j_mayer | { |
932 | 4b6d0a4c | j_mayer | CPUState *env; |
933 | 4b6d0a4c | j_mayer | ppc_tb_t *tb_env; |
934 | 4b6d0a4c | j_mayer | ppcemb_timer_t *ppcemb_timer; |
935 | 4b6d0a4c | j_mayer | |
936 | 4b6d0a4c | j_mayer | env = opaque; |
937 | 4b6d0a4c | j_mayer | tb_env = env->tb_env; |
938 | 4b6d0a4c | j_mayer | ppcemb_timer = tb_env->opaque; |
939 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 27; |
940 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) |
941 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
|
942 | 4b6d0a4c | j_mayer | start_stop_pit(env, tb_env, 1);
|
943 | 4b6d0a4c | j_mayer | #ifdef PPC_DEBUG_TB
|
944 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
945 | e96efcfc | j_mayer | fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " " |
946 | e96efcfc | j_mayer | "%016" PRIx64 "\n", __func__, |
947 | e96efcfc | j_mayer | (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), |
948 | e96efcfc | j_mayer | (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), |
949 | 636aaad7 | j_mayer | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
950 | 636aaad7 | j_mayer | ppcemb_timer->pit_reload); |
951 | 636aaad7 | j_mayer | } |
952 | 4b6d0a4c | j_mayer | #endif
|
953 | 636aaad7 | j_mayer | } |
954 | 636aaad7 | j_mayer | |
955 | 636aaad7 | j_mayer | /* Watchdog timer */
|
956 | 636aaad7 | j_mayer | static void cpu_4xx_wdt_cb (void *opaque) |
957 | 636aaad7 | j_mayer | { |
958 | 636aaad7 | j_mayer | CPUState *env; |
959 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
960 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
961 | 636aaad7 | j_mayer | uint64_t now, next; |
962 | 636aaad7 | j_mayer | |
963 | 636aaad7 | j_mayer | env = opaque; |
964 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
965 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
966 | 636aaad7 | j_mayer | now = qemu_get_clock(vm_clock); |
967 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { |
968 | 636aaad7 | j_mayer | case 0: |
969 | 636aaad7 | j_mayer | next = 1 << 17; |
970 | 636aaad7 | j_mayer | break;
|
971 | 636aaad7 | j_mayer | case 1: |
972 | 636aaad7 | j_mayer | next = 1 << 21; |
973 | 636aaad7 | j_mayer | break;
|
974 | 636aaad7 | j_mayer | case 2: |
975 | 636aaad7 | j_mayer | next = 1 << 25; |
976 | 636aaad7 | j_mayer | break;
|
977 | 636aaad7 | j_mayer | case 3: |
978 | 636aaad7 | j_mayer | next = 1 << 29; |
979 | 636aaad7 | j_mayer | break;
|
980 | 636aaad7 | j_mayer | default:
|
981 | 636aaad7 | j_mayer | /* Cannot occur, but makes gcc happy */
|
982 | 636aaad7 | j_mayer | return;
|
983 | 636aaad7 | j_mayer | } |
984 | dbdd2506 | j_mayer | next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq); |
985 | 636aaad7 | j_mayer | if (next == now)
|
986 | 636aaad7 | j_mayer | next++; |
987 | 4b6d0a4c | j_mayer | #ifdef PPC_DEBUG_TB
|
988 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
989 | e96efcfc | j_mayer | fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__, |
990 | 636aaad7 | j_mayer | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
991 | 636aaad7 | j_mayer | } |
992 | 4b6d0a4c | j_mayer | #endif
|
993 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
994 | 636aaad7 | j_mayer | case 0x0: |
995 | 636aaad7 | j_mayer | case 0x1: |
996 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
997 | 636aaad7 | j_mayer | ppcemb_timer->wdt_next = next; |
998 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 31; |
999 | 636aaad7 | j_mayer | break;
|
1000 | 636aaad7 | j_mayer | case 0x2: |
1001 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
1002 | 636aaad7 | j_mayer | ppcemb_timer->wdt_next = next; |
1003 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 30; |
1004 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) |
1005 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
|
1006 | 636aaad7 | j_mayer | break;
|
1007 | 636aaad7 | j_mayer | case 0x3: |
1008 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] &= ~0x30000000;
|
1009 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
|
1010 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { |
1011 | 636aaad7 | j_mayer | case 0x0: |
1012 | 636aaad7 | j_mayer | /* No reset */
|
1013 | 636aaad7 | j_mayer | break;
|
1014 | 636aaad7 | j_mayer | case 0x1: /* Core reset */ |
1015 | 8ecc7913 | j_mayer | ppc40x_core_reset(env); |
1016 | 8ecc7913 | j_mayer | break;
|
1017 | 636aaad7 | j_mayer | case 0x2: /* Chip reset */ |
1018 | 8ecc7913 | j_mayer | ppc40x_chip_reset(env); |
1019 | 8ecc7913 | j_mayer | break;
|
1020 | 636aaad7 | j_mayer | case 0x3: /* System reset */ |
1021 | 8ecc7913 | j_mayer | ppc40x_system_reset(env); |
1022 | 8ecc7913 | j_mayer | break;
|
1023 | 636aaad7 | j_mayer | } |
1024 | 636aaad7 | j_mayer | } |
1025 | 76a66253 | j_mayer | } |
1026 | 76a66253 | j_mayer | |
1027 | 76a66253 | j_mayer | void store_40x_pit (CPUState *env, target_ulong val)
|
1028 | 76a66253 | j_mayer | { |
1029 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
1030 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
1031 | 636aaad7 | j_mayer | |
1032 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
1033 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
1034 | 4b6d0a4c | j_mayer | #ifdef PPC_DEBUG_TB
|
1035 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
1036 | aae9366a | j_mayer | fprintf(logfile, "%s val" ADDRX "\n", __func__, val); |
1037 | a496775f | j_mayer | } |
1038 | 4b6d0a4c | j_mayer | #endif
|
1039 | 636aaad7 | j_mayer | ppcemb_timer->pit_reload = val; |
1040 | 4b6d0a4c | j_mayer | start_stop_pit(env, tb_env, 0);
|
1041 | 76a66253 | j_mayer | } |
1042 | 76a66253 | j_mayer | |
1043 | 636aaad7 | j_mayer | target_ulong load_40x_pit (CPUState *env) |
1044 | 76a66253 | j_mayer | { |
1045 | 636aaad7 | j_mayer | return cpu_ppc_load_decr(env);
|
1046 | 76a66253 | j_mayer | } |
1047 | 76a66253 | j_mayer | |
1048 | 76a66253 | j_mayer | void store_booke_tsr (CPUState *env, target_ulong val)
|
1049 | 76a66253 | j_mayer | { |
1050 | 4b6d0a4c | j_mayer | #ifdef PPC_DEBUG_TB
|
1051 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
1052 | aae9366a | j_mayer | fprintf(logfile, "%s: val " ADDRX "\n", __func__, val); |
1053 | 4b6d0a4c | j_mayer | } |
1054 | 4b6d0a4c | j_mayer | #endif
|
1055 | 4b6d0a4c | j_mayer | env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
|
1056 | 4b6d0a4c | j_mayer | if (val & 0x80000000) |
1057 | 4b6d0a4c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);
|
1058 | 636aaad7 | j_mayer | } |
1059 | 636aaad7 | j_mayer | |
1060 | 636aaad7 | j_mayer | void store_booke_tcr (CPUState *env, target_ulong val)
|
1061 | 636aaad7 | j_mayer | { |
1062 | 4b6d0a4c | j_mayer | ppc_tb_t *tb_env; |
1063 | 4b6d0a4c | j_mayer | |
1064 | 4b6d0a4c | j_mayer | tb_env = env->tb_env; |
1065 | 4b6d0a4c | j_mayer | #ifdef PPC_DEBUG_TB
|
1066 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
1067 | aae9366a | j_mayer | fprintf(logfile, "%s: val " ADDRX "\n", __func__, val); |
1068 | 4b6d0a4c | j_mayer | } |
1069 | 4b6d0a4c | j_mayer | #endif
|
1070 | 4b6d0a4c | j_mayer | env->spr[SPR_40x_TCR] = val & 0xFFC00000;
|
1071 | 4b6d0a4c | j_mayer | start_stop_pit(env, tb_env, 1);
|
1072 | 8ecc7913 | j_mayer | cpu_4xx_wdt_cb(env); |
1073 | 636aaad7 | j_mayer | } |
1074 | 636aaad7 | j_mayer | |
1075 | 4b6d0a4c | j_mayer | static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq) |
1076 | 4b6d0a4c | j_mayer | { |
1077 | 4b6d0a4c | j_mayer | CPUState *env = opaque; |
1078 | 4b6d0a4c | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
1079 | 4b6d0a4c | j_mayer | |
1080 | 4b6d0a4c | j_mayer | #ifdef PPC_DEBUG_TB
|
1081 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
1082 | aae9366a | j_mayer | fprintf(logfile, "%s set new frequency to %" PRIu32 "\n", __func__, |
1083 | aae9366a | j_mayer | freq); |
1084 | 4b6d0a4c | j_mayer | } |
1085 | 4b6d0a4c | j_mayer | #endif
|
1086 | 4b6d0a4c | j_mayer | tb_env->tb_freq = freq; |
1087 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
1088 | 4b6d0a4c | j_mayer | /* XXX: we should also update all timers */
|
1089 | 4b6d0a4c | j_mayer | } |
1090 | 4b6d0a4c | j_mayer | |
1091 | 8ecc7913 | j_mayer | clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq) |
1092 | 636aaad7 | j_mayer | { |
1093 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
1094 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
1095 | 636aaad7 | j_mayer | |
1096 | 8ecc7913 | j_mayer | tb_env = qemu_mallocz(sizeof(ppc_tb_t));
|
1097 | 4b6d0a4c | j_mayer | if (tb_env == NULL) { |
1098 | 8ecc7913 | j_mayer | return NULL; |
1099 | 4b6d0a4c | j_mayer | } |
1100 | 8ecc7913 | j_mayer | env->tb_env = tb_env; |
1101 | 636aaad7 | j_mayer | ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
|
1102 | 8ecc7913 | j_mayer | tb_env->tb_freq = freq; |
1103 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
1104 | 636aaad7 | j_mayer | tb_env->opaque = ppcemb_timer; |
1105 | 4b6d0a4c | j_mayer | #ifdef PPC_DEBUG_TB
|
1106 | 4b6d0a4c | j_mayer | if (loglevel != 0) { |
1107 | aae9366a | j_mayer | fprintf(logfile, "%s freq %" PRIu32 "\n", __func__, freq); |
1108 | 8ecc7913 | j_mayer | } |
1109 | 4b6d0a4c | j_mayer | #endif
|
1110 | 636aaad7 | j_mayer | if (ppcemb_timer != NULL) { |
1111 | 636aaad7 | j_mayer | /* We use decr timer for PIT */
|
1112 | 636aaad7 | j_mayer | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); |
1113 | 636aaad7 | j_mayer | ppcemb_timer->fit_timer = |
1114 | 636aaad7 | j_mayer | qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env); |
1115 | 636aaad7 | j_mayer | ppcemb_timer->wdt_timer = |
1116 | 636aaad7 | j_mayer | qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env); |
1117 | 636aaad7 | j_mayer | } |
1118 | 8ecc7913 | j_mayer | |
1119 | 4b6d0a4c | j_mayer | return &ppc_emb_set_tb_clk;
|
1120 | 76a66253 | j_mayer | } |
1121 | 76a66253 | j_mayer | |
1122 | 2e719ba3 | j_mayer | /*****************************************************************************/
|
1123 | 2e719ba3 | j_mayer | /* Embedded PowerPC Device Control Registers */
|
1124 | 2e719ba3 | j_mayer | typedef struct ppc_dcrn_t ppc_dcrn_t; |
1125 | 2e719ba3 | j_mayer | struct ppc_dcrn_t {
|
1126 | 2e719ba3 | j_mayer | dcr_read_cb dcr_read; |
1127 | 2e719ba3 | j_mayer | dcr_write_cb dcr_write; |
1128 | 2e719ba3 | j_mayer | void *opaque;
|
1129 | 2e719ba3 | j_mayer | }; |
1130 | 2e719ba3 | j_mayer | |
1131 | a750fc0b | j_mayer | /* XXX: on 460, DCR addresses are 32 bits wide,
|
1132 | a750fc0b | j_mayer | * using DCRIPR to get the 22 upper bits of the DCR address
|
1133 | a750fc0b | j_mayer | */
|
1134 | 2e719ba3 | j_mayer | #define DCRN_NB 1024 |
1135 | 2e719ba3 | j_mayer | struct ppc_dcr_t {
|
1136 | 2e719ba3 | j_mayer | ppc_dcrn_t dcrn[DCRN_NB]; |
1137 | 2e719ba3 | j_mayer | int (*read_error)(int dcrn); |
1138 | 2e719ba3 | j_mayer | int (*write_error)(int dcrn); |
1139 | 2e719ba3 | j_mayer | }; |
1140 | 2e719ba3 | j_mayer | |
1141 | 2e719ba3 | j_mayer | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) |
1142 | 2e719ba3 | j_mayer | { |
1143 | 2e719ba3 | j_mayer | ppc_dcrn_t *dcr; |
1144 | 2e719ba3 | j_mayer | |
1145 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1146 | 2e719ba3 | j_mayer | goto error;
|
1147 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1148 | 2e719ba3 | j_mayer | if (dcr->dcr_read == NULL) |
1149 | 2e719ba3 | j_mayer | goto error;
|
1150 | 2e719ba3 | j_mayer | *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); |
1151 | 2e719ba3 | j_mayer | |
1152 | 2e719ba3 | j_mayer | return 0; |
1153 | 2e719ba3 | j_mayer | |
1154 | 2e719ba3 | j_mayer | error:
|
1155 | 2e719ba3 | j_mayer | if (dcr_env->read_error != NULL) |
1156 | 2e719ba3 | j_mayer | return (*dcr_env->read_error)(dcrn);
|
1157 | 2e719ba3 | j_mayer | |
1158 | 2e719ba3 | j_mayer | return -1; |
1159 | 2e719ba3 | j_mayer | } |
1160 | 2e719ba3 | j_mayer | |
1161 | 2e719ba3 | j_mayer | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) |
1162 | 2e719ba3 | j_mayer | { |
1163 | 2e719ba3 | j_mayer | ppc_dcrn_t *dcr; |
1164 | 2e719ba3 | j_mayer | |
1165 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1166 | 2e719ba3 | j_mayer | goto error;
|
1167 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1168 | 2e719ba3 | j_mayer | if (dcr->dcr_write == NULL) |
1169 | 2e719ba3 | j_mayer | goto error;
|
1170 | 2e719ba3 | j_mayer | (*dcr->dcr_write)(dcr->opaque, dcrn, val); |
1171 | 2e719ba3 | j_mayer | |
1172 | 2e719ba3 | j_mayer | return 0; |
1173 | 2e719ba3 | j_mayer | |
1174 | 2e719ba3 | j_mayer | error:
|
1175 | 2e719ba3 | j_mayer | if (dcr_env->write_error != NULL) |
1176 | 2e719ba3 | j_mayer | return (*dcr_env->write_error)(dcrn);
|
1177 | 2e719ba3 | j_mayer | |
1178 | 2e719ba3 | j_mayer | return -1; |
1179 | 2e719ba3 | j_mayer | } |
1180 | 2e719ba3 | j_mayer | |
1181 | 2e719ba3 | j_mayer | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
1182 | 2e719ba3 | j_mayer | dcr_read_cb dcr_read, dcr_write_cb dcr_write) |
1183 | 2e719ba3 | j_mayer | { |
1184 | 2e719ba3 | j_mayer | ppc_dcr_t *dcr_env; |
1185 | 2e719ba3 | j_mayer | ppc_dcrn_t *dcr; |
1186 | 2e719ba3 | j_mayer | |
1187 | 2e719ba3 | j_mayer | dcr_env = env->dcr_env; |
1188 | 2e719ba3 | j_mayer | if (dcr_env == NULL) |
1189 | 2e719ba3 | j_mayer | return -1; |
1190 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1191 | 2e719ba3 | j_mayer | return -1; |
1192 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1193 | 2e719ba3 | j_mayer | if (dcr->opaque != NULL || |
1194 | 2e719ba3 | j_mayer | dcr->dcr_read != NULL ||
|
1195 | 2e719ba3 | j_mayer | dcr->dcr_write != NULL)
|
1196 | 2e719ba3 | j_mayer | return -1; |
1197 | 2e719ba3 | j_mayer | dcr->opaque = opaque; |
1198 | 2e719ba3 | j_mayer | dcr->dcr_read = dcr_read; |
1199 | 2e719ba3 | j_mayer | dcr->dcr_write = dcr_write; |
1200 | 2e719ba3 | j_mayer | |
1201 | 2e719ba3 | j_mayer | return 0; |
1202 | 2e719ba3 | j_mayer | } |
1203 | 2e719ba3 | j_mayer | |
1204 | 2e719ba3 | j_mayer | int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), |
1205 | 2e719ba3 | j_mayer | int (*write_error)(int dcrn)) |
1206 | 2e719ba3 | j_mayer | { |
1207 | 2e719ba3 | j_mayer | ppc_dcr_t *dcr_env; |
1208 | 2e719ba3 | j_mayer | |
1209 | 2e719ba3 | j_mayer | dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
|
1210 | 2e719ba3 | j_mayer | if (dcr_env == NULL) |
1211 | 2e719ba3 | j_mayer | return -1; |
1212 | 2e719ba3 | j_mayer | dcr_env->read_error = read_error; |
1213 | 2e719ba3 | j_mayer | dcr_env->write_error = write_error; |
1214 | 2e719ba3 | j_mayer | env->dcr_env = dcr_env; |
1215 | 2e719ba3 | j_mayer | |
1216 | 2e719ba3 | j_mayer | return 0; |
1217 | 2e719ba3 | j_mayer | } |
1218 | 2e719ba3 | j_mayer | |
1219 | 9fddaa0c | bellard | #if 0
|
1220 | 9fddaa0c | bellard | /*****************************************************************************/
|
1221 | 9fddaa0c | bellard | /* Handle system reset (for now, just stop emulation) */
|
1222 | 9fddaa0c | bellard | void cpu_ppc_reset (CPUState *env)
|
1223 | 9fddaa0c | bellard | {
|
1224 | 9fddaa0c | bellard | printf("Reset asked... Stop emulation\n");
|
1225 | 9fddaa0c | bellard | abort();
|
1226 | 9fddaa0c | bellard | }
|
1227 | 9fddaa0c | bellard | #endif
|
1228 | 9fddaa0c | bellard | |
1229 | 64201201 | bellard | /*****************************************************************************/
|
1230 | 64201201 | bellard | /* Debug port */
|
1231 | fd0bbb12 | bellard | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
1232 | 64201201 | bellard | { |
1233 | 64201201 | bellard | addr &= 0xF;
|
1234 | 64201201 | bellard | switch (addr) {
|
1235 | 64201201 | bellard | case 0: |
1236 | 64201201 | bellard | printf("%c", val);
|
1237 | 64201201 | bellard | break;
|
1238 | 64201201 | bellard | case 1: |
1239 | 64201201 | bellard | printf("\n");
|
1240 | 64201201 | bellard | fflush(stdout); |
1241 | 64201201 | bellard | break;
|
1242 | 64201201 | bellard | case 2: |
1243 | aae9366a | j_mayer | printf("Set loglevel to %04" PRIx32 "\n", val); |
1244 | fd0bbb12 | bellard | cpu_set_log(val | 0x100);
|
1245 | 64201201 | bellard | break;
|
1246 | 64201201 | bellard | } |
1247 | 64201201 | bellard | } |
1248 | 64201201 | bellard | |
1249 | 64201201 | bellard | /*****************************************************************************/
|
1250 | 64201201 | bellard | /* NVRAM helpers */
|
1251 | 3cbee15b | j_mayer | static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr) |
1252 | 64201201 | bellard | { |
1253 | 3cbee15b | j_mayer | return (*nvram->read_fn)(nvram->opaque, addr);;
|
1254 | 64201201 | bellard | } |
1255 | 64201201 | bellard | |
1256 | 3cbee15b | j_mayer | static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val) |
1257 | 64201201 | bellard | { |
1258 | 3cbee15b | j_mayer | (*nvram->write_fn)(nvram->opaque, addr, val); |
1259 | 64201201 | bellard | } |
1260 | 64201201 | bellard | |
1261 | 3cbee15b | j_mayer | void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value)
|
1262 | 64201201 | bellard | { |
1263 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value); |
1264 | 64201201 | bellard | } |
1265 | 64201201 | bellard | |
1266 | 3cbee15b | j_mayer | uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr) |
1267 | 3cbee15b | j_mayer | { |
1268 | 3cbee15b | j_mayer | return nvram_read(nvram, addr);
|
1269 | 3cbee15b | j_mayer | } |
1270 | 3cbee15b | j_mayer | |
1271 | 3cbee15b | j_mayer | void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value)
|
1272 | 3cbee15b | j_mayer | { |
1273 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value >> 8);
|
1274 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 1, value & 0xFF); |
1275 | 3cbee15b | j_mayer | } |
1276 | 3cbee15b | j_mayer | |
1277 | 3cbee15b | j_mayer | uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr) |
1278 | 64201201 | bellard | { |
1279 | 64201201 | bellard | uint16_t tmp; |
1280 | 64201201 | bellard | |
1281 | 3cbee15b | j_mayer | tmp = nvram_read(nvram, addr) << 8;
|
1282 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 1);
|
1283 | 3cbee15b | j_mayer | |
1284 | 64201201 | bellard | return tmp;
|
1285 | 64201201 | bellard | } |
1286 | 64201201 | bellard | |
1287 | 3cbee15b | j_mayer | void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value)
|
1288 | 64201201 | bellard | { |
1289 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value >> 24);
|
1290 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); |
1291 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); |
1292 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 3, value & 0xFF); |
1293 | 64201201 | bellard | } |
1294 | 64201201 | bellard | |
1295 | 3cbee15b | j_mayer | uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) |
1296 | 64201201 | bellard | { |
1297 | 64201201 | bellard | uint32_t tmp; |
1298 | 64201201 | bellard | |
1299 | 3cbee15b | j_mayer | tmp = nvram_read(nvram, addr) << 24;
|
1300 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 1) << 16; |
1301 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 2) << 8; |
1302 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 3);
|
1303 | 76a66253 | j_mayer | |
1304 | 64201201 | bellard | return tmp;
|
1305 | 64201201 | bellard | } |
1306 | 64201201 | bellard | |
1307 | 3cbee15b | j_mayer | void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
|
1308 | 64201201 | bellard | const unsigned char *str, uint32_t max) |
1309 | 64201201 | bellard | { |
1310 | 64201201 | bellard | int i;
|
1311 | 64201201 | bellard | |
1312 | 64201201 | bellard | for (i = 0; i < max && str[i] != '\0'; i++) { |
1313 | 3cbee15b | j_mayer | nvram_write(nvram, addr + i, str[i]); |
1314 | 64201201 | bellard | } |
1315 | 3cbee15b | j_mayer | nvram_write(nvram, addr + i, str[i]); |
1316 | 3cbee15b | j_mayer | nvram_write(nvram, addr + max - 1, '\0'); |
1317 | 64201201 | bellard | } |
1318 | 64201201 | bellard | |
1319 | 3cbee15b | j_mayer | int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max) |
1320 | 64201201 | bellard | { |
1321 | 64201201 | bellard | int i;
|
1322 | 64201201 | bellard | |
1323 | 64201201 | bellard | memset(dst, 0, max);
|
1324 | 64201201 | bellard | for (i = 0; i < max; i++) { |
1325 | 64201201 | bellard | dst[i] = NVRAM_get_byte(nvram, addr + i); |
1326 | 64201201 | bellard | if (dst[i] == '\0') |
1327 | 64201201 | bellard | break;
|
1328 | 64201201 | bellard | } |
1329 | 64201201 | bellard | |
1330 | 64201201 | bellard | return i;
|
1331 | 64201201 | bellard | } |
1332 | 64201201 | bellard | |
1333 | 64201201 | bellard | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
|
1334 | 64201201 | bellard | { |
1335 | 64201201 | bellard | uint16_t tmp; |
1336 | 64201201 | bellard | uint16_t pd, pd1, pd2; |
1337 | 64201201 | bellard | |
1338 | 64201201 | bellard | tmp = prev >> 8;
|
1339 | 64201201 | bellard | pd = prev ^ value; |
1340 | 64201201 | bellard | pd1 = pd & 0x000F;
|
1341 | 64201201 | bellard | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
1342 | 64201201 | bellard | tmp ^= (pd1 << 3) | (pd1 << 8); |
1343 | 64201201 | bellard | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
1344 | 64201201 | bellard | |
1345 | 64201201 | bellard | return tmp;
|
1346 | 64201201 | bellard | } |
1347 | 64201201 | bellard | |
1348 | 3cbee15b | j_mayer | uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count) |
1349 | 64201201 | bellard | { |
1350 | 64201201 | bellard | uint32_t i; |
1351 | 64201201 | bellard | uint16_t crc = 0xFFFF;
|
1352 | 64201201 | bellard | int odd;
|
1353 | 64201201 | bellard | |
1354 | 64201201 | bellard | odd = count & 1;
|
1355 | 64201201 | bellard | count &= ~1;
|
1356 | 64201201 | bellard | for (i = 0; i != count; i++) { |
1357 | 76a66253 | j_mayer | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
1358 | 64201201 | bellard | } |
1359 | 64201201 | bellard | if (odd) {
|
1360 | 76a66253 | j_mayer | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
|
1361 | 64201201 | bellard | } |
1362 | 64201201 | bellard | |
1363 | 64201201 | bellard | return crc;
|
1364 | 64201201 | bellard | } |
1365 | 64201201 | bellard | |
1366 | fd0bbb12 | bellard | #define CMDLINE_ADDR 0x017ff000 |
1367 | fd0bbb12 | bellard | |
1368 | 3cbee15b | j_mayer | int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
|
1369 | 64201201 | bellard | const unsigned char *arch, |
1370 | 64201201 | bellard | uint32_t RAM_size, int boot_device,
|
1371 | 64201201 | bellard | uint32_t kernel_image, uint32_t kernel_size, |
1372 | fd0bbb12 | bellard | const char *cmdline, |
1373 | 64201201 | bellard | uint32_t initrd_image, uint32_t initrd_size, |
1374 | fd0bbb12 | bellard | uint32_t NVRAM_image, |
1375 | fd0bbb12 | bellard | int width, int height, int depth) |
1376 | 64201201 | bellard | { |
1377 | 64201201 | bellard | uint16_t crc; |
1378 | 64201201 | bellard | |
1379 | 64201201 | bellard | /* Set parameters for Open Hack'Ware BIOS */
|
1380 | 64201201 | bellard | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
1381 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
1382 | 64201201 | bellard | NVRAM_set_word(nvram, 0x14, NVRAM_size);
|
1383 | 64201201 | bellard | NVRAM_set_string(nvram, 0x20, arch, 16); |
1384 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x30, RAM_size);
|
1385 | 64201201 | bellard | NVRAM_set_byte(nvram, 0x34, boot_device);
|
1386 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x38, kernel_image);
|
1387 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x3C, kernel_size);
|
1388 | fd0bbb12 | bellard | if (cmdline) {
|
1389 | fd0bbb12 | bellard | /* XXX: put the cmdline in NVRAM too ? */
|
1390 | fd0bbb12 | bellard | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
1391 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
1392 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
|
1393 | fd0bbb12 | bellard | } else {
|
1394 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, 0); |
1395 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, 0); |
1396 | fd0bbb12 | bellard | } |
1397 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x48, initrd_image);
|
1398 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x4C, initrd_size);
|
1399 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x50, NVRAM_image);
|
1400 | fd0bbb12 | bellard | |
1401 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x54, width);
|
1402 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x56, height);
|
1403 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x58, depth);
|
1404 | fd0bbb12 | bellard | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
1405 | 3cbee15b | j_mayer | NVRAM_set_word(nvram, 0xFC, crc);
|
1406 | 64201201 | bellard | |
1407 | 64201201 | bellard | return 0; |
1408 | a541f297 | bellard | } |