root / target-ppc / cpu.h @ 9b605b9e
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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation cpu definitions for qemu.
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | #if !defined (__CPU_PPC_H__)
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21 | 79aceca5 | bellard | #define __CPU_PPC_H__
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22 | 79aceca5 | bellard | |
23 | 3fc6c082 | bellard | #include "config.h" |
24 | de270b3c | j_mayer | #include <inttypes.h> |
25 | 3fc6c082 | bellard | |
26 | a4f30719 | j_mayer | //#define PPC_EMULATE_32BITS_HYPV
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27 | a4f30719 | j_mayer | |
28 | 76a66253 | j_mayer | #if defined (TARGET_PPC64)
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29 | 3cd7d1dd | j_mayer | /* PowerPC 64 definitions */
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30 | 76a66253 | j_mayer | typedef uint64_t ppc_gpr_t;
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31 | 0487d6a8 | j_mayer | #define TARGET_GPR_BITS 64 |
32 | d9d7210c | j_mayer | #define TARGET_LONG_BITS 64 |
33 | 35cdaad6 | j_mayer | #define TARGET_PAGE_BITS 12 |
34 | 3cd7d1dd | j_mayer | |
35 | 3cd7d1dd | j_mayer | #else /* defined (TARGET_PPC64) */ |
36 | 3cd7d1dd | j_mayer | /* PowerPC 32 definitions */
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37 | d9d7210c | j_mayer | #if (HOST_LONG_BITS >= 64) |
38 | d9d7210c | j_mayer | /* When using 64 bits temporary registers,
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39 | d9d7210c | j_mayer | * we can use 64 bits GPR with no extra cost
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40 | 3cd7d1dd | j_mayer | * It's even an optimization as this will prevent
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41 | d9d7210c | j_mayer | * the compiler to do unuseful masking in the micro-ops.
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42 | d9d7210c | j_mayer | */
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43 | d9d7210c | j_mayer | typedef uint64_t ppc_gpr_t;
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44 | d9d7210c | j_mayer | #define TARGET_GPR_BITS 64 |
45 | 3cd7d1dd | j_mayer | #else /* (HOST_LONG_BITS >= 64) */ |
46 | 76a66253 | j_mayer | typedef uint32_t ppc_gpr_t;
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47 | 0487d6a8 | j_mayer | #define TARGET_GPR_BITS 32 |
48 | 3cd7d1dd | j_mayer | #endif /* (HOST_LONG_BITS >= 64) */ |
49 | 3cd7d1dd | j_mayer | |
50 | d9d7210c | j_mayer | #define TARGET_LONG_BITS 32 |
51 | 3cd7d1dd | j_mayer | |
52 | 3cd7d1dd | j_mayer | #if defined(TARGET_PPCEMB)
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53 | 3cd7d1dd | j_mayer | /* Specific definitions for PowerPC embedded */
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54 | 3cd7d1dd | j_mayer | /* BookE have 36 bits physical address space */
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55 | 3cd7d1dd | j_mayer | #define TARGET_PHYS_ADDR_BITS 64 |
56 | 3cd7d1dd | j_mayer | #if defined(CONFIG_USER_ONLY)
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57 | 3cd7d1dd | j_mayer | /* It looks like a lot of Linux programs assume page size
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58 | 3cd7d1dd | j_mayer | * is 4kB long. This is evil, but we have to deal with it...
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59 | 3cd7d1dd | j_mayer | */
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60 | 35cdaad6 | j_mayer | #define TARGET_PAGE_BITS 12 |
61 | 3cd7d1dd | j_mayer | #else /* defined(CONFIG_USER_ONLY) */ |
62 | 3cd7d1dd | j_mayer | /* Pages can be 1 kB small */
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63 | 3cd7d1dd | j_mayer | #define TARGET_PAGE_BITS 10 |
64 | 3cd7d1dd | j_mayer | #endif /* defined(CONFIG_USER_ONLY) */ |
65 | 3cd7d1dd | j_mayer | #else /* defined(TARGET_PPCEMB) */ |
66 | 3cd7d1dd | j_mayer | /* "standard" PowerPC 32 definitions */
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67 | 3cd7d1dd | j_mayer | #define TARGET_PAGE_BITS 12 |
68 | 3cd7d1dd | j_mayer | #endif /* defined(TARGET_PPCEMB) */ |
69 | 3cd7d1dd | j_mayer | |
70 | 3cd7d1dd | j_mayer | #endif /* defined (TARGET_PPC64) */ |
71 | 3cf1e035 | bellard | |
72 | 9b605b9e | pbrook | /* A ppc_gpr_t should not be printed directly as the high bits may be
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73 | 9b605b9e | pbrook | garbage. It should always be cast to a target_ulong first. */
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74 | 9b605b9e | pbrook | #define REGX TARGET_FMT_lx
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75 | 9b605b9e | pbrook | |
76 | 79aceca5 | bellard | #include "cpu-defs.h" |
77 | 79aceca5 | bellard | |
78 | e96efcfc | j_mayer | #define ADDRX TARGET_FMT_lx
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79 | e96efcfc | j_mayer | #define PADDRX TARGET_FMT_plx
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80 | e96efcfc | j_mayer | |
81 | 79aceca5 | bellard | #include <setjmp.h> |
82 | 79aceca5 | bellard | |
83 | 4ecc3190 | bellard | #include "softfloat.h" |
84 | 4ecc3190 | bellard | |
85 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
86 | 1fddef4b | bellard | |
87 | 76a66253 | j_mayer | #if defined (TARGET_PPC64)
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88 | 76a66253 | j_mayer | #define ELF_MACHINE EM_PPC64
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89 | 76a66253 | j_mayer | #else
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90 | 76a66253 | j_mayer | #define ELF_MACHINE EM_PPC
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91 | 76a66253 | j_mayer | #endif
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92 | 9042c0e2 | ths | |
93 | 3fc6c082 | bellard | /*****************************************************************************/
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94 | a750fc0b | j_mayer | /* MMU model */
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95 | 7820dbf3 | j_mayer | typedef enum powerpc_mmu_t powerpc_mmu_t; |
96 | 7820dbf3 | j_mayer | enum powerpc_mmu_t {
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97 | add78955 | j_mayer | POWERPC_MMU_UNKNOWN = 0x00000000,
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98 | a750fc0b | j_mayer | /* Standard 32 bits PowerPC MMU */
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99 | add78955 | j_mayer | POWERPC_MMU_32B = 0x00000001,
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100 | a750fc0b | j_mayer | /* PowerPC 6xx MMU with software TLB */
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101 | add78955 | j_mayer | POWERPC_MMU_SOFT_6xx = 0x00000002,
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102 | a750fc0b | j_mayer | /* PowerPC 74xx MMU with software TLB */
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103 | add78955 | j_mayer | POWERPC_MMU_SOFT_74xx = 0x00000003,
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104 | a750fc0b | j_mayer | /* PowerPC 4xx MMU with software TLB */
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105 | add78955 | j_mayer | POWERPC_MMU_SOFT_4xx = 0x00000004,
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106 | a750fc0b | j_mayer | /* PowerPC 4xx MMU with software TLB and zones protections */
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107 | add78955 | j_mayer | POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
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108 | b4095fed | j_mayer | /* PowerPC MMU in real mode only */
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109 | add78955 | j_mayer | POWERPC_MMU_REAL = 0x00000006,
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110 | b4095fed | j_mayer | /* Freescale MPC8xx MMU model */
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111 | add78955 | j_mayer | POWERPC_MMU_MPC8xx = 0x00000007,
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112 | a750fc0b | j_mayer | /* BookE MMU model */
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113 | add78955 | j_mayer | POWERPC_MMU_BOOKE = 0x00000008,
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114 | a750fc0b | j_mayer | /* BookE FSL MMU model */
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115 | add78955 | j_mayer | POWERPC_MMU_BOOKE_FSL = 0x00000009,
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116 | faadf50e | j_mayer | /* PowerPC 601 MMU model (specific BATs format) */
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117 | add78955 | j_mayer | POWERPC_MMU_601 = 0x0000000A,
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118 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
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119 | add78955 | j_mayer | #define POWERPC_MMU_64 0x00010000 |
120 | 12de9a39 | j_mayer | /* 64 bits PowerPC MMU */
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121 | add78955 | j_mayer | POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
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122 | add78955 | j_mayer | /* 620 variant (no segment exceptions) */
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123 | add78955 | j_mayer | POWERPC_MMU_620 = POWERPC_MMU_64 | 0x00000002,
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124 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
125 | 3fc6c082 | bellard | }; |
126 | 3fc6c082 | bellard | |
127 | 3fc6c082 | bellard | /*****************************************************************************/
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128 | a750fc0b | j_mayer | /* Exception model */
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129 | 7820dbf3 | j_mayer | typedef enum powerpc_excp_t powerpc_excp_t; |
130 | 7820dbf3 | j_mayer | enum powerpc_excp_t {
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131 | a750fc0b | j_mayer | POWERPC_EXCP_UNKNOWN = 0,
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132 | 3fc6c082 | bellard | /* Standard PowerPC exception model */
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133 | a750fc0b | j_mayer | POWERPC_EXCP_STD, |
134 | 2662a059 | j_mayer | /* PowerPC 40x exception model */
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135 | a750fc0b | j_mayer | POWERPC_EXCP_40x, |
136 | 2662a059 | j_mayer | /* PowerPC 601 exception model */
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137 | a750fc0b | j_mayer | POWERPC_EXCP_601, |
138 | 2662a059 | j_mayer | /* PowerPC 602 exception model */
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139 | a750fc0b | j_mayer | POWERPC_EXCP_602, |
140 | 2662a059 | j_mayer | /* PowerPC 603 exception model */
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141 | a750fc0b | j_mayer | POWERPC_EXCP_603, |
142 | a750fc0b | j_mayer | /* PowerPC 603e exception model */
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143 | a750fc0b | j_mayer | POWERPC_EXCP_603E, |
144 | a750fc0b | j_mayer | /* PowerPC G2 exception model */
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145 | a750fc0b | j_mayer | POWERPC_EXCP_G2, |
146 | 2662a059 | j_mayer | /* PowerPC 604 exception model */
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147 | a750fc0b | j_mayer | POWERPC_EXCP_604, |
148 | 2662a059 | j_mayer | /* PowerPC 7x0 exception model */
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149 | a750fc0b | j_mayer | POWERPC_EXCP_7x0, |
150 | 2662a059 | j_mayer | /* PowerPC 7x5 exception model */
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151 | a750fc0b | j_mayer | POWERPC_EXCP_7x5, |
152 | 2662a059 | j_mayer | /* PowerPC 74xx exception model */
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153 | a750fc0b | j_mayer | POWERPC_EXCP_74xx, |
154 | 2662a059 | j_mayer | /* BookE exception model */
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155 | a750fc0b | j_mayer | POWERPC_EXCP_BOOKE, |
156 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
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157 | 00af685f | j_mayer | /* PowerPC 970 exception model */
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158 | 00af685f | j_mayer | POWERPC_EXCP_970, |
159 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
160 | a750fc0b | j_mayer | }; |
161 | a750fc0b | j_mayer | |
162 | a750fc0b | j_mayer | /*****************************************************************************/
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163 | e1833e1f | j_mayer | /* Exception vectors definitions */
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164 | e1833e1f | j_mayer | enum {
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165 | e1833e1f | j_mayer | POWERPC_EXCP_NONE = -1,
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166 | e1833e1f | j_mayer | /* The 64 first entries are used by the PowerPC embedded specification */
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167 | e1833e1f | j_mayer | POWERPC_EXCP_CRITICAL = 0, /* Critical input */ |
168 | e1833e1f | j_mayer | POWERPC_EXCP_MCHECK = 1, /* Machine check exception */ |
169 | e1833e1f | j_mayer | POWERPC_EXCP_DSI = 2, /* Data storage exception */ |
170 | e1833e1f | j_mayer | POWERPC_EXCP_ISI = 3, /* Instruction storage exception */ |
171 | e1833e1f | j_mayer | POWERPC_EXCP_EXTERNAL = 4, /* External input */ |
172 | e1833e1f | j_mayer | POWERPC_EXCP_ALIGN = 5, /* Alignment exception */ |
173 | e1833e1f | j_mayer | POWERPC_EXCP_PROGRAM = 6, /* Program exception */ |
174 | e1833e1f | j_mayer | POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */ |
175 | e1833e1f | j_mayer | POWERPC_EXCP_SYSCALL = 8, /* System call exception */ |
176 | e1833e1f | j_mayer | POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */ |
177 | e1833e1f | j_mayer | POWERPC_EXCP_DECR = 10, /* Decrementer exception */ |
178 | e1833e1f | j_mayer | POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */ |
179 | e1833e1f | j_mayer | POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */ |
180 | b4095fed | j_mayer | POWERPC_EXCP_DTLB = 13, /* Data TLB miss */ |
181 | b4095fed | j_mayer | POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */ |
182 | e1833e1f | j_mayer | POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */ |
183 | e1833e1f | j_mayer | /* Vectors 16 to 31 are reserved */
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184 | e1833e1f | j_mayer | POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */ |
185 | e1833e1f | j_mayer | POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */ |
186 | e1833e1f | j_mayer | POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */ |
187 | e1833e1f | j_mayer | POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */ |
188 | e1833e1f | j_mayer | POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */ |
189 | e1833e1f | j_mayer | POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */ |
190 | e1833e1f | j_mayer | /* Vectors 38 to 63 are reserved */
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191 | e1833e1f | j_mayer | /* Exceptions defined in the PowerPC server specification */
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192 | e1833e1f | j_mayer | POWERPC_EXCP_RESET = 64, /* System reset exception */ |
193 | e1833e1f | j_mayer | POWERPC_EXCP_DSEG = 65, /* Data segment exception */ |
194 | e1833e1f | j_mayer | POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */ |
195 | e1833e1f | j_mayer | POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */ |
196 | e1833e1f | j_mayer | POWERPC_EXCP_TRACE = 68, /* Trace exception */ |
197 | e1833e1f | j_mayer | POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */ |
198 | e1833e1f | j_mayer | POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */ |
199 | e1833e1f | j_mayer | POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */ |
200 | e1833e1f | j_mayer | POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */ |
201 | e1833e1f | j_mayer | POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */ |
202 | e1833e1f | j_mayer | /* 40x specific exceptions */
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203 | e1833e1f | j_mayer | POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */ |
204 | e1833e1f | j_mayer | /* 601 specific exceptions */
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205 | e1833e1f | j_mayer | POWERPC_EXCP_IO = 75, /* IO error exception */ |
206 | e1833e1f | j_mayer | POWERPC_EXCP_RUNM = 76, /* Run mode exception */ |
207 | e1833e1f | j_mayer | /* 602 specific exceptions */
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208 | e1833e1f | j_mayer | POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */ |
209 | e1833e1f | j_mayer | /* 602/603 specific exceptions */
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210 | b4095fed | j_mayer | POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */ |
211 | e1833e1f | j_mayer | POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */ |
212 | e1833e1f | j_mayer | POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */ |
213 | e1833e1f | j_mayer | /* Exceptions available on most PowerPC */
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214 | e1833e1f | j_mayer | POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */ |
215 | b4095fed | j_mayer | POWERPC_EXCP_DABR = 82, /* Data address breakpoint */ |
216 | b4095fed | j_mayer | POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */ |
217 | b4095fed | j_mayer | POWERPC_EXCP_SMI = 84, /* System management interrupt */ |
218 | b4095fed | j_mayer | POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */ |
219 | e1833e1f | j_mayer | /* 7xx/74xx specific exceptions */
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220 | b4095fed | j_mayer | POWERPC_EXCP_THERM = 86, /* Thermal interrupt */ |
221 | e1833e1f | j_mayer | /* 74xx specific exceptions */
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222 | b4095fed | j_mayer | POWERPC_EXCP_VPUA = 87, /* Vector assist exception */ |
223 | e1833e1f | j_mayer | /* 970FX specific exceptions */
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224 | b4095fed | j_mayer | POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */ |
225 | b4095fed | j_mayer | POWERPC_EXCP_MAINT = 89, /* Maintenance exception */ |
226 | b4095fed | j_mayer | /* Freescale embeded cores specific exceptions */
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227 | b4095fed | j_mayer | POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */ |
228 | b4095fed | j_mayer | POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */ |
229 | b4095fed | j_mayer | POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */ |
230 | b4095fed | j_mayer | POWERPC_EXCP_DTLBE = 93, /* Data TLB error */ |
231 | e1833e1f | j_mayer | /* EOL */
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232 | e1833e1f | j_mayer | POWERPC_EXCP_NB = 96,
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233 | e1833e1f | j_mayer | /* Qemu exceptions: used internally during code translation */
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234 | e1833e1f | j_mayer | POWERPC_EXCP_STOP = 0x200, /* stop translation */ |
235 | e1833e1f | j_mayer | POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ |
236 | e1833e1f | j_mayer | /* Qemu exceptions: special cases we want to stop translation */
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237 | e1833e1f | j_mayer | POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ |
238 | e1833e1f | j_mayer | POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ |
239 | e1833e1f | j_mayer | }; |
240 | e1833e1f | j_mayer | |
241 | e1833e1f | j_mayer | /* Exceptions error codes */
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242 | e1833e1f | j_mayer | enum {
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243 | e1833e1f | j_mayer | /* Exception subtypes for POWERPC_EXCP_ALIGN */
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244 | e1833e1f | j_mayer | POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
245 | e1833e1f | j_mayer | POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
246 | e1833e1f | j_mayer | POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
247 | e1833e1f | j_mayer | POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
248 | e1833e1f | j_mayer | POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
249 | e1833e1f | j_mayer | POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
250 | e1833e1f | j_mayer | /* Exception subtypes for POWERPC_EXCP_PROGRAM */
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251 | e1833e1f | j_mayer | /* FP exceptions */
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252 | e1833e1f | j_mayer | POWERPC_EXCP_FP = 0x10,
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253 | e1833e1f | j_mayer | POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */ |
254 | e1833e1f | j_mayer | POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */ |
255 | e1833e1f | j_mayer | POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
256 | e1833e1f | j_mayer | POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */ |
257 | 7c58044c | j_mayer | POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */ |
258 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ |
259 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
260 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
261 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
262 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
263 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
264 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
265 | e1833e1f | j_mayer | POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
266 | e1833e1f | j_mayer | /* Invalid instruction */
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267 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL = 0x20,
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268 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
269 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
270 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
271 | e1833e1f | j_mayer | POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
272 | e1833e1f | j_mayer | /* Privileged instruction */
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273 | e1833e1f | j_mayer | POWERPC_EXCP_PRIV = 0x30,
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274 | e1833e1f | j_mayer | POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ |
275 | e1833e1f | j_mayer | POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */ |
276 | e1833e1f | j_mayer | /* Trap */
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277 | e1833e1f | j_mayer | POWERPC_EXCP_TRAP = 0x40,
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278 | e1833e1f | j_mayer | }; |
279 | e1833e1f | j_mayer | |
280 | e1833e1f | j_mayer | /*****************************************************************************/
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281 | a750fc0b | j_mayer | /* Input pins model */
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282 | 7820dbf3 | j_mayer | typedef enum powerpc_input_t powerpc_input_t; |
283 | 7820dbf3 | j_mayer | enum powerpc_input_t {
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284 | a750fc0b | j_mayer | PPC_FLAGS_INPUT_UNKNOWN = 0,
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285 | 2662a059 | j_mayer | /* PowerPC 6xx bus */
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286 | a750fc0b | j_mayer | PPC_FLAGS_INPUT_6xx, |
287 | 2662a059 | j_mayer | /* BookE bus */
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288 | a750fc0b | j_mayer | PPC_FLAGS_INPUT_BookE, |
289 | a750fc0b | j_mayer | /* PowerPC 405 bus */
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290 | a750fc0b | j_mayer | PPC_FLAGS_INPUT_405, |
291 | 2662a059 | j_mayer | /* PowerPC 970 bus */
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292 | a750fc0b | j_mayer | PPC_FLAGS_INPUT_970, |
293 | a750fc0b | j_mayer | /* PowerPC 401 bus */
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294 | a750fc0b | j_mayer | PPC_FLAGS_INPUT_401, |
295 | b4095fed | j_mayer | /* Freescale RCPU bus */
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296 | b4095fed | j_mayer | PPC_FLAGS_INPUT_RCPU, |
297 | 3fc6c082 | bellard | }; |
298 | 3fc6c082 | bellard | |
299 | a750fc0b | j_mayer | #define PPC_INPUT(env) (env->bus_model)
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300 | 3fc6c082 | bellard | |
301 | be147d08 | j_mayer | /*****************************************************************************/
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302 | 3fc6c082 | bellard | typedef struct ppc_def_t ppc_def_t; |
303 | a750fc0b | j_mayer | typedef struct opc_handler_t opc_handler_t; |
304 | 79aceca5 | bellard | |
305 | 3fc6c082 | bellard | /*****************************************************************************/
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306 | 3fc6c082 | bellard | /* Types used to describe some PowerPC registers */
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307 | 3fc6c082 | bellard | typedef struct CPUPPCState CPUPPCState; |
308 | 9fddaa0c | bellard | typedef struct ppc_tb_t ppc_tb_t; |
309 | 3fc6c082 | bellard | typedef struct ppc_spr_t ppc_spr_t; |
310 | 3fc6c082 | bellard | typedef struct ppc_dcr_t ppc_dcr_t; |
311 | a9d9eb8f | j_mayer | typedef union ppc_avr_t ppc_avr_t; |
312 | 1d0a48fb | j_mayer | typedef union ppc_tlb_t ppc_tlb_t; |
313 | 76a66253 | j_mayer | |
314 | 3fc6c082 | bellard | /* SPR access micro-ops generations callbacks */
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315 | 3fc6c082 | bellard | struct ppc_spr_t {
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316 | 3fc6c082 | bellard | void (*uea_read)(void *opaque, int spr_num); |
317 | 3fc6c082 | bellard | void (*uea_write)(void *opaque, int spr_num); |
318 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
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319 | 3fc6c082 | bellard | void (*oea_read)(void *opaque, int spr_num); |
320 | 3fc6c082 | bellard | void (*oea_write)(void *opaque, int spr_num); |
321 | be147d08 | j_mayer | void (*hea_read)(void *opaque, int spr_num); |
322 | be147d08 | j_mayer | void (*hea_write)(void *opaque, int spr_num); |
323 | be147d08 | j_mayer | #endif
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324 | 3fc6c082 | bellard | const unsigned char *name; |
325 | 3fc6c082 | bellard | }; |
326 | 3fc6c082 | bellard | |
327 | 3fc6c082 | bellard | /* Altivec registers (128 bits) */
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328 | a9d9eb8f | j_mayer | union ppc_avr_t {
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329 | a9d9eb8f | j_mayer | uint8_t u8[16];
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330 | a9d9eb8f | j_mayer | uint16_t u16[8];
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331 | a9d9eb8f | j_mayer | uint32_t u32[4];
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332 | a9d9eb8f | j_mayer | uint64_t u64[2];
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333 | 3fc6c082 | bellard | }; |
334 | 9fddaa0c | bellard | |
335 | 3fc6c082 | bellard | /* Software TLB cache */
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336 | 1d0a48fb | j_mayer | typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; |
337 | 1d0a48fb | j_mayer | struct ppc6xx_tlb_t {
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338 | 76a66253 | j_mayer | target_ulong pte0; |
339 | 76a66253 | j_mayer | target_ulong pte1; |
340 | 76a66253 | j_mayer | target_ulong EPN; |
341 | 1d0a48fb | j_mayer | }; |
342 | 1d0a48fb | j_mayer | |
343 | 1d0a48fb | j_mayer | typedef struct ppcemb_tlb_t ppcemb_tlb_t; |
344 | 1d0a48fb | j_mayer | struct ppcemb_tlb_t {
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345 | c55e9aef | j_mayer | target_phys_addr_t RPN; |
346 | 1d0a48fb | j_mayer | target_ulong EPN; |
347 | 76a66253 | j_mayer | target_ulong PID; |
348 | c55e9aef | j_mayer | target_ulong size; |
349 | c55e9aef | j_mayer | uint32_t prot; |
350 | c55e9aef | j_mayer | uint32_t attr; /* Storage attributes */
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351 | 1d0a48fb | j_mayer | }; |
352 | 1d0a48fb | j_mayer | |
353 | 1d0a48fb | j_mayer | union ppc_tlb_t {
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354 | 1d0a48fb | j_mayer | ppc6xx_tlb_t tlb6; |
355 | 1d0a48fb | j_mayer | ppcemb_tlb_t tlbe; |
356 | 3fc6c082 | bellard | }; |
357 | 3fc6c082 | bellard | |
358 | 3fc6c082 | bellard | /*****************************************************************************/
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359 | 3fc6c082 | bellard | /* Machine state register bits definition */
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360 | 76a66253 | j_mayer | #define MSR_SF 63 /* Sixty-four-bit mode hflags */ |
361 | bd928eba | j_mayer | #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */ |
362 | 3fc6c082 | bellard | #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
363 | a4f30719 | j_mayer | #define MSR_SHV 60 /* hypervisor state hflags */ |
364 | 363be49c | j_mayer | #define MSR_CM 31 /* Computation mode for BookE hflags */ |
365 | 363be49c | j_mayer | #define MSR_ICM 30 /* Interrupt computation mode for BookE */ |
366 | a4f30719 | j_mayer | #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */ |
367 | 363be49c | j_mayer | #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ |
368 | d26bfc9a | j_mayer | #define MSR_VR 25 /* altivec available x hflags */ |
369 | d26bfc9a | j_mayer | #define MSR_SPE 25 /* SPE enable for BookE x hflags */ |
370 | 76a66253 | j_mayer | #define MSR_AP 23 /* Access privilege state on 602 hflags */ |
371 | 76a66253 | j_mayer | #define MSR_SA 22 /* Supervisor access mode on 602 hflags */ |
372 | 3fc6c082 | bellard | #define MSR_KEY 19 /* key bit on 603e */ |
373 | 25ba3a68 | j_mayer | #define MSR_POW 18 /* Power management */ |
374 | d26bfc9a | j_mayer | #define MSR_TGPR 17 /* TGPR usage on 602/603 x */ |
375 | d26bfc9a | j_mayer | #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */ |
376 | 3fc6c082 | bellard | #define MSR_ILE 16 /* Interrupt little-endian mode */ |
377 | 3fc6c082 | bellard | #define MSR_EE 15 /* External interrupt enable */ |
378 | 76a66253 | j_mayer | #define MSR_PR 14 /* Problem state hflags */ |
379 | 76a66253 | j_mayer | #define MSR_FP 13 /* Floating point available hflags */ |
380 | 3fc6c082 | bellard | #define MSR_ME 12 /* Machine check interrupt enable */ |
381 | 76a66253 | j_mayer | #define MSR_FE0 11 /* Floating point exception mode 0 hflags */ |
382 | d26bfc9a | j_mayer | #define MSR_SE 10 /* Single-step trace enable x hflags */ |
383 | d26bfc9a | j_mayer | #define MSR_DWE 10 /* Debug wait enable on 405 x */ |
384 | d26bfc9a | j_mayer | #define MSR_UBLE 10 /* User BTB lock enable on e500 x */ |
385 | d26bfc9a | j_mayer | #define MSR_BE 9 /* Branch trace enable x hflags */ |
386 | d26bfc9a | j_mayer | #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ |
387 | 76a66253 | j_mayer | #define MSR_FE1 8 /* Floating point exception mode 1 hflags */ |
388 | 3fc6c082 | bellard | #define MSR_AL 7 /* AL bit on POWER */ |
389 | 0411a972 | j_mayer | #define MSR_EP 6 /* Exception prefix on 601 */ |
390 | 3fc6c082 | bellard | #define MSR_IR 5 /* Instruction relocate */ |
391 | 3fc6c082 | bellard | #define MSR_DR 4 /* Data relocate */ |
392 | 25ba3a68 | j_mayer | #define MSR_PE 3 /* Protection enable on 403 */ |
393 | d26bfc9a | j_mayer | #define MSR_PX 2 /* Protection exclusive on 403 x */ |
394 | d26bfc9a | j_mayer | #define MSR_PMM 2 /* Performance monitor mark on POWER x */ |
395 | d26bfc9a | j_mayer | #define MSR_RI 1 /* Recoverable interrupt 1 */ |
396 | d26bfc9a | j_mayer | #define MSR_LE 0 /* Little-endian mode 1 hflags */ |
397 | 0411a972 | j_mayer | |
398 | 0411a972 | j_mayer | #define msr_sf ((env->msr >> MSR_SF) & 1) |
399 | 0411a972 | j_mayer | #define msr_isf ((env->msr >> MSR_ISF) & 1) |
400 | a4f30719 | j_mayer | #define msr_shv ((env->msr >> MSR_SHV) & 1) |
401 | 0411a972 | j_mayer | #define msr_cm ((env->msr >> MSR_CM) & 1) |
402 | 0411a972 | j_mayer | #define msr_icm ((env->msr >> MSR_ICM) & 1) |
403 | a4f30719 | j_mayer | #define msr_thv ((env->msr >> MSR_THV) & 1) |
404 | 0411a972 | j_mayer | #define msr_ucle ((env->msr >> MSR_UCLE) & 1) |
405 | 0411a972 | j_mayer | #define msr_vr ((env->msr >> MSR_VR) & 1) |
406 | 0411a972 | j_mayer | #define msr_spe ((env->msr >> MSR_SE) & 1) |
407 | 0411a972 | j_mayer | #define msr_ap ((env->msr >> MSR_AP) & 1) |
408 | 0411a972 | j_mayer | #define msr_sa ((env->msr >> MSR_SA) & 1) |
409 | 0411a972 | j_mayer | #define msr_key ((env->msr >> MSR_KEY) & 1) |
410 | 0411a972 | j_mayer | #define msr_pow ((env->msr >> MSR_POW) & 1) |
411 | 0411a972 | j_mayer | #define msr_tgpr ((env->msr >> MSR_TGPR) & 1) |
412 | 0411a972 | j_mayer | #define msr_ce ((env->msr >> MSR_CE) & 1) |
413 | 0411a972 | j_mayer | #define msr_ile ((env->msr >> MSR_ILE) & 1) |
414 | 0411a972 | j_mayer | #define msr_ee ((env->msr >> MSR_EE) & 1) |
415 | 0411a972 | j_mayer | #define msr_pr ((env->msr >> MSR_PR) & 1) |
416 | 0411a972 | j_mayer | #define msr_fp ((env->msr >> MSR_FP) & 1) |
417 | 0411a972 | j_mayer | #define msr_me ((env->msr >> MSR_ME) & 1) |
418 | 0411a972 | j_mayer | #define msr_fe0 ((env->msr >> MSR_FE0) & 1) |
419 | 0411a972 | j_mayer | #define msr_se ((env->msr >> MSR_SE) & 1) |
420 | 0411a972 | j_mayer | #define msr_dwe ((env->msr >> MSR_DWE) & 1) |
421 | 0411a972 | j_mayer | #define msr_uble ((env->msr >> MSR_UBLE) & 1) |
422 | 0411a972 | j_mayer | #define msr_be ((env->msr >> MSR_BE) & 1) |
423 | 0411a972 | j_mayer | #define msr_de ((env->msr >> MSR_DE) & 1) |
424 | 0411a972 | j_mayer | #define msr_fe1 ((env->msr >> MSR_FE1) & 1) |
425 | 0411a972 | j_mayer | #define msr_al ((env->msr >> MSR_AL) & 1) |
426 | 0411a972 | j_mayer | #define msr_ep ((env->msr >> MSR_EP) & 1) |
427 | 0411a972 | j_mayer | #define msr_ir ((env->msr >> MSR_IR) & 1) |
428 | 0411a972 | j_mayer | #define msr_dr ((env->msr >> MSR_DR) & 1) |
429 | 0411a972 | j_mayer | #define msr_pe ((env->msr >> MSR_PE) & 1) |
430 | 0411a972 | j_mayer | #define msr_px ((env->msr >> MSR_PX) & 1) |
431 | 0411a972 | j_mayer | #define msr_pmm ((env->msr >> MSR_PMM) & 1) |
432 | 0411a972 | j_mayer | #define msr_ri ((env->msr >> MSR_RI) & 1) |
433 | 0411a972 | j_mayer | #define msr_le ((env->msr >> MSR_LE) & 1) |
434 | a4f30719 | j_mayer | /* Hypervisor bit is more specific */
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435 | a4f30719 | j_mayer | #if defined(TARGET_PPC64)
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436 | a4f30719 | j_mayer | #define MSR_HVB (1ULL << MSR_SHV) |
437 | a4f30719 | j_mayer | #define msr_hv msr_shv
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438 | a4f30719 | j_mayer | #else
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439 | a4f30719 | j_mayer | #if defined(PPC_EMULATE_32BITS_HYPV)
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440 | a4f30719 | j_mayer | #define MSR_HVB (1ULL << MSR_THV) |
441 | a4f30719 | j_mayer | #define msr_hv msr_thv
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442 | a4f30719 | j_mayer | #else
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443 | a4f30719 | j_mayer | #define MSR_HVB (0ULL) |
444 | a4f30719 | j_mayer | #define msr_hv (0) |
445 | a4f30719 | j_mayer | #endif
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446 | a4f30719 | j_mayer | #endif
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447 | 79aceca5 | bellard | |
448 | d26bfc9a | j_mayer | enum {
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449 | 4018bae9 | j_mayer | POWERPC_FLAG_NONE = 0x00000000,
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450 | d26bfc9a | j_mayer | /* Flag for MSR bit 25 signification (VRE/SPE) */
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451 | 4018bae9 | j_mayer | POWERPC_FLAG_SPE = 0x00000001,
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452 | 4018bae9 | j_mayer | POWERPC_FLAG_VRE = 0x00000002,
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453 | d26bfc9a | j_mayer | /* Flag for MSR bit 17 signification (TGPR/CE) */
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454 | 4018bae9 | j_mayer | POWERPC_FLAG_TGPR = 0x00000004,
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455 | 4018bae9 | j_mayer | POWERPC_FLAG_CE = 0x00000008,
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456 | d26bfc9a | j_mayer | /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
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457 | 4018bae9 | j_mayer | POWERPC_FLAG_SE = 0x00000010,
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458 | 4018bae9 | j_mayer | POWERPC_FLAG_DWE = 0x00000020,
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459 | 4018bae9 | j_mayer | POWERPC_FLAG_UBLE = 0x00000040,
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460 | d26bfc9a | j_mayer | /* Flag for MSR bit 9 signification (BE/DE) */
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461 | 4018bae9 | j_mayer | POWERPC_FLAG_BE = 0x00000080,
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462 | 4018bae9 | j_mayer | POWERPC_FLAG_DE = 0x00000100,
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463 | a4f30719 | j_mayer | /* Flag for MSR bit 2 signification (PX/PMM) */
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464 | 4018bae9 | j_mayer | POWERPC_FLAG_PX = 0x00000200,
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465 | 4018bae9 | j_mayer | POWERPC_FLAG_PMM = 0x00000400,
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466 | 4018bae9 | j_mayer | /* Flag for special features */
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467 | 4018bae9 | j_mayer | /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
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468 | 4018bae9 | j_mayer | POWERPC_FLAG_RTC_CLK = 0x00010000,
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469 | 4018bae9 | j_mayer | POWERPC_FLAG_BUS_CLK = 0x00020000,
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470 | d26bfc9a | j_mayer | }; |
471 | d26bfc9a | j_mayer | |
472 | 7c58044c | j_mayer | /*****************************************************************************/
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473 | 7c58044c | j_mayer | /* Floating point status and control register */
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474 | 7c58044c | j_mayer | #define FPSCR_FX 31 /* Floating-point exception summary */ |
475 | 7c58044c | j_mayer | #define FPSCR_FEX 30 /* Floating-point enabled exception summary */ |
476 | 7c58044c | j_mayer | #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */ |
477 | 7c58044c | j_mayer | #define FPSCR_OX 28 /* Floating-point overflow exception */ |
478 | 7c58044c | j_mayer | #define FPSCR_UX 27 /* Floating-point underflow exception */ |
479 | 7c58044c | j_mayer | #define FPSCR_ZX 26 /* Floating-point zero divide exception */ |
480 | 7c58044c | j_mayer | #define FPSCR_XX 25 /* Floating-point inexact exception */ |
481 | 7c58044c | j_mayer | #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */ |
482 | 7c58044c | j_mayer | #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */ |
483 | 7c58044c | j_mayer | #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */ |
484 | 7c58044c | j_mayer | #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */ |
485 | 7c58044c | j_mayer | #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */ |
486 | 7c58044c | j_mayer | #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */ |
487 | 7c58044c | j_mayer | #define FPSCR_FR 18 /* Floating-point fraction rounded */ |
488 | 7c58044c | j_mayer | #define FPSCR_FI 17 /* Floating-point fraction inexact */ |
489 | 7c58044c | j_mayer | #define FPSCR_C 16 /* Floating-point result class descriptor */ |
490 | 7c58044c | j_mayer | #define FPSCR_FL 15 /* Floating-point less than or negative */ |
491 | 7c58044c | j_mayer | #define FPSCR_FG 14 /* Floating-point greater than or negative */ |
492 | 7c58044c | j_mayer | #define FPSCR_FE 13 /* Floating-point equal or zero */ |
493 | 7c58044c | j_mayer | #define FPSCR_FU 12 /* Floating-point unordered or NaN */ |
494 | 7c58044c | j_mayer | #define FPSCR_FPCC 12 /* Floating-point condition code */ |
495 | 7c58044c | j_mayer | #define FPSCR_FPRF 12 /* Floating-point result flags */ |
496 | 7c58044c | j_mayer | #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */ |
497 | 7c58044c | j_mayer | #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */ |
498 | 7c58044c | j_mayer | #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */ |
499 | 7c58044c | j_mayer | #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */ |
500 | 7c58044c | j_mayer | #define FPSCR_OE 6 /* Floating-point overflow exception enable */ |
501 | 7c58044c | j_mayer | #define FPSCR_UE 5 /* Floating-point undeflow exception enable */ |
502 | 7c58044c | j_mayer | #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */ |
503 | 7c58044c | j_mayer | #define FPSCR_XE 3 /* Floating-point inexact exception enable */ |
504 | 7c58044c | j_mayer | #define FPSCR_NI 2 /* Floating-point non-IEEE mode */ |
505 | 7c58044c | j_mayer | #define FPSCR_RN1 1 |
506 | 7c58044c | j_mayer | #define FPSCR_RN 0 /* Floating-point rounding control */ |
507 | 7c58044c | j_mayer | #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1) |
508 | 7c58044c | j_mayer | #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1) |
509 | 7c58044c | j_mayer | #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1) |
510 | 7c58044c | j_mayer | #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1) |
511 | 7c58044c | j_mayer | #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1) |
512 | 7c58044c | j_mayer | #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1) |
513 | 7c58044c | j_mayer | #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1) |
514 | 7c58044c | j_mayer | #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1) |
515 | 7c58044c | j_mayer | #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1) |
516 | 7c58044c | j_mayer | #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1) |
517 | 7c58044c | j_mayer | #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1) |
518 | 7c58044c | j_mayer | #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1) |
519 | 7c58044c | j_mayer | #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF) |
520 | 7c58044c | j_mayer | #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1) |
521 | 7c58044c | j_mayer | #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1) |
522 | 7c58044c | j_mayer | #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1) |
523 | 7c58044c | j_mayer | #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1) |
524 | 7c58044c | j_mayer | #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1) |
525 | 7c58044c | j_mayer | #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1) |
526 | 7c58044c | j_mayer | #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1) |
527 | 7c58044c | j_mayer | #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1) |
528 | 7c58044c | j_mayer | #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1) |
529 | 7c58044c | j_mayer | #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3) |
530 | 7c58044c | j_mayer | /* Invalid operation exception summary */
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531 | 7c58044c | j_mayer | #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \ |
532 | 7c58044c | j_mayer | (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \ |
533 | 7c58044c | j_mayer | (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \ |
534 | 7c58044c | j_mayer | (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \ |
535 | 7c58044c | j_mayer | (1 << FPSCR_VXCVI)))
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536 | 7c58044c | j_mayer | /* exception summary */
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537 | 7c58044c | j_mayer | #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F) |
538 | 7c58044c | j_mayer | /* enabled exception summary */
|
539 | 7c58044c | j_mayer | #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
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540 | 7c58044c | j_mayer | 0x1F)
|
541 | 7c58044c | j_mayer | |
542 | 7c58044c | j_mayer | /*****************************************************************************/
|
543 | 7c58044c | j_mayer | /* The whole PowerPC CPU context */
|
544 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 3 |
545 | 6ebbf390 | j_mayer | |
546 | 3fc6c082 | bellard | struct CPUPPCState {
|
547 | 3fc6c082 | bellard | /* First are the most commonly used resources
|
548 | 3fc6c082 | bellard | * during translated code execution
|
549 | 3fc6c082 | bellard | */
|
550 | 57c26279 | j_mayer | #if (HOST_LONG_BITS == 32) |
551 | 3fc6c082 | bellard | /* temporary fixed-point registers
|
552 | 57c26279 | j_mayer | * used to emulate 64 bits registers on 32 bits hosts
|
553 | 5fafdf24 | ths | */
|
554 | 57c26279 | j_mayer | uint64_t t0, t1, t2; |
555 | 3fc6c082 | bellard | #endif
|
556 | a9d9eb8f | j_mayer | ppc_avr_t avr0, avr1, avr2; |
557 | d9bce9d9 | j_mayer | |
558 | 79aceca5 | bellard | /* general purpose registers */
|
559 | 76a66253 | j_mayer | ppc_gpr_t gpr[32];
|
560 | 65d6c0f3 | j_mayer | #if !defined(TARGET_PPC64)
|
561 | 3cd7d1dd | j_mayer | /* Storage for GPR MSB, used by the SPE extension */
|
562 | 3cd7d1dd | j_mayer | ppc_gpr_t gprh[32];
|
563 | 3cd7d1dd | j_mayer | #endif
|
564 | 3fc6c082 | bellard | /* LR */
|
565 | 3fc6c082 | bellard | target_ulong lr; |
566 | 3fc6c082 | bellard | /* CTR */
|
567 | 3fc6c082 | bellard | target_ulong ctr; |
568 | 3fc6c082 | bellard | /* condition register */
|
569 | 3fc6c082 | bellard | uint8_t crf[8];
|
570 | 79aceca5 | bellard | /* XER */
|
571 | 3fc6c082 | bellard | /* XXX: We use only 5 fields, but we want to keep the structure aligned */
|
572 | 3fc6c082 | bellard | uint8_t xer[8];
|
573 | 79aceca5 | bellard | /* Reservation address */
|
574 | 3fc6c082 | bellard | target_ulong reserve; |
575 | 3fc6c082 | bellard | |
576 | 3fc6c082 | bellard | /* Those ones are used in supervisor mode only */
|
577 | 79aceca5 | bellard | /* machine state register */
|
578 | 0411a972 | j_mayer | target_ulong msr; |
579 | 3fc6c082 | bellard | /* temporary general purpose registers */
|
580 | 76a66253 | j_mayer | ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */ |
581 | 3fc6c082 | bellard | |
582 | 3fc6c082 | bellard | /* Floating point execution context */
|
583 | 76a66253 | j_mayer | /* temporary float registers */
|
584 | 4ecc3190 | bellard | float64 ft0; |
585 | 4ecc3190 | bellard | float64 ft1; |
586 | 4ecc3190 | bellard | float64 ft2; |
587 | 4ecc3190 | bellard | float_status fp_status; |
588 | 3fc6c082 | bellard | /* floating point registers */
|
589 | 3fc6c082 | bellard | float64 fpr[32];
|
590 | 3fc6c082 | bellard | /* floating point status and control register */
|
591 | 7c58044c | j_mayer | uint32_t fpscr; |
592 | 4ecc3190 | bellard | |
593 | a316d335 | bellard | CPU_COMMON |
594 | a316d335 | bellard | |
595 | 50443c98 | bellard | int halted; /* TRUE if the CPU is in suspend state */ |
596 | 50443c98 | bellard | |
597 | ac9eb073 | bellard | int access_type; /* when a memory exception occurs, the access |
598 | ac9eb073 | bellard | type is stored here */
|
599 | a541f297 | bellard | |
600 | f2e63a42 | j_mayer | /* MMU context - only relevant for full system emulation */
|
601 | f2e63a42 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
602 | f2e63a42 | j_mayer | #if defined(TARGET_PPC64)
|
603 | 3fc6c082 | bellard | /* Address space register */
|
604 | 3fc6c082 | bellard | target_ulong asr; |
605 | f2e63a42 | j_mayer | /* PowerPC 64 SLB area */
|
606 | f2e63a42 | j_mayer | int slb_nr;
|
607 | f2e63a42 | j_mayer | #endif
|
608 | 3fc6c082 | bellard | /* segment registers */
|
609 | 3fc6c082 | bellard | target_ulong sdr1; |
610 | 3fc6c082 | bellard | target_ulong sr[16];
|
611 | 3fc6c082 | bellard | /* BATs */
|
612 | 3fc6c082 | bellard | int nb_BATs;
|
613 | 3fc6c082 | bellard | target_ulong DBAT[2][8]; |
614 | 3fc6c082 | bellard | target_ulong IBAT[2][8]; |
615 | f2e63a42 | j_mayer | /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
|
616 | f2e63a42 | j_mayer | int nb_tlb; /* Total number of TLB */ |
617 | f2e63a42 | j_mayer | int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ |
618 | f2e63a42 | j_mayer | int nb_ways; /* Number of ways in the TLB set */ |
619 | f2e63a42 | j_mayer | int last_way; /* Last used way used to allocate TLB in a LRU way */ |
620 | f2e63a42 | j_mayer | int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ |
621 | f2e63a42 | j_mayer | int nb_pids; /* Number of available PID registers */ |
622 | f2e63a42 | j_mayer | ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
|
623 | f2e63a42 | j_mayer | /* 403 dedicated access protection registers */
|
624 | f2e63a42 | j_mayer | target_ulong pb[4];
|
625 | f2e63a42 | j_mayer | #endif
|
626 | 9fddaa0c | bellard | |
627 | 3fc6c082 | bellard | /* Other registers */
|
628 | 3fc6c082 | bellard | /* Special purpose registers */
|
629 | 3fc6c082 | bellard | target_ulong spr[1024];
|
630 | f2e63a42 | j_mayer | ppc_spr_t spr_cb[1024];
|
631 | 3fc6c082 | bellard | /* Altivec registers */
|
632 | 3fc6c082 | bellard | ppc_avr_t avr[32];
|
633 | 3fc6c082 | bellard | uint32_t vscr; |
634 | d9bce9d9 | j_mayer | /* SPE registers */
|
635 | d9bce9d9 | j_mayer | ppc_gpr_t spe_acc; |
636 | 0487d6a8 | j_mayer | float_status spe_status; |
637 | d9bce9d9 | j_mayer | uint32_t spe_fscr; |
638 | 3fc6c082 | bellard | |
639 | 3fc6c082 | bellard | /* Internal devices resources */
|
640 | 9fddaa0c | bellard | /* Time base and decrementer */
|
641 | 9fddaa0c | bellard | ppc_tb_t *tb_env; |
642 | 3fc6c082 | bellard | /* Device control registers */
|
643 | 3fc6c082 | bellard | ppc_dcr_t *dcr_env; |
644 | 3fc6c082 | bellard | |
645 | d63001d1 | j_mayer | int dcache_line_size;
|
646 | d63001d1 | j_mayer | int icache_line_size;
|
647 | d63001d1 | j_mayer | |
648 | 3fc6c082 | bellard | /* Those resources are used during exception processing */
|
649 | 3fc6c082 | bellard | /* CPU model definition */
|
650 | a750fc0b | j_mayer | target_ulong msr_mask; |
651 | 7820dbf3 | j_mayer | powerpc_mmu_t mmu_model; |
652 | 7820dbf3 | j_mayer | powerpc_excp_t excp_model; |
653 | 7820dbf3 | j_mayer | powerpc_input_t bus_model; |
654 | 237c0af0 | j_mayer | int bfd_mach;
|
655 | 3fc6c082 | bellard | uint32_t flags; |
656 | 3fc6c082 | bellard | |
657 | 3fc6c082 | bellard | int exception_index;
|
658 | 3fc6c082 | bellard | int error_code;
|
659 | 3fc6c082 | bellard | int interrupt_request;
|
660 | 47103572 | j_mayer | uint32_t pending_interrupts; |
661 | e9df014c | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
662 | e9df014c | j_mayer | /* This is the IRQ controller, which is implementation dependant
|
663 | e9df014c | j_mayer | * and only relevant when emulating a complete machine.
|
664 | e9df014c | j_mayer | */
|
665 | e9df014c | j_mayer | uint32_t irq_input_state; |
666 | e9df014c | j_mayer | void **irq_inputs;
|
667 | e1833e1f | j_mayer | /* Exception vectors */
|
668 | e1833e1f | j_mayer | target_ulong excp_vectors[POWERPC_EXCP_NB]; |
669 | e1833e1f | j_mayer | target_ulong excp_prefix; |
670 | e1833e1f | j_mayer | target_ulong ivor_mask; |
671 | e1833e1f | j_mayer | target_ulong ivpr_mask; |
672 | d63001d1 | j_mayer | target_ulong hreset_vector; |
673 | e9df014c | j_mayer | #endif
|
674 | 3fc6c082 | bellard | |
675 | 3fc6c082 | bellard | /* Those resources are used only during code translation */
|
676 | 3fc6c082 | bellard | /* Next instruction pointer */
|
677 | 3fc6c082 | bellard | target_ulong nip; |
678 | f2e63a42 | j_mayer | |
679 | 3fc6c082 | bellard | /* opcode handlers */
|
680 | 3fc6c082 | bellard | opc_handler_t *opcodes[0x40];
|
681 | 3fc6c082 | bellard | |
682 | 3fc6c082 | bellard | /* Those resources are used only in Qemu core */
|
683 | 3fc6c082 | bellard | jmp_buf jmp_env; |
684 | 3fc6c082 | bellard | int user_mode_only; /* user mode only simulation */ |
685 | 056401ea | j_mayer | target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
|
686 | 056401ea | j_mayer | target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */
|
687 | 6ebbf390 | j_mayer | int mmu_idx; /* precomputed MMU index to speed up mem accesses */ |
688 | 3fc6c082 | bellard | |
689 | 9fddaa0c | bellard | /* Power management */
|
690 | 9fddaa0c | bellard | int power_mode;
|
691 | cd346349 | j_mayer | int (*check_pow)(CPUPPCState *env);
|
692 | a541f297 | bellard | |
693 | 6d506e6d | bellard | /* temporary hack to handle OSI calls (only used if non NULL) */
|
694 | 6d506e6d | bellard | int (*osi_call)(struct CPUPPCState *env); |
695 | 3fc6c082 | bellard | }; |
696 | 79aceca5 | bellard | |
697 | 76a66253 | j_mayer | /* Context used internally during MMU translations */
|
698 | 76a66253 | j_mayer | typedef struct mmu_ctx_t mmu_ctx_t; |
699 | 76a66253 | j_mayer | struct mmu_ctx_t {
|
700 | 76a66253 | j_mayer | target_phys_addr_t raddr; /* Real address */
|
701 | 76a66253 | j_mayer | int prot; /* Protection bits */ |
702 | 76a66253 | j_mayer | target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */ |
703 | 76a66253 | j_mayer | target_ulong ptem; /* Virtual segment ID | API */
|
704 | 76a66253 | j_mayer | int key; /* Access key */ |
705 | b227a8e9 | j_mayer | int nx; /* Non-execute area */ |
706 | 76a66253 | j_mayer | }; |
707 | 76a66253 | j_mayer | |
708 | 3fc6c082 | bellard | /*****************************************************************************/
|
709 | aaed909a | bellard | CPUPPCState *cpu_ppc_init (const char *cpu_model); |
710 | 36081602 | j_mayer | int cpu_ppc_exec (CPUPPCState *s);
|
711 | 36081602 | j_mayer | void cpu_ppc_close (CPUPPCState *s);
|
712 | 79aceca5 | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
|
713 | 79aceca5 | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
|
714 | 79aceca5 | bellard | is returned if the signal was handled by the virtual CPU. */
|
715 | 36081602 | j_mayer | int cpu_ppc_signal_handler (int host_signum, void *pinfo, |
716 | 36081602 | j_mayer | void *puc);
|
717 | 79aceca5 | bellard | |
718 | a541f297 | bellard | void do_interrupt (CPUPPCState *env);
|
719 | e9df014c | j_mayer | void ppc_hw_interrupt (CPUPPCState *env);
|
720 | 36081602 | j_mayer | void cpu_loop_exit (void); |
721 | a541f297 | bellard | |
722 | 9a64fbe4 | bellard | void dump_stack (CPUPPCState *env);
|
723 | a541f297 | bellard | |
724 | 76a66253 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
725 | 3fc6c082 | bellard | target_ulong do_load_ibatu (CPUPPCState *env, int nr);
|
726 | 3fc6c082 | bellard | target_ulong do_load_ibatl (CPUPPCState *env, int nr);
|
727 | 3fc6c082 | bellard | void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value); |
728 | 3fc6c082 | bellard | void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value); |
729 | 3fc6c082 | bellard | target_ulong do_load_dbatu (CPUPPCState *env, int nr);
|
730 | 3fc6c082 | bellard | target_ulong do_load_dbatl (CPUPPCState *env, int nr);
|
731 | 3fc6c082 | bellard | void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value); |
732 | 3fc6c082 | bellard | void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value); |
733 | 056401ea | j_mayer | void do_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value); |
734 | 056401ea | j_mayer | void do_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value); |
735 | 3fc6c082 | bellard | target_ulong do_load_sdr1 (CPUPPCState *env); |
736 | 3fc6c082 | bellard | void do_store_sdr1 (CPUPPCState *env, target_ulong value);
|
737 | d9bce9d9 | j_mayer | #if defined(TARGET_PPC64)
|
738 | d9bce9d9 | j_mayer | target_ulong ppc_load_asr (CPUPPCState *env); |
739 | d9bce9d9 | j_mayer | void ppc_store_asr (CPUPPCState *env, target_ulong value);
|
740 | 12de9a39 | j_mayer | target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
|
741 | 12de9a39 | j_mayer | void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs); |
742 | 12de9a39 | j_mayer | #endif /* defined(TARGET_PPC64) */ |
743 | 12de9a39 | j_mayer | #if 0 // Unused
|
744 | 3fc6c082 | bellard | target_ulong do_load_sr (CPUPPCState *env, int srnum);
|
745 | 76a66253 | j_mayer | #endif
|
746 | 12de9a39 | j_mayer | void do_store_sr (CPUPPCState *env, int srnum, target_ulong value); |
747 | 12de9a39 | j_mayer | #endif /* !defined(CONFIG_USER_ONLY) */ |
748 | bfa1e5cf | j_mayer | target_ulong ppc_load_xer (CPUPPCState *env); |
749 | bfa1e5cf | j_mayer | void ppc_store_xer (CPUPPCState *env, target_ulong value);
|
750 | 0411a972 | j_mayer | void ppc_store_msr (CPUPPCState *env, target_ulong value);
|
751 | 3fc6c082 | bellard | |
752 | 0a032cbe | j_mayer | void cpu_ppc_reset (void *opaque); |
753 | a541f297 | bellard | |
754 | 3fc6c082 | bellard | void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
755 | aaed909a | bellard | |
756 | aaed909a | bellard | const ppc_def_t *cpu_ppc_find_by_name (const unsigned char *name); |
757 | aaed909a | bellard | int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def); |
758 | 85c4adf6 | bellard | |
759 | 9fddaa0c | bellard | /* Time-base and decrementer management */
|
760 | 9fddaa0c | bellard | #ifndef NO_CPU_IO_DEFS
|
761 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbl (CPUPPCState *env); |
762 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbu (CPUPPCState *env); |
763 | 9fddaa0c | bellard | void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
|
764 | 9fddaa0c | bellard | void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
|
765 | a062e36c | j_mayer | uint32_t cpu_ppc_load_atbl (CPUPPCState *env); |
766 | a062e36c | j_mayer | uint32_t cpu_ppc_load_atbu (CPUPPCState *env); |
767 | a062e36c | j_mayer | void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
|
768 | a062e36c | j_mayer | void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
|
769 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_decr (CPUPPCState *env); |
770 | 9fddaa0c | bellard | void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
|
771 | 58a7d328 | j_mayer | uint32_t cpu_ppc_load_hdecr (CPUPPCState *env); |
772 | 58a7d328 | j_mayer | void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
|
773 | 58a7d328 | j_mayer | uint64_t cpu_ppc_load_purr (CPUPPCState *env); |
774 | 58a7d328 | j_mayer | void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
|
775 | d9bce9d9 | j_mayer | uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env); |
776 | d9bce9d9 | j_mayer | uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env); |
777 | d9bce9d9 | j_mayer | #if !defined(CONFIG_USER_ONLY)
|
778 | d9bce9d9 | j_mayer | void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
|
779 | d9bce9d9 | j_mayer | void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
|
780 | d9bce9d9 | j_mayer | target_ulong load_40x_pit (CPUPPCState *env); |
781 | d9bce9d9 | j_mayer | void store_40x_pit (CPUPPCState *env, target_ulong val);
|
782 | 8ecc7913 | j_mayer | void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
|
783 | c294fc58 | j_mayer | void store_40x_sler (CPUPPCState *env, uint32_t val);
|
784 | d9bce9d9 | j_mayer | void store_booke_tcr (CPUPPCState *env, target_ulong val);
|
785 | d9bce9d9 | j_mayer | void store_booke_tsr (CPUPPCState *env, target_ulong val);
|
786 | 0a032cbe | j_mayer | void ppc_tlb_invalidate_all (CPUPPCState *env);
|
787 | daf4f96e | j_mayer | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
|
788 | daf4f96e | j_mayer | #if defined(TARGET_PPC64)
|
789 | daf4f96e | j_mayer | void ppc_slb_invalidate_all (CPUPPCState *env);
|
790 | daf4f96e | j_mayer | void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
|
791 | daf4f96e | j_mayer | #endif
|
792 | 36081602 | j_mayer | int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
|
793 | d9bce9d9 | j_mayer | #endif
|
794 | 9fddaa0c | bellard | #endif
|
795 | 79aceca5 | bellard | |
796 | 2e719ba3 | j_mayer | /* Device control registers */
|
797 | 2e719ba3 | j_mayer | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp); |
798 | 2e719ba3 | j_mayer | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); |
799 | 2e719ba3 | j_mayer | |
800 | 9467d44c | ths | #define CPUState CPUPPCState
|
801 | 9467d44c | ths | #define cpu_init cpu_ppc_init
|
802 | 9467d44c | ths | #define cpu_exec cpu_ppc_exec
|
803 | 9467d44c | ths | #define cpu_gen_code cpu_ppc_gen_code
|
804 | 9467d44c | ths | #define cpu_signal_handler cpu_ppc_signal_handler
|
805 | c732abe2 | j_mayer | #define cpu_list ppc_cpu_list
|
806 | 9467d44c | ths | |
807 | 6ebbf390 | j_mayer | /* MMU modes definitions */
|
808 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _user
|
809 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _kernel
|
810 | 6ebbf390 | j_mayer | #define MMU_MODE2_SUFFIX _hypv
|
811 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 0 |
812 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
813 | 6ebbf390 | j_mayer | { |
814 | 6ebbf390 | j_mayer | return env->mmu_idx;
|
815 | 6ebbf390 | j_mayer | } |
816 | 6ebbf390 | j_mayer | |
817 | 79aceca5 | bellard | #include "cpu-all.h" |
818 | 79aceca5 | bellard | |
819 | 3fc6c082 | bellard | /*****************************************************************************/
|
820 | 3fc6c082 | bellard | /* Registers definitions */
|
821 | 79aceca5 | bellard | #define XER_SO 31 |
822 | 79aceca5 | bellard | #define XER_OV 30 |
823 | 79aceca5 | bellard | #define XER_CA 29 |
824 | 3fc6c082 | bellard | #define XER_CMP 8 |
825 | 36081602 | j_mayer | #define XER_BC 0 |
826 | 3fc6c082 | bellard | #define xer_so env->xer[4] |
827 | 3fc6c082 | bellard | #define xer_ov env->xer[6] |
828 | 3fc6c082 | bellard | #define xer_ca env->xer[2] |
829 | 3fc6c082 | bellard | #define xer_cmp env->xer[1] |
830 | 36081602 | j_mayer | #define xer_bc env->xer[0] |
831 | 79aceca5 | bellard | |
832 | 3fc6c082 | bellard | /* SPR definitions */
|
833 | 80d11f44 | j_mayer | #define SPR_MQ (0x000) |
834 | 80d11f44 | j_mayer | #define SPR_XER (0x001) |
835 | 80d11f44 | j_mayer | #define SPR_601_VRTCU (0x004) |
836 | 80d11f44 | j_mayer | #define SPR_601_VRTCL (0x005) |
837 | 80d11f44 | j_mayer | #define SPR_601_UDECR (0x006) |
838 | 80d11f44 | j_mayer | #define SPR_LR (0x008) |
839 | 80d11f44 | j_mayer | #define SPR_CTR (0x009) |
840 | 80d11f44 | j_mayer | #define SPR_DSISR (0x012) |
841 | 80d11f44 | j_mayer | #define SPR_DAR (0x013) /* DAE for PowerPC 601 */ |
842 | 80d11f44 | j_mayer | #define SPR_601_RTCU (0x014) |
843 | 80d11f44 | j_mayer | #define SPR_601_RTCL (0x015) |
844 | 80d11f44 | j_mayer | #define SPR_DECR (0x016) |
845 | 80d11f44 | j_mayer | #define SPR_SDR1 (0x019) |
846 | 80d11f44 | j_mayer | #define SPR_SRR0 (0x01A) |
847 | 80d11f44 | j_mayer | #define SPR_SRR1 (0x01B) |
848 | 80d11f44 | j_mayer | #define SPR_AMR (0x01D) |
849 | 80d11f44 | j_mayer | #define SPR_BOOKE_PID (0x030) |
850 | 80d11f44 | j_mayer | #define SPR_BOOKE_DECAR (0x036) |
851 | 80d11f44 | j_mayer | #define SPR_BOOKE_CSRR0 (0x03A) |
852 | 80d11f44 | j_mayer | #define SPR_BOOKE_CSRR1 (0x03B) |
853 | 80d11f44 | j_mayer | #define SPR_BOOKE_DEAR (0x03D) |
854 | 80d11f44 | j_mayer | #define SPR_BOOKE_ESR (0x03E) |
855 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVPR (0x03F) |
856 | 80d11f44 | j_mayer | #define SPR_MPC_EIE (0x050) |
857 | 80d11f44 | j_mayer | #define SPR_MPC_EID (0x051) |
858 | 80d11f44 | j_mayer | #define SPR_MPC_NRI (0x052) |
859 | 80d11f44 | j_mayer | #define SPR_CTRL (0x088) |
860 | 80d11f44 | j_mayer | #define SPR_MPC_CMPA (0x090) |
861 | 80d11f44 | j_mayer | #define SPR_MPC_CMPB (0x091) |
862 | 80d11f44 | j_mayer | #define SPR_MPC_CMPC (0x092) |
863 | 80d11f44 | j_mayer | #define SPR_MPC_CMPD (0x093) |
864 | 80d11f44 | j_mayer | #define SPR_MPC_ECR (0x094) |
865 | 80d11f44 | j_mayer | #define SPR_MPC_DER (0x095) |
866 | 80d11f44 | j_mayer | #define SPR_MPC_COUNTA (0x096) |
867 | 80d11f44 | j_mayer | #define SPR_MPC_COUNTB (0x097) |
868 | 80d11f44 | j_mayer | #define SPR_UCTRL (0x098) |
869 | 80d11f44 | j_mayer | #define SPR_MPC_CMPE (0x098) |
870 | 80d11f44 | j_mayer | #define SPR_MPC_CMPF (0x099) |
871 | 80d11f44 | j_mayer | #define SPR_MPC_CMPG (0x09A) |
872 | 80d11f44 | j_mayer | #define SPR_MPC_CMPH (0x09B) |
873 | 80d11f44 | j_mayer | #define SPR_MPC_LCTRL1 (0x09C) |
874 | 80d11f44 | j_mayer | #define SPR_MPC_LCTRL2 (0x09D) |
875 | 80d11f44 | j_mayer | #define SPR_MPC_ICTRL (0x09E) |
876 | 80d11f44 | j_mayer | #define SPR_MPC_BAR (0x09F) |
877 | 80d11f44 | j_mayer | #define SPR_VRSAVE (0x100) |
878 | 80d11f44 | j_mayer | #define SPR_USPRG0 (0x100) |
879 | 80d11f44 | j_mayer | #define SPR_USPRG1 (0x101) |
880 | 80d11f44 | j_mayer | #define SPR_USPRG2 (0x102) |
881 | 80d11f44 | j_mayer | #define SPR_USPRG3 (0x103) |
882 | 80d11f44 | j_mayer | #define SPR_USPRG4 (0x104) |
883 | 80d11f44 | j_mayer | #define SPR_USPRG5 (0x105) |
884 | 80d11f44 | j_mayer | #define SPR_USPRG6 (0x106) |
885 | 80d11f44 | j_mayer | #define SPR_USPRG7 (0x107) |
886 | 80d11f44 | j_mayer | #define SPR_VTBL (0x10C) |
887 | 80d11f44 | j_mayer | #define SPR_VTBU (0x10D) |
888 | 80d11f44 | j_mayer | #define SPR_SPRG0 (0x110) |
889 | 80d11f44 | j_mayer | #define SPR_SPRG1 (0x111) |
890 | 80d11f44 | j_mayer | #define SPR_SPRG2 (0x112) |
891 | 80d11f44 | j_mayer | #define SPR_SPRG3 (0x113) |
892 | 80d11f44 | j_mayer | #define SPR_SPRG4 (0x114) |
893 | 80d11f44 | j_mayer | #define SPR_SCOMC (0x114) |
894 | 80d11f44 | j_mayer | #define SPR_SPRG5 (0x115) |
895 | 80d11f44 | j_mayer | #define SPR_SCOMD (0x115) |
896 | 80d11f44 | j_mayer | #define SPR_SPRG6 (0x116) |
897 | 80d11f44 | j_mayer | #define SPR_SPRG7 (0x117) |
898 | 80d11f44 | j_mayer | #define SPR_ASR (0x118) |
899 | 80d11f44 | j_mayer | #define SPR_EAR (0x11A) |
900 | 80d11f44 | j_mayer | #define SPR_TBL (0x11C) |
901 | 80d11f44 | j_mayer | #define SPR_TBU (0x11D) |
902 | 80d11f44 | j_mayer | #define SPR_TBU40 (0x11E) |
903 | 80d11f44 | j_mayer | #define SPR_SVR (0x11E) |
904 | 80d11f44 | j_mayer | #define SPR_BOOKE_PIR (0x11E) |
905 | 80d11f44 | j_mayer | #define SPR_PVR (0x11F) |
906 | 80d11f44 | j_mayer | #define SPR_HSPRG0 (0x130) |
907 | 80d11f44 | j_mayer | #define SPR_BOOKE_DBSR (0x130) |
908 | 80d11f44 | j_mayer | #define SPR_HSPRG1 (0x131) |
909 | 80d11f44 | j_mayer | #define SPR_HDSISR (0x132) |
910 | 80d11f44 | j_mayer | #define SPR_HDAR (0x133) |
911 | 80d11f44 | j_mayer | #define SPR_BOOKE_DBCR0 (0x134) |
912 | 80d11f44 | j_mayer | #define SPR_IBCR (0x135) |
913 | 80d11f44 | j_mayer | #define SPR_PURR (0x135) |
914 | 80d11f44 | j_mayer | #define SPR_BOOKE_DBCR1 (0x135) |
915 | 80d11f44 | j_mayer | #define SPR_DBCR (0x136) |
916 | 80d11f44 | j_mayer | #define SPR_HDEC (0x136) |
917 | 80d11f44 | j_mayer | #define SPR_BOOKE_DBCR2 (0x136) |
918 | 80d11f44 | j_mayer | #define SPR_HIOR (0x137) |
919 | 80d11f44 | j_mayer | #define SPR_MBAR (0x137) |
920 | 80d11f44 | j_mayer | #define SPR_RMOR (0x138) |
921 | 80d11f44 | j_mayer | #define SPR_BOOKE_IAC1 (0x138) |
922 | 80d11f44 | j_mayer | #define SPR_HRMOR (0x139) |
923 | 80d11f44 | j_mayer | #define SPR_BOOKE_IAC2 (0x139) |
924 | 80d11f44 | j_mayer | #define SPR_HSRR0 (0x13A) |
925 | 80d11f44 | j_mayer | #define SPR_BOOKE_IAC3 (0x13A) |
926 | 80d11f44 | j_mayer | #define SPR_HSRR1 (0x13B) |
927 | 80d11f44 | j_mayer | #define SPR_BOOKE_IAC4 (0x13B) |
928 | 80d11f44 | j_mayer | #define SPR_LPCR (0x13C) |
929 | 80d11f44 | j_mayer | #define SPR_BOOKE_DAC1 (0x13C) |
930 | 80d11f44 | j_mayer | #define SPR_LPIDR (0x13D) |
931 | 80d11f44 | j_mayer | #define SPR_DABR2 (0x13D) |
932 | 80d11f44 | j_mayer | #define SPR_BOOKE_DAC2 (0x13D) |
933 | 80d11f44 | j_mayer | #define SPR_BOOKE_DVC1 (0x13E) |
934 | 80d11f44 | j_mayer | #define SPR_BOOKE_DVC2 (0x13F) |
935 | 80d11f44 | j_mayer | #define SPR_BOOKE_TSR (0x150) |
936 | 80d11f44 | j_mayer | #define SPR_BOOKE_TCR (0x154) |
937 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR0 (0x190) |
938 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR1 (0x191) |
939 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR2 (0x192) |
940 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR3 (0x193) |
941 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR4 (0x194) |
942 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR5 (0x195) |
943 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR6 (0x196) |
944 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR7 (0x197) |
945 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR8 (0x198) |
946 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR9 (0x199) |
947 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR10 (0x19A) |
948 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR11 (0x19B) |
949 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR12 (0x19C) |
950 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR13 (0x19D) |
951 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR14 (0x19E) |
952 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR15 (0x19F) |
953 | 80d11f44 | j_mayer | #define SPR_BOOKE_SPEFSCR (0x200) |
954 | 80d11f44 | j_mayer | #define SPR_Exxx_BBEAR (0x201) |
955 | 80d11f44 | j_mayer | #define SPR_Exxx_BBTAR (0x202) |
956 | 80d11f44 | j_mayer | #define SPR_Exxx_L1CFG0 (0x203) |
957 | 80d11f44 | j_mayer | #define SPR_Exxx_NPIDR (0x205) |
958 | 80d11f44 | j_mayer | #define SPR_ATBL (0x20E) |
959 | 80d11f44 | j_mayer | #define SPR_ATBU (0x20F) |
960 | 80d11f44 | j_mayer | #define SPR_IBAT0U (0x210) |
961 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR32 (0x210) |
962 | 80d11f44 | j_mayer | #define SPR_RCPU_MI_GRA (0x210) |
963 | 80d11f44 | j_mayer | #define SPR_IBAT0L (0x211) |
964 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR33 (0x211) |
965 | 80d11f44 | j_mayer | #define SPR_IBAT1U (0x212) |
966 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR34 (0x212) |
967 | 80d11f44 | j_mayer | #define SPR_IBAT1L (0x213) |
968 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR35 (0x213) |
969 | 80d11f44 | j_mayer | #define SPR_IBAT2U (0x214) |
970 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR36 (0x214) |
971 | 80d11f44 | j_mayer | #define SPR_IBAT2L (0x215) |
972 | 80d11f44 | j_mayer | #define SPR_BOOKE_IVOR37 (0x215) |
973 | 80d11f44 | j_mayer | #define SPR_IBAT3U (0x216) |
974 | 80d11f44 | j_mayer | #define SPR_IBAT3L (0x217) |
975 | 80d11f44 | j_mayer | #define SPR_DBAT0U (0x218) |
976 | 80d11f44 | j_mayer | #define SPR_RCPU_L2U_GRA (0x218) |
977 | 80d11f44 | j_mayer | #define SPR_DBAT0L (0x219) |
978 | 80d11f44 | j_mayer | #define SPR_DBAT1U (0x21A) |
979 | 80d11f44 | j_mayer | #define SPR_DBAT1L (0x21B) |
980 | 80d11f44 | j_mayer | #define SPR_DBAT2U (0x21C) |
981 | 80d11f44 | j_mayer | #define SPR_DBAT2L (0x21D) |
982 | 80d11f44 | j_mayer | #define SPR_DBAT3U (0x21E) |
983 | 80d11f44 | j_mayer | #define SPR_DBAT3L (0x21F) |
984 | 80d11f44 | j_mayer | #define SPR_IBAT4U (0x230) |
985 | 80d11f44 | j_mayer | #define SPR_RPCU_BBCMCR (0x230) |
986 | 80d11f44 | j_mayer | #define SPR_MPC_IC_CST (0x230) |
987 | 80d11f44 | j_mayer | #define SPR_Exxx_CTXCR (0x230) |
988 | 80d11f44 | j_mayer | #define SPR_IBAT4L (0x231) |
989 | 80d11f44 | j_mayer | #define SPR_MPC_IC_ADR (0x231) |
990 | 80d11f44 | j_mayer | #define SPR_Exxx_DBCR3 (0x231) |
991 | 80d11f44 | j_mayer | #define SPR_IBAT5U (0x232) |
992 | 80d11f44 | j_mayer | #define SPR_MPC_IC_DAT (0x232) |
993 | 80d11f44 | j_mayer | #define SPR_Exxx_DBCNT (0x232) |
994 | 80d11f44 | j_mayer | #define SPR_IBAT5L (0x233) |
995 | 80d11f44 | j_mayer | #define SPR_IBAT6U (0x234) |
996 | 80d11f44 | j_mayer | #define SPR_IBAT6L (0x235) |
997 | 80d11f44 | j_mayer | #define SPR_IBAT7U (0x236) |
998 | 80d11f44 | j_mayer | #define SPR_IBAT7L (0x237) |
999 | 80d11f44 | j_mayer | #define SPR_DBAT4U (0x238) |
1000 | 80d11f44 | j_mayer | #define SPR_RCPU_L2U_MCR (0x238) |
1001 | 80d11f44 | j_mayer | #define SPR_MPC_DC_CST (0x238) |
1002 | 80d11f44 | j_mayer | #define SPR_Exxx_ALTCTXCR (0x238) |
1003 | 80d11f44 | j_mayer | #define SPR_DBAT4L (0x239) |
1004 | 80d11f44 | j_mayer | #define SPR_MPC_DC_ADR (0x239) |
1005 | 80d11f44 | j_mayer | #define SPR_DBAT5U (0x23A) |
1006 | 80d11f44 | j_mayer | #define SPR_BOOKE_MCSRR0 (0x23A) |
1007 | 80d11f44 | j_mayer | #define SPR_MPC_DC_DAT (0x23A) |
1008 | 80d11f44 | j_mayer | #define SPR_DBAT5L (0x23B) |
1009 | 80d11f44 | j_mayer | #define SPR_BOOKE_MCSRR1 (0x23B) |
1010 | 80d11f44 | j_mayer | #define SPR_DBAT6U (0x23C) |
1011 | 80d11f44 | j_mayer | #define SPR_BOOKE_MCSR (0x23C) |
1012 | 80d11f44 | j_mayer | #define SPR_DBAT6L (0x23D) |
1013 | 80d11f44 | j_mayer | #define SPR_Exxx_MCAR (0x23D) |
1014 | 80d11f44 | j_mayer | #define SPR_DBAT7U (0x23E) |
1015 | 80d11f44 | j_mayer | #define SPR_BOOKE_DSRR0 (0x23E) |
1016 | 80d11f44 | j_mayer | #define SPR_DBAT7L (0x23F) |
1017 | 80d11f44 | j_mayer | #define SPR_BOOKE_DSRR1 (0x23F) |
1018 | 80d11f44 | j_mayer | #define SPR_BOOKE_SPRG8 (0x25C) |
1019 | 80d11f44 | j_mayer | #define SPR_BOOKE_SPRG9 (0x25D) |
1020 | 80d11f44 | j_mayer | #define SPR_BOOKE_MAS0 (0x270) |
1021 | 80d11f44 | j_mayer | #define SPR_BOOKE_MAS1 (0x271) |
1022 | 80d11f44 | j_mayer | #define SPR_BOOKE_MAS2 (0x272) |
1023 | 80d11f44 | j_mayer | #define SPR_BOOKE_MAS3 (0x273) |
1024 | 80d11f44 | j_mayer | #define SPR_BOOKE_MAS4 (0x274) |
1025 | 80d11f44 | j_mayer | #define SPR_BOOKE_MAS5 (0x275) |
1026 | 80d11f44 | j_mayer | #define SPR_BOOKE_MAS6 (0x276) |
1027 | 80d11f44 | j_mayer | #define SPR_BOOKE_PID1 (0x279) |
1028 | 80d11f44 | j_mayer | #define SPR_BOOKE_PID2 (0x27A) |
1029 | 80d11f44 | j_mayer | #define SPR_MPC_DPDR (0x280) |
1030 | 80d11f44 | j_mayer | #define SPR_MPC_IMMR (0x288) |
1031 | 80d11f44 | j_mayer | #define SPR_BOOKE_TLB0CFG (0x2B0) |
1032 | 80d11f44 | j_mayer | #define SPR_BOOKE_TLB1CFG (0x2B1) |
1033 | 80d11f44 | j_mayer | #define SPR_BOOKE_TLB2CFG (0x2B2) |
1034 | 80d11f44 | j_mayer | #define SPR_BOOKE_TLB3CFG (0x2B3) |
1035 | 80d11f44 | j_mayer | #define SPR_BOOKE_EPR (0x2BE) |
1036 | 80d11f44 | j_mayer | #define SPR_PERF0 (0x300) |
1037 | 80d11f44 | j_mayer | #define SPR_RCPU_MI_RBA0 (0x300) |
1038 | 80d11f44 | j_mayer | #define SPR_MPC_MI_CTR (0x300) |
1039 | 80d11f44 | j_mayer | #define SPR_PERF1 (0x301) |
1040 | 80d11f44 | j_mayer | #define SPR_RCPU_MI_RBA1 (0x301) |
1041 | 80d11f44 | j_mayer | #define SPR_PERF2 (0x302) |
1042 | 80d11f44 | j_mayer | #define SPR_RCPU_MI_RBA2 (0x302) |
1043 | 80d11f44 | j_mayer | #define SPR_MPC_MI_AP (0x302) |
1044 | 80d11f44 | j_mayer | #define SPR_PERF3 (0x303) |
1045 | 082c6681 | j_mayer | #define SPR_620_PMC1R (0x303) |
1046 | 80d11f44 | j_mayer | #define SPR_RCPU_MI_RBA3 (0x303) |
1047 | 80d11f44 | j_mayer | #define SPR_MPC_MI_EPN (0x303) |
1048 | 80d11f44 | j_mayer | #define SPR_PERF4 (0x304) |
1049 | 082c6681 | j_mayer | #define SPR_620_PMC2R (0x304) |
1050 | 80d11f44 | j_mayer | #define SPR_PERF5 (0x305) |
1051 | 80d11f44 | j_mayer | #define SPR_MPC_MI_TWC (0x305) |
1052 | 80d11f44 | j_mayer | #define SPR_PERF6 (0x306) |
1053 | 80d11f44 | j_mayer | #define SPR_MPC_MI_RPN (0x306) |
1054 | 80d11f44 | j_mayer | #define SPR_PERF7 (0x307) |
1055 | 80d11f44 | j_mayer | #define SPR_PERF8 (0x308) |
1056 | 80d11f44 | j_mayer | #define SPR_RCPU_L2U_RBA0 (0x308) |
1057 | 80d11f44 | j_mayer | #define SPR_MPC_MD_CTR (0x308) |
1058 | 80d11f44 | j_mayer | #define SPR_PERF9 (0x309) |
1059 | 80d11f44 | j_mayer | #define SPR_RCPU_L2U_RBA1 (0x309) |
1060 | 80d11f44 | j_mayer | #define SPR_MPC_MD_CASID (0x309) |
1061 | 80d11f44 | j_mayer | #define SPR_PERFA (0x30A) |
1062 | 80d11f44 | j_mayer | #define SPR_RCPU_L2U_RBA2 (0x30A) |
1063 | 80d11f44 | j_mayer | #define SPR_MPC_MD_AP (0x30A) |
1064 | 80d11f44 | j_mayer | #define SPR_PERFB (0x30B) |
1065 | 082c6681 | j_mayer | #define SPR_620_MMCR0R (0x30B) |
1066 | 80d11f44 | j_mayer | #define SPR_RCPU_L2U_RBA3 (0x30B) |
1067 | 80d11f44 | j_mayer | #define SPR_MPC_MD_EPN (0x30B) |
1068 | 80d11f44 | j_mayer | #define SPR_PERFC (0x30C) |
1069 | 80d11f44 | j_mayer | #define SPR_MPC_MD_TWB (0x30C) |
1070 | 80d11f44 | j_mayer | #define SPR_PERFD (0x30D) |
1071 | 80d11f44 | j_mayer | #define SPR_MPC_MD_TWC (0x30D) |
1072 | 80d11f44 | j_mayer | #define SPR_PERFE (0x30E) |
1073 | 80d11f44 | j_mayer | #define SPR_MPC_MD_RPN (0x30E) |
1074 | 80d11f44 | j_mayer | #define SPR_PERFF (0x30F) |
1075 | 80d11f44 | j_mayer | #define SPR_MPC_MD_TW (0x30F) |
1076 | 80d11f44 | j_mayer | #define SPR_UPERF0 (0x310) |
1077 | 80d11f44 | j_mayer | #define SPR_UPERF1 (0x311) |
1078 | 80d11f44 | j_mayer | #define SPR_UPERF2 (0x312) |
1079 | 80d11f44 | j_mayer | #define SPR_UPERF3 (0x313) |
1080 | 082c6681 | j_mayer | #define SPR_620_PMC1W (0x313) |
1081 | 80d11f44 | j_mayer | #define SPR_UPERF4 (0x314) |
1082 | 082c6681 | j_mayer | #define SPR_620_PMC2W (0x314) |
1083 | 80d11f44 | j_mayer | #define SPR_UPERF5 (0x315) |
1084 | 80d11f44 | j_mayer | #define SPR_UPERF6 (0x316) |
1085 | 80d11f44 | j_mayer | #define SPR_UPERF7 (0x317) |
1086 | 80d11f44 | j_mayer | #define SPR_UPERF8 (0x318) |
1087 | 80d11f44 | j_mayer | #define SPR_UPERF9 (0x319) |
1088 | 80d11f44 | j_mayer | #define SPR_UPERFA (0x31A) |
1089 | 80d11f44 | j_mayer | #define SPR_UPERFB (0x31B) |
1090 | 082c6681 | j_mayer | #define SPR_620_MMCR0W (0x31B) |
1091 | 80d11f44 | j_mayer | #define SPR_UPERFC (0x31C) |
1092 | 80d11f44 | j_mayer | #define SPR_UPERFD (0x31D) |
1093 | 80d11f44 | j_mayer | #define SPR_UPERFE (0x31E) |
1094 | 80d11f44 | j_mayer | #define SPR_UPERFF (0x31F) |
1095 | 80d11f44 | j_mayer | #define SPR_RCPU_MI_RA0 (0x320) |
1096 | 80d11f44 | j_mayer | #define SPR_MPC_MI_DBCAM (0x320) |
1097 | 80d11f44 | j_mayer | #define SPR_RCPU_MI_RA1 (0x321) |
1098 | 80d11f44 | j_mayer | #define SPR_MPC_MI_DBRAM0 (0x321) |
1099 | 80d11f44 | j_mayer | #define SPR_RCPU_MI_RA2 (0x322) |
1100 | 80d11f44 | j_mayer | #define SPR_MPC_MI_DBRAM1 (0x322) |
1101 | 80d11f44 | j_mayer | #define SPR_RCPU_MI_RA3 (0x323) |
1102 | 80d11f44 | j_mayer | #define SPR_RCPU_L2U_RA0 (0x328) |
1103 | 80d11f44 | j_mayer | #define SPR_MPC_MD_DBCAM (0x328) |
1104 | 80d11f44 | j_mayer | #define SPR_RCPU_L2U_RA1 (0x329) |
1105 | 80d11f44 | j_mayer | #define SPR_MPC_MD_DBRAM0 (0x329) |
1106 | 80d11f44 | j_mayer | #define SPR_RCPU_L2U_RA2 (0x32A) |
1107 | 80d11f44 | j_mayer | #define SPR_MPC_MD_DBRAM1 (0x32A) |
1108 | 80d11f44 | j_mayer | #define SPR_RCPU_L2U_RA3 (0x32B) |
1109 | 80d11f44 | j_mayer | #define SPR_440_INV0 (0x370) |
1110 | 80d11f44 | j_mayer | #define SPR_440_INV1 (0x371) |
1111 | 80d11f44 | j_mayer | #define SPR_440_INV2 (0x372) |
1112 | 80d11f44 | j_mayer | #define SPR_440_INV3 (0x373) |
1113 | 80d11f44 | j_mayer | #define SPR_440_ITV0 (0x374) |
1114 | 80d11f44 | j_mayer | #define SPR_440_ITV1 (0x375) |
1115 | 80d11f44 | j_mayer | #define SPR_440_ITV2 (0x376) |
1116 | 80d11f44 | j_mayer | #define SPR_440_ITV3 (0x377) |
1117 | 80d11f44 | j_mayer | #define SPR_440_CCR1 (0x378) |
1118 | 80d11f44 | j_mayer | #define SPR_DCRIPR (0x37B) |
1119 | 80d11f44 | j_mayer | #define SPR_PPR (0x380) |
1120 | bd928eba | j_mayer | #define SPR_750_GQR0 (0x390) |
1121 | 80d11f44 | j_mayer | #define SPR_440_DNV0 (0x390) |
1122 | bd928eba | j_mayer | #define SPR_750_GQR1 (0x391) |
1123 | 80d11f44 | j_mayer | #define SPR_440_DNV1 (0x391) |
1124 | bd928eba | j_mayer | #define SPR_750_GQR2 (0x392) |
1125 | 80d11f44 | j_mayer | #define SPR_440_DNV2 (0x392) |
1126 | bd928eba | j_mayer | #define SPR_750_GQR3 (0x393) |
1127 | 80d11f44 | j_mayer | #define SPR_440_DNV3 (0x393) |
1128 | bd928eba | j_mayer | #define SPR_750_GQR4 (0x394) |
1129 | 80d11f44 | j_mayer | #define SPR_440_DTV0 (0x394) |
1130 | bd928eba | j_mayer | #define SPR_750_GQR5 (0x395) |
1131 | 80d11f44 | j_mayer | #define SPR_440_DTV1 (0x395) |
1132 | bd928eba | j_mayer | #define SPR_750_GQR6 (0x396) |
1133 | 80d11f44 | j_mayer | #define SPR_440_DTV2 (0x396) |
1134 | bd928eba | j_mayer | #define SPR_750_GQR7 (0x397) |
1135 | 80d11f44 | j_mayer | #define SPR_440_DTV3 (0x397) |
1136 | bd928eba | j_mayer | #define SPR_750_THRM4 (0x398) |
1137 | bd928eba | j_mayer | #define SPR_750CL_HID2 (0x398) |
1138 | 80d11f44 | j_mayer | #define SPR_440_DVLIM (0x398) |
1139 | bd928eba | j_mayer | #define SPR_750_WPAR (0x399) |
1140 | 80d11f44 | j_mayer | #define SPR_440_IVLIM (0x399) |
1141 | bd928eba | j_mayer | #define SPR_750_DMAU (0x39A) |
1142 | bd928eba | j_mayer | #define SPR_750_DMAL (0x39B) |
1143 | 80d11f44 | j_mayer | #define SPR_440_RSTCFG (0x39B) |
1144 | 80d11f44 | j_mayer | #define SPR_BOOKE_DCDBTRL (0x39C) |
1145 | 80d11f44 | j_mayer | #define SPR_BOOKE_DCDBTRH (0x39D) |
1146 | 80d11f44 | j_mayer | #define SPR_BOOKE_ICDBTRL (0x39E) |
1147 | 80d11f44 | j_mayer | #define SPR_BOOKE_ICDBTRH (0x39F) |
1148 | 80d11f44 | j_mayer | #define SPR_UMMCR2 (0x3A0) |
1149 | 80d11f44 | j_mayer | #define SPR_UPMC5 (0x3A1) |
1150 | 80d11f44 | j_mayer | #define SPR_UPMC6 (0x3A2) |
1151 | 80d11f44 | j_mayer | #define SPR_UBAMR (0x3A7) |
1152 | 80d11f44 | j_mayer | #define SPR_UMMCR0 (0x3A8) |
1153 | 80d11f44 | j_mayer | #define SPR_UPMC1 (0x3A9) |
1154 | 80d11f44 | j_mayer | #define SPR_UPMC2 (0x3AA) |
1155 | 80d11f44 | j_mayer | #define SPR_USIAR (0x3AB) |
1156 | 80d11f44 | j_mayer | #define SPR_UMMCR1 (0x3AC) |
1157 | 80d11f44 | j_mayer | #define SPR_UPMC3 (0x3AD) |
1158 | 80d11f44 | j_mayer | #define SPR_UPMC4 (0x3AE) |
1159 | 80d11f44 | j_mayer | #define SPR_USDA (0x3AF) |
1160 | 80d11f44 | j_mayer | #define SPR_40x_ZPR (0x3B0) |
1161 | 80d11f44 | j_mayer | #define SPR_BOOKE_MAS7 (0x3B0) |
1162 | 80d11f44 | j_mayer | #define SPR_620_PMR0 (0x3B0) |
1163 | 80d11f44 | j_mayer | #define SPR_MMCR2 (0x3B0) |
1164 | 80d11f44 | j_mayer | #define SPR_PMC5 (0x3B1) |
1165 | 80d11f44 | j_mayer | #define SPR_40x_PID (0x3B1) |
1166 | 80d11f44 | j_mayer | #define SPR_620_PMR1 (0x3B1) |
1167 | 80d11f44 | j_mayer | #define SPR_PMC6 (0x3B2) |
1168 | 80d11f44 | j_mayer | #define SPR_440_MMUCR (0x3B2) |
1169 | 80d11f44 | j_mayer | #define SPR_620_PMR2 (0x3B2) |
1170 | 80d11f44 | j_mayer | #define SPR_4xx_CCR0 (0x3B3) |
1171 | 80d11f44 | j_mayer | #define SPR_BOOKE_EPLC (0x3B3) |
1172 | 80d11f44 | j_mayer | #define SPR_620_PMR3 (0x3B3) |
1173 | 80d11f44 | j_mayer | #define SPR_405_IAC3 (0x3B4) |
1174 | 80d11f44 | j_mayer | #define SPR_BOOKE_EPSC (0x3B4) |
1175 | 80d11f44 | j_mayer | #define SPR_620_PMR4 (0x3B4) |
1176 | 80d11f44 | j_mayer | #define SPR_405_IAC4 (0x3B5) |
1177 | 80d11f44 | j_mayer | #define SPR_620_PMR5 (0x3B5) |
1178 | 80d11f44 | j_mayer | #define SPR_405_DVC1 (0x3B6) |
1179 | 80d11f44 | j_mayer | #define SPR_620_PMR6 (0x3B6) |
1180 | 80d11f44 | j_mayer | #define SPR_405_DVC2 (0x3B7) |
1181 | 80d11f44 | j_mayer | #define SPR_620_PMR7 (0x3B7) |
1182 | 80d11f44 | j_mayer | #define SPR_BAMR (0x3B7) |
1183 | 80d11f44 | j_mayer | #define SPR_MMCR0 (0x3B8) |
1184 | 80d11f44 | j_mayer | #define SPR_620_PMR8 (0x3B8) |
1185 | 80d11f44 | j_mayer | #define SPR_PMC1 (0x3B9) |
1186 | 80d11f44 | j_mayer | #define SPR_40x_SGR (0x3B9) |
1187 | 80d11f44 | j_mayer | #define SPR_620_PMR9 (0x3B9) |
1188 | 80d11f44 | j_mayer | #define SPR_PMC2 (0x3BA) |
1189 | 80d11f44 | j_mayer | #define SPR_40x_DCWR (0x3BA) |
1190 | 80d11f44 | j_mayer | #define SPR_620_PMRA (0x3BA) |
1191 | 80d11f44 | j_mayer | #define SPR_SIAR (0x3BB) |
1192 | 80d11f44 | j_mayer | #define SPR_405_SLER (0x3BB) |
1193 | 80d11f44 | j_mayer | #define SPR_620_PMRB (0x3BB) |
1194 | 80d11f44 | j_mayer | #define SPR_MMCR1 (0x3BC) |
1195 | 80d11f44 | j_mayer | #define SPR_405_SU0R (0x3BC) |
1196 | 80d11f44 | j_mayer | #define SPR_620_PMRC (0x3BC) |
1197 | 80d11f44 | j_mayer | #define SPR_401_SKR (0x3BC) |
1198 | 80d11f44 | j_mayer | #define SPR_PMC3 (0x3BD) |
1199 | 80d11f44 | j_mayer | #define SPR_405_DBCR1 (0x3BD) |
1200 | 80d11f44 | j_mayer | #define SPR_620_PMRD (0x3BD) |
1201 | 80d11f44 | j_mayer | #define SPR_PMC4 (0x3BE) |
1202 | 80d11f44 | j_mayer | #define SPR_620_PMRE (0x3BE) |
1203 | 80d11f44 | j_mayer | #define SPR_SDA (0x3BF) |
1204 | 80d11f44 | j_mayer | #define SPR_620_PMRF (0x3BF) |
1205 | 80d11f44 | j_mayer | #define SPR_403_VTBL (0x3CC) |
1206 | 80d11f44 | j_mayer | #define SPR_403_VTBU (0x3CD) |
1207 | 80d11f44 | j_mayer | #define SPR_DMISS (0x3D0) |
1208 | 80d11f44 | j_mayer | #define SPR_DCMP (0x3D1) |
1209 | 80d11f44 | j_mayer | #define SPR_HASH1 (0x3D2) |
1210 | 80d11f44 | j_mayer | #define SPR_HASH2 (0x3D3) |
1211 | 80d11f44 | j_mayer | #define SPR_BOOKE_ICDBDR (0x3D3) |
1212 | 80d11f44 | j_mayer | #define SPR_TLBMISS (0x3D4) |
1213 | 80d11f44 | j_mayer | #define SPR_IMISS (0x3D4) |
1214 | 80d11f44 | j_mayer | #define SPR_40x_ESR (0x3D4) |
1215 | 80d11f44 | j_mayer | #define SPR_PTEHI (0x3D5) |
1216 | 80d11f44 | j_mayer | #define SPR_ICMP (0x3D5) |
1217 | 80d11f44 | j_mayer | #define SPR_40x_DEAR (0x3D5) |
1218 | 80d11f44 | j_mayer | #define SPR_PTELO (0x3D6) |
1219 | 80d11f44 | j_mayer | #define SPR_RPA (0x3D6) |
1220 | 80d11f44 | j_mayer | #define SPR_40x_EVPR (0x3D6) |
1221 | 80d11f44 | j_mayer | #define SPR_L3PM (0x3D7) |
1222 | 80d11f44 | j_mayer | #define SPR_403_CDBCR (0x3D7) |
1223 | 80d11f44 | j_mayer | #define SPR_L3OHCR (0x3D8) |
1224 | 80d11f44 | j_mayer | #define SPR_TCR (0x3D8) |
1225 | 80d11f44 | j_mayer | #define SPR_40x_TSR (0x3D8) |
1226 | 80d11f44 | j_mayer | #define SPR_IBR (0x3DA) |
1227 | 80d11f44 | j_mayer | #define SPR_40x_TCR (0x3DA) |
1228 | 80d11f44 | j_mayer | #define SPR_ESASRR (0x3DB) |
1229 | 80d11f44 | j_mayer | #define SPR_40x_PIT (0x3DB) |
1230 | 80d11f44 | j_mayer | #define SPR_403_TBL (0x3DC) |
1231 | 80d11f44 | j_mayer | #define SPR_403_TBU (0x3DD) |
1232 | 80d11f44 | j_mayer | #define SPR_SEBR (0x3DE) |
1233 | 80d11f44 | j_mayer | #define SPR_40x_SRR2 (0x3DE) |
1234 | 80d11f44 | j_mayer | #define SPR_SER (0x3DF) |
1235 | 80d11f44 | j_mayer | #define SPR_40x_SRR3 (0x3DF) |
1236 | 80d11f44 | j_mayer | #define SPR_L3ITCR0 (0x3E8) |
1237 | 80d11f44 | j_mayer | #define SPR_L3ITCR1 (0x3E9) |
1238 | 80d11f44 | j_mayer | #define SPR_L3ITCR2 (0x3EA) |
1239 | 80d11f44 | j_mayer | #define SPR_L3ITCR3 (0x3EB) |
1240 | 80d11f44 | j_mayer | #define SPR_HID0 (0x3F0) |
1241 | 80d11f44 | j_mayer | #define SPR_40x_DBSR (0x3F0) |
1242 | 80d11f44 | j_mayer | #define SPR_HID1 (0x3F1) |
1243 | 80d11f44 | j_mayer | #define SPR_IABR (0x3F2) |
1244 | 80d11f44 | j_mayer | #define SPR_40x_DBCR0 (0x3F2) |
1245 | 80d11f44 | j_mayer | #define SPR_601_HID2 (0x3F2) |
1246 | 80d11f44 | j_mayer | #define SPR_Exxx_L1CSR0 (0x3F2) |
1247 | 80d11f44 | j_mayer | #define SPR_ICTRL (0x3F3) |
1248 | 80d11f44 | j_mayer | #define SPR_HID2 (0x3F3) |
1249 | bd928eba | j_mayer | #define SPR_750CL_HID4 (0x3F3) |
1250 | 80d11f44 | j_mayer | #define SPR_Exxx_L1CSR1 (0x3F3) |
1251 | 80d11f44 | j_mayer | #define SPR_440_DBDR (0x3F3) |
1252 | 80d11f44 | j_mayer | #define SPR_LDSTDB (0x3F4) |
1253 | bd928eba | j_mayer | #define SPR_750_TDCL (0x3F4) |
1254 | 80d11f44 | j_mayer | #define SPR_40x_IAC1 (0x3F4) |
1255 | 80d11f44 | j_mayer | #define SPR_MMUCSR0 (0x3F4) |
1256 | 80d11f44 | j_mayer | #define SPR_DABR (0x3F5) |
1257 | 3fc6c082 | bellard | #define DABR_MASK (~(target_ulong)0x7) |
1258 | 80d11f44 | j_mayer | #define SPR_Exxx_BUCSR (0x3F5) |
1259 | 80d11f44 | j_mayer | #define SPR_40x_IAC2 (0x3F5) |
1260 | 80d11f44 | j_mayer | #define SPR_601_HID5 (0x3F5) |
1261 | 80d11f44 | j_mayer | #define SPR_40x_DAC1 (0x3F6) |
1262 | 80d11f44 | j_mayer | #define SPR_MSSCR0 (0x3F6) |
1263 | 80d11f44 | j_mayer | #define SPR_970_HID5 (0x3F6) |
1264 | 80d11f44 | j_mayer | #define SPR_MSSSR0 (0x3F7) |
1265 | 80d11f44 | j_mayer | #define SPR_DABRX (0x3F7) |
1266 | 80d11f44 | j_mayer | #define SPR_40x_DAC2 (0x3F7) |
1267 | 80d11f44 | j_mayer | #define SPR_MMUCFG (0x3F7) |
1268 | 80d11f44 | j_mayer | #define SPR_LDSTCR (0x3F8) |
1269 | 80d11f44 | j_mayer | #define SPR_L2PMCR (0x3F8) |
1270 | bd928eba | j_mayer | #define SPR_750FX_HID2 (0x3F8) |
1271 | 082c6681 | j_mayer | #define SPR_620_BUSCSR (0x3F8) |
1272 | 80d11f44 | j_mayer | #define SPR_Exxx_L1FINV0 (0x3F8) |
1273 | 80d11f44 | j_mayer | #define SPR_L2CR (0x3F9) |
1274 | 082c6681 | j_mayer | #define SPR_620_L2CR (0x3F9) |
1275 | 80d11f44 | j_mayer | #define SPR_L3CR (0x3FA) |
1276 | bd928eba | j_mayer | #define SPR_750_TDCH (0x3FA) |
1277 | 80d11f44 | j_mayer | #define SPR_IABR2 (0x3FA) |
1278 | 80d11f44 | j_mayer | #define SPR_40x_DCCR (0x3FA) |
1279 | 082c6681 | j_mayer | #define SPR_620_L2SR (0x3FA) |
1280 | 80d11f44 | j_mayer | #define SPR_ICTC (0x3FB) |
1281 | 80d11f44 | j_mayer | #define SPR_40x_ICCR (0x3FB) |
1282 | 80d11f44 | j_mayer | #define SPR_THRM1 (0x3FC) |
1283 | 80d11f44 | j_mayer | #define SPR_403_PBL1 (0x3FC) |
1284 | 80d11f44 | j_mayer | #define SPR_SP (0x3FD) |
1285 | 80d11f44 | j_mayer | #define SPR_THRM2 (0x3FD) |
1286 | 80d11f44 | j_mayer | #define SPR_403_PBU1 (0x3FD) |
1287 | 80d11f44 | j_mayer | #define SPR_604_HID13 (0x3FD) |
1288 | 80d11f44 | j_mayer | #define SPR_LT (0x3FE) |
1289 | 80d11f44 | j_mayer | #define SPR_THRM3 (0x3FE) |
1290 | 80d11f44 | j_mayer | #define SPR_RCPU_FPECR (0x3FE) |
1291 | 80d11f44 | j_mayer | #define SPR_403_PBL2 (0x3FE) |
1292 | 80d11f44 | j_mayer | #define SPR_PIR (0x3FF) |
1293 | 80d11f44 | j_mayer | #define SPR_403_PBU2 (0x3FF) |
1294 | 80d11f44 | j_mayer | #define SPR_601_HID15 (0x3FF) |
1295 | 80d11f44 | j_mayer | #define SPR_604_HID15 (0x3FF) |
1296 | 80d11f44 | j_mayer | #define SPR_E500_SVR (0x3FF) |
1297 | 79aceca5 | bellard | |
1298 | 76a66253 | j_mayer | /*****************************************************************************/
|
1299 | 9a64fbe4 | bellard | /* Memory access type :
|
1300 | 9a64fbe4 | bellard | * may be needed for precise access rights control and precise exceptions.
|
1301 | 9a64fbe4 | bellard | */
|
1302 | 79aceca5 | bellard | enum {
|
1303 | 9a64fbe4 | bellard | /* 1 bit to define user level / supervisor access */
|
1304 | 9a64fbe4 | bellard | ACCESS_USER = 0x00,
|
1305 | 9a64fbe4 | bellard | ACCESS_SUPER = 0x01,
|
1306 | 9a64fbe4 | bellard | /* Type of instruction that generated the access */
|
1307 | 9a64fbe4 | bellard | ACCESS_CODE = 0x10, /* Code fetch access */ |
1308 | 9a64fbe4 | bellard | ACCESS_INT = 0x20, /* Integer load/store access */ |
1309 | 9a64fbe4 | bellard | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
1310 | 9a64fbe4 | bellard | ACCESS_RES = 0x40, /* load/store with reservation */ |
1311 | 9a64fbe4 | bellard | ACCESS_EXT = 0x50, /* external access */ |
1312 | 9a64fbe4 | bellard | ACCESS_CACHE = 0x60, /* Cache manipulation */ |
1313 | 9a64fbe4 | bellard | }; |
1314 | 9a64fbe4 | bellard | |
1315 | 47103572 | j_mayer | /* Hardware interruption sources:
|
1316 | 47103572 | j_mayer | * all those exception can be raised simulteaneously
|
1317 | 47103572 | j_mayer | */
|
1318 | e9df014c | j_mayer | /* Input pins definitions */
|
1319 | e9df014c | j_mayer | enum {
|
1320 | e9df014c | j_mayer | /* 6xx bus input pins */
|
1321 | 24be5ae3 | j_mayer | PPC6xx_INPUT_HRESET = 0,
|
1322 | 24be5ae3 | j_mayer | PPC6xx_INPUT_SRESET = 1,
|
1323 | 24be5ae3 | j_mayer | PPC6xx_INPUT_CKSTP_IN = 2,
|
1324 | 24be5ae3 | j_mayer | PPC6xx_INPUT_MCP = 3,
|
1325 | 24be5ae3 | j_mayer | PPC6xx_INPUT_SMI = 4,
|
1326 | 24be5ae3 | j_mayer | PPC6xx_INPUT_INT = 5,
|
1327 | d68f1306 | j_mayer | PPC6xx_INPUT_TBEN = 6,
|
1328 | d68f1306 | j_mayer | PPC6xx_INPUT_WAKEUP = 7,
|
1329 | d68f1306 | j_mayer | PPC6xx_INPUT_NB, |
1330 | 24be5ae3 | j_mayer | }; |
1331 | 24be5ae3 | j_mayer | |
1332 | 24be5ae3 | j_mayer | enum {
|
1333 | e9df014c | j_mayer | /* Embedded PowerPC input pins */
|
1334 | 24be5ae3 | j_mayer | PPCBookE_INPUT_HRESET = 0,
|
1335 | 24be5ae3 | j_mayer | PPCBookE_INPUT_SRESET = 1,
|
1336 | 24be5ae3 | j_mayer | PPCBookE_INPUT_CKSTP_IN = 2,
|
1337 | 24be5ae3 | j_mayer | PPCBookE_INPUT_MCP = 3,
|
1338 | 24be5ae3 | j_mayer | PPCBookE_INPUT_SMI = 4,
|
1339 | 24be5ae3 | j_mayer | PPCBookE_INPUT_INT = 5,
|
1340 | 24be5ae3 | j_mayer | PPCBookE_INPUT_CINT = 6,
|
1341 | d68f1306 | j_mayer | PPCBookE_INPUT_NB, |
1342 | 24be5ae3 | j_mayer | }; |
1343 | 24be5ae3 | j_mayer | |
1344 | 24be5ae3 | j_mayer | enum {
|
1345 | 4e290a0b | j_mayer | /* PowerPC 40x input pins */
|
1346 | 4e290a0b | j_mayer | PPC40x_INPUT_RESET_CORE = 0,
|
1347 | 4e290a0b | j_mayer | PPC40x_INPUT_RESET_CHIP = 1,
|
1348 | 4e290a0b | j_mayer | PPC40x_INPUT_RESET_SYS = 2,
|
1349 | 4e290a0b | j_mayer | PPC40x_INPUT_CINT = 3,
|
1350 | 4e290a0b | j_mayer | PPC40x_INPUT_INT = 4,
|
1351 | 4e290a0b | j_mayer | PPC40x_INPUT_HALT = 5,
|
1352 | 4e290a0b | j_mayer | PPC40x_INPUT_DEBUG = 6,
|
1353 | 4e290a0b | j_mayer | PPC40x_INPUT_NB, |
1354 | e9df014c | j_mayer | }; |
1355 | e9df014c | j_mayer | |
1356 | b4095fed | j_mayer | enum {
|
1357 | b4095fed | j_mayer | /* RCPU input pins */
|
1358 | b4095fed | j_mayer | PPCRCPU_INPUT_PORESET = 0,
|
1359 | b4095fed | j_mayer | PPCRCPU_INPUT_HRESET = 1,
|
1360 | b4095fed | j_mayer | PPCRCPU_INPUT_SRESET = 2,
|
1361 | b4095fed | j_mayer | PPCRCPU_INPUT_IRQ0 = 3,
|
1362 | b4095fed | j_mayer | PPCRCPU_INPUT_IRQ1 = 4,
|
1363 | b4095fed | j_mayer | PPCRCPU_INPUT_IRQ2 = 5,
|
1364 | b4095fed | j_mayer | PPCRCPU_INPUT_IRQ3 = 6,
|
1365 | b4095fed | j_mayer | PPCRCPU_INPUT_IRQ4 = 7,
|
1366 | b4095fed | j_mayer | PPCRCPU_INPUT_IRQ5 = 8,
|
1367 | b4095fed | j_mayer | PPCRCPU_INPUT_IRQ6 = 9,
|
1368 | b4095fed | j_mayer | PPCRCPU_INPUT_IRQ7 = 10,
|
1369 | b4095fed | j_mayer | PPCRCPU_INPUT_NB, |
1370 | b4095fed | j_mayer | }; |
1371 | b4095fed | j_mayer | |
1372 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
|
1373 | d0dfae6e | j_mayer | enum {
|
1374 | d0dfae6e | j_mayer | /* PowerPC 970 input pins */
|
1375 | d0dfae6e | j_mayer | PPC970_INPUT_HRESET = 0,
|
1376 | d0dfae6e | j_mayer | PPC970_INPUT_SRESET = 1,
|
1377 | d0dfae6e | j_mayer | PPC970_INPUT_CKSTP = 2,
|
1378 | d0dfae6e | j_mayer | PPC970_INPUT_TBEN = 3,
|
1379 | d0dfae6e | j_mayer | PPC970_INPUT_MCP = 4,
|
1380 | d0dfae6e | j_mayer | PPC970_INPUT_INT = 5,
|
1381 | d0dfae6e | j_mayer | PPC970_INPUT_THINT = 6,
|
1382 | 7b62a955 | j_mayer | PPC970_INPUT_NB, |
1383 | d0dfae6e | j_mayer | }; |
1384 | 00af685f | j_mayer | #endif
|
1385 | d0dfae6e | j_mayer | |
1386 | e9df014c | j_mayer | /* Hardware exceptions definitions */
|
1387 | 47103572 | j_mayer | enum {
|
1388 | e9df014c | j_mayer | /* External hardware exception sources */
|
1389 | e1833e1f | j_mayer | PPC_INTERRUPT_RESET = 0, /* Reset exception */ |
1390 | d68f1306 | j_mayer | PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
|
1391 | d68f1306 | j_mayer | PPC_INTERRUPT_MCK, /* Machine check exception */
|
1392 | d68f1306 | j_mayer | PPC_INTERRUPT_EXT, /* External interrupt */
|
1393 | d68f1306 | j_mayer | PPC_INTERRUPT_SMI, /* System management interrupt */
|
1394 | d68f1306 | j_mayer | PPC_INTERRUPT_CEXT, /* Critical external interrupt */
|
1395 | d68f1306 | j_mayer | PPC_INTERRUPT_DEBUG, /* External debug exception */
|
1396 | d68f1306 | j_mayer | PPC_INTERRUPT_THERM, /* Thermal exception */
|
1397 | e9df014c | j_mayer | /* Internal hardware exception sources */
|
1398 | d68f1306 | j_mayer | PPC_INTERRUPT_DECR, /* Decrementer exception */
|
1399 | d68f1306 | j_mayer | PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
|
1400 | d68f1306 | j_mayer | PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
|
1401 | d68f1306 | j_mayer | PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
|
1402 | d68f1306 | j_mayer | PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
|
1403 | d68f1306 | j_mayer | PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
|
1404 | d68f1306 | j_mayer | PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
|
1405 | d68f1306 | j_mayer | PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
|
1406 | 47103572 | j_mayer | }; |
1407 | 47103572 | j_mayer | |
1408 | 9a64fbe4 | bellard | /*****************************************************************************/
|
1409 | 9a64fbe4 | bellard | |
1410 | 79aceca5 | bellard | #endif /* !defined (__CPU_PPC_H__) */ |