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1 | 05ee37eb | balrog | /*
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2 | 05ee37eb | balrog | * CFI parallel flash with Intel command set emulation
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3 | 05ee37eb | balrog | *
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4 | 05ee37eb | balrog | * Copyright (c) 2006 Thorsten Zitterell
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5 | 05ee37eb | balrog | * Copyright (c) 2005 Jocelyn Mayer
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6 | 05ee37eb | balrog | *
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7 | 05ee37eb | balrog | * This library is free software; you can redistribute it and/or
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8 | 05ee37eb | balrog | * modify it under the terms of the GNU Lesser General Public
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9 | 05ee37eb | balrog | * License as published by the Free Software Foundation; either
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10 | 05ee37eb | balrog | * version 2 of the License, or (at your option) any later version.
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11 | 05ee37eb | balrog | *
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12 | 05ee37eb | balrog | * This library is distributed in the hope that it will be useful,
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13 | 05ee37eb | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 05ee37eb | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 05ee37eb | balrog | * Lesser General Public License for more details.
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16 | 05ee37eb | balrog | *
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17 | 05ee37eb | balrog | * You should have received a copy of the GNU Lesser General Public
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18 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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19 | 05ee37eb | balrog | */
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20 | 05ee37eb | balrog | |
21 | 05ee37eb | balrog | /*
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22 | 05ee37eb | balrog | * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
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23 | 05ee37eb | balrog | * Supported commands/modes are:
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24 | 05ee37eb | balrog | * - flash read
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25 | 05ee37eb | balrog | * - flash write
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26 | 05ee37eb | balrog | * - flash ID read
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27 | 05ee37eb | balrog | * - sector erase
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28 | 05ee37eb | balrog | * - CFI queries
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29 | 05ee37eb | balrog | *
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30 | 05ee37eb | balrog | * It does not support timings
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31 | 05ee37eb | balrog | * It does not support flash interleaving
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32 | 05ee37eb | balrog | * It does not implement software data protection as found in many real chips
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33 | 05ee37eb | balrog | * It does not implement erase suspend/resume commands
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34 | 05ee37eb | balrog | * It does not implement multiple sectors erase
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35 | 05ee37eb | balrog | *
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36 | 05ee37eb | balrog | * It does not implement much more ...
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37 | 05ee37eb | balrog | */
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38 | 05ee37eb | balrog | |
39 | 87ecb68b | pbrook | #include "hw.h" |
40 | 87ecb68b | pbrook | #include "flash.h" |
41 | 87ecb68b | pbrook | #include "block.h" |
42 | 87ecb68b | pbrook | #include "qemu-timer.h" |
43 | 05ee37eb | balrog | |
44 | 001faf32 | Blue Swirl | #define PFLASH_BUG(fmt, ...) \
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45 | 05ee37eb | balrog | do { \
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46 | 001faf32 | Blue Swirl | printf("PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \ |
47 | 05ee37eb | balrog | exit(1); \
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48 | 05ee37eb | balrog | } while(0) |
49 | 05ee37eb | balrog | |
50 | 05ee37eb | balrog | /* #define PFLASH_DEBUG */
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51 | 05ee37eb | balrog | #ifdef PFLASH_DEBUG
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52 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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53 | 05ee37eb | balrog | do { \
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54 | 001faf32 | Blue Swirl | printf("PFLASH: " fmt , ## __VA_ARGS__); \ |
55 | 05ee37eb | balrog | } while (0) |
56 | 05ee37eb | balrog | #else
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57 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do { } while (0) |
58 | 05ee37eb | balrog | #endif
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59 | 05ee37eb | balrog | |
60 | c227f099 | Anthony Liguori | struct pflash_t {
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61 | 05ee37eb | balrog | BlockDriverState *bs; |
62 | c227f099 | Anthony Liguori | target_phys_addr_t base; |
63 | c227f099 | Anthony Liguori | target_phys_addr_t sector_len; |
64 | c227f099 | Anthony Liguori | target_phys_addr_t total_len; |
65 | 05ee37eb | balrog | int width;
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66 | 05ee37eb | balrog | int wcycle; /* if 0, the flash is read normally */ |
67 | 05ee37eb | balrog | int bypass;
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68 | 05ee37eb | balrog | int ro;
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69 | 05ee37eb | balrog | uint8_t cmd; |
70 | 05ee37eb | balrog | uint8_t status; |
71 | 05ee37eb | balrog | uint16_t ident[4];
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72 | 05ee37eb | balrog | uint8_t cfi_len; |
73 | 05ee37eb | balrog | uint8_t cfi_table[0x52];
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74 | c227f099 | Anthony Liguori | target_phys_addr_t counter; |
75 | 05ee37eb | balrog | QEMUTimer *timer; |
76 | c227f099 | Anthony Liguori | ram_addr_t off; |
77 | 05ee37eb | balrog | int fl_mem;
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78 | 05ee37eb | balrog | void *storage;
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79 | 05ee37eb | balrog | }; |
80 | 05ee37eb | balrog | |
81 | 05ee37eb | balrog | static void pflash_timer (void *opaque) |
82 | 05ee37eb | balrog | { |
83 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
84 | 05ee37eb | balrog | |
85 | 05ee37eb | balrog | DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
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86 | 05ee37eb | balrog | /* Reset flash */
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87 | 05ee37eb | balrog | pfl->status ^= 0x80;
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88 | 05ee37eb | balrog | if (pfl->bypass) {
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89 | 05ee37eb | balrog | pfl->wcycle = 2;
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90 | 05ee37eb | balrog | } else {
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91 | 05ee37eb | balrog | cpu_register_physical_memory(pfl->base, pfl->total_len, |
92 | 05ee37eb | balrog | pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
93 | 05ee37eb | balrog | pfl->wcycle = 0;
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94 | 05ee37eb | balrog | } |
95 | 05ee37eb | balrog | pfl->cmd = 0;
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96 | 05ee37eb | balrog | } |
97 | 05ee37eb | balrog | |
98 | c227f099 | Anthony Liguori | static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
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99 | 42a89d77 | Paul Brook | int width)
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100 | 05ee37eb | balrog | { |
101 | c227f099 | Anthony Liguori | target_phys_addr_t boff; |
102 | 05ee37eb | balrog | uint32_t ret; |
103 | 05ee37eb | balrog | uint8_t *p; |
104 | 05ee37eb | balrog | |
105 | 05ee37eb | balrog | ret = -1;
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106 | 05ee37eb | balrog | boff = offset & 0xFF; /* why this here ?? */ |
107 | 05ee37eb | balrog | |
108 | 05ee37eb | balrog | if (pfl->width == 2) |
109 | 05ee37eb | balrog | boff = boff >> 1;
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110 | 05ee37eb | balrog | else if (pfl->width == 4) |
111 | 05ee37eb | balrog | boff = boff >> 2;
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112 | 05ee37eb | balrog | |
113 | fad8c772 | Edgar E. Iglesias | #if 0
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114 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n",
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115 | 06adb549 | balrog | __func__, offset, pfl->cmd, width);
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116 | fad8c772 | Edgar E. Iglesias | #endif
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117 | 05ee37eb | balrog | switch (pfl->cmd) {
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118 | 05ee37eb | balrog | case 0x00: |
119 | 05ee37eb | balrog | /* Flash area read */
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120 | 05ee37eb | balrog | p = pfl->storage; |
121 | 05ee37eb | balrog | switch (width) {
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122 | 05ee37eb | balrog | case 1: |
123 | 05ee37eb | balrog | ret = p[offset]; |
124 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n", |
125 | c8b153d7 | ths | __func__, offset, ret); |
126 | 05ee37eb | balrog | break;
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127 | 05ee37eb | balrog | case 2: |
128 | 05ee37eb | balrog | #if defined(TARGET_WORDS_BIGENDIAN)
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129 | 05ee37eb | balrog | ret = p[offset] << 8;
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130 | 05ee37eb | balrog | ret |= p[offset + 1];
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131 | 05ee37eb | balrog | #else
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132 | 05ee37eb | balrog | ret = p[offset]; |
133 | 05ee37eb | balrog | ret |= p[offset + 1] << 8; |
134 | 05ee37eb | balrog | #endif
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135 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n", |
136 | c8b153d7 | ths | __func__, offset, ret); |
137 | 05ee37eb | balrog | break;
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138 | 05ee37eb | balrog | case 4: |
139 | 05ee37eb | balrog | #if defined(TARGET_WORDS_BIGENDIAN)
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140 | 05ee37eb | balrog | ret = p[offset] << 24;
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141 | 05ee37eb | balrog | ret |= p[offset + 1] << 16; |
142 | 05ee37eb | balrog | ret |= p[offset + 2] << 8; |
143 | 05ee37eb | balrog | ret |= p[offset + 3];
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144 | 05ee37eb | balrog | #else
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145 | 05ee37eb | balrog | ret = p[offset]; |
146 | 05ee37eb | balrog | ret |= p[offset + 1] << 8; |
147 | 05ee37eb | balrog | ret |= p[offset + 1] << 8; |
148 | 05ee37eb | balrog | ret |= p[offset + 2] << 16; |
149 | 05ee37eb | balrog | ret |= p[offset + 3] << 24; |
150 | 05ee37eb | balrog | #endif
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151 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n", |
152 | c8b153d7 | ths | __func__, offset, ret); |
153 | 05ee37eb | balrog | break;
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154 | 05ee37eb | balrog | default:
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155 | 05ee37eb | balrog | DPRINTF("BUG in %s\n", __func__);
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156 | 05ee37eb | balrog | } |
157 | 05ee37eb | balrog | |
158 | 05ee37eb | balrog | break;
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159 | 05ee37eb | balrog | case 0x20: /* Block erase */ |
160 | 05ee37eb | balrog | case 0x50: /* Clear status register */ |
161 | 05ee37eb | balrog | case 0x60: /* Block /un)lock */ |
162 | 05ee37eb | balrog | case 0x70: /* Status Register */ |
163 | 05ee37eb | balrog | case 0xe8: /* Write block */ |
164 | 05ee37eb | balrog | /* Status register read */
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165 | 05ee37eb | balrog | ret = pfl->status; |
166 | 05ee37eb | balrog | DPRINTF("%s: status %x\n", __func__, ret);
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167 | 05ee37eb | balrog | break;
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168 | 05ee37eb | balrog | case 0x98: /* Query mode */ |
169 | 05ee37eb | balrog | if (boff > pfl->cfi_len)
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170 | 05ee37eb | balrog | ret = 0;
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171 | 05ee37eb | balrog | else
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172 | 05ee37eb | balrog | ret = pfl->cfi_table[boff]; |
173 | 05ee37eb | balrog | break;
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174 | 05ee37eb | balrog | default:
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175 | 05ee37eb | balrog | /* This should never happen : reset state & treat it as a read */
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176 | 05ee37eb | balrog | DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
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177 | 05ee37eb | balrog | pfl->wcycle = 0;
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178 | 05ee37eb | balrog | pfl->cmd = 0;
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179 | 05ee37eb | balrog | } |
180 | 05ee37eb | balrog | return ret;
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181 | 05ee37eb | balrog | } |
182 | 05ee37eb | balrog | |
183 | 05ee37eb | balrog | /* update flash content on disk */
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184 | c227f099 | Anthony Liguori | static void pflash_update(pflash_t *pfl, int offset, |
185 | 05ee37eb | balrog | int size)
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186 | 05ee37eb | balrog | { |
187 | 05ee37eb | balrog | int offset_end;
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188 | 05ee37eb | balrog | if (pfl->bs) {
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189 | 05ee37eb | balrog | offset_end = offset + size; |
190 | 05ee37eb | balrog | /* round to sectors */
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191 | 05ee37eb | balrog | offset = offset >> 9;
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192 | 05ee37eb | balrog | offset_end = (offset_end + 511) >> 9; |
193 | 05ee37eb | balrog | bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
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194 | 05ee37eb | balrog | offset_end - offset); |
195 | 05ee37eb | balrog | } |
196 | 05ee37eb | balrog | } |
197 | 05ee37eb | balrog | |
198 | c227f099 | Anthony Liguori | static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset, |
199 | d361be25 | balrog | uint32_t value, int width)
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200 | d361be25 | balrog | { |
201 | d361be25 | balrog | uint8_t *p = pfl->storage; |
202 | d361be25 | balrog | |
203 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: block write offset " TARGET_FMT_plx
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204 | fad8c772 | Edgar E. Iglesias | " value %x counter " TARGET_FMT_plx "\n", |
205 | d361be25 | balrog | __func__, offset, value, pfl->counter); |
206 | d361be25 | balrog | switch (width) {
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207 | d361be25 | balrog | case 1: |
208 | d361be25 | balrog | p[offset] = value; |
209 | d361be25 | balrog | pflash_update(pfl, offset, 1);
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210 | d361be25 | balrog | break;
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211 | d361be25 | balrog | case 2: |
212 | d361be25 | balrog | #if defined(TARGET_WORDS_BIGENDIAN)
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213 | d361be25 | balrog | p[offset] = value >> 8;
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214 | d361be25 | balrog | p[offset + 1] = value;
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215 | d361be25 | balrog | #else
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216 | d361be25 | balrog | p[offset] = value; |
217 | d361be25 | balrog | p[offset + 1] = value >> 8; |
218 | d361be25 | balrog | #endif
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219 | d361be25 | balrog | pflash_update(pfl, offset, 2);
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220 | d361be25 | balrog | break;
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221 | d361be25 | balrog | case 4: |
222 | d361be25 | balrog | #if defined(TARGET_WORDS_BIGENDIAN)
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223 | d361be25 | balrog | p[offset] = value >> 24;
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224 | d361be25 | balrog | p[offset + 1] = value >> 16; |
225 | d361be25 | balrog | p[offset + 2] = value >> 8; |
226 | d361be25 | balrog | p[offset + 3] = value;
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227 | d361be25 | balrog | #else
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228 | d361be25 | balrog | p[offset] = value; |
229 | d361be25 | balrog | p[offset + 1] = value >> 8; |
230 | d361be25 | balrog | p[offset + 2] = value >> 16; |
231 | d361be25 | balrog | p[offset + 3] = value >> 24; |
232 | d361be25 | balrog | #endif
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233 | d361be25 | balrog | pflash_update(pfl, offset, 4);
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234 | d361be25 | balrog | break;
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235 | d361be25 | balrog | } |
236 | d361be25 | balrog | |
237 | d361be25 | balrog | } |
238 | d361be25 | balrog | |
239 | c227f099 | Anthony Liguori | static void pflash_write(pflash_t *pfl, target_phys_addr_t offset, |
240 | 42a89d77 | Paul Brook | uint32_t value, int width)
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241 | 05ee37eb | balrog | { |
242 | c227f099 | Anthony Liguori | target_phys_addr_t boff; |
243 | 05ee37eb | balrog | uint8_t *p; |
244 | 05ee37eb | balrog | uint8_t cmd; |
245 | 05ee37eb | balrog | |
246 | 05ee37eb | balrog | cmd = value; |
247 | 05ee37eb | balrog | |
248 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n", |
249 | c8b153d7 | ths | __func__, offset, value, width, pfl->wcycle); |
250 | 05ee37eb | balrog | |
251 | 05ee37eb | balrog | /* Set the device in I/O access mode */
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252 | 05ee37eb | balrog | cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem); |
253 | 05ee37eb | balrog | boff = offset & (pfl->sector_len - 1);
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254 | 05ee37eb | balrog | |
255 | 05ee37eb | balrog | if (pfl->width == 2) |
256 | 05ee37eb | balrog | boff = boff >> 1;
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257 | 05ee37eb | balrog | else if (pfl->width == 4) |
258 | 05ee37eb | balrog | boff = boff >> 2;
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259 | 05ee37eb | balrog | |
260 | 05ee37eb | balrog | switch (pfl->wcycle) {
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261 | 05ee37eb | balrog | case 0: |
262 | 05ee37eb | balrog | /* read mode */
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263 | 05ee37eb | balrog | switch (cmd) {
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264 | 05ee37eb | balrog | case 0x00: /* ??? */ |
265 | 05ee37eb | balrog | goto reset_flash;
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266 | d361be25 | balrog | case 0x10: /* Single Byte Program */ |
267 | d361be25 | balrog | case 0x40: /* Single Byte Program */ |
268 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: Single Byte Program\n", __func__);
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269 | d361be25 | balrog | break;
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270 | 05ee37eb | balrog | case 0x20: /* Block erase */ |
271 | 05ee37eb | balrog | p = pfl->storage; |
272 | 05ee37eb | balrog | offset &= ~(pfl->sector_len - 1);
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273 | 05ee37eb | balrog | |
274 | fad8c772 | Edgar E. Iglesias | DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes " |
275 | fad8c772 | Edgar E. Iglesias | TARGET_FMT_plx "\n",
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276 | c8b153d7 | ths | __func__, offset, pfl->sector_len); |
277 | 05ee37eb | balrog | |
278 | 05ee37eb | balrog | memset(p + offset, 0xff, pfl->sector_len);
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279 | 05ee37eb | balrog | pflash_update(pfl, offset, pfl->sector_len); |
280 | 05ee37eb | balrog | pfl->status |= 0x80; /* Ready! */ |
281 | 05ee37eb | balrog | break;
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282 | 05ee37eb | balrog | case 0x50: /* Clear status bits */ |
283 | 05ee37eb | balrog | DPRINTF("%s: Clear status bits\n", __func__);
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284 | 05ee37eb | balrog | pfl->status = 0x0;
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285 | 05ee37eb | balrog | goto reset_flash;
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286 | 05ee37eb | balrog | case 0x60: /* Block (un)lock */ |
287 | 05ee37eb | balrog | DPRINTF("%s: Block unlock\n", __func__);
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288 | 05ee37eb | balrog | break;
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289 | 05ee37eb | balrog | case 0x70: /* Status Register */ |
290 | 05ee37eb | balrog | DPRINTF("%s: Read status register\n", __func__);
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291 | 05ee37eb | balrog | pfl->cmd = cmd; |
292 | 05ee37eb | balrog | return;
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293 | 05ee37eb | balrog | case 0x98: /* CFI query */ |
294 | 05ee37eb | balrog | DPRINTF("%s: CFI query\n", __func__);
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295 | 05ee37eb | balrog | break;
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296 | 05ee37eb | balrog | case 0xe8: /* Write to buffer */ |
297 | 05ee37eb | balrog | DPRINTF("%s: Write to buffer\n", __func__);
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298 | 05ee37eb | balrog | pfl->status |= 0x80; /* Ready! */ |
299 | 05ee37eb | balrog | break;
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300 | 05ee37eb | balrog | case 0xff: /* Read array mode */ |
301 | 05ee37eb | balrog | DPRINTF("%s: Read array mode\n", __func__);
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302 | 05ee37eb | balrog | goto reset_flash;
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303 | 05ee37eb | balrog | default:
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304 | 05ee37eb | balrog | goto error_flash;
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305 | 05ee37eb | balrog | } |
306 | 05ee37eb | balrog | pfl->wcycle++; |
307 | 05ee37eb | balrog | pfl->cmd = cmd; |
308 | 05ee37eb | balrog | return;
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309 | 05ee37eb | balrog | case 1: |
310 | 05ee37eb | balrog | switch (pfl->cmd) {
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311 | d361be25 | balrog | case 0x10: /* Single Byte Program */ |
312 | d361be25 | balrog | case 0x40: /* Single Byte Program */ |
313 | d361be25 | balrog | DPRINTF("%s: Single Byte Program\n", __func__);
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314 | d361be25 | balrog | pflash_data_write(pfl, offset, value, width); |
315 | d361be25 | balrog | pfl->status |= 0x80; /* Ready! */ |
316 | d361be25 | balrog | pfl->wcycle = 0;
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317 | d361be25 | balrog | break;
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318 | 05ee37eb | balrog | case 0x20: /* Block erase */ |
319 | 05ee37eb | balrog | case 0x28: |
320 | 05ee37eb | balrog | if (cmd == 0xd0) { /* confirm */ |
321 | 3656744c | balrog | pfl->wcycle = 0;
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322 | 05ee37eb | balrog | pfl->status |= 0x80;
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323 | 9248f413 | aurel32 | } else if (cmd == 0xff) { /* read array mode */ |
324 | 05ee37eb | balrog | goto reset_flash;
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325 | 05ee37eb | balrog | } else
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326 | 05ee37eb | balrog | goto error_flash;
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327 | 05ee37eb | balrog | |
328 | 05ee37eb | balrog | break;
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329 | 05ee37eb | balrog | case 0xe8: |
330 | 71fb2348 | balrog | DPRINTF("%s: block write of %x bytes\n", __func__, value);
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331 | 71fb2348 | balrog | pfl->counter = value; |
332 | 05ee37eb | balrog | pfl->wcycle++; |
333 | 05ee37eb | balrog | break;
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334 | 05ee37eb | balrog | case 0x60: |
335 | 05ee37eb | balrog | if (cmd == 0xd0) { |
336 | 05ee37eb | balrog | pfl->wcycle = 0;
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337 | 05ee37eb | balrog | pfl->status |= 0x80;
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338 | 05ee37eb | balrog | } else if (cmd == 0x01) { |
339 | 05ee37eb | balrog | pfl->wcycle = 0;
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340 | 05ee37eb | balrog | pfl->status |= 0x80;
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341 | 05ee37eb | balrog | } else if (cmd == 0xff) { |
342 | 05ee37eb | balrog | goto reset_flash;
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343 | 05ee37eb | balrog | } else {
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344 | 05ee37eb | balrog | DPRINTF("%s: Unknown (un)locking command\n", __func__);
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345 | 05ee37eb | balrog | goto reset_flash;
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346 | 05ee37eb | balrog | } |
347 | 05ee37eb | balrog | break;
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348 | 05ee37eb | balrog | case 0x98: |
349 | 05ee37eb | balrog | if (cmd == 0xff) { |
350 | 05ee37eb | balrog | goto reset_flash;
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351 | 05ee37eb | balrog | } else {
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352 | 05ee37eb | balrog | DPRINTF("%s: leaving query mode\n", __func__);
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353 | 05ee37eb | balrog | } |
354 | 05ee37eb | balrog | break;
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355 | 05ee37eb | balrog | default:
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356 | 05ee37eb | balrog | goto error_flash;
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357 | 05ee37eb | balrog | } |
358 | 05ee37eb | balrog | return;
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359 | 05ee37eb | balrog | case 2: |
360 | 05ee37eb | balrog | switch (pfl->cmd) {
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361 | 05ee37eb | balrog | case 0xe8: /* Block write */ |
362 | d361be25 | balrog | pflash_data_write(pfl, offset, value, width); |
363 | 05ee37eb | balrog | |
364 | 05ee37eb | balrog | pfl->status |= 0x80;
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365 | 05ee37eb | balrog | |
366 | 05ee37eb | balrog | if (!pfl->counter) {
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367 | 05ee37eb | balrog | DPRINTF("%s: block write finished\n", __func__);
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368 | 05ee37eb | balrog | pfl->wcycle++; |
369 | 05ee37eb | balrog | } |
370 | 05ee37eb | balrog | |
371 | 05ee37eb | balrog | pfl->counter--; |
372 | 05ee37eb | balrog | break;
|
373 | 7317b8ca | balrog | default:
|
374 | 7317b8ca | balrog | goto error_flash;
|
375 | 05ee37eb | balrog | } |
376 | 05ee37eb | balrog | return;
|
377 | 05ee37eb | balrog | case 3: /* Confirm mode */ |
378 | 05ee37eb | balrog | switch (pfl->cmd) {
|
379 | 05ee37eb | balrog | case 0xe8: /* Block write */ |
380 | 05ee37eb | balrog | if (cmd == 0xd0) { |
381 | 05ee37eb | balrog | pfl->wcycle = 0;
|
382 | 05ee37eb | balrog | pfl->status |= 0x80;
|
383 | 05ee37eb | balrog | } else {
|
384 | 05ee37eb | balrog | DPRINTF("%s: unknown command for \"write block\"\n", __func__);
|
385 | 05ee37eb | balrog | PFLASH_BUG("Write block confirm");
|
386 | 7317b8ca | balrog | goto reset_flash;
|
387 | 05ee37eb | balrog | } |
388 | 7317b8ca | balrog | break;
|
389 | 7317b8ca | balrog | default:
|
390 | 7317b8ca | balrog | goto error_flash;
|
391 | 05ee37eb | balrog | } |
392 | 05ee37eb | balrog | return;
|
393 | 05ee37eb | balrog | default:
|
394 | 05ee37eb | balrog | /* Should never happen */
|
395 | 05ee37eb | balrog | DPRINTF("%s: invalid write state\n", __func__);
|
396 | 05ee37eb | balrog | goto reset_flash;
|
397 | 05ee37eb | balrog | } |
398 | 05ee37eb | balrog | return;
|
399 | 05ee37eb | balrog | |
400 | 05ee37eb | balrog | error_flash:
|
401 | 05ee37eb | balrog | printf("%s: Unimplemented flash cmd sequence "
|
402 | 42a89d77 | Paul Brook | "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)\n", |
403 | c8b153d7 | ths | __func__, offset, pfl->wcycle, pfl->cmd, value); |
404 | 05ee37eb | balrog | |
405 | 05ee37eb | balrog | reset_flash:
|
406 | 05ee37eb | balrog | cpu_register_physical_memory(pfl->base, pfl->total_len, |
407 | 05ee37eb | balrog | pfl->off | IO_MEM_ROMD | pfl->fl_mem); |
408 | 05ee37eb | balrog | |
409 | 05ee37eb | balrog | pfl->bypass = 0;
|
410 | 05ee37eb | balrog | pfl->wcycle = 0;
|
411 | 05ee37eb | balrog | pfl->cmd = 0;
|
412 | 05ee37eb | balrog | return;
|
413 | 05ee37eb | balrog | } |
414 | 05ee37eb | balrog | |
415 | 05ee37eb | balrog | |
416 | c227f099 | Anthony Liguori | static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr) |
417 | 05ee37eb | balrog | { |
418 | 05ee37eb | balrog | return pflash_read(opaque, addr, 1); |
419 | 05ee37eb | balrog | } |
420 | 05ee37eb | balrog | |
421 | c227f099 | Anthony Liguori | static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr) |
422 | 05ee37eb | balrog | { |
423 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
424 | 05ee37eb | balrog | |
425 | 05ee37eb | balrog | return pflash_read(pfl, addr, 2); |
426 | 05ee37eb | balrog | } |
427 | 05ee37eb | balrog | |
428 | c227f099 | Anthony Liguori | static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr) |
429 | 05ee37eb | balrog | { |
430 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
431 | 05ee37eb | balrog | |
432 | 05ee37eb | balrog | return pflash_read(pfl, addr, 4); |
433 | 05ee37eb | balrog | } |
434 | 05ee37eb | balrog | |
435 | c227f099 | Anthony Liguori | static void pflash_writeb (void *opaque, target_phys_addr_t addr, |
436 | 05ee37eb | balrog | uint32_t value) |
437 | 05ee37eb | balrog | { |
438 | 05ee37eb | balrog | pflash_write(opaque, addr, value, 1);
|
439 | 05ee37eb | balrog | } |
440 | 05ee37eb | balrog | |
441 | c227f099 | Anthony Liguori | static void pflash_writew (void *opaque, target_phys_addr_t addr, |
442 | 05ee37eb | balrog | uint32_t value) |
443 | 05ee37eb | balrog | { |
444 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
445 | 05ee37eb | balrog | |
446 | 05ee37eb | balrog | pflash_write(pfl, addr, value, 2);
|
447 | 05ee37eb | balrog | } |
448 | 05ee37eb | balrog | |
449 | c227f099 | Anthony Liguori | static void pflash_writel (void *opaque, target_phys_addr_t addr, |
450 | 05ee37eb | balrog | uint32_t value) |
451 | 05ee37eb | balrog | { |
452 | c227f099 | Anthony Liguori | pflash_t *pfl = opaque; |
453 | 05ee37eb | balrog | |
454 | 05ee37eb | balrog | pflash_write(pfl, addr, value, 4);
|
455 | 05ee37eb | balrog | } |
456 | 05ee37eb | balrog | |
457 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pflash_write_ops[] = { |
458 | 05ee37eb | balrog | &pflash_writeb, |
459 | 05ee37eb | balrog | &pflash_writew, |
460 | 05ee37eb | balrog | &pflash_writel, |
461 | 05ee37eb | balrog | }; |
462 | 05ee37eb | balrog | |
463 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pflash_read_ops[] = { |
464 | 05ee37eb | balrog | &pflash_readb, |
465 | 05ee37eb | balrog | &pflash_readw, |
466 | 05ee37eb | balrog | &pflash_readl, |
467 | 05ee37eb | balrog | }; |
468 | 05ee37eb | balrog | |
469 | 05ee37eb | balrog | /* Count trailing zeroes of a 32 bits quantity */
|
470 | 05ee37eb | balrog | static int ctz32 (uint32_t n) |
471 | 05ee37eb | balrog | { |
472 | 05ee37eb | balrog | int ret;
|
473 | 05ee37eb | balrog | |
474 | 05ee37eb | balrog | ret = 0;
|
475 | 05ee37eb | balrog | if (!(n & 0xFFFF)) { |
476 | 05ee37eb | balrog | ret += 16;
|
477 | 05ee37eb | balrog | n = n >> 16;
|
478 | 05ee37eb | balrog | } |
479 | 05ee37eb | balrog | if (!(n & 0xFF)) { |
480 | 05ee37eb | balrog | ret += 8;
|
481 | 05ee37eb | balrog | n = n >> 8;
|
482 | 05ee37eb | balrog | } |
483 | 05ee37eb | balrog | if (!(n & 0xF)) { |
484 | 05ee37eb | balrog | ret += 4;
|
485 | 05ee37eb | balrog | n = n >> 4;
|
486 | 05ee37eb | balrog | } |
487 | 05ee37eb | balrog | if (!(n & 0x3)) { |
488 | 05ee37eb | balrog | ret += 2;
|
489 | 05ee37eb | balrog | n = n >> 2;
|
490 | 05ee37eb | balrog | } |
491 | 05ee37eb | balrog | if (!(n & 0x1)) { |
492 | 05ee37eb | balrog | ret++; |
493 | 05ee37eb | balrog | n = n >> 1;
|
494 | 05ee37eb | balrog | } |
495 | 05ee37eb | balrog | #if 0 /* This is not necessary as n is never 0 */
|
496 | 05ee37eb | balrog | if (!n)
|
497 | 05ee37eb | balrog | ret++;
|
498 | 05ee37eb | balrog | #endif
|
499 | 05ee37eb | balrog | |
500 | 05ee37eb | balrog | return ret;
|
501 | 05ee37eb | balrog | } |
502 | 05ee37eb | balrog | |
503 | c227f099 | Anthony Liguori | pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, |
504 | c8b153d7 | ths | BlockDriverState *bs, uint32_t sector_len, |
505 | 88eeee0a | balrog | int nb_blocs, int width, |
506 | 88eeee0a | balrog | uint16_t id0, uint16_t id1, |
507 | 88eeee0a | balrog | uint16_t id2, uint16_t id3) |
508 | 05ee37eb | balrog | { |
509 | c227f099 | Anthony Liguori | pflash_t *pfl; |
510 | c227f099 | Anthony Liguori | target_phys_addr_t total_len; |
511 | d0e7605e | Vijay Kumar | int ret;
|
512 | 05ee37eb | balrog | |
513 | 05ee37eb | balrog | total_len = sector_len * nb_blocs; |
514 | 05ee37eb | balrog | |
515 | 05ee37eb | balrog | /* XXX: to be fixed */
|
516 | c8b153d7 | ths | #if 0
|
517 | 05ee37eb | balrog | if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
|
518 | 05ee37eb | balrog | total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
|
519 | 05ee37eb | balrog | return NULL;
|
520 | c8b153d7 | ths | #endif
|
521 | 05ee37eb | balrog | |
522 | c227f099 | Anthony Liguori | pfl = qemu_mallocz(sizeof(pflash_t));
|
523 | 05ee37eb | balrog | |
524 | 5c130f65 | pbrook | /* FIXME: Allocate ram ourselves. */
|
525 | 5c130f65 | pbrook | pfl->storage = qemu_get_ram_ptr(off); |
526 | 1eed09cb | Avi Kivity | pfl->fl_mem = cpu_register_io_memory( |
527 | 05ee37eb | balrog | pflash_read_ops, pflash_write_ops, pfl); |
528 | 05ee37eb | balrog | pfl->off = off; |
529 | 05ee37eb | balrog | cpu_register_physical_memory(base, total_len, |
530 | 05ee37eb | balrog | off | pfl->fl_mem | IO_MEM_ROMD); |
531 | 05ee37eb | balrog | |
532 | 05ee37eb | balrog | pfl->bs = bs; |
533 | 05ee37eb | balrog | if (pfl->bs) {
|
534 | 05ee37eb | balrog | /* read the initial flash content */
|
535 | d0e7605e | Vijay Kumar | ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); |
536 | d0e7605e | Vijay Kumar | if (ret < 0) { |
537 | d0e7605e | Vijay Kumar | cpu_unregister_io_memory(pfl->fl_mem); |
538 | d0e7605e | Vijay Kumar | qemu_free(pfl); |
539 | d0e7605e | Vijay Kumar | return NULL; |
540 | d0e7605e | Vijay Kumar | } |
541 | 05ee37eb | balrog | } |
542 | 05ee37eb | balrog | #if 0 /* XXX: there should be a bit to set up read-only,
|
543 | 05ee37eb | balrog | * the same way the hardware does (with WP pin).
|
544 | 05ee37eb | balrog | */
|
545 | 05ee37eb | balrog | pfl->ro = 1;
|
546 | 05ee37eb | balrog | #else
|
547 | 05ee37eb | balrog | pfl->ro = 0;
|
548 | 05ee37eb | balrog | #endif
|
549 | 05ee37eb | balrog | pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl); |
550 | 05ee37eb | balrog | pfl->base = base; |
551 | 05ee37eb | balrog | pfl->sector_len = sector_len; |
552 | 05ee37eb | balrog | pfl->total_len = total_len; |
553 | 05ee37eb | balrog | pfl->width = width; |
554 | 05ee37eb | balrog | pfl->wcycle = 0;
|
555 | 05ee37eb | balrog | pfl->cmd = 0;
|
556 | 05ee37eb | balrog | pfl->status = 0;
|
557 | 05ee37eb | balrog | pfl->ident[0] = id0;
|
558 | 05ee37eb | balrog | pfl->ident[1] = id1;
|
559 | 05ee37eb | balrog | pfl->ident[2] = id2;
|
560 | 05ee37eb | balrog | pfl->ident[3] = id3;
|
561 | 05ee37eb | balrog | /* Hardcoded CFI table */
|
562 | 05ee37eb | balrog | pfl->cfi_len = 0x52;
|
563 | 05ee37eb | balrog | /* Standard "QRY" string */
|
564 | 05ee37eb | balrog | pfl->cfi_table[0x10] = 'Q'; |
565 | 05ee37eb | balrog | pfl->cfi_table[0x11] = 'R'; |
566 | 05ee37eb | balrog | pfl->cfi_table[0x12] = 'Y'; |
567 | 05ee37eb | balrog | /* Command set (Intel) */
|
568 | 05ee37eb | balrog | pfl->cfi_table[0x13] = 0x01; |
569 | 05ee37eb | balrog | pfl->cfi_table[0x14] = 0x00; |
570 | 05ee37eb | balrog | /* Primary extended table address (none) */
|
571 | 05ee37eb | balrog | pfl->cfi_table[0x15] = 0x31; |
572 | 05ee37eb | balrog | pfl->cfi_table[0x16] = 0x00; |
573 | 05ee37eb | balrog | /* Alternate command set (none) */
|
574 | 05ee37eb | balrog | pfl->cfi_table[0x17] = 0x00; |
575 | 05ee37eb | balrog | pfl->cfi_table[0x18] = 0x00; |
576 | 05ee37eb | balrog | /* Alternate extended table (none) */
|
577 | 05ee37eb | balrog | pfl->cfi_table[0x19] = 0x00; |
578 | 05ee37eb | balrog | pfl->cfi_table[0x1A] = 0x00; |
579 | 05ee37eb | balrog | /* Vcc min */
|
580 | 05ee37eb | balrog | pfl->cfi_table[0x1B] = 0x45; |
581 | 05ee37eb | balrog | /* Vcc max */
|
582 | 05ee37eb | balrog | pfl->cfi_table[0x1C] = 0x55; |
583 | 05ee37eb | balrog | /* Vpp min (no Vpp pin) */
|
584 | 05ee37eb | balrog | pfl->cfi_table[0x1D] = 0x00; |
585 | 05ee37eb | balrog | /* Vpp max (no Vpp pin) */
|
586 | 05ee37eb | balrog | pfl->cfi_table[0x1E] = 0x00; |
587 | 05ee37eb | balrog | /* Reserved */
|
588 | 05ee37eb | balrog | pfl->cfi_table[0x1F] = 0x07; |
589 | 05ee37eb | balrog | /* Timeout for min size buffer write */
|
590 | 05ee37eb | balrog | pfl->cfi_table[0x20] = 0x07; |
591 | 05ee37eb | balrog | /* Typical timeout for block erase */
|
592 | 05ee37eb | balrog | pfl->cfi_table[0x21] = 0x0a; |
593 | 05ee37eb | balrog | /* Typical timeout for full chip erase (4096 ms) */
|
594 | 05ee37eb | balrog | pfl->cfi_table[0x22] = 0x00; |
595 | 05ee37eb | balrog | /* Reserved */
|
596 | 05ee37eb | balrog | pfl->cfi_table[0x23] = 0x04; |
597 | 05ee37eb | balrog | /* Max timeout for buffer write */
|
598 | 05ee37eb | balrog | pfl->cfi_table[0x24] = 0x04; |
599 | 05ee37eb | balrog | /* Max timeout for block erase */
|
600 | 05ee37eb | balrog | pfl->cfi_table[0x25] = 0x04; |
601 | 05ee37eb | balrog | /* Max timeout for chip erase */
|
602 | 05ee37eb | balrog | pfl->cfi_table[0x26] = 0x00; |
603 | 05ee37eb | balrog | /* Device size */
|
604 | 05ee37eb | balrog | pfl->cfi_table[0x27] = ctz32(total_len); // + 1; |
605 | 05ee37eb | balrog | /* Flash device interface (8 & 16 bits) */
|
606 | 05ee37eb | balrog | pfl->cfi_table[0x28] = 0x02; |
607 | 05ee37eb | balrog | pfl->cfi_table[0x29] = 0x00; |
608 | 05ee37eb | balrog | /* Max number of bytes in multi-bytes write */
|
609 | 71fb2348 | balrog | pfl->cfi_table[0x2A] = 0x0B; |
610 | 05ee37eb | balrog | pfl->cfi_table[0x2B] = 0x00; |
611 | 05ee37eb | balrog | /* Number of erase block regions (uniform) */
|
612 | 05ee37eb | balrog | pfl->cfi_table[0x2C] = 0x01; |
613 | 05ee37eb | balrog | /* Erase block region 1 */
|
614 | 05ee37eb | balrog | pfl->cfi_table[0x2D] = nb_blocs - 1; |
615 | 05ee37eb | balrog | pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; |
616 | 05ee37eb | balrog | pfl->cfi_table[0x2F] = sector_len >> 8; |
617 | 05ee37eb | balrog | pfl->cfi_table[0x30] = sector_len >> 16; |
618 | 05ee37eb | balrog | |
619 | 05ee37eb | balrog | /* Extended */
|
620 | 05ee37eb | balrog | pfl->cfi_table[0x31] = 'P'; |
621 | 05ee37eb | balrog | pfl->cfi_table[0x32] = 'R'; |
622 | 05ee37eb | balrog | pfl->cfi_table[0x33] = 'I'; |
623 | 05ee37eb | balrog | |
624 | 05ee37eb | balrog | pfl->cfi_table[0x34] = '1'; |
625 | 05ee37eb | balrog | pfl->cfi_table[0x35] = '1'; |
626 | 05ee37eb | balrog | |
627 | 05ee37eb | balrog | pfl->cfi_table[0x36] = 0x00; |
628 | 05ee37eb | balrog | pfl->cfi_table[0x37] = 0x00; |
629 | 05ee37eb | balrog | pfl->cfi_table[0x38] = 0x00; |
630 | 05ee37eb | balrog | pfl->cfi_table[0x39] = 0x00; |
631 | 05ee37eb | balrog | |
632 | 05ee37eb | balrog | pfl->cfi_table[0x3a] = 0x00; |
633 | 05ee37eb | balrog | |
634 | 05ee37eb | balrog | pfl->cfi_table[0x3b] = 0x00; |
635 | 05ee37eb | balrog | pfl->cfi_table[0x3c] = 0x00; |
636 | 05ee37eb | balrog | |
637 | 05ee37eb | balrog | return pfl;
|
638 | 05ee37eb | balrog | } |