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Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
Add 'static' to please Sparse
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Replace always_inline with inline
We define inline as always_inline.
Update to a hopefully more future proof FSF address
target-alpha: remove amask helper
The direct use of helper_amask in translate.c was bogus (as env is notassigned). Directly code amask in tcg and remove the helper.
Signed-off-by: Tristan Gingold <gingold@adacore.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-alpha: remove helper_load_implver
There is no need to use an helper. Directly load the value with tcg code.
Signed-off-by: Tristan Gingold <gingold@adacore.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7074 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: overflow condition for sublv and subqv
The conditions to detect overflow in sub operations was wrong.
This patch is necessary to boot Tru64.
target-alpha: tb_flush helper should flush the tb (and not the tlb).
Looks to be a typo fix.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6926 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-alpha: use CPU_Float/CPU_Double instead of ugly casts
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5771 c046a42c-6fe2-441c-8c8c-71466251a162
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: fix cmpbge instruction
The cmpbge instruction should compare all 8 bytes of one 64-bit value withanother. However, we were looping with a < 7 condition which was skippingthe top byte. So if we were doing a compare where the top byte was...
target-alpha: convert palcode ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5360 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert FP ops to TCG
- Convert FP ops to TCG- Fix S format- Implement F and G formats (untested)- Fix MF_FPCR an MT_FPCR- Fix FTOIS, FTOIT, ITOFF, ITOFS, ITOFT- Fix CPYSN, CPYSE
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5354 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert remaining arith3 functions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5254 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: switch a few helpers to TCG
Switch a few helpers to TCG and implement RC and RS instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5247 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert byte manipulation instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5246 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert arith2 instructions to TCG
Replace gen_arith2 generic macro and dyngon ops by instruction specificoptimized TCG code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5235 c046a42c-6fe2-441c-8c8c-71466251a162
Fix off-by-one unwinding error.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc host compile problem reported by Shaddy Baddah
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3750 c046a42c-6fe2-441c-8c8c-71466251a162
fixed invalid type
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3582 c046a42c-6fe2-441c-8c8c-71466251a162
Adjust s390 addresses (the MSB is defined as "to be ignored").
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3486 c046a42c-6fe2-441c-8c8c-71466251a162
Make Alpha and PowerPC targets use shared helpers for clz, clo, ctz, cto and ctpop.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3466 c046a42c-6fe2-441c-8c8c-71466251a162
Alpha coding style and inlining fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3462 c046a42c-6fe2-441c-8c8c-71466251a162
Use host-utils for Alpha 64x64 bits multiplications.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3443 c046a42c-6fe2-441c-8c8c-71466251a162
Generate micro-ops for Alpha executive and supervisor modes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3385 c046a42c-6fe2-441c-8c8c-71466251a162
Replace is_user variable with mmu_idx in softmmu core, allowing support of more than 2 mmu access modes.Add backward compatibility is_user variable in targets code when needed.Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions....
find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
Alpha architecture emulation core.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2597 c046a42c-6fe2-441c-8c8c-71466251a162