History | View | Annotate | Download (13 kB)
target-xtensa: Let cpu_xtensa_init() return XtensaCPU
Make the include paths for cpu-qom.h consistent to allow using XtensaCPUin cpu.h.
Turn cpu_init macro into a static inline function returningCPUXtensaState for backwards compatibility.
Signed-off-by: Andreas Färber <afaerber@suse.de>...
target-xtensa: QOM'ify CPU
Embed CPUXtensaState as first member of XtensaCPU.Let CPUClass::reset() call cpu_state_reset() for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: QOM'ify CPU reset
Move code from cpu_state_reset() into QOM xtensa_cpu_reset().To avoid moving reset_mmu() and dependencies, make it non-static.
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
target-xtensa: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUXtensaState/g" target-xtensa/*.[hc] sed -i "s/#define CPUXtensaState/#define CPUState/" target-xtensa/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
target-xtensa: add DBREAK data breakpoints
Add DBREAKA/DBREAKC SRs and implement DBREAK breakpoints as debugwatchpoints.
This implementation is not fully compliant to ISA: when a breakpoint isset to an unmapped/inaccessible memory address it generates TLB/memory...
target-xtensa: add ICOUNT SR and debug exception
ICOUNT SR gets incremented on every instruction completion provided thatCINTLEVEL at the beginning of the instruction execution is lower thanICOUNTLEVEL.
When ICOUNT would increment to 0 a debug exception is raised if...
target-xtensa: add DEBUGCAUSE SR and configuration
DEBUGCAUSE SR holds information about the most recent debug exception.See ISA, 4.7.7 for more details.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
target-xtensa: implement instruction breakpoints
Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK andBREAK.N instructions and IBREAK breakpoints.
IBREAK breakpoint address is considered constant for TB lifetime.On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated....
target-xtensa: implement info tlb monitor command
Command dumps valid ITLB and DTLB entries.
target-xtensa: extract core configuration from overlay
Introduce overlay_tool.h that defines core configuration blocks fromdata available in the linux architecture variant overlay.
Overlay data is automatically generated in the core configurationprocess by Tensilica tools and can be directly converted to qemu xtensa...
target-xtensa: implement external interrupt mapping
Xtensa cores may have different mapping of external interrupt pins tointernal IRQ numers. Implement API to acquire core IRQ by its externalinterrupt number.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>...
target-xtensa: increase xtensa options accuracy
- add separate options for each operation in the MISC_OP;- add an option for MULSH/MULUH;- put S32C1I under conditional store option.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-xtensa: implement MAC16 option
See ISA, 4.3.7 for the details.
- add ACC and MR special registers;- implement MAC16 and all inner MAC* opcode groups.
target-xtensa: fix guest hang on masked CCOMPARE interrupt
QEMU timer is used to post CCOMPARE interrupt when the core is halted.If that CCOMPARE interrupt is masked off then the timer must be rearmedin the callback, otherwise it will be rearmed next time the core goes to...
target-xtensa: implement relocatable vectors
See ISA, 4.4.3 for details.
Vector addresses recorded in core configuration are absolute values thatcorrespond to default VECBASE value.
target-xtensa: add gdb support
Specific xtensa processor overlay for GDB contains register map inthe gdb/xtensa-config.c. This description is used by the GDB to e.g.parse 'g' response packets and it may be reused in the qemu's gdbstub(only XTREG definitions for non-pseudoregisters are needed)....
target-xtensa: implement memory protection options
- TLB opcode group;- region protection option (ISA, 4.6.3);- region translation option (ISA, 4.6.4);- MMU option (ISA, 4.6.5).
Cache control attribute bits are not used by this implementation.
target-xtensa: implement boolean option
See ISA, 4.3.9
target-xtensa: implement windowed registers
See ISA, 4.7.1 for details.
Physical registers and currently visible window are separate fields inCPUEnv. Only current window is accessible to TCG. On operations thatchange window base helpers copy current window to and from physical...
target-xtensa: implement loop option
See ISA, 4.3.2 for details.
Operations that change LEND SR value invalidate TBs at the old and atthe new LEND. LEND value at TB compilation time is considered constantand loop instruction is generated based on this value....
target-xtensa: implement extended L32R
See ISA, 4.3.3 for details.
TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR.
target-xtensa: implement interrupt option
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interruptoption) and 4.4.8 (timer interrupt option) for details.
target-xtensa: implement CPENABLE and PRID SRs
target-xtensa: implement shifts (ST1 and RST1 groups)
- ST1: SAR (shift amount special register) manipulation, NSA;- RST1: shifts, 16-bit multiplication.
target-xtensa: implement LSAI group
- base + offset load/store operations for 1/2/4 byte values;- cache operations (not implemented);- multiprocessor synchronization operations.
target-xtensa: add PS register and access control
target-xtensa: implement exceptions
- mark privileged opcodes with ring check;- make debug exception on exception handler entry.
target-xtensa: add special and user registers
Special Registers hold the majority of the state added to the processorby the options. See ISA, 5.3 for details.
User Registers hold state added in support of designer's TIE and in somecases of options that Tensilica provides. See ISA, 5.4 for details....
target-xtensa: add target stubs
target-xtensa: implement disas_xtensa_insn
Set up disas_xtensa_insn switch structure, mark required options on highlevel groups. Implement arithmetic/bit logic/jump/call0.
Implement code generation loop with single step/breakpoint checking.