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/*
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* Marvell MV88W8618 / Freecom MusicPal emulation.
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*
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* Copyright (c) 2008 Jan Kiszka
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*
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* This code is licenced under the GNU GPL v2.
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*/
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#include "sysbus.h" |
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#include "arm-misc.h" |
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#include "devices.h" |
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#include "net.h" |
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#include "sysemu.h" |
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#include "boards.h" |
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#include "pc.h" |
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#include "qemu-timer.h" |
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#include "block.h" |
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#include "flash.h" |
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#include "console.h" |
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#include "i2c.h" |
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|
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#define MP_MISC_BASE 0x80002000 |
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#define MP_MISC_SIZE 0x00001000 |
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|
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#define MP_ETH_BASE 0x80008000 |
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#define MP_ETH_SIZE 0x00001000 |
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|
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#define MP_WLAN_BASE 0x8000C000 |
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#define MP_WLAN_SIZE 0x00000800 |
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|
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#define MP_UART1_BASE 0x8000C840 |
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#define MP_UART2_BASE 0x8000C940 |
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|
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#define MP_GPIO_BASE 0x8000D000 |
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#define MP_GPIO_SIZE 0x00001000 |
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|
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#define MP_FLASHCFG_BASE 0x90006000 |
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#define MP_FLASHCFG_SIZE 0x00001000 |
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|
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#define MP_AUDIO_BASE 0x90007000 |
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|
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#define MP_PIC_BASE 0x90008000 |
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#define MP_PIC_SIZE 0x00001000 |
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|
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#define MP_PIT_BASE 0x90009000 |
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#define MP_PIT_SIZE 0x00001000 |
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|
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#define MP_LCD_BASE 0x9000c000 |
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#define MP_LCD_SIZE 0x00001000 |
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|
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#define MP_SRAM_BASE 0xC0000000 |
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#define MP_SRAM_SIZE 0x00020000 |
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|
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#define MP_RAM_DEFAULT_SIZE 32*1024*1024 |
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#define MP_FLASH_SIZE_MAX 32*1024*1024 |
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|
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#define MP_TIMER1_IRQ 4 |
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#define MP_TIMER2_IRQ 5 |
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#define MP_TIMER3_IRQ 6 |
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#define MP_TIMER4_IRQ 7 |
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#define MP_EHCI_IRQ 8 |
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#define MP_ETH_IRQ 9 |
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#define MP_UART1_IRQ 11 |
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#define MP_UART2_IRQ 11 |
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#define MP_GPIO_IRQ 12 |
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#define MP_RTC_IRQ 28 |
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#define MP_AUDIO_IRQ 30 |
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|
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/* Wolfson 8750 I2C address */
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#define MP_WM_ADDR 0x1A |
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|
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/* Ethernet register offsets */
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#define MP_ETH_SMIR 0x010 |
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#define MP_ETH_PCXR 0x408 |
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#define MP_ETH_SDCMR 0x448 |
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#define MP_ETH_ICR 0x450 |
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#define MP_ETH_IMR 0x458 |
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#define MP_ETH_FRDP0 0x480 |
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#define MP_ETH_FRDP1 0x484 |
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#define MP_ETH_FRDP2 0x488 |
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#define MP_ETH_FRDP3 0x48C |
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#define MP_ETH_CRDP0 0x4A0 |
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#define MP_ETH_CRDP1 0x4A4 |
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#define MP_ETH_CRDP2 0x4A8 |
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#define MP_ETH_CRDP3 0x4AC |
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#define MP_ETH_CTDP0 0x4E0 |
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#define MP_ETH_CTDP1 0x4E4 |
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#define MP_ETH_CTDP2 0x4E8 |
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#define MP_ETH_CTDP3 0x4EC |
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|
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/* MII PHY access */
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#define MP_ETH_SMIR_DATA 0x0000FFFF |
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#define MP_ETH_SMIR_ADDR 0x03FF0000 |
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#define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */ |
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#define MP_ETH_SMIR_RDVALID (1 << 27) |
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|
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/* PHY registers */
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#define MP_ETH_PHY1_BMSR 0x00210000 |
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#define MP_ETH_PHY1_PHYSID1 0x00410000 |
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#define MP_ETH_PHY1_PHYSID2 0x00610000 |
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|
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#define MP_PHY_BMSR_LINK 0x0004 |
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#define MP_PHY_BMSR_AUTONEG 0x0008 |
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|
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#define MP_PHY_88E3015 0x01410E20 |
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|
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/* TX descriptor status */
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#define MP_ETH_TX_OWN (1 << 31) |
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|
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/* RX descriptor status */
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#define MP_ETH_RX_OWN (1 << 31) |
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|
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/* Interrupt cause/mask bits */
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#define MP_ETH_IRQ_RX_BIT 0 |
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#define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT) |
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#define MP_ETH_IRQ_TXHI_BIT 2 |
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#define MP_ETH_IRQ_TXLO_BIT 3 |
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|
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/* Port config bits */
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#define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */ |
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|
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/* SDMA command bits */
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#define MP_ETH_CMD_TXHI (1 << 23) |
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#define MP_ETH_CMD_TXLO (1 << 22) |
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|
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typedef struct mv88w8618_tx_desc { |
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uint32_t cmdstat; |
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uint16_t res; |
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uint16_t bytes; |
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uint32_t buffer; |
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uint32_t next; |
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} mv88w8618_tx_desc; |
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|
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typedef struct mv88w8618_rx_desc { |
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uint32_t cmdstat; |
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uint16_t bytes; |
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uint16_t buffer_size; |
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uint32_t buffer; |
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uint32_t next; |
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} mv88w8618_rx_desc; |
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|
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typedef struct mv88w8618_eth_state { |
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SysBusDevice busdev; |
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qemu_irq irq; |
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uint32_t smir; |
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uint32_t icr; |
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uint32_t imr; |
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int mmio_index;
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uint32_t vlan_header; |
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uint32_t tx_queue[2];
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uint32_t rx_queue[4];
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uint32_t frx_queue[4];
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uint32_t cur_rx[4];
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NICState *nic; |
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NICConf conf; |
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} mv88w8618_eth_state; |
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static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc) |
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{ |
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cpu_to_le32s(&desc->cmdstat); |
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cpu_to_le16s(&desc->bytes); |
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cpu_to_le16s(&desc->buffer_size); |
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cpu_to_le32s(&desc->buffer); |
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cpu_to_le32s(&desc->next); |
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cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); |
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} |
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static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc) |
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{ |
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cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); |
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le32_to_cpus(&desc->cmdstat); |
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le16_to_cpus(&desc->bytes); |
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le16_to_cpus(&desc->buffer_size); |
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le32_to_cpus(&desc->buffer); |
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le32_to_cpus(&desc->next); |
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} |
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static int eth_can_receive(VLANClientState *nc) |
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{ |
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return 1; |
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} |
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static ssize_t eth_receive(VLANClientState *nc, const uint8_t *buf, size_t size) |
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{ |
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mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque; |
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uint32_t desc_addr; |
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mv88w8618_rx_desc desc; |
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int i;
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for (i = 0; i < 4; i++) { |
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desc_addr = s->cur_rx[i]; |
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if (!desc_addr) {
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continue;
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} |
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do {
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eth_rx_desc_get(desc_addr, &desc); |
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if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
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cpu_physical_memory_write(desc.buffer + s->vlan_header, |
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buf, size); |
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desc.bytes = size + s->vlan_header; |
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desc.cmdstat &= ~MP_ETH_RX_OWN; |
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s->cur_rx[i] = desc.next; |
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s->icr |= MP_ETH_IRQ_RX; |
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if (s->icr & s->imr) {
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qemu_irq_raise(s->irq); |
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} |
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eth_rx_desc_put(desc_addr, &desc); |
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return size;
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} |
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desc_addr = desc.next; |
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} while (desc_addr != s->rx_queue[i]);
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} |
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return size;
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} |
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static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc) |
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{ |
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cpu_to_le32s(&desc->cmdstat); |
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cpu_to_le16s(&desc->res); |
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cpu_to_le16s(&desc->bytes); |
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cpu_to_le32s(&desc->buffer); |
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cpu_to_le32s(&desc->next); |
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cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc)); |
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} |
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static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc) |
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{ |
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cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc)); |
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le32_to_cpus(&desc->cmdstat); |
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le16_to_cpus(&desc->res); |
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le16_to_cpus(&desc->bytes); |
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le32_to_cpus(&desc->buffer); |
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le32_to_cpus(&desc->next); |
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} |
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static void eth_send(mv88w8618_eth_state *s, int queue_index) |
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{ |
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uint32_t desc_addr = s->tx_queue[queue_index]; |
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mv88w8618_tx_desc desc; |
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uint32_t next_desc; |
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uint8_t buf[2048];
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int len;
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do {
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eth_tx_desc_get(desc_addr, &desc); |
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next_desc = desc.next; |
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if (desc.cmdstat & MP_ETH_TX_OWN) {
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len = desc.bytes; |
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if (len < 2048) { |
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cpu_physical_memory_read(desc.buffer, buf, len); |
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qemu_send_packet(&s->nic->nc, buf, len); |
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} |
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desc.cmdstat &= ~MP_ETH_TX_OWN; |
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s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
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eth_tx_desc_put(desc_addr, &desc); |
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} |
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desc_addr = next_desc; |
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} while (desc_addr != s->tx_queue[queue_index]);
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} |
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static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset) |
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{ |
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mv88w8618_eth_state *s = opaque; |
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switch (offset) {
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case MP_ETH_SMIR:
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if (s->smir & MP_ETH_SMIR_OPCODE) {
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switch (s->smir & MP_ETH_SMIR_ADDR) {
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case MP_ETH_PHY1_BMSR:
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return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
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MP_ETH_SMIR_RDVALID; |
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case MP_ETH_PHY1_PHYSID1:
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return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID; |
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case MP_ETH_PHY1_PHYSID2:
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return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID; |
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default:
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return MP_ETH_SMIR_RDVALID;
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} |
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} |
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return 0; |
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|
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case MP_ETH_ICR:
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return s->icr;
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|
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case MP_ETH_IMR:
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return s->imr;
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|
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case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
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return s->frx_queue[(offset - MP_ETH_FRDP0)/4]; |
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|
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case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
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return s->rx_queue[(offset - MP_ETH_CRDP0)/4]; |
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|
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case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
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return s->tx_queue[(offset - MP_ETH_CTDP0)/4]; |
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|
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default:
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return 0; |
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} |
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} |
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|
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static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset, |
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uint32_t value) |
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{ |
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mv88w8618_eth_state *s = opaque; |
307 |
|
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switch (offset) {
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case MP_ETH_SMIR:
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s->smir = value; |
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break;
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|
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case MP_ETH_PCXR:
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s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2; |
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break;
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|
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case MP_ETH_SDCMR:
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if (value & MP_ETH_CMD_TXHI) {
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eth_send(s, 1);
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} |
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if (value & MP_ETH_CMD_TXLO) {
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eth_send(s, 0);
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} |
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if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
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qemu_irq_raise(s->irq); |
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} |
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break;
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|
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case MP_ETH_ICR:
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s->icr &= value; |
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break;
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|
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case MP_ETH_IMR:
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s->imr = value; |
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if (s->icr & s->imr) {
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qemu_irq_raise(s->irq); |
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} |
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break;
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|
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case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
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s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
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break;
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|
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case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
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s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
|
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s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
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break;
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|
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case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
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s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
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break;
|
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} |
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} |
354 |
|
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static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = { |
356 |
mv88w8618_eth_read, |
357 |
mv88w8618_eth_read, |
358 |
mv88w8618_eth_read |
359 |
}; |
360 |
|
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static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = { |
362 |
mv88w8618_eth_write, |
363 |
mv88w8618_eth_write, |
364 |
mv88w8618_eth_write |
365 |
}; |
366 |
|
367 |
static void eth_cleanup(VLANClientState *nc) |
368 |
{ |
369 |
mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque; |
370 |
|
371 |
s->nic = NULL;
|
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} |
373 |
|
374 |
static NetClientInfo net_mv88w8618_info = {
|
375 |
.type = NET_CLIENT_TYPE_NIC, |
376 |
.size = sizeof(NICState),
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.can_receive = eth_can_receive, |
378 |
.receive = eth_receive, |
379 |
.cleanup = eth_cleanup, |
380 |
}; |
381 |
|
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static int mv88w8618_eth_init(SysBusDevice *dev) |
383 |
{ |
384 |
mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev); |
385 |
|
386 |
sysbus_init_irq(dev, &s->irq); |
387 |
s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf, |
388 |
dev->qdev.info->name, dev->qdev.id, s); |
389 |
s->mmio_index = cpu_register_io_memory(mv88w8618_eth_readfn, |
390 |
mv88w8618_eth_writefn, s); |
391 |
sysbus_init_mmio(dev, MP_ETH_SIZE, s->mmio_index); |
392 |
return 0; |
393 |
} |
394 |
|
395 |
static const VMStateDescription mv88w8618_eth_vmsd = { |
396 |
.name = "mv88w8618_eth",
|
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.version_id = 1,
|
398 |
.minimum_version_id = 1,
|
399 |
.minimum_version_id_old = 1,
|
400 |
.fields = (VMStateField[]) { |
401 |
VMSTATE_UINT32(smir, mv88w8618_eth_state), |
402 |
VMSTATE_UINT32(icr, mv88w8618_eth_state), |
403 |
VMSTATE_UINT32(imr, mv88w8618_eth_state), |
404 |
VMSTATE_UINT32(vlan_header, mv88w8618_eth_state), |
405 |
VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2),
|
406 |
VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4),
|
407 |
VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4),
|
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VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4),
|
409 |
VMSTATE_END_OF_LIST() |
410 |
} |
411 |
}; |
412 |
|
413 |
static SysBusDeviceInfo mv88w8618_eth_info = {
|
414 |
.init = mv88w8618_eth_init, |
415 |
.qdev.name = "mv88w8618_eth",
|
416 |
.qdev.size = sizeof(mv88w8618_eth_state),
|
417 |
.qdev.vmsd = &mv88w8618_eth_vmsd, |
418 |
.qdev.props = (Property[]) { |
419 |
DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf), |
420 |
DEFINE_PROP_END_OF_LIST(), |
421 |
}, |
422 |
}; |
423 |
|
424 |
/* LCD register offsets */
|
425 |
#define MP_LCD_IRQCTRL 0x180 |
426 |
#define MP_LCD_IRQSTAT 0x184 |
427 |
#define MP_LCD_SPICTRL 0x1ac |
428 |
#define MP_LCD_INST 0x1bc |
429 |
#define MP_LCD_DATA 0x1c0 |
430 |
|
431 |
/* Mode magics */
|
432 |
#define MP_LCD_SPI_DATA 0x00100011 |
433 |
#define MP_LCD_SPI_CMD 0x00104011 |
434 |
#define MP_LCD_SPI_INVALID 0x00000000 |
435 |
|
436 |
/* Commmands */
|
437 |
#define MP_LCD_INST_SETPAGE0 0xB0 |
438 |
/* ... */
|
439 |
#define MP_LCD_INST_SETPAGE7 0xB7 |
440 |
|
441 |
#define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */ |
442 |
|
443 |
typedef struct musicpal_lcd_state { |
444 |
SysBusDevice busdev; |
445 |
uint32_t brightness; |
446 |
uint32_t mode; |
447 |
uint32_t irqctrl; |
448 |
uint32_t page; |
449 |
uint32_t page_off; |
450 |
DisplayState *ds; |
451 |
uint8_t video_ram[128*64/8]; |
452 |
} musicpal_lcd_state; |
453 |
|
454 |
static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
|
455 |
{ |
456 |
switch (s->brightness) {
|
457 |
case 7: |
458 |
return col;
|
459 |
case 0: |
460 |
return 0; |
461 |
default:
|
462 |
return (col * s->brightness) / 7; |
463 |
} |
464 |
} |
465 |
|
466 |
#define SET_LCD_PIXEL(depth, type) \
|
467 |
static inline void glue(set_lcd_pixel, depth) \ |
468 |
(musicpal_lcd_state *s, int x, int y, type col) \ |
469 |
{ \ |
470 |
int dx, dy; \
|
471 |
type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \ |
472 |
\ |
473 |
for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \ |
474 |
for (dx = 0; dx < 3; dx++, pixel++) \ |
475 |
*pixel = col; \ |
476 |
} |
477 |
SET_LCD_PIXEL(8, uint8_t)
|
478 |
SET_LCD_PIXEL(16, uint16_t)
|
479 |
SET_LCD_PIXEL(32, uint32_t)
|
480 |
|
481 |
#include "pixel_ops.h" |
482 |
|
483 |
static void lcd_refresh(void *opaque) |
484 |
{ |
485 |
musicpal_lcd_state *s = opaque; |
486 |
int x, y, col;
|
487 |
|
488 |
switch (ds_get_bits_per_pixel(s->ds)) {
|
489 |
case 0: |
490 |
return;
|
491 |
#define LCD_REFRESH(depth, func) \
|
492 |
case depth: \
|
493 |
col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \ |
494 |
scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \ |
495 |
scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
|
496 |
for (x = 0; x < 128; x++) { \ |
497 |
for (y = 0; y < 64; y++) { \ |
498 |
if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \ |
499 |
glue(set_lcd_pixel, depth)(s, x, y, col); \ |
500 |
} else { \
|
501 |
glue(set_lcd_pixel, depth)(s, x, y, 0); \
|
502 |
} \ |
503 |
} \ |
504 |
} \ |
505 |
break;
|
506 |
LCD_REFRESH(8, rgb_to_pixel8)
|
507 |
LCD_REFRESH(16, rgb_to_pixel16)
|
508 |
LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
|
509 |
rgb_to_pixel32bgr : rgb_to_pixel32)) |
510 |
default:
|
511 |
hw_error("unsupported colour depth %i\n",
|
512 |
ds_get_bits_per_pixel(s->ds)); |
513 |
} |
514 |
|
515 |
dpy_update(s->ds, 0, 0, 128*3, 64*3); |
516 |
} |
517 |
|
518 |
static void lcd_invalidate(void *opaque) |
519 |
{ |
520 |
} |
521 |
|
522 |
static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level) |
523 |
{ |
524 |
musicpal_lcd_state *s = opaque; |
525 |
s->brightness &= ~(1 << irq);
|
526 |
s->brightness |= level << irq; |
527 |
} |
528 |
|
529 |
static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset) |
530 |
{ |
531 |
musicpal_lcd_state *s = opaque; |
532 |
|
533 |
switch (offset) {
|
534 |
case MP_LCD_IRQCTRL:
|
535 |
return s->irqctrl;
|
536 |
|
537 |
default:
|
538 |
return 0; |
539 |
} |
540 |
} |
541 |
|
542 |
static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset, |
543 |
uint32_t value) |
544 |
{ |
545 |
musicpal_lcd_state *s = opaque; |
546 |
|
547 |
switch (offset) {
|
548 |
case MP_LCD_IRQCTRL:
|
549 |
s->irqctrl = value; |
550 |
break;
|
551 |
|
552 |
case MP_LCD_SPICTRL:
|
553 |
if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
|
554 |
s->mode = value; |
555 |
} else {
|
556 |
s->mode = MP_LCD_SPI_INVALID; |
557 |
} |
558 |
break;
|
559 |
|
560 |
case MP_LCD_INST:
|
561 |
if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
|
562 |
s->page = value - MP_LCD_INST_SETPAGE0; |
563 |
s->page_off = 0;
|
564 |
} |
565 |
break;
|
566 |
|
567 |
case MP_LCD_DATA:
|
568 |
if (s->mode == MP_LCD_SPI_CMD) {
|
569 |
if (value >= MP_LCD_INST_SETPAGE0 &&
|
570 |
value <= MP_LCD_INST_SETPAGE7) { |
571 |
s->page = value - MP_LCD_INST_SETPAGE0; |
572 |
s->page_off = 0;
|
573 |
} |
574 |
} else if (s->mode == MP_LCD_SPI_DATA) { |
575 |
s->video_ram[s->page*128 + s->page_off] = value;
|
576 |
s->page_off = (s->page_off + 1) & 127; |
577 |
} |
578 |
break;
|
579 |
} |
580 |
} |
581 |
|
582 |
static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = { |
583 |
musicpal_lcd_read, |
584 |
musicpal_lcd_read, |
585 |
musicpal_lcd_read |
586 |
}; |
587 |
|
588 |
static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = { |
589 |
musicpal_lcd_write, |
590 |
musicpal_lcd_write, |
591 |
musicpal_lcd_write |
592 |
}; |
593 |
|
594 |
static int musicpal_lcd_init(SysBusDevice *dev) |
595 |
{ |
596 |
musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev); |
597 |
int iomemtype;
|
598 |
|
599 |
s->brightness = 7;
|
600 |
|
601 |
iomemtype = cpu_register_io_memory(musicpal_lcd_readfn, |
602 |
musicpal_lcd_writefn, s); |
603 |
sysbus_init_mmio(dev, MP_LCD_SIZE, iomemtype); |
604 |
|
605 |
s->ds = graphic_console_init(lcd_refresh, lcd_invalidate, |
606 |
NULL, NULL, s); |
607 |
qemu_console_resize(s->ds, 128*3, 64*3); |
608 |
|
609 |
qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
|
610 |
|
611 |
return 0; |
612 |
} |
613 |
|
614 |
static const VMStateDescription musicpal_lcd_vmsd = { |
615 |
.name = "musicpal_lcd",
|
616 |
.version_id = 1,
|
617 |
.minimum_version_id = 1,
|
618 |
.minimum_version_id_old = 1,
|
619 |
.fields = (VMStateField[]) { |
620 |
VMSTATE_UINT32(brightness, musicpal_lcd_state), |
621 |
VMSTATE_UINT32(mode, musicpal_lcd_state), |
622 |
VMSTATE_UINT32(irqctrl, musicpal_lcd_state), |
623 |
VMSTATE_UINT32(page, musicpal_lcd_state), |
624 |
VMSTATE_UINT32(page_off, musicpal_lcd_state), |
625 |
VMSTATE_BUFFER(video_ram, musicpal_lcd_state), |
626 |
VMSTATE_END_OF_LIST() |
627 |
} |
628 |
}; |
629 |
|
630 |
static SysBusDeviceInfo musicpal_lcd_info = {
|
631 |
.init = musicpal_lcd_init, |
632 |
.qdev.name = "musicpal_lcd",
|
633 |
.qdev.size = sizeof(musicpal_lcd_state),
|
634 |
.qdev.vmsd = &musicpal_lcd_vmsd, |
635 |
}; |
636 |
|
637 |
/* PIC register offsets */
|
638 |
#define MP_PIC_STATUS 0x00 |
639 |
#define MP_PIC_ENABLE_SET 0x08 |
640 |
#define MP_PIC_ENABLE_CLR 0x0C |
641 |
|
642 |
typedef struct mv88w8618_pic_state |
643 |
{ |
644 |
SysBusDevice busdev; |
645 |
uint32_t level; |
646 |
uint32_t enabled; |
647 |
qemu_irq parent_irq; |
648 |
} mv88w8618_pic_state; |
649 |
|
650 |
static void mv88w8618_pic_update(mv88w8618_pic_state *s) |
651 |
{ |
652 |
qemu_set_irq(s->parent_irq, (s->level & s->enabled)); |
653 |
} |
654 |
|
655 |
static void mv88w8618_pic_set_irq(void *opaque, int irq, int level) |
656 |
{ |
657 |
mv88w8618_pic_state *s = opaque; |
658 |
|
659 |
if (level) {
|
660 |
s->level |= 1 << irq;
|
661 |
} else {
|
662 |
s->level &= ~(1 << irq);
|
663 |
} |
664 |
mv88w8618_pic_update(s); |
665 |
} |
666 |
|
667 |
static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset) |
668 |
{ |
669 |
mv88w8618_pic_state *s = opaque; |
670 |
|
671 |
switch (offset) {
|
672 |
case MP_PIC_STATUS:
|
673 |
return s->level & s->enabled;
|
674 |
|
675 |
default:
|
676 |
return 0; |
677 |
} |
678 |
} |
679 |
|
680 |
static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset, |
681 |
uint32_t value) |
682 |
{ |
683 |
mv88w8618_pic_state *s = opaque; |
684 |
|
685 |
switch (offset) {
|
686 |
case MP_PIC_ENABLE_SET:
|
687 |
s->enabled |= value; |
688 |
break;
|
689 |
|
690 |
case MP_PIC_ENABLE_CLR:
|
691 |
s->enabled &= ~value; |
692 |
s->level &= ~value; |
693 |
break;
|
694 |
} |
695 |
mv88w8618_pic_update(s); |
696 |
} |
697 |
|
698 |
static void mv88w8618_pic_reset(DeviceState *d) |
699 |
{ |
700 |
mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, |
701 |
sysbus_from_qdev(d)); |
702 |
|
703 |
s->level = 0;
|
704 |
s->enabled = 0;
|
705 |
} |
706 |
|
707 |
static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = { |
708 |
mv88w8618_pic_read, |
709 |
mv88w8618_pic_read, |
710 |
mv88w8618_pic_read |
711 |
}; |
712 |
|
713 |
static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = { |
714 |
mv88w8618_pic_write, |
715 |
mv88w8618_pic_write, |
716 |
mv88w8618_pic_write |
717 |
}; |
718 |
|
719 |
static int mv88w8618_pic_init(SysBusDevice *dev) |
720 |
{ |
721 |
mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev); |
722 |
int iomemtype;
|
723 |
|
724 |
qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
|
725 |
sysbus_init_irq(dev, &s->parent_irq); |
726 |
iomemtype = cpu_register_io_memory(mv88w8618_pic_readfn, |
727 |
mv88w8618_pic_writefn, s); |
728 |
sysbus_init_mmio(dev, MP_PIC_SIZE, iomemtype); |
729 |
return 0; |
730 |
} |
731 |
|
732 |
static const VMStateDescription mv88w8618_pic_vmsd = { |
733 |
.name = "mv88w8618_pic",
|
734 |
.version_id = 1,
|
735 |
.minimum_version_id = 1,
|
736 |
.minimum_version_id_old = 1,
|
737 |
.fields = (VMStateField[]) { |
738 |
VMSTATE_UINT32(level, mv88w8618_pic_state), |
739 |
VMSTATE_UINT32(enabled, mv88w8618_pic_state), |
740 |
VMSTATE_END_OF_LIST() |
741 |
} |
742 |
}; |
743 |
|
744 |
static SysBusDeviceInfo mv88w8618_pic_info = {
|
745 |
.init = mv88w8618_pic_init, |
746 |
.qdev.name = "mv88w8618_pic",
|
747 |
.qdev.size = sizeof(mv88w8618_pic_state),
|
748 |
.qdev.reset = mv88w8618_pic_reset, |
749 |
.qdev.vmsd = &mv88w8618_pic_vmsd, |
750 |
}; |
751 |
|
752 |
/* PIT register offsets */
|
753 |
#define MP_PIT_TIMER1_LENGTH 0x00 |
754 |
/* ... */
|
755 |
#define MP_PIT_TIMER4_LENGTH 0x0C |
756 |
#define MP_PIT_CONTROL 0x10 |
757 |
#define MP_PIT_TIMER1_VALUE 0x14 |
758 |
/* ... */
|
759 |
#define MP_PIT_TIMER4_VALUE 0x20 |
760 |
#define MP_BOARD_RESET 0x34 |
761 |
|
762 |
/* Magic board reset value (probably some watchdog behind it) */
|
763 |
#define MP_BOARD_RESET_MAGIC 0x10000 |
764 |
|
765 |
typedef struct mv88w8618_timer_state { |
766 |
ptimer_state *ptimer; |
767 |
uint32_t limit; |
768 |
int freq;
|
769 |
qemu_irq irq; |
770 |
} mv88w8618_timer_state; |
771 |
|
772 |
typedef struct mv88w8618_pit_state { |
773 |
SysBusDevice busdev; |
774 |
mv88w8618_timer_state timer[4];
|
775 |
} mv88w8618_pit_state; |
776 |
|
777 |
static void mv88w8618_timer_tick(void *opaque) |
778 |
{ |
779 |
mv88w8618_timer_state *s = opaque; |
780 |
|
781 |
qemu_irq_raise(s->irq); |
782 |
} |
783 |
|
784 |
static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s, |
785 |
uint32_t freq) |
786 |
{ |
787 |
QEMUBH *bh; |
788 |
|
789 |
sysbus_init_irq(dev, &s->irq); |
790 |
s->freq = freq; |
791 |
|
792 |
bh = qemu_bh_new(mv88w8618_timer_tick, s); |
793 |
s->ptimer = ptimer_init(bh); |
794 |
} |
795 |
|
796 |
static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset) |
797 |
{ |
798 |
mv88w8618_pit_state *s = opaque; |
799 |
mv88w8618_timer_state *t; |
800 |
|
801 |
switch (offset) {
|
802 |
case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
|
803 |
t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
|
804 |
return ptimer_get_count(t->ptimer);
|
805 |
|
806 |
default:
|
807 |
return 0; |
808 |
} |
809 |
} |
810 |
|
811 |
static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset, |
812 |
uint32_t value) |
813 |
{ |
814 |
mv88w8618_pit_state *s = opaque; |
815 |
mv88w8618_timer_state *t; |
816 |
int i;
|
817 |
|
818 |
switch (offset) {
|
819 |
case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
|
820 |
t = &s->timer[offset >> 2];
|
821 |
t->limit = value; |
822 |
if (t->limit > 0) { |
823 |
ptimer_set_limit(t->ptimer, t->limit, 1);
|
824 |
} else {
|
825 |
ptimer_stop(t->ptimer); |
826 |
} |
827 |
break;
|
828 |
|
829 |
case MP_PIT_CONTROL:
|
830 |
for (i = 0; i < 4; i++) { |
831 |
t = &s->timer[i]; |
832 |
if (value & 0xf && t->limit > 0) { |
833 |
ptimer_set_limit(t->ptimer, t->limit, 0);
|
834 |
ptimer_set_freq(t->ptimer, t->freq); |
835 |
ptimer_run(t->ptimer, 0);
|
836 |
} else {
|
837 |
ptimer_stop(t->ptimer); |
838 |
} |
839 |
value >>= 4;
|
840 |
} |
841 |
break;
|
842 |
|
843 |
case MP_BOARD_RESET:
|
844 |
if (value == MP_BOARD_RESET_MAGIC) {
|
845 |
qemu_system_reset_request(); |
846 |
} |
847 |
break;
|
848 |
} |
849 |
} |
850 |
|
851 |
static void mv88w8618_pit_reset(DeviceState *d) |
852 |
{ |
853 |
mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, |
854 |
sysbus_from_qdev(d)); |
855 |
int i;
|
856 |
|
857 |
for (i = 0; i < 4; i++) { |
858 |
ptimer_stop(s->timer[i].ptimer); |
859 |
s->timer[i].limit = 0;
|
860 |
} |
861 |
} |
862 |
|
863 |
static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = { |
864 |
mv88w8618_pit_read, |
865 |
mv88w8618_pit_read, |
866 |
mv88w8618_pit_read |
867 |
}; |
868 |
|
869 |
static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = { |
870 |
mv88w8618_pit_write, |
871 |
mv88w8618_pit_write, |
872 |
mv88w8618_pit_write |
873 |
}; |
874 |
|
875 |
static int mv88w8618_pit_init(SysBusDevice *dev) |
876 |
{ |
877 |
int iomemtype;
|
878 |
mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev); |
879 |
int i;
|
880 |
|
881 |
/* Letting them all run at 1 MHz is likely just a pragmatic
|
882 |
* simplification. */
|
883 |
for (i = 0; i < 4; i++) { |
884 |
mv88w8618_timer_init(dev, &s->timer[i], 1000000);
|
885 |
} |
886 |
|
887 |
iomemtype = cpu_register_io_memory(mv88w8618_pit_readfn, |
888 |
mv88w8618_pit_writefn, s); |
889 |
sysbus_init_mmio(dev, MP_PIT_SIZE, iomemtype); |
890 |
return 0; |
891 |
} |
892 |
|
893 |
static const VMStateDescription mv88w8618_timer_vmsd = { |
894 |
.name = "timer",
|
895 |
.version_id = 1,
|
896 |
.minimum_version_id = 1,
|
897 |
.minimum_version_id_old = 1,
|
898 |
.fields = (VMStateField[]) { |
899 |
VMSTATE_PTIMER(ptimer, mv88w8618_timer_state), |
900 |
VMSTATE_UINT32(limit, mv88w8618_timer_state), |
901 |
VMSTATE_END_OF_LIST() |
902 |
} |
903 |
}; |
904 |
|
905 |
static const VMStateDescription mv88w8618_pit_vmsd = { |
906 |
.name = "mv88w8618_pit",
|
907 |
.version_id = 1,
|
908 |
.minimum_version_id = 1,
|
909 |
.minimum_version_id_old = 1,
|
910 |
.fields = (VMStateField[]) { |
911 |
VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1, |
912 |
mv88w8618_timer_vmsd, mv88w8618_timer_state), |
913 |
VMSTATE_END_OF_LIST() |
914 |
} |
915 |
}; |
916 |
|
917 |
static SysBusDeviceInfo mv88w8618_pit_info = {
|
918 |
.init = mv88w8618_pit_init, |
919 |
.qdev.name = "mv88w8618_pit",
|
920 |
.qdev.size = sizeof(mv88w8618_pit_state),
|
921 |
.qdev.reset = mv88w8618_pit_reset, |
922 |
.qdev.vmsd = &mv88w8618_pit_vmsd, |
923 |
}; |
924 |
|
925 |
/* Flash config register offsets */
|
926 |
#define MP_FLASHCFG_CFGR0 0x04 |
927 |
|
928 |
typedef struct mv88w8618_flashcfg_state { |
929 |
SysBusDevice busdev; |
930 |
uint32_t cfgr0; |
931 |
} mv88w8618_flashcfg_state; |
932 |
|
933 |
static uint32_t mv88w8618_flashcfg_read(void *opaque, |
934 |
target_phys_addr_t offset) |
935 |
{ |
936 |
mv88w8618_flashcfg_state *s = opaque; |
937 |
|
938 |
switch (offset) {
|
939 |
case MP_FLASHCFG_CFGR0:
|
940 |
return s->cfgr0;
|
941 |
|
942 |
default:
|
943 |
return 0; |
944 |
} |
945 |
} |
946 |
|
947 |
static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset, |
948 |
uint32_t value) |
949 |
{ |
950 |
mv88w8618_flashcfg_state *s = opaque; |
951 |
|
952 |
switch (offset) {
|
953 |
case MP_FLASHCFG_CFGR0:
|
954 |
s->cfgr0 = value; |
955 |
break;
|
956 |
} |
957 |
} |
958 |
|
959 |
static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = { |
960 |
mv88w8618_flashcfg_read, |
961 |
mv88w8618_flashcfg_read, |
962 |
mv88w8618_flashcfg_read |
963 |
}; |
964 |
|
965 |
static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = { |
966 |
mv88w8618_flashcfg_write, |
967 |
mv88w8618_flashcfg_write, |
968 |
mv88w8618_flashcfg_write |
969 |
}; |
970 |
|
971 |
static int mv88w8618_flashcfg_init(SysBusDevice *dev) |
972 |
{ |
973 |
int iomemtype;
|
974 |
mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev); |
975 |
|
976 |
s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */ |
977 |
iomemtype = cpu_register_io_memory(mv88w8618_flashcfg_readfn, |
978 |
mv88w8618_flashcfg_writefn, s); |
979 |
sysbus_init_mmio(dev, MP_FLASHCFG_SIZE, iomemtype); |
980 |
return 0; |
981 |
} |
982 |
|
983 |
static const VMStateDescription mv88w8618_flashcfg_vmsd = { |
984 |
.name = "mv88w8618_flashcfg",
|
985 |
.version_id = 1,
|
986 |
.minimum_version_id = 1,
|
987 |
.minimum_version_id_old = 1,
|
988 |
.fields = (VMStateField[]) { |
989 |
VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state), |
990 |
VMSTATE_END_OF_LIST() |
991 |
} |
992 |
}; |
993 |
|
994 |
static SysBusDeviceInfo mv88w8618_flashcfg_info = {
|
995 |
.init = mv88w8618_flashcfg_init, |
996 |
.qdev.name = "mv88w8618_flashcfg",
|
997 |
.qdev.size = sizeof(mv88w8618_flashcfg_state),
|
998 |
.qdev.vmsd = &mv88w8618_flashcfg_vmsd, |
999 |
}; |
1000 |
|
1001 |
/* Misc register offsets */
|
1002 |
#define MP_MISC_BOARD_REVISION 0x18 |
1003 |
|
1004 |
#define MP_BOARD_REVISION 0x31 |
1005 |
|
1006 |
static uint32_t musicpal_misc_read(void *opaque, target_phys_addr_t offset) |
1007 |
{ |
1008 |
switch (offset) {
|
1009 |
case MP_MISC_BOARD_REVISION:
|
1010 |
return MP_BOARD_REVISION;
|
1011 |
|
1012 |
default:
|
1013 |
return 0; |
1014 |
} |
1015 |
} |
1016 |
|
1017 |
static void musicpal_misc_write(void *opaque, target_phys_addr_t offset, |
1018 |
uint32_t value) |
1019 |
{ |
1020 |
} |
1021 |
|
1022 |
static CPUReadMemoryFunc * const musicpal_misc_readfn[] = { |
1023 |
musicpal_misc_read, |
1024 |
musicpal_misc_read, |
1025 |
musicpal_misc_read, |
1026 |
}; |
1027 |
|
1028 |
static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = { |
1029 |
musicpal_misc_write, |
1030 |
musicpal_misc_write, |
1031 |
musicpal_misc_write, |
1032 |
}; |
1033 |
|
1034 |
static void musicpal_misc_init(void) |
1035 |
{ |
1036 |
int iomemtype;
|
1037 |
|
1038 |
iomemtype = cpu_register_io_memory(musicpal_misc_readfn, |
1039 |
musicpal_misc_writefn, NULL);
|
1040 |
cpu_register_physical_memory(MP_MISC_BASE, MP_MISC_SIZE, iomemtype); |
1041 |
} |
1042 |
|
1043 |
/* WLAN register offsets */
|
1044 |
#define MP_WLAN_MAGIC1 0x11c |
1045 |
#define MP_WLAN_MAGIC2 0x124 |
1046 |
|
1047 |
static uint32_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset) |
1048 |
{ |
1049 |
switch (offset) {
|
1050 |
/* Workaround to allow loading the binary-only wlandrv.ko crap
|
1051 |
* from the original Freecom firmware. */
|
1052 |
case MP_WLAN_MAGIC1:
|
1053 |
return ~3; |
1054 |
case MP_WLAN_MAGIC2:
|
1055 |
return -1; |
1056 |
|
1057 |
default:
|
1058 |
return 0; |
1059 |
} |
1060 |
} |
1061 |
|
1062 |
static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset, |
1063 |
uint32_t value) |
1064 |
{ |
1065 |
} |
1066 |
|
1067 |
static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = { |
1068 |
mv88w8618_wlan_read, |
1069 |
mv88w8618_wlan_read, |
1070 |
mv88w8618_wlan_read, |
1071 |
}; |
1072 |
|
1073 |
static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = { |
1074 |
mv88w8618_wlan_write, |
1075 |
mv88w8618_wlan_write, |
1076 |
mv88w8618_wlan_write, |
1077 |
}; |
1078 |
|
1079 |
static int mv88w8618_wlan_init(SysBusDevice *dev) |
1080 |
{ |
1081 |
int iomemtype;
|
1082 |
|
1083 |
iomemtype = cpu_register_io_memory(mv88w8618_wlan_readfn, |
1084 |
mv88w8618_wlan_writefn, NULL);
|
1085 |
sysbus_init_mmio(dev, MP_WLAN_SIZE, iomemtype); |
1086 |
return 0; |
1087 |
} |
1088 |
|
1089 |
/* GPIO register offsets */
|
1090 |
#define MP_GPIO_OE_LO 0x008 |
1091 |
#define MP_GPIO_OUT_LO 0x00c |
1092 |
#define MP_GPIO_IN_LO 0x010 |
1093 |
#define MP_GPIO_IER_LO 0x014 |
1094 |
#define MP_GPIO_IMR_LO 0x018 |
1095 |
#define MP_GPIO_ISR_LO 0x020 |
1096 |
#define MP_GPIO_OE_HI 0x508 |
1097 |
#define MP_GPIO_OUT_HI 0x50c |
1098 |
#define MP_GPIO_IN_HI 0x510 |
1099 |
#define MP_GPIO_IER_HI 0x514 |
1100 |
#define MP_GPIO_IMR_HI 0x518 |
1101 |
#define MP_GPIO_ISR_HI 0x520 |
1102 |
|
1103 |
/* GPIO bits & masks */
|
1104 |
#define MP_GPIO_LCD_BRIGHTNESS 0x00070000 |
1105 |
#define MP_GPIO_I2C_DATA_BIT 29 |
1106 |
#define MP_GPIO_I2C_CLOCK_BIT 30 |
1107 |
|
1108 |
/* LCD brightness bits in GPIO_OE_HI */
|
1109 |
#define MP_OE_LCD_BRIGHTNESS 0x0007 |
1110 |
|
1111 |
typedef struct musicpal_gpio_state { |
1112 |
SysBusDevice busdev; |
1113 |
uint32_t lcd_brightness; |
1114 |
uint32_t out_state; |
1115 |
uint32_t in_state; |
1116 |
uint32_t ier; |
1117 |
uint32_t imr; |
1118 |
uint32_t isr; |
1119 |
qemu_irq irq; |
1120 |
qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */ |
1121 |
} musicpal_gpio_state; |
1122 |
|
1123 |
static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) { |
1124 |
int i;
|
1125 |
uint32_t brightness; |
1126 |
|
1127 |
/* compute brightness ratio */
|
1128 |
switch (s->lcd_brightness) {
|
1129 |
case 0x00000007: |
1130 |
brightness = 0;
|
1131 |
break;
|
1132 |
|
1133 |
case 0x00020000: |
1134 |
brightness = 1;
|
1135 |
break;
|
1136 |
|
1137 |
case 0x00020001: |
1138 |
brightness = 2;
|
1139 |
break;
|
1140 |
|
1141 |
case 0x00040000: |
1142 |
brightness = 3;
|
1143 |
break;
|
1144 |
|
1145 |
case 0x00010006: |
1146 |
brightness = 4;
|
1147 |
break;
|
1148 |
|
1149 |
case 0x00020005: |
1150 |
brightness = 5;
|
1151 |
break;
|
1152 |
|
1153 |
case 0x00040003: |
1154 |
brightness = 6;
|
1155 |
break;
|
1156 |
|
1157 |
case 0x00030004: |
1158 |
default:
|
1159 |
brightness = 7;
|
1160 |
} |
1161 |
|
1162 |
/* set lcd brightness GPIOs */
|
1163 |
for (i = 0; i <= 2; i++) { |
1164 |
qemu_set_irq(s->out[i], (brightness >> i) & 1);
|
1165 |
} |
1166 |
} |
1167 |
|
1168 |
static void musicpal_gpio_pin_event(void *opaque, int pin, int level) |
1169 |
{ |
1170 |
musicpal_gpio_state *s = opaque; |
1171 |
uint32_t mask = 1 << pin;
|
1172 |
uint32_t delta = level << pin; |
1173 |
uint32_t old = s->in_state & mask; |
1174 |
|
1175 |
s->in_state &= ~mask; |
1176 |
s->in_state |= delta; |
1177 |
|
1178 |
if ((old ^ delta) &&
|
1179 |
((level && (s->imr & mask)) || (!level && (s->ier & mask)))) { |
1180 |
s->isr = mask; |
1181 |
qemu_irq_raise(s->irq); |
1182 |
} |
1183 |
} |
1184 |
|
1185 |
static uint32_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset) |
1186 |
{ |
1187 |
musicpal_gpio_state *s = opaque; |
1188 |
|
1189 |
switch (offset) {
|
1190 |
case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
1191 |
return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
|
1192 |
|
1193 |
case MP_GPIO_OUT_LO:
|
1194 |
return s->out_state & 0xFFFF; |
1195 |
case MP_GPIO_OUT_HI:
|
1196 |
return s->out_state >> 16; |
1197 |
|
1198 |
case MP_GPIO_IN_LO:
|
1199 |
return s->in_state & 0xFFFF; |
1200 |
case MP_GPIO_IN_HI:
|
1201 |
return s->in_state >> 16; |
1202 |
|
1203 |
case MP_GPIO_IER_LO:
|
1204 |
return s->ier & 0xFFFF; |
1205 |
case MP_GPIO_IER_HI:
|
1206 |
return s->ier >> 16; |
1207 |
|
1208 |
case MP_GPIO_IMR_LO:
|
1209 |
return s->imr & 0xFFFF; |
1210 |
case MP_GPIO_IMR_HI:
|
1211 |
return s->imr >> 16; |
1212 |
|
1213 |
case MP_GPIO_ISR_LO:
|
1214 |
return s->isr & 0xFFFF; |
1215 |
case MP_GPIO_ISR_HI:
|
1216 |
return s->isr >> 16; |
1217 |
|
1218 |
default:
|
1219 |
return 0; |
1220 |
} |
1221 |
} |
1222 |
|
1223 |
static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset, |
1224 |
uint32_t value) |
1225 |
{ |
1226 |
musicpal_gpio_state *s = opaque; |
1227 |
switch (offset) {
|
1228 |
case MP_GPIO_OE_HI: /* used for LCD brightness control */ |
1229 |
s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) | |
1230 |
(value & MP_OE_LCD_BRIGHTNESS); |
1231 |
musicpal_gpio_brightness_update(s); |
1232 |
break;
|
1233 |
|
1234 |
case MP_GPIO_OUT_LO:
|
1235 |
s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF); |
1236 |
break;
|
1237 |
case MP_GPIO_OUT_HI:
|
1238 |
s->out_state = (s->out_state & 0xFFFF) | (value << 16); |
1239 |
s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
|
1240 |
(s->out_state & MP_GPIO_LCD_BRIGHTNESS); |
1241 |
musicpal_gpio_brightness_update(s); |
1242 |
qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1); |
1243 |
qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1); |
1244 |
break;
|
1245 |
|
1246 |
case MP_GPIO_IER_LO:
|
1247 |
s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF); |
1248 |
break;
|
1249 |
case MP_GPIO_IER_HI:
|
1250 |
s->ier = (s->ier & 0xFFFF) | (value << 16); |
1251 |
break;
|
1252 |
|
1253 |
case MP_GPIO_IMR_LO:
|
1254 |
s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF); |
1255 |
break;
|
1256 |
case MP_GPIO_IMR_HI:
|
1257 |
s->imr = (s->imr & 0xFFFF) | (value << 16); |
1258 |
break;
|
1259 |
} |
1260 |
} |
1261 |
|
1262 |
static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = { |
1263 |
musicpal_gpio_read, |
1264 |
musicpal_gpio_read, |
1265 |
musicpal_gpio_read, |
1266 |
}; |
1267 |
|
1268 |
static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = { |
1269 |
musicpal_gpio_write, |
1270 |
musicpal_gpio_write, |
1271 |
musicpal_gpio_write, |
1272 |
}; |
1273 |
|
1274 |
static void musicpal_gpio_reset(DeviceState *d) |
1275 |
{ |
1276 |
musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, |
1277 |
sysbus_from_qdev(d)); |
1278 |
|
1279 |
s->lcd_brightness = 0;
|
1280 |
s->out_state = 0;
|
1281 |
s->in_state = 0xffffffff;
|
1282 |
s->ier = 0;
|
1283 |
s->imr = 0;
|
1284 |
s->isr = 0;
|
1285 |
} |
1286 |
|
1287 |
static int musicpal_gpio_init(SysBusDevice *dev) |
1288 |
{ |
1289 |
musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev); |
1290 |
int iomemtype;
|
1291 |
|
1292 |
sysbus_init_irq(dev, &s->irq); |
1293 |
|
1294 |
iomemtype = cpu_register_io_memory(musicpal_gpio_readfn, |
1295 |
musicpal_gpio_writefn, s); |
1296 |
sysbus_init_mmio(dev, MP_GPIO_SIZE, iomemtype); |
1297 |
|
1298 |
qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out)); |
1299 |
|
1300 |
qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
|
1301 |
|
1302 |
return 0; |
1303 |
} |
1304 |
|
1305 |
static const VMStateDescription musicpal_gpio_vmsd = { |
1306 |
.name = "musicpal_gpio",
|
1307 |
.version_id = 1,
|
1308 |
.minimum_version_id = 1,
|
1309 |
.minimum_version_id_old = 1,
|
1310 |
.fields = (VMStateField[]) { |
1311 |
VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state), |
1312 |
VMSTATE_UINT32(out_state, musicpal_gpio_state), |
1313 |
VMSTATE_UINT32(in_state, musicpal_gpio_state), |
1314 |
VMSTATE_UINT32(ier, musicpal_gpio_state), |
1315 |
VMSTATE_UINT32(imr, musicpal_gpio_state), |
1316 |
VMSTATE_UINT32(isr, musicpal_gpio_state), |
1317 |
VMSTATE_END_OF_LIST() |
1318 |
} |
1319 |
}; |
1320 |
|
1321 |
static SysBusDeviceInfo musicpal_gpio_info = {
|
1322 |
.init = musicpal_gpio_init, |
1323 |
.qdev.name = "musicpal_gpio",
|
1324 |
.qdev.size = sizeof(musicpal_gpio_state),
|
1325 |
.qdev.reset = musicpal_gpio_reset, |
1326 |
.qdev.vmsd = &musicpal_gpio_vmsd, |
1327 |
}; |
1328 |
|
1329 |
/* Keyboard codes & masks */
|
1330 |
#define KEY_RELEASED 0x80 |
1331 |
#define KEY_CODE 0x7f |
1332 |
|
1333 |
#define KEYCODE_TAB 0x0f |
1334 |
#define KEYCODE_ENTER 0x1c |
1335 |
#define KEYCODE_F 0x21 |
1336 |
#define KEYCODE_M 0x32 |
1337 |
|
1338 |
#define KEYCODE_EXTENDED 0xe0 |
1339 |
#define KEYCODE_UP 0x48 |
1340 |
#define KEYCODE_DOWN 0x50 |
1341 |
#define KEYCODE_LEFT 0x4b |
1342 |
#define KEYCODE_RIGHT 0x4d |
1343 |
|
1344 |
#define MP_KEY_WHEEL_VOL (1 << 0) |
1345 |
#define MP_KEY_WHEEL_VOL_INV (1 << 1) |
1346 |
#define MP_KEY_WHEEL_NAV (1 << 2) |
1347 |
#define MP_KEY_WHEEL_NAV_INV (1 << 3) |
1348 |
#define MP_KEY_BTN_FAVORITS (1 << 4) |
1349 |
#define MP_KEY_BTN_MENU (1 << 5) |
1350 |
#define MP_KEY_BTN_VOLUME (1 << 6) |
1351 |
#define MP_KEY_BTN_NAVIGATION (1 << 7) |
1352 |
|
1353 |
typedef struct musicpal_key_state { |
1354 |
SysBusDevice busdev; |
1355 |
uint32_t kbd_extended; |
1356 |
uint32_t pressed_keys; |
1357 |
qemu_irq out[8];
|
1358 |
} musicpal_key_state; |
1359 |
|
1360 |
static void musicpal_key_event(void *opaque, int keycode) |
1361 |
{ |
1362 |
musicpal_key_state *s = opaque; |
1363 |
uint32_t event = 0;
|
1364 |
int i;
|
1365 |
|
1366 |
if (keycode == KEYCODE_EXTENDED) {
|
1367 |
s->kbd_extended = 1;
|
1368 |
return;
|
1369 |
} |
1370 |
|
1371 |
if (s->kbd_extended) {
|
1372 |
switch (keycode & KEY_CODE) {
|
1373 |
case KEYCODE_UP:
|
1374 |
event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; |
1375 |
break;
|
1376 |
|
1377 |
case KEYCODE_DOWN:
|
1378 |
event = MP_KEY_WHEEL_NAV; |
1379 |
break;
|
1380 |
|
1381 |
case KEYCODE_LEFT:
|
1382 |
event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; |
1383 |
break;
|
1384 |
|
1385 |
case KEYCODE_RIGHT:
|
1386 |
event = MP_KEY_WHEEL_VOL; |
1387 |
break;
|
1388 |
} |
1389 |
} else {
|
1390 |
switch (keycode & KEY_CODE) {
|
1391 |
case KEYCODE_F:
|
1392 |
event = MP_KEY_BTN_FAVORITS; |
1393 |
break;
|
1394 |
|
1395 |
case KEYCODE_TAB:
|
1396 |
event = MP_KEY_BTN_VOLUME; |
1397 |
break;
|
1398 |
|
1399 |
case KEYCODE_ENTER:
|
1400 |
event = MP_KEY_BTN_NAVIGATION; |
1401 |
break;
|
1402 |
|
1403 |
case KEYCODE_M:
|
1404 |
event = MP_KEY_BTN_MENU; |
1405 |
break;
|
1406 |
} |
1407 |
/* Do not repeat already pressed buttons */
|
1408 |
if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
|
1409 |
event = 0;
|
1410 |
} |
1411 |
} |
1412 |
|
1413 |
if (event) {
|
1414 |
/* Raise GPIO pin first if repeating a key */
|
1415 |
if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
|
1416 |
for (i = 0; i <= 7; i++) { |
1417 |
if (event & (1 << i)) { |
1418 |
qemu_set_irq(s->out[i], 1);
|
1419 |
} |
1420 |
} |
1421 |
} |
1422 |
for (i = 0; i <= 7; i++) { |
1423 |
if (event & (1 << i)) { |
1424 |
qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED)); |
1425 |
} |
1426 |
} |
1427 |
if (keycode & KEY_RELEASED) {
|
1428 |
s->pressed_keys &= ~event; |
1429 |
} else {
|
1430 |
s->pressed_keys |= event; |
1431 |
} |
1432 |
} |
1433 |
|
1434 |
s->kbd_extended = 0;
|
1435 |
} |
1436 |
|
1437 |
static int musicpal_key_init(SysBusDevice *dev) |
1438 |
{ |
1439 |
musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev); |
1440 |
|
1441 |
sysbus_init_mmio(dev, 0x0, 0); |
1442 |
|
1443 |
s->kbd_extended = 0;
|
1444 |
s->pressed_keys = 0;
|
1445 |
|
1446 |
qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out)); |
1447 |
|
1448 |
qemu_add_kbd_event_handler(musicpal_key_event, s); |
1449 |
|
1450 |
return 0; |
1451 |
} |
1452 |
|
1453 |
static const VMStateDescription musicpal_key_vmsd = { |
1454 |
.name = "musicpal_key",
|
1455 |
.version_id = 1,
|
1456 |
.minimum_version_id = 1,
|
1457 |
.minimum_version_id_old = 1,
|
1458 |
.fields = (VMStateField[]) { |
1459 |
VMSTATE_UINT32(kbd_extended, musicpal_key_state), |
1460 |
VMSTATE_UINT32(pressed_keys, musicpal_key_state), |
1461 |
VMSTATE_END_OF_LIST() |
1462 |
} |
1463 |
}; |
1464 |
|
1465 |
static SysBusDeviceInfo musicpal_key_info = {
|
1466 |
.init = musicpal_key_init, |
1467 |
.qdev.name = "musicpal_key",
|
1468 |
.qdev.size = sizeof(musicpal_key_state),
|
1469 |
.qdev.vmsd = &musicpal_key_vmsd, |
1470 |
}; |
1471 |
|
1472 |
static struct arm_boot_info musicpal_binfo = { |
1473 |
.loader_start = 0x0,
|
1474 |
.board_id = 0x20e,
|
1475 |
}; |
1476 |
|
1477 |
static void musicpal_init(ram_addr_t ram_size, |
1478 |
const char *boot_device, |
1479 |
const char *kernel_filename, const char *kernel_cmdline, |
1480 |
const char *initrd_filename, const char *cpu_model) |
1481 |
{ |
1482 |
CPUState *env; |
1483 |
qemu_irq *cpu_pic; |
1484 |
qemu_irq pic[32];
|
1485 |
DeviceState *dev; |
1486 |
DeviceState *i2c_dev; |
1487 |
DeviceState *lcd_dev; |
1488 |
DeviceState *key_dev; |
1489 |
#ifdef HAS_AUDIO
|
1490 |
DeviceState *wm8750_dev; |
1491 |
SysBusDevice *s; |
1492 |
#endif
|
1493 |
i2c_bus *i2c; |
1494 |
int i;
|
1495 |
unsigned long flash_size; |
1496 |
DriveInfo *dinfo; |
1497 |
ram_addr_t sram_off; |
1498 |
|
1499 |
if (!cpu_model) {
|
1500 |
cpu_model = "arm926";
|
1501 |
} |
1502 |
env = cpu_init(cpu_model); |
1503 |
if (!env) {
|
1504 |
fprintf(stderr, "Unable to find CPU definition\n");
|
1505 |
exit(1);
|
1506 |
} |
1507 |
cpu_pic = arm_pic_init_cpu(env); |
1508 |
|
1509 |
/* For now we use a fixed - the original - RAM size */
|
1510 |
cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
|
1511 |
qemu_ram_alloc(MP_RAM_DEFAULT_SIZE)); |
1512 |
|
1513 |
sram_off = qemu_ram_alloc(MP_SRAM_SIZE); |
1514 |
cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off); |
1515 |
|
1516 |
dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
|
1517 |
cpu_pic[ARM_PIC_CPU_IRQ]); |
1518 |
for (i = 0; i < 32; i++) { |
1519 |
pic[i] = qdev_get_gpio_in(dev, i); |
1520 |
} |
1521 |
sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
|
1522 |
pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], |
1523 |
pic[MP_TIMER4_IRQ], NULL);
|
1524 |
|
1525 |
if (serial_hds[0]) { |
1526 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1527 |
serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000, |
1528 |
serial_hds[0], 1, 1); |
1529 |
#else
|
1530 |
serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000, |
1531 |
serial_hds[0], 1, 0); |
1532 |
#endif
|
1533 |
} |
1534 |
if (serial_hds[1]) { |
1535 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1536 |
serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000, |
1537 |
serial_hds[1], 1, 1); |
1538 |
#else
|
1539 |
serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000, |
1540 |
serial_hds[1], 1, 0); |
1541 |
#endif
|
1542 |
} |
1543 |
|
1544 |
/* Register flash */
|
1545 |
dinfo = drive_get(IF_PFLASH, 0, 0); |
1546 |
if (dinfo) {
|
1547 |
flash_size = bdrv_getlength(dinfo->bdrv); |
1548 |
if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 && |
1549 |
flash_size != 32*1024*1024) { |
1550 |
fprintf(stderr, "Invalid flash image size\n");
|
1551 |
exit(1);
|
1552 |
} |
1553 |
|
1554 |
/*
|
1555 |
* The original U-Boot accesses the flash at 0xFE000000 instead of
|
1556 |
* 0xFF800000 (if there is 8 MB flash). So remap flash access if the
|
1557 |
* image is smaller than 32 MB.
|
1558 |
*/
|
1559 |
#ifdef TARGET_WORDS_BIGENDIAN
|
1560 |
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
|
1561 |
dinfo->bdrv, 0x10000,
|
1562 |
(flash_size + 0xffff) >> 16, |
1563 |
MP_FLASH_SIZE_MAX / flash_size, |
1564 |
2, 0x00BF, 0x236D, 0x0000, 0x0000, |
1565 |
0x5555, 0x2AAA, 1); |
1566 |
#else
|
1567 |
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
|
1568 |
dinfo->bdrv, 0x10000,
|
1569 |
(flash_size + 0xffff) >> 16, |
1570 |
MP_FLASH_SIZE_MAX / flash_size, |
1571 |
2, 0x00BF, 0x236D, 0x0000, 0x0000, |
1572 |
0x5555, 0x2AAA, 0); |
1573 |
#endif
|
1574 |
|
1575 |
} |
1576 |
sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL); |
1577 |
|
1578 |
qemu_check_nic_model(&nd_table[0], "mv88w8618"); |
1579 |
dev = qdev_create(NULL, "mv88w8618_eth"); |
1580 |
qdev_set_nic_properties(dev, &nd_table[0]);
|
1581 |
qdev_init_nofail(dev); |
1582 |
sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
|
1583 |
sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
|
1584 |
|
1585 |
sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL); |
1586 |
|
1587 |
musicpal_misc_init(); |
1588 |
|
1589 |
dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
|
1590 |
i2c_dev = sysbus_create_simple("gpio_i2c", 0, NULL); |
1591 |
i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
|
1592 |
|
1593 |
lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL); |
1594 |
key_dev = sysbus_create_simple("musicpal_key", 0, NULL); |
1595 |
|
1596 |
/* I2C read data */
|
1597 |
qdev_connect_gpio_out(i2c_dev, 0,
|
1598 |
qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT)); |
1599 |
/* I2C data */
|
1600 |
qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0)); |
1601 |
/* I2C clock */
|
1602 |
qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1)); |
1603 |
|
1604 |
for (i = 0; i < 3; i++) { |
1605 |
qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i)); |
1606 |
} |
1607 |
for (i = 0; i < 4; i++) { |
1608 |
qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
|
1609 |
} |
1610 |
for (i = 4; i < 8; i++) { |
1611 |
qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
|
1612 |
} |
1613 |
|
1614 |
#ifdef HAS_AUDIO
|
1615 |
wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
|
1616 |
dev = qdev_create(NULL, "mv88w8618_audio"); |
1617 |
s = sysbus_from_qdev(dev); |
1618 |
qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
|
1619 |
qdev_init_nofail(dev); |
1620 |
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
|
1621 |
sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
|
1622 |
#endif
|
1623 |
|
1624 |
musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE; |
1625 |
musicpal_binfo.kernel_filename = kernel_filename; |
1626 |
musicpal_binfo.kernel_cmdline = kernel_cmdline; |
1627 |
musicpal_binfo.initrd_filename = initrd_filename; |
1628 |
arm_load_kernel(env, &musicpal_binfo); |
1629 |
} |
1630 |
|
1631 |
static QEMUMachine musicpal_machine = {
|
1632 |
.name = "musicpal",
|
1633 |
.desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
|
1634 |
.init = musicpal_init, |
1635 |
}; |
1636 |
|
1637 |
static void musicpal_machine_init(void) |
1638 |
{ |
1639 |
qemu_register_machine(&musicpal_machine); |
1640 |
} |
1641 |
|
1642 |
machine_init(musicpal_machine_init); |
1643 |
|
1644 |
static void musicpal_register_devices(void) |
1645 |
{ |
1646 |
sysbus_register_withprop(&mv88w8618_pic_info); |
1647 |
sysbus_register_withprop(&mv88w8618_pit_info); |
1648 |
sysbus_register_withprop(&mv88w8618_flashcfg_info); |
1649 |
sysbus_register_withprop(&mv88w8618_eth_info); |
1650 |
sysbus_register_dev("mv88w8618_wlan", sizeof(SysBusDevice), |
1651 |
mv88w8618_wlan_init); |
1652 |
sysbus_register_withprop(&musicpal_lcd_info); |
1653 |
sysbus_register_withprop(&musicpal_gpio_info); |
1654 |
sysbus_register_withprop(&musicpal_key_info); |
1655 |
} |
1656 |
|
1657 |
device_init(musicpal_register_devices) |