root / hw / mc146818rtc.c @ a03f7874
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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU MC146818 RTC emulation
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3 | 5fafdf24 | ths | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sysemu.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | aa28b9bf | Blue Swirl | #include "apic.h" |
29 | 87ecb68b | pbrook | #include "isa.h" |
30 | 16b29ae1 | aliguori | #include "hpet_emul.h" |
31 | 80cabfad | bellard | |
32 | 80cabfad | bellard | //#define DEBUG_CMOS
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33 | 80cabfad | bellard | |
34 | dd17765b | Gleb Natapov | #define RTC_REINJECT_ON_ACK_COUNT 20 |
35 | ba32edab | Gleb Natapov | |
36 | 80cabfad | bellard | #define RTC_SECONDS 0 |
37 | 80cabfad | bellard | #define RTC_SECONDS_ALARM 1 |
38 | 80cabfad | bellard | #define RTC_MINUTES 2 |
39 | 80cabfad | bellard | #define RTC_MINUTES_ALARM 3 |
40 | 80cabfad | bellard | #define RTC_HOURS 4 |
41 | 80cabfad | bellard | #define RTC_HOURS_ALARM 5 |
42 | 80cabfad | bellard | #define RTC_ALARM_DONT_CARE 0xC0 |
43 | 80cabfad | bellard | |
44 | 80cabfad | bellard | #define RTC_DAY_OF_WEEK 6 |
45 | 80cabfad | bellard | #define RTC_DAY_OF_MONTH 7 |
46 | 80cabfad | bellard | #define RTC_MONTH 8 |
47 | 80cabfad | bellard | #define RTC_YEAR 9 |
48 | 80cabfad | bellard | |
49 | 80cabfad | bellard | #define RTC_REG_A 10 |
50 | 80cabfad | bellard | #define RTC_REG_B 11 |
51 | 80cabfad | bellard | #define RTC_REG_C 12 |
52 | 80cabfad | bellard | #define RTC_REG_D 13 |
53 | 80cabfad | bellard | |
54 | dff38e7b | bellard | #define REG_A_UIP 0x80 |
55 | 80cabfad | bellard | |
56 | 100d9891 | aurel32 | #define REG_B_SET 0x80 |
57 | 100d9891 | aurel32 | #define REG_B_PIE 0x40 |
58 | 100d9891 | aurel32 | #define REG_B_AIE 0x20 |
59 | 100d9891 | aurel32 | #define REG_B_UIE 0x10 |
60 | 100d9891 | aurel32 | #define REG_B_SQWE 0x08 |
61 | 100d9891 | aurel32 | #define REG_B_DM 0x04 |
62 | dff38e7b | bellard | |
63 | 72716184 | Anthony Liguori | #define REG_C_UF 0x10 |
64 | 72716184 | Anthony Liguori | #define REG_C_IRQF 0x80 |
65 | 72716184 | Anthony Liguori | #define REG_C_PF 0x40 |
66 | 72716184 | Anthony Liguori | #define REG_C_AF 0x20 |
67 | 72716184 | Anthony Liguori | |
68 | dff38e7b | bellard | struct RTCState {
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69 | 32e0c826 | Gerd Hoffmann | ISADevice dev; |
70 | dff38e7b | bellard | uint8_t cmos_data[128];
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71 | dff38e7b | bellard | uint8_t cmos_index; |
72 | 43f493af | bellard | struct tm current_tm;
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73 | 32e0c826 | Gerd Hoffmann | int32_t base_year; |
74 | d537cf6c | pbrook | qemu_irq irq; |
75 | 100d9891 | aurel32 | qemu_irq sqw_irq; |
76 | 18c6e2ff | ths | int it_shift;
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77 | dff38e7b | bellard | /* periodic timer */
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78 | dff38e7b | bellard | QEMUTimer *periodic_timer; |
79 | dff38e7b | bellard | int64_t next_periodic_time; |
80 | dff38e7b | bellard | /* second update */
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81 | dff38e7b | bellard | int64_t next_second_time; |
82 | ba32edab | Gleb Natapov | uint16_t irq_reinject_on_ack_count; |
83 | 73822ec8 | aliguori | uint32_t irq_coalesced; |
84 | 73822ec8 | aliguori | uint32_t period; |
85 | 93b66569 | aliguori | QEMUTimer *coalesced_timer; |
86 | dff38e7b | bellard | QEMUTimer *second_timer; |
87 | dff38e7b | bellard | QEMUTimer *second_timer2; |
88 | dff38e7b | bellard | }; |
89 | dff38e7b | bellard | |
90 | e0ca7b94 | Juan Quintela | static void rtc_irq_raise(qemu_irq irq) |
91 | e0ca7b94 | Juan Quintela | { |
92 | c50c2d68 | aurel32 | /* When HPET is operating in legacy mode, RTC interrupts are disabled
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93 | 16b29ae1 | aliguori | * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
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94 | c50c2d68 | aurel32 | * mode is established while interrupt is raised. We want it to
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95 | 16b29ae1 | aliguori | * be lowered in any case
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96 | c50c2d68 | aurel32 | */
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97 | ce88f890 | Juan Quintela | #if defined TARGET_I386
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98 | c50c2d68 | aurel32 | if (!hpet_in_legacy_mode())
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99 | 16b29ae1 | aliguori | #endif
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100 | 16b29ae1 | aliguori | qemu_irq_raise(irq); |
101 | 16b29ae1 | aliguori | } |
102 | 16b29ae1 | aliguori | |
103 | dff38e7b | bellard | static void rtc_set_time(RTCState *s); |
104 | dff38e7b | bellard | static void rtc_copy_date(RTCState *s); |
105 | dff38e7b | bellard | |
106 | 93b66569 | aliguori | #ifdef TARGET_I386
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107 | 93b66569 | aliguori | static void rtc_coalesced_timer_update(RTCState *s) |
108 | 93b66569 | aliguori | { |
109 | 93b66569 | aliguori | if (s->irq_coalesced == 0) { |
110 | 93b66569 | aliguori | qemu_del_timer(s->coalesced_timer); |
111 | 93b66569 | aliguori | } else {
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112 | 93b66569 | aliguori | /* divide each RTC interval to 2 - 8 smaller intervals */
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113 | 93b66569 | aliguori | int c = MIN(s->irq_coalesced, 7) + 1; |
114 | 6875204c | Jan Kiszka | int64_t next_clock = qemu_get_clock(rtc_clock) + |
115 | 6875204c | Jan Kiszka | muldiv64(s->period / c, get_ticks_per_sec(), 32768);
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116 | 93b66569 | aliguori | qemu_mod_timer(s->coalesced_timer, next_clock); |
117 | 93b66569 | aliguori | } |
118 | 93b66569 | aliguori | } |
119 | 93b66569 | aliguori | |
120 | 93b66569 | aliguori | static void rtc_coalesced_timer(void *opaque) |
121 | 93b66569 | aliguori | { |
122 | 93b66569 | aliguori | RTCState *s = opaque; |
123 | 93b66569 | aliguori | |
124 | 93b66569 | aliguori | if (s->irq_coalesced != 0) { |
125 | 93b66569 | aliguori | apic_reset_irq_delivered(); |
126 | 93b66569 | aliguori | s->cmos_data[RTC_REG_C] |= 0xc0;
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127 | 93b66569 | aliguori | rtc_irq_raise(s->irq); |
128 | 93b66569 | aliguori | if (apic_get_irq_delivered()) {
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129 | 93b66569 | aliguori | s->irq_coalesced--; |
130 | 93b66569 | aliguori | } |
131 | 93b66569 | aliguori | } |
132 | 93b66569 | aliguori | |
133 | 93b66569 | aliguori | rtc_coalesced_timer_update(s); |
134 | 93b66569 | aliguori | } |
135 | 93b66569 | aliguori | #endif
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136 | 93b66569 | aliguori | |
137 | dff38e7b | bellard | static void rtc_timer_update(RTCState *s, int64_t current_time) |
138 | dff38e7b | bellard | { |
139 | dff38e7b | bellard | int period_code, period;
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140 | dff38e7b | bellard | int64_t cur_clock, next_irq_clock; |
141 | 100d9891 | aurel32 | int enable_pie;
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142 | dff38e7b | bellard | |
143 | dff38e7b | bellard | period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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144 | ce88f890 | Juan Quintela | #if defined TARGET_I386
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145 | c50c2d68 | aurel32 | /* disable periodic timer if hpet is in legacy mode, since interrupts are
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146 | 16b29ae1 | aliguori | * disabled anyway.
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147 | 16b29ae1 | aliguori | */
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148 | a8b01dd8 | pbrook | enable_pie = !hpet_in_legacy_mode(); |
149 | 16b29ae1 | aliguori | #else
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150 | 100d9891 | aurel32 | enable_pie = 1;
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151 | 16b29ae1 | aliguori | #endif
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152 | 100d9891 | aurel32 | if (period_code != 0 |
153 | 100d9891 | aurel32 | && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie) |
154 | 100d9891 | aurel32 | || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { |
155 | dff38e7b | bellard | if (period_code <= 2) |
156 | dff38e7b | bellard | period_code += 7;
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157 | dff38e7b | bellard | /* period in 32 Khz cycles */
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158 | dff38e7b | bellard | period = 1 << (period_code - 1); |
159 | 73822ec8 | aliguori | #ifdef TARGET_I386
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160 | 73822ec8 | aliguori | if(period != s->period)
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161 | 73822ec8 | aliguori | s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
162 | 73822ec8 | aliguori | s->period = period; |
163 | 73822ec8 | aliguori | #endif
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164 | dff38e7b | bellard | /* compute 32 khz clock */
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165 | 6ee093c9 | Juan Quintela | cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
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166 | dff38e7b | bellard | next_irq_clock = (cur_clock & ~(period - 1)) + period;
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167 | 6875204c | Jan Kiszka | s->next_periodic_time = |
168 | 6875204c | Jan Kiszka | muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1; |
169 | dff38e7b | bellard | qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
170 | dff38e7b | bellard | } else {
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171 | 73822ec8 | aliguori | #ifdef TARGET_I386
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172 | 73822ec8 | aliguori | s->irq_coalesced = 0;
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173 | 73822ec8 | aliguori | #endif
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174 | dff38e7b | bellard | qemu_del_timer(s->periodic_timer); |
175 | dff38e7b | bellard | } |
176 | dff38e7b | bellard | } |
177 | dff38e7b | bellard | |
178 | dff38e7b | bellard | static void rtc_periodic_timer(void *opaque) |
179 | dff38e7b | bellard | { |
180 | dff38e7b | bellard | RTCState *s = opaque; |
181 | dff38e7b | bellard | |
182 | dff38e7b | bellard | rtc_timer_update(s, s->next_periodic_time); |
183 | 100d9891 | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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184 | 100d9891 | aurel32 | s->cmos_data[RTC_REG_C] |= 0xc0;
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185 | 93b66569 | aliguori | #ifdef TARGET_I386
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186 | 93b66569 | aliguori | if(rtc_td_hack) {
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187 | ba32edab | Gleb Natapov | if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
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188 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count = 0;
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189 | 93b66569 | aliguori | apic_reset_irq_delivered(); |
190 | 93b66569 | aliguori | rtc_irq_raise(s->irq); |
191 | 93b66569 | aliguori | if (!apic_get_irq_delivered()) {
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192 | 93b66569 | aliguori | s->irq_coalesced++; |
193 | 93b66569 | aliguori | rtc_coalesced_timer_update(s); |
194 | 93b66569 | aliguori | } |
195 | 93b66569 | aliguori | } else
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196 | 93b66569 | aliguori | #endif
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197 | 100d9891 | aurel32 | rtc_irq_raise(s->irq); |
198 | 100d9891 | aurel32 | } |
199 | 100d9891 | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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200 | 100d9891 | aurel32 | /* Not square wave at all but we don't want 2048Hz interrupts!
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201 | 100d9891 | aurel32 | Must be seen as a pulse. */
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202 | 100d9891 | aurel32 | qemu_irq_raise(s->sqw_irq); |
203 | 100d9891 | aurel32 | } |
204 | dff38e7b | bellard | } |
205 | 80cabfad | bellard | |
206 | b41a2cd1 | bellard | static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
207 | 80cabfad | bellard | { |
208 | b41a2cd1 | bellard | RTCState *s = opaque; |
209 | 80cabfad | bellard | |
210 | 80cabfad | bellard | if ((addr & 1) == 0) { |
211 | 80cabfad | bellard | s->cmos_index = data & 0x7f;
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212 | 80cabfad | bellard | } else {
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213 | 80cabfad | bellard | #ifdef DEBUG_CMOS
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214 | 80cabfad | bellard | printf("cmos: write index=0x%02x val=0x%02x\n",
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215 | 80cabfad | bellard | s->cmos_index, data); |
216 | 3b46e624 | ths | #endif
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217 | dff38e7b | bellard | switch(s->cmos_index) {
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218 | 80cabfad | bellard | case RTC_SECONDS_ALARM:
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219 | 80cabfad | bellard | case RTC_MINUTES_ALARM:
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220 | 80cabfad | bellard | case RTC_HOURS_ALARM:
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221 | 80cabfad | bellard | /* XXX: not supported */
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222 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
223 | 80cabfad | bellard | break;
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224 | 80cabfad | bellard | case RTC_SECONDS:
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225 | 80cabfad | bellard | case RTC_MINUTES:
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226 | 80cabfad | bellard | case RTC_HOURS:
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227 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
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228 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
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229 | 80cabfad | bellard | case RTC_MONTH:
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230 | 80cabfad | bellard | case RTC_YEAR:
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231 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
232 | dff38e7b | bellard | /* if in set mode, do not update the time */
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233 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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234 | dff38e7b | bellard | rtc_set_time(s); |
235 | dff38e7b | bellard | } |
236 | 80cabfad | bellard | break;
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237 | 80cabfad | bellard | case RTC_REG_A:
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238 | dff38e7b | bellard | /* UIP bit is read only */
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239 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
240 | dff38e7b | bellard | (s->cmos_data[RTC_REG_A] & REG_A_UIP); |
241 | 6875204c | Jan Kiszka | rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
242 | dff38e7b | bellard | break;
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243 | 80cabfad | bellard | case RTC_REG_B:
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244 | dff38e7b | bellard | if (data & REG_B_SET) {
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245 | dff38e7b | bellard | /* set mode: reset UIP mode */
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246 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
247 | dff38e7b | bellard | data &= ~REG_B_UIE; |
248 | dff38e7b | bellard | } else {
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249 | dff38e7b | bellard | /* if disabling set mode, update the time */
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250 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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251 | dff38e7b | bellard | rtc_set_time(s); |
252 | dff38e7b | bellard | } |
253 | dff38e7b | bellard | } |
254 | dff38e7b | bellard | s->cmos_data[RTC_REG_B] = data; |
255 | 6875204c | Jan Kiszka | rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
256 | 80cabfad | bellard | break;
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257 | 80cabfad | bellard | case RTC_REG_C:
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258 | 80cabfad | bellard | case RTC_REG_D:
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259 | 80cabfad | bellard | /* cannot write to them */
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260 | 80cabfad | bellard | break;
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261 | 80cabfad | bellard | default:
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262 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
263 | 80cabfad | bellard | break;
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264 | 80cabfad | bellard | } |
265 | 80cabfad | bellard | } |
266 | 80cabfad | bellard | } |
267 | 80cabfad | bellard | |
268 | abd0c6bd | Paul Brook | static inline int rtc_to_bcd(RTCState *s, int a) |
269 | 80cabfad | bellard | { |
270 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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271 | dff38e7b | bellard | return a;
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272 | dff38e7b | bellard | } else {
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273 | dff38e7b | bellard | return ((a / 10) << 4) | (a % 10); |
274 | dff38e7b | bellard | } |
275 | 80cabfad | bellard | } |
276 | 80cabfad | bellard | |
277 | abd0c6bd | Paul Brook | static inline int rtc_from_bcd(RTCState *s, int a) |
278 | 80cabfad | bellard | { |
279 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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280 | dff38e7b | bellard | return a;
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281 | dff38e7b | bellard | } else {
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282 | dff38e7b | bellard | return ((a >> 4) * 10) + (a & 0x0f); |
283 | dff38e7b | bellard | } |
284 | dff38e7b | bellard | } |
285 | dff38e7b | bellard | |
286 | dff38e7b | bellard | static void rtc_set_time(RTCState *s) |
287 | dff38e7b | bellard | { |
288 | 43f493af | bellard | struct tm *tm = &s->current_tm;
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289 | dff38e7b | bellard | |
290 | abd0c6bd | Paul Brook | tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
291 | abd0c6bd | Paul Brook | tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); |
292 | abd0c6bd | Paul Brook | tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
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293 | 43f493af | bellard | if (!(s->cmos_data[RTC_REG_B] & 0x02) && |
294 | 43f493af | bellard | (s->cmos_data[RTC_HOURS] & 0x80)) {
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295 | 43f493af | bellard | tm->tm_hour += 12;
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296 | 43f493af | bellard | } |
297 | abd0c6bd | Paul Brook | tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
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298 | abd0c6bd | Paul Brook | tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
299 | abd0c6bd | Paul Brook | tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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300 | abd0c6bd | Paul Brook | tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
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301 | 80cd3478 | Luiz Capitulino | |
302 | 80cd3478 | Luiz Capitulino | rtc_change_mon_event(tm); |
303 | 43f493af | bellard | } |
304 | 43f493af | bellard | |
305 | 43f493af | bellard | static void rtc_copy_date(RTCState *s) |
306 | 43f493af | bellard | { |
307 | 43f493af | bellard | const struct tm *tm = &s->current_tm; |
308 | 42fc73a1 | aurel32 | int year;
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309 | dff38e7b | bellard | |
310 | abd0c6bd | Paul Brook | s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
311 | abd0c6bd | Paul Brook | s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); |
312 | 43f493af | bellard | if (s->cmos_data[RTC_REG_B] & 0x02) { |
313 | 43f493af | bellard | /* 24 hour format */
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314 | abd0c6bd | Paul Brook | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
315 | 43f493af | bellard | } else {
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316 | 43f493af | bellard | /* 12 hour format */
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317 | abd0c6bd | Paul Brook | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour % 12);
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318 | 43f493af | bellard | if (tm->tm_hour >= 12) |
319 | 43f493af | bellard | s->cmos_data[RTC_HOURS] |= 0x80;
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320 | 43f493af | bellard | } |
321 | abd0c6bd | Paul Brook | s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
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322 | abd0c6bd | Paul Brook | s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); |
323 | abd0c6bd | Paul Brook | s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
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324 | 42fc73a1 | aurel32 | year = (tm->tm_year - s->base_year) % 100;
|
325 | 42fc73a1 | aurel32 | if (year < 0) |
326 | 42fc73a1 | aurel32 | year += 100;
|
327 | abd0c6bd | Paul Brook | s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year); |
328 | 43f493af | bellard | } |
329 | 43f493af | bellard | |
330 | 43f493af | bellard | /* month is between 0 and 11. */
|
331 | 43f493af | bellard | static int get_days_in_month(int month, int year) |
332 | 43f493af | bellard | { |
333 | 5fafdf24 | ths | static const int days_tab[12] = { |
334 | 5fafdf24 | ths | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
335 | 43f493af | bellard | }; |
336 | 43f493af | bellard | int d;
|
337 | 43f493af | bellard | if ((unsigned )month >= 12) |
338 | 43f493af | bellard | return 31; |
339 | 43f493af | bellard | d = days_tab[month]; |
340 | 43f493af | bellard | if (month == 1) { |
341 | 43f493af | bellard | if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) |
342 | 43f493af | bellard | d++; |
343 | 43f493af | bellard | } |
344 | 43f493af | bellard | return d;
|
345 | 43f493af | bellard | } |
346 | 43f493af | bellard | |
347 | 43f493af | bellard | /* update 'tm' to the next second */
|
348 | 43f493af | bellard | static void rtc_next_second(struct tm *tm) |
349 | 43f493af | bellard | { |
350 | 43f493af | bellard | int days_in_month;
|
351 | 43f493af | bellard | |
352 | 43f493af | bellard | tm->tm_sec++; |
353 | 43f493af | bellard | if ((unsigned)tm->tm_sec >= 60) { |
354 | 43f493af | bellard | tm->tm_sec = 0;
|
355 | 43f493af | bellard | tm->tm_min++; |
356 | 43f493af | bellard | if ((unsigned)tm->tm_min >= 60) { |
357 | 43f493af | bellard | tm->tm_min = 0;
|
358 | 43f493af | bellard | tm->tm_hour++; |
359 | 43f493af | bellard | if ((unsigned)tm->tm_hour >= 24) { |
360 | 43f493af | bellard | tm->tm_hour = 0;
|
361 | 43f493af | bellard | /* next day */
|
362 | 43f493af | bellard | tm->tm_wday++; |
363 | 43f493af | bellard | if ((unsigned)tm->tm_wday >= 7) |
364 | 43f493af | bellard | tm->tm_wday = 0;
|
365 | 5fafdf24 | ths | days_in_month = get_days_in_month(tm->tm_mon, |
366 | 43f493af | bellard | tm->tm_year + 1900);
|
367 | 43f493af | bellard | tm->tm_mday++; |
368 | 43f493af | bellard | if (tm->tm_mday < 1) { |
369 | 43f493af | bellard | tm->tm_mday = 1;
|
370 | 43f493af | bellard | } else if (tm->tm_mday > days_in_month) { |
371 | 43f493af | bellard | tm->tm_mday = 1;
|
372 | 43f493af | bellard | tm->tm_mon++; |
373 | 43f493af | bellard | if (tm->tm_mon >= 12) { |
374 | 43f493af | bellard | tm->tm_mon = 0;
|
375 | 43f493af | bellard | tm->tm_year++; |
376 | 43f493af | bellard | } |
377 | 43f493af | bellard | } |
378 | 43f493af | bellard | } |
379 | 43f493af | bellard | } |
380 | 43f493af | bellard | } |
381 | dff38e7b | bellard | } |
382 | dff38e7b | bellard | |
383 | 43f493af | bellard | |
384 | dff38e7b | bellard | static void rtc_update_second(void *opaque) |
385 | dff38e7b | bellard | { |
386 | dff38e7b | bellard | RTCState *s = opaque; |
387 | 4721c457 | bellard | int64_t delay; |
388 | dff38e7b | bellard | |
389 | dff38e7b | bellard | /* if the oscillator is not in normal operation, we do not update */
|
390 | dff38e7b | bellard | if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { |
391 | 6ee093c9 | Juan Quintela | s->next_second_time += get_ticks_per_sec(); |
392 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
393 | dff38e7b | bellard | } else {
|
394 | 43f493af | bellard | rtc_next_second(&s->current_tm); |
395 | 3b46e624 | ths | |
396 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
397 | dff38e7b | bellard | /* update in progress bit */
|
398 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
399 | dff38e7b | bellard | } |
400 | 4721c457 | bellard | /* should be 244 us = 8 / 32768 seconds, but currently the
|
401 | 4721c457 | bellard | timers do not have the necessary resolution. */
|
402 | 6ee093c9 | Juan Quintela | delay = (get_ticks_per_sec() * 1) / 100; |
403 | 4721c457 | bellard | if (delay < 1) |
404 | 4721c457 | bellard | delay = 1;
|
405 | 5fafdf24 | ths | qemu_mod_timer(s->second_timer2, |
406 | 4721c457 | bellard | s->next_second_time + delay); |
407 | dff38e7b | bellard | } |
408 | dff38e7b | bellard | } |
409 | dff38e7b | bellard | |
410 | dff38e7b | bellard | static void rtc_update_second2(void *opaque) |
411 | dff38e7b | bellard | { |
412 | dff38e7b | bellard | RTCState *s = opaque; |
413 | dff38e7b | bellard | |
414 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
415 | dff38e7b | bellard | rtc_copy_date(s); |
416 | dff38e7b | bellard | } |
417 | dff38e7b | bellard | |
418 | dff38e7b | bellard | /* check alarm */
|
419 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
|
420 | dff38e7b | bellard | if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
421 | 43f493af | bellard | s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) && |
422 | dff38e7b | bellard | ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
423 | 43f493af | bellard | s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) && |
424 | dff38e7b | bellard | ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
425 | 43f493af | bellard | s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) { |
426 | dff38e7b | bellard | |
427 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] |= 0xa0;
|
428 | 16b29ae1 | aliguori | rtc_irq_raise(s->irq); |
429 | dff38e7b | bellard | } |
430 | dff38e7b | bellard | } |
431 | dff38e7b | bellard | |
432 | dff38e7b | bellard | /* update ended interrupt */
|
433 | 98815437 | Bernhard Kauer | s->cmos_data[RTC_REG_C] |= REG_C_UF; |
434 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
|
435 | 98815437 | Bernhard Kauer | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
436 | 98815437 | Bernhard Kauer | rtc_irq_raise(s->irq); |
437 | dff38e7b | bellard | } |
438 | dff38e7b | bellard | |
439 | dff38e7b | bellard | /* clear update in progress bit */
|
440 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
441 | dff38e7b | bellard | |
442 | 6ee093c9 | Juan Quintela | s->next_second_time += get_ticks_per_sec(); |
443 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
444 | 80cabfad | bellard | } |
445 | 80cabfad | bellard | |
446 | b41a2cd1 | bellard | static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
447 | 80cabfad | bellard | { |
448 | b41a2cd1 | bellard | RTCState *s = opaque; |
449 | 80cabfad | bellard | int ret;
|
450 | 80cabfad | bellard | if ((addr & 1) == 0) { |
451 | 80cabfad | bellard | return 0xff; |
452 | 80cabfad | bellard | } else {
|
453 | 80cabfad | bellard | switch(s->cmos_index) {
|
454 | 80cabfad | bellard | case RTC_SECONDS:
|
455 | 80cabfad | bellard | case RTC_MINUTES:
|
456 | 80cabfad | bellard | case RTC_HOURS:
|
457 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
|
458 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
|
459 | 80cabfad | bellard | case RTC_MONTH:
|
460 | 80cabfad | bellard | case RTC_YEAR:
|
461 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
462 | 80cabfad | bellard | break;
|
463 | 80cabfad | bellard | case RTC_REG_A:
|
464 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
465 | 80cabfad | bellard | break;
|
466 | 80cabfad | bellard | case RTC_REG_C:
|
467 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
468 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
469 | ba32edab | Gleb Natapov | #ifdef TARGET_I386
|
470 | ba32edab | Gleb Natapov | if(s->irq_coalesced &&
|
471 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) { |
472 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count++; |
473 | ba32edab | Gleb Natapov | apic_reset_irq_delivered(); |
474 | ba32edab | Gleb Natapov | qemu_irq_raise(s->irq); |
475 | ba32edab | Gleb Natapov | if (apic_get_irq_delivered())
|
476 | ba32edab | Gleb Natapov | s->irq_coalesced--; |
477 | ba32edab | Gleb Natapov | break;
|
478 | ba32edab | Gleb Natapov | } |
479 | ba32edab | Gleb Natapov | #endif
|
480 | ba32edab | Gleb Natapov | |
481 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] = 0x00;
|
482 | 80cabfad | bellard | break;
|
483 | 80cabfad | bellard | default:
|
484 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
485 | 80cabfad | bellard | break;
|
486 | 80cabfad | bellard | } |
487 | 80cabfad | bellard | #ifdef DEBUG_CMOS
|
488 | 80cabfad | bellard | printf("cmos: read index=0x%02x val=0x%02x\n",
|
489 | 80cabfad | bellard | s->cmos_index, ret); |
490 | 80cabfad | bellard | #endif
|
491 | 80cabfad | bellard | return ret;
|
492 | 80cabfad | bellard | } |
493 | 80cabfad | bellard | } |
494 | 80cabfad | bellard | |
495 | dff38e7b | bellard | void rtc_set_memory(RTCState *s, int addr, int val) |
496 | dff38e7b | bellard | { |
497 | dff38e7b | bellard | if (addr >= 0 && addr <= 127) |
498 | dff38e7b | bellard | s->cmos_data[addr] = val; |
499 | dff38e7b | bellard | } |
500 | dff38e7b | bellard | |
501 | dff38e7b | bellard | void rtc_set_date(RTCState *s, const struct tm *tm) |
502 | dff38e7b | bellard | { |
503 | 43f493af | bellard | s->current_tm = *tm; |
504 | dff38e7b | bellard | rtc_copy_date(s); |
505 | dff38e7b | bellard | } |
506 | dff38e7b | bellard | |
507 | ea55ffb3 | ths | /* PC cmos mappings */
|
508 | ea55ffb3 | ths | #define REG_IBM_CENTURY_BYTE 0x32 |
509 | ea55ffb3 | ths | #define REG_IBM_PS2_CENTURY_BYTE 0x37 |
510 | ea55ffb3 | ths | |
511 | 9596ebb7 | pbrook | static void rtc_set_date_from_host(RTCState *s) |
512 | ea55ffb3 | ths | { |
513 | f6503059 | balrog | struct tm tm;
|
514 | ea55ffb3 | ths | int val;
|
515 | ea55ffb3 | ths | |
516 | ea55ffb3 | ths | /* set the CMOS date */
|
517 | f6503059 | balrog | qemu_get_timedate(&tm, 0);
|
518 | f6503059 | balrog | rtc_set_date(s, &tm); |
519 | ea55ffb3 | ths | |
520 | abd0c6bd | Paul Brook | val = rtc_to_bcd(s, (tm.tm_year / 100) + 19); |
521 | ea55ffb3 | ths | rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val); |
522 | ea55ffb3 | ths | rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val); |
523 | ea55ffb3 | ths | } |
524 | ea55ffb3 | ths | |
525 | 6b075b8a | Juan Quintela | static int rtc_post_load(void *opaque, int version_id) |
526 | 80cabfad | bellard | { |
527 | 6b075b8a | Juan Quintela | #ifdef TARGET_I386
|
528 | dff38e7b | bellard | RTCState *s = opaque; |
529 | dff38e7b | bellard | |
530 | 048c74c4 | Juan Quintela | if (version_id >= 2) { |
531 | 048c74c4 | Juan Quintela | if (rtc_td_hack) {
|
532 | 048c74c4 | Juan Quintela | rtc_coalesced_timer_update(s); |
533 | 048c74c4 | Juan Quintela | } |
534 | 048c74c4 | Juan Quintela | } |
535 | 6b075b8a | Juan Quintela | #endif
|
536 | 73822ec8 | aliguori | return 0; |
537 | 73822ec8 | aliguori | } |
538 | 73822ec8 | aliguori | |
539 | 6b075b8a | Juan Quintela | static const VMStateDescription vmstate_rtc = { |
540 | 6b075b8a | Juan Quintela | .name = "mc146818rtc",
|
541 | 6b075b8a | Juan Quintela | .version_id = 2,
|
542 | 6b075b8a | Juan Quintela | .minimum_version_id = 1,
|
543 | 6b075b8a | Juan Quintela | .minimum_version_id_old = 1,
|
544 | 6b075b8a | Juan Quintela | .post_load = rtc_post_load, |
545 | 6b075b8a | Juan Quintela | .fields = (VMStateField []) { |
546 | 6b075b8a | Juan Quintela | VMSTATE_BUFFER(cmos_data, RTCState), |
547 | 6b075b8a | Juan Quintela | VMSTATE_UINT8(cmos_index, RTCState), |
548 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_sec, RTCState), |
549 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_min, RTCState), |
550 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_hour, RTCState), |
551 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_wday, RTCState), |
552 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_mday, RTCState), |
553 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_mon, RTCState), |
554 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_year, RTCState), |
555 | 6b075b8a | Juan Quintela | VMSTATE_TIMER(periodic_timer, RTCState), |
556 | 6b075b8a | Juan Quintela | VMSTATE_INT64(next_periodic_time, RTCState), |
557 | 6b075b8a | Juan Quintela | VMSTATE_INT64(next_second_time, RTCState), |
558 | 6b075b8a | Juan Quintela | VMSTATE_TIMER(second_timer, RTCState), |
559 | 6b075b8a | Juan Quintela | VMSTATE_TIMER(second_timer2, RTCState), |
560 | 6b075b8a | Juan Quintela | VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
|
561 | 6b075b8a | Juan Quintela | VMSTATE_UINT32_V(period, RTCState, 2),
|
562 | 6b075b8a | Juan Quintela | VMSTATE_END_OF_LIST() |
563 | 6b075b8a | Juan Quintela | } |
564 | 6b075b8a | Juan Quintela | }; |
565 | 6b075b8a | Juan Quintela | |
566 | eeb7c03c | Gleb Natapov | static void rtc_reset(void *opaque) |
567 | eeb7c03c | Gleb Natapov | { |
568 | eeb7c03c | Gleb Natapov | RTCState *s = opaque; |
569 | eeb7c03c | Gleb Natapov | |
570 | 72716184 | Anthony Liguori | s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
571 | 72716184 | Anthony Liguori | s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); |
572 | eeb7c03c | Gleb Natapov | |
573 | 72716184 | Anthony Liguori | qemu_irq_lower(s->irq); |
574 | eeb7c03c | Gleb Natapov | |
575 | eeb7c03c | Gleb Natapov | #ifdef TARGET_I386
|
576 | eeb7c03c | Gleb Natapov | if (rtc_td_hack)
|
577 | eeb7c03c | Gleb Natapov | s->irq_coalesced = 0;
|
578 | eeb7c03c | Gleb Natapov | #endif
|
579 | eeb7c03c | Gleb Natapov | } |
580 | eeb7c03c | Gleb Natapov | |
581 | 32e0c826 | Gerd Hoffmann | static int rtc_initfn(ISADevice *dev) |
582 | dff38e7b | bellard | { |
583 | 32e0c826 | Gerd Hoffmann | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
584 | 32e0c826 | Gerd Hoffmann | int base = 0x70; |
585 | 32e0c826 | Gerd Hoffmann | int isairq = 8; |
586 | dff38e7b | bellard | |
587 | 32e0c826 | Gerd Hoffmann | isa_init_irq(dev, &s->irq, isairq); |
588 | 80cabfad | bellard | |
589 | 80cabfad | bellard | s->cmos_data[RTC_REG_A] = 0x26;
|
590 | 80cabfad | bellard | s->cmos_data[RTC_REG_B] = 0x02;
|
591 | 80cabfad | bellard | s->cmos_data[RTC_REG_C] = 0x00;
|
592 | 80cabfad | bellard | s->cmos_data[RTC_REG_D] = 0x80;
|
593 | 80cabfad | bellard | |
594 | ea55ffb3 | ths | rtc_set_date_from_host(s); |
595 | ea55ffb3 | ths | |
596 | 6875204c | Jan Kiszka | s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s); |
597 | 93b66569 | aliguori | #ifdef TARGET_I386
|
598 | 93b66569 | aliguori | if (rtc_td_hack)
|
599 | 6875204c | Jan Kiszka | s->coalesced_timer = |
600 | 6875204c | Jan Kiszka | qemu_new_timer(rtc_clock, rtc_coalesced_timer, s); |
601 | 93b66569 | aliguori | #endif
|
602 | 6875204c | Jan Kiszka | s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s); |
603 | 6875204c | Jan Kiszka | s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s); |
604 | dff38e7b | bellard | |
605 | 6875204c | Jan Kiszka | s->next_second_time = |
606 | 6875204c | Jan Kiszka | qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100; |
607 | dff38e7b | bellard | qemu_mod_timer(s->second_timer2, s->next_second_time); |
608 | dff38e7b | bellard | |
609 | b41a2cd1 | bellard | register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
610 | b41a2cd1 | bellard | register_ioport_read(base, 2, 1, cmos_ioport_read, s); |
611 | dff38e7b | bellard | |
612 | 6b075b8a | Juan Quintela | vmstate_register(base, &vmstate_rtc, s); |
613 | a08d4367 | Jan Kiszka | qemu_register_reset(rtc_reset, s); |
614 | 32e0c826 | Gerd Hoffmann | return 0; |
615 | 32e0c826 | Gerd Hoffmann | } |
616 | 32e0c826 | Gerd Hoffmann | |
617 | 32e0c826 | Gerd Hoffmann | RTCState *rtc_init(int base_year)
|
618 | 32e0c826 | Gerd Hoffmann | { |
619 | 32e0c826 | Gerd Hoffmann | ISADevice *dev; |
620 | eeb7c03c | Gleb Natapov | |
621 | 32e0c826 | Gerd Hoffmann | dev = isa_create("mc146818rtc");
|
622 | 32e0c826 | Gerd Hoffmann | qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
|
623 | e23a1b33 | Markus Armbruster | qdev_init_nofail(&dev->qdev); |
624 | 32e0c826 | Gerd Hoffmann | return DO_UPCAST(RTCState, dev, dev);
|
625 | 80cabfad | bellard | } |
626 | 80cabfad | bellard | |
627 | 32e0c826 | Gerd Hoffmann | static ISADeviceInfo mc146818rtc_info = {
|
628 | 32e0c826 | Gerd Hoffmann | .qdev.name = "mc146818rtc",
|
629 | 32e0c826 | Gerd Hoffmann | .qdev.size = sizeof(RTCState),
|
630 | 32e0c826 | Gerd Hoffmann | .qdev.no_user = 1,
|
631 | 32e0c826 | Gerd Hoffmann | .init = rtc_initfn, |
632 | 32e0c826 | Gerd Hoffmann | .qdev.props = (Property[]) { |
633 | 32e0c826 | Gerd Hoffmann | DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), |
634 | 32e0c826 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
635 | 32e0c826 | Gerd Hoffmann | } |
636 | 32e0c826 | Gerd Hoffmann | }; |
637 | 32e0c826 | Gerd Hoffmann | |
638 | 32e0c826 | Gerd Hoffmann | static void mc146818rtc_register(void) |
639 | 100d9891 | aurel32 | { |
640 | 32e0c826 | Gerd Hoffmann | isa_qdev_register(&mc146818rtc_info); |
641 | 100d9891 | aurel32 | } |
642 | 32e0c826 | Gerd Hoffmann | device_init(mc146818rtc_register) |