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Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
cpu_loop_exit: avoid using AREG0
Make cpu_loop_exit() take a parameter for CPUState instead of relyingon global env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
PPC: move TLBs to their own arrays
Until now, we've created a union over multiple different TLB types andallocated that union. While it's a waste of memory (and cache) to allocateTLB information for a TLB type with much information when you only needlittle, it also inflicts another issue....
PPC: E500: Use MAS registers instead of internal TLB representation
The natural format for e500 cores to do TLB manipulation with are the MASregisters. Instead of converting them into some internal representationand back again when the guest reads them, we can just keep the data...
target-ppc: remove old CONFIG_SOFTFLOAT #ifdef
target-ppc has been switched to softfloat only long ago, but afew #ifdef CONFIG_SOFTFLOAT have been forgotten. Remove them.
Cc: Alexander Graf <agraf@suse.de>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
Delete unused tb_invalidate_page_range
tb_invalidate_page_range() was intended to be used to invalidate anarea of a TB which the guest explicitly flushes from i-cache. However,QEMU detects writes to code areas where TBs have been generated, sohis has never been useful....
PPC: Implement e500 (FSL) MMU
Most of the code to support e500 style MMUs is already in place, butwe're missing on some of the special TLB0-TLB1 handling code and slightlydifferent TLB modification.
This patch adds support for the FSL style MMU.
Signed-off-by: Alexander Graf <agraf@suse.de>
Remove unused function parameter from cpu_restore_state
The previous patch removed the need for parameter puc.Is is now unused, so remove it.
Cc: Aurelien Jarno <aurelien@aurel32.net>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <weil@mail.berlios.de>
target-ppc: fix SPE comparison functions
efstst*() functions are fast SPE funtions which do not take into accountspecial values (infinites, NaN, etc.), while efscmp*() functions areIEEE754 compliant.
Given that float32_*() functions are IEEE754 compliant, the efscmp*()...
softfloat: rename float*_eq() into float*_eq_quiet()
float*_eq functions have a different semantics than other comparisonfunctions. Fix that by first renaming float*_quiet() into float*_eq_quiet().
Note that it is purely mechanical, and the behaviour should be unchanged....
target-ppc: remove #ifdef FLOAT128
Now that PPC defaults to softfloat which always provides float128support, there is no need to keep two version of the code, depending iffloat128 support is available or not. Suggested by Peter Maydell.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
Use existing helper function to implement popcntd instruction
The recent patches adding partial support for POWER7 cpu emulation includedimplementing the popcntd instruction. The support for this was open coded,but host-utils.h already included a function implementing an equivalent...
Clean up PowerPC SLB handling code
Currently the SLB information when emulating a PowerPC 970 isstoreed in a structure with the unhelpfully named fields 'tmp'and 'tmp64'. While the layout in these fields does match thedescription of the SLB in the architecture document, it is not...
Implement PowerPC slbmfee and slbmfev instructions
For a 64-bit PowerPC target, qemu correctly implements translationthrough the segment lookaside buffer. Likewise it supports theslbmte instruction which is used to load entries into the SLB.
However, it does not emulate the slbmfee and slbmfev instructions...
Implement missing parts of the logic for the POWER PURR
The PURR (Processor Utilization Resource Register) is a register foundon recent POWER CPUs. The guts of implementing it at least enough toget by are already present in qemu, however some of the helper...
Correct ppc popcntb logic, implement popcntw and popcntd
qemu already includes support for the popcntb instruction introducedin POWER5 (although it doesn't actually allow you to choose POWER5).
However, the logic is slightly incorrect: it will generate results...
target-ppc: fix wrong NaN tests
Some tests in FPU emulation code were wrongly using float64_is_nan()before commit 185698715dfb18c82ad2a5dbc169908602d43e81, and wronglyusing float64_is_quiet_nan() after. Fix them by using float64_is_any_nan()instead.
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>...
target-ppc: fix sNaN propagation
The current FPU code returns 0.0 if one of the operand is asignaling NaN and the VXSNAN exception is disabled.
fload_invalid_op_excp() doesn't return a qNaN in case of a VXSNANexception as the operand should be propagated instead of a new...
target-ppc: use float32_is_any_nan()
Use the new function float32_is_any_nan() instead offloat32_is_quiet_nan() || float32_is_signaling_nan().
Acked-by: Alexander Graf <agraf@suse.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: fix default qNaN
On PPC the default qNaN doesn't have the sign bit set.
target-ppc: remove PRECISE_EMULATION define
The PRECISE_EMULATION is "hardcoded" to one in target-ppc/exec.h and notsomething easily tunable. Remove it and non-precise emulation code asit doesn't make a noticeable difference in speed. People wanting speed...
softfloat: Rename float*_is_nan() functions to float*_is_quiet_nan()
The softfloat functions float*_is_nan() were badly misnamed,because they return true only for quiet NaNs, not for all NaNs.Rename them to float*_is_quiet_nan() to more accurately reflect...
ppc: avoid write only variables
Compiling with GCC 4.6.0 20100925 produced warnings:/src/qemu/target-ppc/op_helper.c: In function 'helper_icbi':/src/qemu/target-ppc/op_helper.c:351:14: error: variable 'tmp' set but not used [-Werror=unused-but-set-variable]...
ppc: Minor 40x MMU fixes
Signed-off-by: John Clark <clarkjc@runbox.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
PPC: Suppress gcc warnings with -Wtype-limits
The hack added by c5b76b381081680633e2e0a91216507430409fb2 was notenough to avoid warnings with gcc flag -Wtype-limits. Add a new macroto fix both problems.
target-ppc: add vexptefp instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: fix RFI by clearing some bits of MSR
Since commit 2ada0ed, "Return From Interrupt" is broken for PPC processorsbecause some interrupt specifics bits of SRR1 are copied to MSR.
SRR1 is a save of MSR during interrupt.During RFI, MSR must be restored from SRR1....
target-ppc: change DCR helpers to target_long arguments
The recent transition to always have the DCR helper functions take 32 bitvalues broke the PPC64 target, as target_long became 64 bits there.
This patch changes DCR helpers to target_long arguments, and cast the values...
ppc-40x: Correct check for Endian swapping TLB entries.
Bailout on 40x TLB entries with endianess swapping only if the entryis valid.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
ppc-40x: Get TLB attributes from TLBLO.
The ZSEL was incorrectly beeing decoded from TLBHI. Decode it fromTLBLO instead.
PPC: Make DCR uint32_t
For what I know DCR is always 32 bits wide, so we should also use uint32_t topass it along the stacks.
This fixes a warning when compiling qemu-system-ppc64 with KVM enabled, makingit compile without --disable-werror
Signed-off-by: Alexander Graf <agraf@suse.de>...
PPC64: Fix alternate timebase
Fix the alternate time base the same way as the default timebase. SPR_ATBLshould return a 64-bit value on 64 bit implementations.
PPC64: Fix timebase
On PPC we have a 64-bit time base. Usually (PPC32) this is accessed usingtwo separate 32 bit SPR accesses to SPR_TBU and SPR_TBL.
On PPC64 the SPR_TBL register acts as 64 bit though, so we get the full64 bits as return value. If we only take the lower ones, fine. But Linux...
Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Somethinglike this must be presented on the list first so people can provide input...
Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the timebeing.
Signed-off-by: malc <av1474@comtv.ru>
Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Replace always_inline with inline
We define inline as always_inline.
target-ppc: retain l{w,d}arx loaded value
We do this so we can check on the corresponding stc{w,d}x. whether thevalue has changed. It's a poor man's form of implementing atomicoperations and is valid only for NPTL usermode Linux emulation.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Update to a hopefully more future proof FSF address
Fix mingw32 build warnings
Work around buffer and ioctlsocket argument type signedness problemsSuppress a prototype which is unused on mingw32Expand a macro to avoid warnings from some GCC versions
Fix typo that leads to out of bounds array access on big endian systems
targe-ppc: optimize mfcr and mtcrf
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162
Fix RFI
The current implementation masks some MSR bits from SRR1 as it isgiven on rfi(d). This looks pretty wrong and breaks Altivec.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6754 c046a42c-6fe2-441c-8c8c-71466251a162
Implement slbmte
In order to modify SLB entries on recent PPC64 machines, the slbmteinstruction is used.
This patch implements the slbmte instruction and makes the "bridge" mode code use the slb set functions, so we can move the SLB intothe CPU struct later....
target-ppc: Add vrsqrtefp instruction
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6574 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add vrefp instruction
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6573 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add vct{u,s}xs instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6572 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add vcmp{eq, ge, gt, b}fp{, .} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6571 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add vmaddfp and vnmsubfp instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6570 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add v{add,sub}fp instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6569 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add v{max,min}fp instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6568 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: change instruction name vrlogefp into vlogefp
Thanks to Nathan Froyd for noticing that.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6532 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: add vrlogefp instruction
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6519 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix previous commit
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6516 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: use the new float constants
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6515 c046a42c-6fe2-441c-8c8c-71466251a162
Add vcf{u,s}x instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6513 c046a42c-6fe2-441c-8c8c-71466251a162
Add vrfi{m,n,p,z} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6512 c046a42c-6fe2-441c-8c8c-71466251a162
Add various NaN-handling macros
These simplify the implementation of the floating-point Altivecinstructions and reduce clutter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6511 c046a42c-6fe2-441c-8c8c-71466251a162
Make mtvscr use a helper
Do this so we can set float statuses once per mtvscr, rather than onceper Altivec instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6508 c046a42c-6fe2-441c-8c8c-71466251a162
Rename spe_status to vec_status
Only one of Altivec and SPE will be available on a given chip.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6506 c046a42c-6fe2-441c-8c8c-71466251a162
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Clean up debugging code #ifdefs (Eduardo Habkost)
Use macros to avoid #ifdefs on debugging code.
This patch doesn't try to merge logging macros from different files,but just unify the debugging code #ifdefs onto a macro on each file. Afurther cleanup can unify the debugging macros on a common header, later...
Add v{add, sub}{s, u}{b, h, w}s instructions
Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6254 c046a42c-6fe2-441c-8c8c-71466251a162
Add vspltis{b,h,w} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6238 c046a42c-6fe2-441c-8c8c-71466251a162
Add vs{l,r} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6237 c046a42c-6fe2-441c-8c8c-71466251a162
Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6236 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix compilation on BigEndian
This fixes BigEndian compilation for target-ppc.
(Michael Buesch)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6193 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsumsws, vsum2sws, and vsum4{sbs, shs,ubs} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6189 c046a42c-6fe2-441c-8c8c-71466251a162
Add {l,st}ve{b,h,w}x instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6188 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmladduhm instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6187 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmsumsh{m,s} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6186 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmsumuh{m,s} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6185 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmh{,r}addshs instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6184 c046a42c-6fe2-441c-8c8c-71466251a162
Add vpkpx instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6183 c046a42c-6fe2-441c-8c8c-71466251a162
Add vpks{h, w}{s, u}s, vpku{h, w}us, and vpku{h, w}um instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6182 c046a42c-6fe2-441c-8c8c-71466251a162
Add saturating arithmetic conversion functions for subsequent instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6181 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsel and vperm instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6180 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmsum{u,m}bm instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6179 c046a42c-6fe2-441c-8c8c-71466251a162
Add vupk{h,l}s{b,h} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6177 c046a42c-6fe2-441c-8c8c-71466251a162
Add vupk{h,l}px instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6176 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsplt{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6174 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsldoi instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6171 c046a42c-6fe2-441c-8c8c-71466251a162
Add vrl{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6170 c046a42c-6fe2-441c-8c8c-71466251a162
Add lvs{l,r} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6169 c046a42c-6fe2-441c-8c8c-71466251a162
Add v{add,sub}cuw instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6168 c046a42c-6fe2-441c-8c8c-71466251a162
Add vs{l,r}o instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6167 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsl{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6166 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsr{,a}{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6165 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmul{e,o}{s,u}{b,h} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6164 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmrg{l,h}{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6163 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Add v{min, max}{s, u}{b, h, w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6157 c046a42c-6fe2-441c-8c8c-71466251a162
Add vavg{s,u}{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6156 c046a42c-6fe2-441c-8c8c-71466251a162
Add v{add,sub}u{b,h,w}m instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6155 c046a42c-6fe2-441c-8c8c-71466251a162
Add helper macros for later patches.
Remove N_ELEMS, VECTOR_FOR, and VECTOR_FOR_I macros. Retain theVECTOR_FOR_INORDER_I macros as the clearest way of expressing the intentof iterating over elements in their stored target-endian order.
target-ppc: improve correctness of the fsel instruction
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6139 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix stsw/stswi instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6138 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: use float_flag_divbyzero instead of checking the operands
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6097 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix fres, fsqrte and remove useless code
- fres and fsqrte should not assign a float32 number to a float64 value.- fre, fres and fsqrte are checking for cases already taken into account by softfloat and softfloat native. Remove those useless tests....