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1 | 3475187d | bellard | /*
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2 | c7ba218d | blueswir1 | * QEMU Sun4u/Sun4v System Emulator
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pci.h" |
26 | 18e08a55 | Michael S. Tsirkin | #include "apb_pci.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | 488cb996 | Gerd Hoffmann | #include "serial.h" |
29 | 87ecb68b | pbrook | #include "nvram.h" |
30 | 87ecb68b | pbrook | #include "fdc.h" |
31 | 87ecb68b | pbrook | #include "net.h" |
32 | 87ecb68b | pbrook | #include "qemu-timer.h" |
33 | 87ecb68b | pbrook | #include "sysemu.h" |
34 | 87ecb68b | pbrook | #include "boards.h" |
35 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
36 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
37 | 1baffa46 | Blue Swirl | #include "sysbus.h" |
38 | 977e1244 | Gerd Hoffmann | #include "ide.h" |
39 | ca20cf32 | Blue Swirl | #include "loader.h" |
40 | ca20cf32 | Blue Swirl | #include "elf.h" |
41 | 2446333c | Blue Swirl | #include "blockdev.h" |
42 | 39186d8a | Richard Henderson | #include "exec-memory.h" |
43 | 3475187d | bellard | |
44 | 9d926598 | blueswir1 | //#define DEBUG_IRQ
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45 | b430a225 | Blue Swirl | //#define DEBUG_EBUS
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46 | 8f4efc55 | Igor V. Kovalenko | //#define DEBUG_TIMER
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47 | 9d926598 | blueswir1 | |
48 | 9d926598 | blueswir1 | #ifdef DEBUG_IRQ
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49 | b430a225 | Blue Swirl | #define CPUIRQ_DPRINTF(fmt, ...) \
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50 | 001faf32 | Blue Swirl | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
51 | 9d926598 | blueswir1 | #else
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52 | b430a225 | Blue Swirl | #define CPUIRQ_DPRINTF(fmt, ...)
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53 | b430a225 | Blue Swirl | #endif
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54 | b430a225 | Blue Swirl | |
55 | b430a225 | Blue Swirl | #ifdef DEBUG_EBUS
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56 | b430a225 | Blue Swirl | #define EBUS_DPRINTF(fmt, ...) \
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57 | b430a225 | Blue Swirl | do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) |
58 | b430a225 | Blue Swirl | #else
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59 | b430a225 | Blue Swirl | #define EBUS_DPRINTF(fmt, ...)
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60 | 9d926598 | blueswir1 | #endif
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61 | 9d926598 | blueswir1 | |
62 | 8f4efc55 | Igor V. Kovalenko | #ifdef DEBUG_TIMER
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63 | 8f4efc55 | Igor V. Kovalenko | #define TIMER_DPRINTF(fmt, ...) \
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64 | 8f4efc55 | Igor V. Kovalenko | do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) |
65 | 8f4efc55 | Igor V. Kovalenko | #else
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66 | 8f4efc55 | Igor V. Kovalenko | #define TIMER_DPRINTF(fmt, ...)
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67 | 8f4efc55 | Igor V. Kovalenko | #endif
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68 | 8f4efc55 | Igor V. Kovalenko | |
69 | 83469015 | bellard | #define KERNEL_LOAD_ADDR 0x00404000 |
70 | 83469015 | bellard | #define CMDLINE_ADDR 0x003ff000 |
71 | ac2e9d66 | blueswir1 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
72 | f930d07e | blueswir1 | #define PROM_VADDR 0x000ffd00000ULL |
73 | 83469015 | bellard | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
74 | f930d07e | blueswir1 | #define APB_MEM_BASE 0x1ff00000000ULL |
75 | d63baf92 | Igor V. Kovalenko | #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) |
76 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc64" |
77 | 83469015 | bellard | #define NVRAM_SIZE 0x2000 |
78 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
79 | 3cce6243 | blueswir1 | #define BIOS_CFG_IOPORT 0x510 |
80 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
81 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |
82 | 7589690c | Blue Swirl | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) |
83 | 3475187d | bellard | |
84 | 361dea40 | Blue Swirl | #define IVEC_MAX 0x30 |
85 | 9d926598 | blueswir1 | |
86 | 8fa211e8 | blueswir1 | #define TICK_MAX 0x7fffffffffffffffULL |
87 | 8fa211e8 | blueswir1 | |
88 | c7ba218d | blueswir1 | struct hwdef {
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89 | c7ba218d | blueswir1 | const char * const default_cpu_model; |
90 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
91 | e87231d4 | blueswir1 | uint64_t prom_addr; |
92 | e87231d4 | blueswir1 | uint64_t console_serial_base; |
93 | c7ba218d | blueswir1 | }; |
94 | c7ba218d | blueswir1 | |
95 | c5e6fb7e | Avi Kivity | typedef struct EbusState { |
96 | c5e6fb7e | Avi Kivity | PCIDevice pci_dev; |
97 | c5e6fb7e | Avi Kivity | MemoryRegion bar0; |
98 | c5e6fb7e | Avi Kivity | MemoryRegion bar1; |
99 | c5e6fb7e | Avi Kivity | } EbusState; |
100 | c5e6fb7e | Avi Kivity | |
101 | 3475187d | bellard | int DMA_get_channel_mode (int nchan) |
102 | 3475187d | bellard | { |
103 | 3475187d | bellard | return 0; |
104 | 3475187d | bellard | } |
105 | 3475187d | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
106 | 3475187d | bellard | { |
107 | 3475187d | bellard | return 0; |
108 | 3475187d | bellard | } |
109 | 3475187d | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
110 | 3475187d | bellard | { |
111 | 3475187d | bellard | return 0; |
112 | 3475187d | bellard | } |
113 | 3475187d | bellard | void DMA_hold_DREQ (int nchan) {} |
114 | 3475187d | bellard | void DMA_release_DREQ (int nchan) {} |
115 | 3475187d | bellard | void DMA_schedule(int nchan) {} |
116 | 4556bd8b | Blue Swirl | |
117 | 4556bd8b | Blue Swirl | void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) |
118 | 4556bd8b | Blue Swirl | { |
119 | 4556bd8b | Blue Swirl | } |
120 | 4556bd8b | Blue Swirl | |
121 | 3475187d | bellard | void DMA_register_channel (int nchan, |
122 | 3475187d | bellard | DMA_transfer_handler transfer_handler, |
123 | 3475187d | bellard | void *opaque)
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124 | 3475187d | bellard | { |
125 | 3475187d | bellard | } |
126 | 3475187d | bellard | |
127 | 513f789f | blueswir1 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
128 | 81864572 | blueswir1 | { |
129 | 513f789f | blueswir1 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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130 | 81864572 | blueswir1 | return 0; |
131 | 81864572 | blueswir1 | } |
132 | 81864572 | blueswir1 | |
133 | 43a34704 | Blue Swirl | static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size, |
134 | 43a34704 | Blue Swirl | const char *arch, ram_addr_t RAM_size, |
135 | 43a34704 | Blue Swirl | const char *boot_devices, |
136 | 43a34704 | Blue Swirl | uint32_t kernel_image, uint32_t kernel_size, |
137 | 43a34704 | Blue Swirl | const char *cmdline, |
138 | 43a34704 | Blue Swirl | uint32_t initrd_image, uint32_t initrd_size, |
139 | 43a34704 | Blue Swirl | uint32_t NVRAM_image, |
140 | 43a34704 | Blue Swirl | int width, int height, int depth, |
141 | 43a34704 | Blue Swirl | const uint8_t *macaddr)
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142 | 83469015 | bellard | { |
143 | 66508601 | blueswir1 | unsigned int i; |
144 | 66508601 | blueswir1 | uint32_t start, end; |
145 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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146 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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147 | d2c63fc1 | blueswir1 | |
148 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
149 | d2c63fc1 | blueswir1 | |
150 | 513f789f | blueswir1 | start = 0;
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151 | 83469015 | bellard | |
152 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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153 | 66508601 | blueswir1 | // Variable partition
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154 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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155 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
156 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
157 | 66508601 | blueswir1 | |
158 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
159 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
160 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
161 | d2c63fc1 | blueswir1 | |
162 | d2c63fc1 | blueswir1 | // End marker
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163 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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164 | 66508601 | blueswir1 | |
165 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
166 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
167 | 66508601 | blueswir1 | |
168 | 66508601 | blueswir1 | // free partition
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169 | 66508601 | blueswir1 | start = end; |
170 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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171 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
172 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
173 | 66508601 | blueswir1 | |
174 | 66508601 | blueswir1 | end = 0x1fd0;
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175 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
176 | d2c63fc1 | blueswir1 | |
177 | 0d31cb99 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
178 | 0d31cb99 | blueswir1 | |
179 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
180 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
181 | 66508601 | blueswir1 | |
182 | 83469015 | bellard | return 0; |
183 | 3475187d | bellard | } |
184 | 5f2bf0fe | Blue Swirl | |
185 | 5f2bf0fe | Blue Swirl | static uint64_t sun4u_load_kernel(const char *kernel_filename, |
186 | 5f2bf0fe | Blue Swirl | const char *initrd_filename, |
187 | 5f2bf0fe | Blue Swirl | ram_addr_t RAM_size, uint64_t *initrd_size, |
188 | 5f2bf0fe | Blue Swirl | uint64_t *initrd_addr, uint64_t *kernel_addr, |
189 | 5f2bf0fe | Blue Swirl | uint64_t *kernel_entry) |
190 | 636aa70a | Blue Swirl | { |
191 | 636aa70a | Blue Swirl | int linux_boot;
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192 | 636aa70a | Blue Swirl | unsigned int i; |
193 | 636aa70a | Blue Swirl | long kernel_size;
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194 | 6908d9ce | Blue Swirl | uint8_t *ptr; |
195 | 5f2bf0fe | Blue Swirl | uint64_t kernel_top; |
196 | 636aa70a | Blue Swirl | |
197 | 636aa70a | Blue Swirl | linux_boot = (kernel_filename != NULL);
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198 | 636aa70a | Blue Swirl | |
199 | 636aa70a | Blue Swirl | kernel_size = 0;
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200 | 636aa70a | Blue Swirl | if (linux_boot) {
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201 | ca20cf32 | Blue Swirl | int bswap_needed;
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202 | ca20cf32 | Blue Swirl | |
203 | ca20cf32 | Blue Swirl | #ifdef BSWAP_NEEDED
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204 | ca20cf32 | Blue Swirl | bswap_needed = 1;
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205 | ca20cf32 | Blue Swirl | #else
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206 | ca20cf32 | Blue Swirl | bswap_needed = 0;
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207 | ca20cf32 | Blue Swirl | #endif
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208 | 5f2bf0fe | Blue Swirl | kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, |
209 | 5f2bf0fe | Blue Swirl | kernel_addr, &kernel_top, 1, ELF_MACHINE, 0); |
210 | 5f2bf0fe | Blue Swirl | if (kernel_size < 0) { |
211 | 5f2bf0fe | Blue Swirl | *kernel_addr = KERNEL_LOAD_ADDR; |
212 | 5f2bf0fe | Blue Swirl | *kernel_entry = KERNEL_LOAD_ADDR; |
213 | 636aa70a | Blue Swirl | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
214 | ca20cf32 | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
215 | ca20cf32 | Blue Swirl | TARGET_PAGE_SIZE); |
216 | 5f2bf0fe | Blue Swirl | } |
217 | 5f2bf0fe | Blue Swirl | if (kernel_size < 0) { |
218 | 636aa70a | Blue Swirl | kernel_size = load_image_targphys(kernel_filename, |
219 | 636aa70a | Blue Swirl | KERNEL_LOAD_ADDR, |
220 | 636aa70a | Blue Swirl | RAM_size - KERNEL_LOAD_ADDR); |
221 | 5f2bf0fe | Blue Swirl | } |
222 | 636aa70a | Blue Swirl | if (kernel_size < 0) { |
223 | 636aa70a | Blue Swirl | fprintf(stderr, "qemu: could not load kernel '%s'\n",
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224 | 636aa70a | Blue Swirl | kernel_filename); |
225 | 636aa70a | Blue Swirl | exit(1);
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226 | 636aa70a | Blue Swirl | } |
227 | 5f2bf0fe | Blue Swirl | /* load initrd above kernel */
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228 | 636aa70a | Blue Swirl | *initrd_size = 0;
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229 | 636aa70a | Blue Swirl | if (initrd_filename) {
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230 | 5f2bf0fe | Blue Swirl | *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); |
231 | 5f2bf0fe | Blue Swirl | |
232 | 636aa70a | Blue Swirl | *initrd_size = load_image_targphys(initrd_filename, |
233 | 5f2bf0fe | Blue Swirl | *initrd_addr, |
234 | 5f2bf0fe | Blue Swirl | RAM_size - *initrd_addr); |
235 | 5f2bf0fe | Blue Swirl | if ((int)*initrd_size < 0) { |
236 | 636aa70a | Blue Swirl | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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237 | 636aa70a | Blue Swirl | initrd_filename); |
238 | 636aa70a | Blue Swirl | exit(1);
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239 | 636aa70a | Blue Swirl | } |
240 | 636aa70a | Blue Swirl | } |
241 | 636aa70a | Blue Swirl | if (*initrd_size > 0) { |
242 | 636aa70a | Blue Swirl | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
243 | 5f2bf0fe | Blue Swirl | ptr = rom_ptr(*kernel_addr + i); |
244 | 6908d9ce | Blue Swirl | if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ |
245 | 5f2bf0fe | Blue Swirl | stl_p(ptr + 24, *initrd_addr + *kernel_addr);
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246 | 6908d9ce | Blue Swirl | stl_p(ptr + 28, *initrd_size);
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247 | 636aa70a | Blue Swirl | break;
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248 | 636aa70a | Blue Swirl | } |
249 | 636aa70a | Blue Swirl | } |
250 | 636aa70a | Blue Swirl | } |
251 | 636aa70a | Blue Swirl | } |
252 | 636aa70a | Blue Swirl | return kernel_size;
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253 | 636aa70a | Blue Swirl | } |
254 | 3475187d | bellard | |
255 | 98cec4a2 | Andreas Färber | void cpu_check_irqs(CPUSPARCState *env)
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256 | 9d926598 | blueswir1 | { |
257 | d532b26c | Igor V. Kovalenko | uint32_t pil = env->pil_in | |
258 | d532b26c | Igor V. Kovalenko | (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); |
259 | d532b26c | Igor V. Kovalenko | |
260 | a7be9bad | Artyom Tarasenko | /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
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261 | a7be9bad | Artyom Tarasenko | if (env->ivec_status & 0x20) { |
262 | a7be9bad | Artyom Tarasenko | return;
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263 | a7be9bad | Artyom Tarasenko | } |
264 | d532b26c | Igor V. Kovalenko | /* check if TM or SM in SOFTINT are set
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265 | d532b26c | Igor V. Kovalenko | setting these also causes interrupt 14 */
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266 | d532b26c | Igor V. Kovalenko | if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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267 | d532b26c | Igor V. Kovalenko | pil |= 1 << 14; |
268 | d532b26c | Igor V. Kovalenko | } |
269 | d532b26c | Igor V. Kovalenko | |
270 | 9f94778c | Artyom Tarasenko | /* The bit corresponding to psrpil is (1<< psrpil), the next bit
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271 | 9f94778c | Artyom Tarasenko | is (2 << psrpil). */
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272 | 9f94778c | Artyom Tarasenko | if (pil < (2 << env->psrpil)){ |
273 | d532b26c | Igor V. Kovalenko | if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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274 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
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275 | d532b26c | Igor V. Kovalenko | env->interrupt_index); |
276 | d532b26c | Igor V. Kovalenko | env->interrupt_index = 0;
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277 | d532b26c | Igor V. Kovalenko | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
278 | d532b26c | Igor V. Kovalenko | } |
279 | d532b26c | Igor V. Kovalenko | return;
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280 | d532b26c | Igor V. Kovalenko | } |
281 | d532b26c | Igor V. Kovalenko | |
282 | d532b26c | Igor V. Kovalenko | if (cpu_interrupts_enabled(env)) {
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283 | 9d926598 | blueswir1 | |
284 | 9d926598 | blueswir1 | unsigned int i; |
285 | 9d926598 | blueswir1 | |
286 | d532b26c | Igor V. Kovalenko | for (i = 15; i > env->psrpil; i--) { |
287 | 9d926598 | blueswir1 | if (pil & (1 << i)) { |
288 | 9d926598 | blueswir1 | int old_interrupt = env->interrupt_index;
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289 | d532b26c | Igor V. Kovalenko | int new_interrupt = TT_EXTINT | i;
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290 | d532b26c | Igor V. Kovalenko | |
291 | a7be9bad | Artyom Tarasenko | if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt |
292 | a7be9bad | Artyom Tarasenko | && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
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293 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
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294 | d532b26c | Igor V. Kovalenko | "current %x >= pending %x\n",
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295 | d532b26c | Igor V. Kovalenko | env->tl, cpu_tsptr(env)->tt, new_interrupt); |
296 | d532b26c | Igor V. Kovalenko | } else if (old_interrupt != new_interrupt) { |
297 | d532b26c | Igor V. Kovalenko | env->interrupt_index = new_interrupt; |
298 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
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299 | d532b26c | Igor V. Kovalenko | old_interrupt, new_interrupt); |
300 | 9d926598 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
301 | 9d926598 | blueswir1 | } |
302 | 9d926598 | blueswir1 | break;
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303 | 9d926598 | blueswir1 | } |
304 | 9d926598 | blueswir1 | } |
305 | 9f94778c | Artyom Tarasenko | } else if (env->interrupt_request & CPU_INTERRUPT_HARD) { |
306 | d532b26c | Igor V. Kovalenko | CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
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307 | d532b26c | Igor V. Kovalenko | "current interrupt %x\n",
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308 | d532b26c | Igor V. Kovalenko | pil, env->pil_in, env->softint, env->interrupt_index); |
309 | 9f94778c | Artyom Tarasenko | env->interrupt_index = 0;
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310 | 9f94778c | Artyom Tarasenko | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
311 | 9d926598 | blueswir1 | } |
312 | 9d926598 | blueswir1 | } |
313 | 9d926598 | blueswir1 | |
314 | ce18c558 | Andreas Färber | static void cpu_kick_irq(SPARCCPU *cpu) |
315 | 8f4efc55 | Igor V. Kovalenko | { |
316 | ce18c558 | Andreas Färber | CPUSPARCState *env = &cpu->env; |
317 | ce18c558 | Andreas Färber | |
318 | 8f4efc55 | Igor V. Kovalenko | env->halted = 0;
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319 | 8f4efc55 | Igor V. Kovalenko | cpu_check_irqs(env); |
320 | 94ad5b00 | Paolo Bonzini | qemu_cpu_kick(env); |
321 | 8f4efc55 | Igor V. Kovalenko | } |
322 | 8f4efc55 | Igor V. Kovalenko | |
323 | 361dea40 | Blue Swirl | static void cpu_set_ivec_irq(void *opaque, int irq, int level) |
324 | 9d926598 | blueswir1 | { |
325 | b64ba4b2 | Andreas Färber | SPARCCPU *cpu = opaque; |
326 | b64ba4b2 | Andreas Färber | CPUSPARCState *env = &cpu->env; |
327 | 9d926598 | blueswir1 | |
328 | 9d926598 | blueswir1 | if (level) {
|
329 | 23cf96e1 | Artyom Tarasenko | if (!(env->ivec_status & 0x20)) { |
330 | 23cf96e1 | Artyom Tarasenko | CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
|
331 | 23cf96e1 | Artyom Tarasenko | env->halted = 0;
|
332 | 23cf96e1 | Artyom Tarasenko | env->interrupt_index = TT_IVEC; |
333 | 23cf96e1 | Artyom Tarasenko | env->ivec_status |= 0x20;
|
334 | 23cf96e1 | Artyom Tarasenko | env->ivec_data[0] = (0x1f << 6) | irq; |
335 | 23cf96e1 | Artyom Tarasenko | env->ivec_data[1] = 0; |
336 | 23cf96e1 | Artyom Tarasenko | env->ivec_data[2] = 0; |
337 | 23cf96e1 | Artyom Tarasenko | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
338 | 23cf96e1 | Artyom Tarasenko | } |
339 | 23cf96e1 | Artyom Tarasenko | } else {
|
340 | 23cf96e1 | Artyom Tarasenko | if (env->ivec_status & 0x20) { |
341 | 23cf96e1 | Artyom Tarasenko | CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
|
342 | 23cf96e1 | Artyom Tarasenko | env->ivec_status &= ~0x20;
|
343 | 23cf96e1 | Artyom Tarasenko | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
344 | 23cf96e1 | Artyom Tarasenko | } |
345 | 9d926598 | blueswir1 | } |
346 | 9d926598 | blueswir1 | } |
347 | 9d926598 | blueswir1 | |
348 | e87231d4 | blueswir1 | typedef struct ResetData { |
349 | 403d7a2d | Andreas Färber | SPARCCPU *cpu; |
350 | 44a99354 | Blue Swirl | uint64_t prom_addr; |
351 | e87231d4 | blueswir1 | } ResetData; |
352 | e87231d4 | blueswir1 | |
353 | 8f4efc55 | Igor V. Kovalenko | void cpu_put_timer(QEMUFile *f, CPUTimer *s)
|
354 | 8f4efc55 | Igor V. Kovalenko | { |
355 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be32s(f, &s->frequency); |
356 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be32s(f, &s->disabled); |
357 | 8f4efc55 | Igor V. Kovalenko | qemu_put_be64s(f, &s->disabled_mask); |
358 | 8f4efc55 | Igor V. Kovalenko | qemu_put_sbe64s(f, &s->clock_offset); |
359 | 8f4efc55 | Igor V. Kovalenko | |
360 | 8f4efc55 | Igor V. Kovalenko | qemu_put_timer(f, s->qtimer); |
361 | 8f4efc55 | Igor V. Kovalenko | } |
362 | 8f4efc55 | Igor V. Kovalenko | |
363 | 8f4efc55 | Igor V. Kovalenko | void cpu_get_timer(QEMUFile *f, CPUTimer *s)
|
364 | 8f4efc55 | Igor V. Kovalenko | { |
365 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be32s(f, &s->frequency); |
366 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be32s(f, &s->disabled); |
367 | 8f4efc55 | Igor V. Kovalenko | qemu_get_be64s(f, &s->disabled_mask); |
368 | 8f4efc55 | Igor V. Kovalenko | qemu_get_sbe64s(f, &s->clock_offset); |
369 | 8f4efc55 | Igor V. Kovalenko | |
370 | 8f4efc55 | Igor V. Kovalenko | qemu_get_timer(f, s->qtimer); |
371 | 8f4efc55 | Igor V. Kovalenko | } |
372 | 8f4efc55 | Igor V. Kovalenko | |
373 | 6b678e1f | Andreas Färber | static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu, |
374 | 8f4efc55 | Igor V. Kovalenko | QEMUBHFunc *cb, uint32_t frequency, |
375 | 8f4efc55 | Igor V. Kovalenko | uint64_t disabled_mask) |
376 | 8f4efc55 | Igor V. Kovalenko | { |
377 | 7267c094 | Anthony Liguori | CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
|
378 | 8f4efc55 | Igor V. Kovalenko | |
379 | 8f4efc55 | Igor V. Kovalenko | timer->name = name; |
380 | 8f4efc55 | Igor V. Kovalenko | timer->frequency = frequency; |
381 | 8f4efc55 | Igor V. Kovalenko | timer->disabled_mask = disabled_mask; |
382 | 8f4efc55 | Igor V. Kovalenko | |
383 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = 1;
|
384 | 74475455 | Paolo Bonzini | timer->clock_offset = qemu_get_clock_ns(vm_clock); |
385 | 8f4efc55 | Igor V. Kovalenko | |
386 | 6b678e1f | Andreas Färber | timer->qtimer = qemu_new_timer_ns(vm_clock, cb, cpu); |
387 | 8f4efc55 | Igor V. Kovalenko | |
388 | 8f4efc55 | Igor V. Kovalenko | return timer;
|
389 | 8f4efc55 | Igor V. Kovalenko | } |
390 | 8f4efc55 | Igor V. Kovalenko | |
391 | 8f4efc55 | Igor V. Kovalenko | static void cpu_timer_reset(CPUTimer *timer) |
392 | 8f4efc55 | Igor V. Kovalenko | { |
393 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = 1;
|
394 | 74475455 | Paolo Bonzini | timer->clock_offset = qemu_get_clock_ns(vm_clock); |
395 | 8f4efc55 | Igor V. Kovalenko | |
396 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
397 | 8f4efc55 | Igor V. Kovalenko | } |
398 | 8f4efc55 | Igor V. Kovalenko | |
399 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
400 | c68ea704 | bellard | { |
401 | e87231d4 | blueswir1 | ResetData *s = (ResetData *)opaque; |
402 | 403d7a2d | Andreas Färber | CPUSPARCState *env = &s->cpu->env; |
403 | 44a99354 | Blue Swirl | static unsigned int nr_resets; |
404 | 20c9f095 | blueswir1 | |
405 | 403d7a2d | Andreas Färber | cpu_reset(CPU(s->cpu)); |
406 | 8f4efc55 | Igor V. Kovalenko | |
407 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->tick); |
408 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->stick); |
409 | 8f4efc55 | Igor V. Kovalenko | cpu_timer_reset(env->hstick); |
410 | 8f4efc55 | Igor V. Kovalenko | |
411 | e87231d4 | blueswir1 | env->gregs[1] = 0; // Memory start |
412 | e87231d4 | blueswir1 | env->gregs[2] = ram_size; // Memory size |
413 | e87231d4 | blueswir1 | env->gregs[3] = 0; // Machine description XXX |
414 | 44a99354 | Blue Swirl | if (nr_resets++ == 0) { |
415 | 44a99354 | Blue Swirl | /* Power on reset */
|
416 | 44a99354 | Blue Swirl | env->pc = s->prom_addr + 0x20ULL;
|
417 | 44a99354 | Blue Swirl | } else {
|
418 | 44a99354 | Blue Swirl | env->pc = s->prom_addr + 0x40ULL;
|
419 | 44a99354 | Blue Swirl | } |
420 | e87231d4 | blueswir1 | env->npc = env->pc + 4;
|
421 | 20c9f095 | blueswir1 | } |
422 | 20c9f095 | blueswir1 | |
423 | 22548760 | blueswir1 | static void tick_irq(void *opaque) |
424 | 20c9f095 | blueswir1 | { |
425 | 6b678e1f | Andreas Färber | SPARCCPU *cpu = opaque; |
426 | 6b678e1f | Andreas Färber | CPUSPARCState *env = &cpu->env; |
427 | 20c9f095 | blueswir1 | |
428 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->tick; |
429 | 8f4efc55 | Igor V. Kovalenko | |
430 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
431 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
|
432 | 8f4efc55 | Igor V. Kovalenko | return;
|
433 | 8f4efc55 | Igor V. Kovalenko | } else {
|
434 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("tick: fire\n");
|
435 | 8fa211e8 | blueswir1 | } |
436 | 8f4efc55 | Igor V. Kovalenko | |
437 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_TIMER; |
438 | ce18c558 | Andreas Färber | cpu_kick_irq(cpu); |
439 | 20c9f095 | blueswir1 | } |
440 | 20c9f095 | blueswir1 | |
441 | 22548760 | blueswir1 | static void stick_irq(void *opaque) |
442 | 20c9f095 | blueswir1 | { |
443 | 6b678e1f | Andreas Färber | SPARCCPU *cpu = opaque; |
444 | 6b678e1f | Andreas Färber | CPUSPARCState *env = &cpu->env; |
445 | 20c9f095 | blueswir1 | |
446 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->stick; |
447 | 8f4efc55 | Igor V. Kovalenko | |
448 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
449 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
|
450 | 8f4efc55 | Igor V. Kovalenko | return;
|
451 | 8f4efc55 | Igor V. Kovalenko | } else {
|
452 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("stick: fire\n");
|
453 | 8fa211e8 | blueswir1 | } |
454 | 8f4efc55 | Igor V. Kovalenko | |
455 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_STIMER; |
456 | ce18c558 | Andreas Färber | cpu_kick_irq(cpu); |
457 | 20c9f095 | blueswir1 | } |
458 | 20c9f095 | blueswir1 | |
459 | 22548760 | blueswir1 | static void hstick_irq(void *opaque) |
460 | 20c9f095 | blueswir1 | { |
461 | 6b678e1f | Andreas Färber | SPARCCPU *cpu = opaque; |
462 | 6b678e1f | Andreas Färber | CPUSPARCState *env = &cpu->env; |
463 | 20c9f095 | blueswir1 | |
464 | 8f4efc55 | Igor V. Kovalenko | CPUTimer* timer = env->hstick; |
465 | 8f4efc55 | Igor V. Kovalenko | |
466 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled) {
|
467 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
|
468 | 8f4efc55 | Igor V. Kovalenko | return;
|
469 | 8f4efc55 | Igor V. Kovalenko | } else {
|
470 | 8f4efc55 | Igor V. Kovalenko | CPUIRQ_DPRINTF("hstick: fire\n");
|
471 | 8fa211e8 | blueswir1 | } |
472 | 8f4efc55 | Igor V. Kovalenko | |
473 | 8f4efc55 | Igor V. Kovalenko | env->softint |= SOFTINT_STIMER; |
474 | ce18c558 | Andreas Färber | cpu_kick_irq(cpu); |
475 | 8f4efc55 | Igor V. Kovalenko | } |
476 | 8f4efc55 | Igor V. Kovalenko | |
477 | 8f4efc55 | Igor V. Kovalenko | static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
|
478 | 8f4efc55 | Igor V. Kovalenko | { |
479 | 8f4efc55 | Igor V. Kovalenko | return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
|
480 | 8f4efc55 | Igor V. Kovalenko | } |
481 | 8f4efc55 | Igor V. Kovalenko | |
482 | 8f4efc55 | Igor V. Kovalenko | static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
|
483 | 8f4efc55 | Igor V. Kovalenko | { |
484 | 8f4efc55 | Igor V. Kovalenko | return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
|
485 | c68ea704 | bellard | } |
486 | c68ea704 | bellard | |
487 | 8f4efc55 | Igor V. Kovalenko | void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
|
488 | f4b1a842 | blueswir1 | { |
489 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_count = count & ~timer->disabled_mask; |
490 | 8f4efc55 | Igor V. Kovalenko | uint64_t disabled_bit = count & timer->disabled_mask; |
491 | 8f4efc55 | Igor V. Kovalenko | |
492 | 74475455 | Paolo Bonzini | int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) - |
493 | 8f4efc55 | Igor V. Kovalenko | cpu_to_timer_ticks(real_count, timer->frequency); |
494 | 8f4efc55 | Igor V. Kovalenko | |
495 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
|
496 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_count, |
497 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", timer); |
498 | 8f4efc55 | Igor V. Kovalenko | |
499 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = disabled_bit ? 1 : 0; |
500 | 8f4efc55 | Igor V. Kovalenko | timer->clock_offset = vm_clock_offset; |
501 | f4b1a842 | blueswir1 | } |
502 | f4b1a842 | blueswir1 | |
503 | 8f4efc55 | Igor V. Kovalenko | uint64_t cpu_tick_get_count(CPUTimer *timer) |
504 | f4b1a842 | blueswir1 | { |
505 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_count = timer_to_cpu_ticks( |
506 | 74475455 | Paolo Bonzini | qemu_get_clock_ns(vm_clock) - timer->clock_offset, |
507 | 8f4efc55 | Igor V. Kovalenko | timer->frequency); |
508 | 8f4efc55 | Igor V. Kovalenko | |
509 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
|
510 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_count, |
511 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", timer); |
512 | 8f4efc55 | Igor V. Kovalenko | |
513 | 8f4efc55 | Igor V. Kovalenko | if (timer->disabled)
|
514 | 8f4efc55 | Igor V. Kovalenko | real_count |= timer->disabled_mask; |
515 | 8f4efc55 | Igor V. Kovalenko | |
516 | 8f4efc55 | Igor V. Kovalenko | return real_count;
|
517 | f4b1a842 | blueswir1 | } |
518 | f4b1a842 | blueswir1 | |
519 | 8f4efc55 | Igor V. Kovalenko | void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
|
520 | f4b1a842 | blueswir1 | { |
521 | 74475455 | Paolo Bonzini | int64_t now = qemu_get_clock_ns(vm_clock); |
522 | 8f4efc55 | Igor V. Kovalenko | |
523 | 8f4efc55 | Igor V. Kovalenko | uint64_t real_limit = limit & ~timer->disabled_mask; |
524 | 8f4efc55 | Igor V. Kovalenko | timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; |
525 | 8f4efc55 | Igor V. Kovalenko | |
526 | 8f4efc55 | Igor V. Kovalenko | int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + |
527 | 8f4efc55 | Igor V. Kovalenko | timer->clock_offset; |
528 | 8f4efc55 | Igor V. Kovalenko | |
529 | 8f4efc55 | Igor V. Kovalenko | if (expires < now) {
|
530 | 8f4efc55 | Igor V. Kovalenko | expires = now + 1;
|
531 | 8f4efc55 | Igor V. Kovalenko | } |
532 | 8f4efc55 | Igor V. Kovalenko | |
533 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
|
534 | 8f4efc55 | Igor V. Kovalenko | "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
|
535 | 8f4efc55 | Igor V. Kovalenko | timer->name, real_limit, |
536 | 8f4efc55 | Igor V. Kovalenko | timer->disabled?"disabled":"enabled", |
537 | 8f4efc55 | Igor V. Kovalenko | timer, limit, |
538 | 8f4efc55 | Igor V. Kovalenko | timer_to_cpu_ticks(now - timer->clock_offset, |
539 | 8f4efc55 | Igor V. Kovalenko | timer->frequency), |
540 | 8f4efc55 | Igor V. Kovalenko | timer_to_cpu_ticks(expires - now, timer->frequency)); |
541 | 8f4efc55 | Igor V. Kovalenko | |
542 | 8f4efc55 | Igor V. Kovalenko | if (!real_limit) {
|
543 | 8f4efc55 | Igor V. Kovalenko | TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
|
544 | 8f4efc55 | Igor V. Kovalenko | timer->name); |
545 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
546 | 8f4efc55 | Igor V. Kovalenko | } else if (timer->disabled) { |
547 | 8f4efc55 | Igor V. Kovalenko | qemu_del_timer(timer->qtimer); |
548 | 8f4efc55 | Igor V. Kovalenko | } else {
|
549 | 8f4efc55 | Igor V. Kovalenko | qemu_mod_timer(timer->qtimer, expires); |
550 | 8f4efc55 | Igor V. Kovalenko | } |
551 | f4b1a842 | blueswir1 | } |
552 | f4b1a842 | blueswir1 | |
553 | 361dea40 | Blue Swirl | static void isa_irq_handler(void *opaque, int n, int level) |
554 | 1387fe4a | Blue Swirl | { |
555 | 361dea40 | Blue Swirl | static const int isa_irq_to_ivec[16] = { |
556 | 361dea40 | Blue Swirl | [1] = 0x29, /* keyboard */ |
557 | 361dea40 | Blue Swirl | [4] = 0x2b, /* serial */ |
558 | 361dea40 | Blue Swirl | [6] = 0x27, /* floppy */ |
559 | 361dea40 | Blue Swirl | [7] = 0x22, /* parallel */ |
560 | 361dea40 | Blue Swirl | [12] = 0x2a, /* mouse */ |
561 | 361dea40 | Blue Swirl | }; |
562 | 361dea40 | Blue Swirl | qemu_irq *irqs = opaque; |
563 | 361dea40 | Blue Swirl | int ivec;
|
564 | 361dea40 | Blue Swirl | |
565 | 361dea40 | Blue Swirl | assert(n < 16);
|
566 | 361dea40 | Blue Swirl | ivec = isa_irq_to_ivec[n]; |
567 | 361dea40 | Blue Swirl | EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec);
|
568 | 361dea40 | Blue Swirl | if (ivec) {
|
569 | 361dea40 | Blue Swirl | qemu_set_irq(irqs[ivec], level); |
570 | 361dea40 | Blue Swirl | } |
571 | 1387fe4a | Blue Swirl | } |
572 | 1387fe4a | Blue Swirl | |
573 | c190ea07 | blueswir1 | /* EBUS (Eight bit bus) bridge */
|
574 | 48a18b3c | Hervé Poussineau | static ISABus *
|
575 | 361dea40 | Blue Swirl | pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs)
|
576 | c190ea07 | blueswir1 | { |
577 | 1387fe4a | Blue Swirl | qemu_irq *isa_irq; |
578 | ab953e28 | Hervé Poussineau | PCIDevice *pci_dev; |
579 | 48a18b3c | Hervé Poussineau | ISABus *isa_bus; |
580 | 1387fe4a | Blue Swirl | |
581 | ab953e28 | Hervé Poussineau | pci_dev = pci_create_simple(bus, devfn, "ebus");
|
582 | ab953e28 | Hervé Poussineau | isa_bus = DO_UPCAST(ISABus, qbus, |
583 | ab953e28 | Hervé Poussineau | qdev_get_child_bus(&pci_dev->qdev, "isa.0"));
|
584 | 361dea40 | Blue Swirl | isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16);
|
585 | 48a18b3c | Hervé Poussineau | isa_bus_irqs(isa_bus, isa_irq); |
586 | 48a18b3c | Hervé Poussineau | return isa_bus;
|
587 | 53e3c4f9 | Blue Swirl | } |
588 | c190ea07 | blueswir1 | |
589 | 81a322d4 | Gerd Hoffmann | static int |
590 | c5e6fb7e | Avi Kivity | pci_ebus_init1(PCIDevice *pci_dev) |
591 | 53e3c4f9 | Blue Swirl | { |
592 | c5e6fb7e | Avi Kivity | EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); |
593 | c5e6fb7e | Avi Kivity | |
594 | c2d0d012 | Richard Henderson | isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev)); |
595 | c5e6fb7e | Avi Kivity | |
596 | c5e6fb7e | Avi Kivity | pci_dev->config[0x04] = 0x06; // command = bus master, pci mem |
597 | c5e6fb7e | Avi Kivity | pci_dev->config[0x05] = 0x00; |
598 | c5e6fb7e | Avi Kivity | pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
599 | c5e6fb7e | Avi Kivity | pci_dev->config[0x07] = 0x03; // status = medium devsel |
600 | c5e6fb7e | Avi Kivity | pci_dev->config[0x09] = 0x00; // programming i/f |
601 | c5e6fb7e | Avi Kivity | pci_dev->config[0x0D] = 0x0a; // latency_timer |
602 | c5e6fb7e | Avi Kivity | |
603 | c5e6fb7e | Avi Kivity | isa_mmio_setup(&s->bar0, 0x1000000);
|
604 | e824b2cc | Avi Kivity | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
|
605 | c5e6fb7e | Avi Kivity | isa_mmio_setup(&s->bar1, 0x800000);
|
606 | e824b2cc | Avi Kivity | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
|
607 | 81a322d4 | Gerd Hoffmann | return 0; |
608 | c190ea07 | blueswir1 | } |
609 | c190ea07 | blueswir1 | |
610 | 40021f08 | Anthony Liguori | static void ebus_class_init(ObjectClass *klass, void *data) |
611 | 40021f08 | Anthony Liguori | { |
612 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
613 | 40021f08 | Anthony Liguori | |
614 | 40021f08 | Anthony Liguori | k->init = pci_ebus_init1; |
615 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_SUN; |
616 | 40021f08 | Anthony Liguori | k->device_id = PCI_DEVICE_ID_SUN_EBUS; |
617 | 40021f08 | Anthony Liguori | k->revision = 0x01;
|
618 | 40021f08 | Anthony Liguori | k->class_id = PCI_CLASS_BRIDGE_OTHER; |
619 | 40021f08 | Anthony Liguori | } |
620 | 40021f08 | Anthony Liguori | |
621 | 39bffca2 | Anthony Liguori | static TypeInfo ebus_info = {
|
622 | 39bffca2 | Anthony Liguori | .name = "ebus",
|
623 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
624 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(EbusState),
|
625 | 39bffca2 | Anthony Liguori | .class_init = ebus_class_init, |
626 | 53e3c4f9 | Blue Swirl | }; |
627 | 53e3c4f9 | Blue Swirl | |
628 | d4edce38 | Avi Kivity | typedef struct PROMState { |
629 | d4edce38 | Avi Kivity | SysBusDevice busdev; |
630 | d4edce38 | Avi Kivity | MemoryRegion prom; |
631 | d4edce38 | Avi Kivity | } PROMState; |
632 | d4edce38 | Avi Kivity | |
633 | 409dbce5 | Aurelien Jarno | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
634 | 409dbce5 | Aurelien Jarno | { |
635 | a8170e5e | Avi Kivity | hwaddr *base_addr = (hwaddr *)opaque; |
636 | 409dbce5 | Aurelien Jarno | return addr + *base_addr - PROM_VADDR;
|
637 | 409dbce5 | Aurelien Jarno | } |
638 | 409dbce5 | Aurelien Jarno | |
639 | 1baffa46 | Blue Swirl | /* Boot PROM (OpenBIOS) */
|
640 | a8170e5e | Avi Kivity | static void prom_init(hwaddr addr, const char *bios_name) |
641 | 1baffa46 | Blue Swirl | { |
642 | 1baffa46 | Blue Swirl | DeviceState *dev; |
643 | 1baffa46 | Blue Swirl | SysBusDevice *s; |
644 | 1baffa46 | Blue Swirl | char *filename;
|
645 | 1baffa46 | Blue Swirl | int ret;
|
646 | 1baffa46 | Blue Swirl | |
647 | 1baffa46 | Blue Swirl | dev = qdev_create(NULL, "openprom"); |
648 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
649 | 1baffa46 | Blue Swirl | s = sysbus_from_qdev(dev); |
650 | 1baffa46 | Blue Swirl | |
651 | 1baffa46 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
652 | 1baffa46 | Blue Swirl | |
653 | 1baffa46 | Blue Swirl | /* load boot prom */
|
654 | 1baffa46 | Blue Swirl | if (bios_name == NULL) { |
655 | 1baffa46 | Blue Swirl | bios_name = PROM_FILENAME; |
656 | 1baffa46 | Blue Swirl | } |
657 | 1baffa46 | Blue Swirl | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); |
658 | 1baffa46 | Blue Swirl | if (filename) {
|
659 | 409dbce5 | Aurelien Jarno | ret = load_elf(filename, translate_prom_address, &addr, |
660 | 409dbce5 | Aurelien Jarno | NULL, NULL, NULL, 1, ELF_MACHINE, 0); |
661 | 1baffa46 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
662 | 1baffa46 | Blue Swirl | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); |
663 | 1baffa46 | Blue Swirl | } |
664 | 7267c094 | Anthony Liguori | g_free(filename); |
665 | 1baffa46 | Blue Swirl | } else {
|
666 | 1baffa46 | Blue Swirl | ret = -1;
|
667 | 1baffa46 | Blue Swirl | } |
668 | 1baffa46 | Blue Swirl | if (ret < 0 || ret > PROM_SIZE_MAX) { |
669 | 1baffa46 | Blue Swirl | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
670 | 1baffa46 | Blue Swirl | exit(1);
|
671 | 1baffa46 | Blue Swirl | } |
672 | 1baffa46 | Blue Swirl | } |
673 | 1baffa46 | Blue Swirl | |
674 | 81a322d4 | Gerd Hoffmann | static int prom_init1(SysBusDevice *dev) |
675 | 1baffa46 | Blue Swirl | { |
676 | d4edce38 | Avi Kivity | PROMState *s = FROM_SYSBUS(PROMState, dev); |
677 | 1baffa46 | Blue Swirl | |
678 | c5705a77 | Avi Kivity | memory_region_init_ram(&s->prom, "sun4u.prom", PROM_SIZE_MAX);
|
679 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&s->prom); |
680 | d4edce38 | Avi Kivity | memory_region_set_readonly(&s->prom, true);
|
681 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &s->prom); |
682 | 81a322d4 | Gerd Hoffmann | return 0; |
683 | 1baffa46 | Blue Swirl | } |
684 | 1baffa46 | Blue Swirl | |
685 | 999e12bb | Anthony Liguori | static Property prom_properties[] = {
|
686 | 999e12bb | Anthony Liguori | {/* end of property list */},
|
687 | 999e12bb | Anthony Liguori | }; |
688 | 999e12bb | Anthony Liguori | |
689 | 999e12bb | Anthony Liguori | static void prom_class_init(ObjectClass *klass, void *data) |
690 | 999e12bb | Anthony Liguori | { |
691 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
692 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
693 | 999e12bb | Anthony Liguori | |
694 | 999e12bb | Anthony Liguori | k->init = prom_init1; |
695 | 39bffca2 | Anthony Liguori | dc->props = prom_properties; |
696 | 999e12bb | Anthony Liguori | } |
697 | 999e12bb | Anthony Liguori | |
698 | 39bffca2 | Anthony Liguori | static TypeInfo prom_info = {
|
699 | 39bffca2 | Anthony Liguori | .name = "openprom",
|
700 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
701 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PROMState),
|
702 | 39bffca2 | Anthony Liguori | .class_init = prom_class_init, |
703 | 1baffa46 | Blue Swirl | }; |
704 | 1baffa46 | Blue Swirl | |
705 | bda42033 | Blue Swirl | |
706 | bda42033 | Blue Swirl | typedef struct RamDevice |
707 | bda42033 | Blue Swirl | { |
708 | bda42033 | Blue Swirl | SysBusDevice busdev; |
709 | d4edce38 | Avi Kivity | MemoryRegion ram; |
710 | 04843626 | Blue Swirl | uint64_t size; |
711 | bda42033 | Blue Swirl | } RamDevice; |
712 | bda42033 | Blue Swirl | |
713 | bda42033 | Blue Swirl | /* System RAM */
|
714 | 81a322d4 | Gerd Hoffmann | static int ram_init1(SysBusDevice *dev) |
715 | bda42033 | Blue Swirl | { |
716 | bda42033 | Blue Swirl | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
717 | bda42033 | Blue Swirl | |
718 | c5705a77 | Avi Kivity | memory_region_init_ram(&d->ram, "sun4u.ram", d->size);
|
719 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&d->ram); |
720 | 750ecd44 | Avi Kivity | sysbus_init_mmio(dev, &d->ram); |
721 | 81a322d4 | Gerd Hoffmann | return 0; |
722 | bda42033 | Blue Swirl | } |
723 | bda42033 | Blue Swirl | |
724 | a8170e5e | Avi Kivity | static void ram_init(hwaddr addr, ram_addr_t RAM_size) |
725 | bda42033 | Blue Swirl | { |
726 | bda42033 | Blue Swirl | DeviceState *dev; |
727 | bda42033 | Blue Swirl | SysBusDevice *s; |
728 | bda42033 | Blue Swirl | RamDevice *d; |
729 | bda42033 | Blue Swirl | |
730 | bda42033 | Blue Swirl | /* allocate RAM */
|
731 | bda42033 | Blue Swirl | dev = qdev_create(NULL, "memory"); |
732 | bda42033 | Blue Swirl | s = sysbus_from_qdev(dev); |
733 | bda42033 | Blue Swirl | |
734 | bda42033 | Blue Swirl | d = FROM_SYSBUS(RamDevice, s); |
735 | bda42033 | Blue Swirl | d->size = RAM_size; |
736 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
737 | bda42033 | Blue Swirl | |
738 | bda42033 | Blue Swirl | sysbus_mmio_map(s, 0, addr);
|
739 | bda42033 | Blue Swirl | } |
740 | bda42033 | Blue Swirl | |
741 | 999e12bb | Anthony Liguori | static Property ram_properties[] = {
|
742 | 999e12bb | Anthony Liguori | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
743 | 999e12bb | Anthony Liguori | DEFINE_PROP_END_OF_LIST(), |
744 | 999e12bb | Anthony Liguori | }; |
745 | 999e12bb | Anthony Liguori | |
746 | 999e12bb | Anthony Liguori | static void ram_class_init(ObjectClass *klass, void *data) |
747 | 999e12bb | Anthony Liguori | { |
748 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
749 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
750 | 999e12bb | Anthony Liguori | |
751 | 999e12bb | Anthony Liguori | k->init = ram_init1; |
752 | 39bffca2 | Anthony Liguori | dc->props = ram_properties; |
753 | 999e12bb | Anthony Liguori | } |
754 | 999e12bb | Anthony Liguori | |
755 | 39bffca2 | Anthony Liguori | static TypeInfo ram_info = {
|
756 | 39bffca2 | Anthony Liguori | .name = "memory",
|
757 | 39bffca2 | Anthony Liguori | .parent = TYPE_SYS_BUS_DEVICE, |
758 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(RamDevice),
|
759 | 39bffca2 | Anthony Liguori | .class_init = ram_class_init, |
760 | bda42033 | Blue Swirl | }; |
761 | bda42033 | Blue Swirl | |
762 | f9d1465f | Andreas Färber | static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) |
763 | 3475187d | bellard | { |
764 | 8ebdf9dc | Andreas Färber | SPARCCPU *cpu; |
765 | 98cec4a2 | Andreas Färber | CPUSPARCState *env; |
766 | e87231d4 | blueswir1 | ResetData *reset_info; |
767 | 3475187d | bellard | |
768 | 8f4efc55 | Igor V. Kovalenko | uint32_t tick_frequency = 100*1000000; |
769 | 8f4efc55 | Igor V. Kovalenko | uint32_t stick_frequency = 100*1000000; |
770 | 8f4efc55 | Igor V. Kovalenko | uint32_t hstick_frequency = 100*1000000; |
771 | 8f4efc55 | Igor V. Kovalenko | |
772 | 8ebdf9dc | Andreas Färber | if (cpu_model == NULL) { |
773 | c7ba218d | blueswir1 | cpu_model = hwdef->default_cpu_model; |
774 | 8ebdf9dc | Andreas Färber | } |
775 | 8ebdf9dc | Andreas Färber | cpu = cpu_sparc_init(cpu_model); |
776 | 8ebdf9dc | Andreas Färber | if (cpu == NULL) { |
777 | 62724a37 | blueswir1 | fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
778 | 62724a37 | blueswir1 | exit(1);
|
779 | 62724a37 | blueswir1 | } |
780 | 8ebdf9dc | Andreas Färber | env = &cpu->env; |
781 | 20c9f095 | blueswir1 | |
782 | 6b678e1f | Andreas Färber | env->tick = cpu_timer_create("tick", cpu, tick_irq,
|
783 | 8f4efc55 | Igor V. Kovalenko | tick_frequency, TICK_NPT_MASK); |
784 | 8f4efc55 | Igor V. Kovalenko | |
785 | 6b678e1f | Andreas Färber | env->stick = cpu_timer_create("stick", cpu, stick_irq,
|
786 | 8f4efc55 | Igor V. Kovalenko | stick_frequency, TICK_INT_DIS); |
787 | 20c9f095 | blueswir1 | |
788 | 6b678e1f | Andreas Färber | env->hstick = cpu_timer_create("hstick", cpu, hstick_irq,
|
789 | 8f4efc55 | Igor V. Kovalenko | hstick_frequency, TICK_INT_DIS); |
790 | e87231d4 | blueswir1 | |
791 | 7267c094 | Anthony Liguori | reset_info = g_malloc0(sizeof(ResetData));
|
792 | 403d7a2d | Andreas Färber | reset_info->cpu = cpu; |
793 | 44a99354 | Blue Swirl | reset_info->prom_addr = hwdef->prom_addr; |
794 | a08d4367 | Jan Kiszka | qemu_register_reset(main_cpu_reset, reset_info); |
795 | c68ea704 | bellard | |
796 | f9d1465f | Andreas Färber | return cpu;
|
797 | 7b833f5b | Blue Swirl | } |
798 | 7b833f5b | Blue Swirl | |
799 | 38bc50f7 | Richard Henderson | static void sun4uv_init(MemoryRegion *address_space_mem, |
800 | 38bc50f7 | Richard Henderson | ram_addr_t RAM_size, |
801 | 7b833f5b | Blue Swirl | const char *boot_devices, |
802 | 7b833f5b | Blue Swirl | const char *kernel_filename, const char *kernel_cmdline, |
803 | 7b833f5b | Blue Swirl | const char *initrd_filename, const char *cpu_model, |
804 | 7b833f5b | Blue Swirl | const struct hwdef *hwdef) |
805 | 7b833f5b | Blue Swirl | { |
806 | f9d1465f | Andreas Färber | SPARCCPU *cpu; |
807 | 43a34704 | Blue Swirl | M48t59State *nvram; |
808 | 7b833f5b | Blue Swirl | unsigned int i; |
809 | 5f2bf0fe | Blue Swirl | uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; |
810 | 7b833f5b | Blue Swirl | PCIBus *pci_bus, *pci_bus2, *pci_bus3; |
811 | 48a18b3c | Hervé Poussineau | ISABus *isa_bus; |
812 | 361dea40 | Blue Swirl | qemu_irq *ivec_irqs, *pbm_irqs; |
813 | f455e98c | Gerd Hoffmann | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
814 | fd8014e1 | Gerd Hoffmann | DriveInfo *fd[MAX_FD]; |
815 | 7b833f5b | Blue Swirl | void *fw_cfg;
|
816 | 7b833f5b | Blue Swirl | |
817 | 7b833f5b | Blue Swirl | /* init CPUs */
|
818 | f9d1465f | Andreas Färber | cpu = cpu_devinit(cpu_model, hwdef); |
819 | 7b833f5b | Blue Swirl | |
820 | bda42033 | Blue Swirl | /* set up devices */
|
821 | bda42033 | Blue Swirl | ram_init(0, RAM_size);
|
822 | 3475187d | bellard | |
823 | 1baffa46 | Blue Swirl | prom_init(hwdef->prom_addr, bios_name); |
824 | 3475187d | bellard | |
825 | b64ba4b2 | Andreas Färber | ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX); |
826 | 361dea40 | Blue Swirl | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2, |
827 | 361dea40 | Blue Swirl | &pci_bus3, &pbm_irqs); |
828 | f2898771 | Aurelien Jarno | pci_vga_init(pci_bus); |
829 | 83469015 | bellard | |
830 | c190ea07 | blueswir1 | // XXX Should be pci_bus3
|
831 | 361dea40 | Blue Swirl | isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
|
832 | c190ea07 | blueswir1 | |
833 | e87231d4 | blueswir1 | i = 0;
|
834 | e87231d4 | blueswir1 | if (hwdef->console_serial_base) {
|
835 | 38bc50f7 | Richard Henderson | serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
|
836 | 39186d8a | Richard Henderson | NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); |
837 | e87231d4 | blueswir1 | i++; |
838 | e87231d4 | blueswir1 | } |
839 | e87231d4 | blueswir1 | for(; i < MAX_SERIAL_PORTS; i++) {
|
840 | 83469015 | bellard | if (serial_hds[i]) {
|
841 | 48a18b3c | Hervé Poussineau | serial_isa_init(isa_bus, i, serial_hds[i]); |
842 | 83469015 | bellard | } |
843 | 83469015 | bellard | } |
844 | 83469015 | bellard | |
845 | 83469015 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
846 | 83469015 | bellard | if (parallel_hds[i]) {
|
847 | 48a18b3c | Hervé Poussineau | parallel_init(isa_bus, i, parallel_hds[i]); |
848 | 83469015 | bellard | } |
849 | 83469015 | bellard | } |
850 | 83469015 | bellard | |
851 | cb457d76 | aliguori | for(i = 0; i < nb_nics; i++) |
852 | 07caea31 | Markus Armbruster | pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL); |
853 | 83469015 | bellard | |
854 | 75717903 | Isaku Yamahata | ide_drive_get(hd, MAX_IDE_BUS); |
855 | e4bcb14c | ths | |
856 | 3b898dda | blueswir1 | pci_cmd646_ide_init(pci_bus, hd, 1);
|
857 | 3b898dda | blueswir1 | |
858 | 48a18b3c | Hervé Poussineau | isa_create_simple(isa_bus, "i8042");
|
859 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
860 | fd8014e1 | Gerd Hoffmann | fd[i] = drive_get(IF_FLOPPY, 0, i);
|
861 | e4bcb14c | ths | } |
862 | 48a18b3c | Hervé Poussineau | fdctrl_init_isa(isa_bus, fd); |
863 | 48a18b3c | Hervé Poussineau | nvram = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59); |
864 | 636aa70a | Blue Swirl | |
865 | 636aa70a | Blue Swirl | initrd_size = 0;
|
866 | 5f2bf0fe | Blue Swirl | initrd_addr = 0;
|
867 | 636aa70a | Blue Swirl | kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename, |
868 | 5f2bf0fe | Blue Swirl | ram_size, &initrd_size, &initrd_addr, |
869 | 5f2bf0fe | Blue Swirl | &kernel_addr, &kernel_entry); |
870 | 636aa70a | Blue Swirl | |
871 | 22548760 | blueswir1 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
|
872 | 5f2bf0fe | Blue Swirl | kernel_addr, kernel_size, |
873 | 0d31cb99 | blueswir1 | kernel_cmdline, |
874 | 5f2bf0fe | Blue Swirl | initrd_addr, initrd_size, |
875 | 0d31cb99 | blueswir1 | /* XXX: need an option to load a NVRAM image */
|
876 | 0d31cb99 | blueswir1 | 0,
|
877 | 0d31cb99 | blueswir1 | graphic_width, graphic_height, graphic_depth, |
878 | 0d31cb99 | blueswir1 | (uint8_t *)&nd_table[0].macaddr);
|
879 | 83469015 | bellard | |
880 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
881 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
882 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
883 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
884 | 5f2bf0fe | Blue Swirl | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); |
885 | 5f2bf0fe | Blue Swirl | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
886 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
887 | 9c9b0512 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
888 | 9c9b0512 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
889 | 6bb4ca57 | Blue Swirl | fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA, |
890 | 6bb4ca57 | Blue Swirl | (uint8_t*)strdup(kernel_cmdline), |
891 | 6bb4ca57 | Blue Swirl | strlen(kernel_cmdline) + 1);
|
892 | 513f789f | blueswir1 | } else {
|
893 | 9c9b0512 | Blue Swirl | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
894 | 513f789f | blueswir1 | } |
895 | 5f2bf0fe | Blue Swirl | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
896 | 5f2bf0fe | Blue Swirl | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
897 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
|
898 | 7589690c | Blue Swirl | |
899 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); |
900 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); |
901 | 7589690c | Blue Swirl | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); |
902 | 7589690c | Blue Swirl | |
903 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
904 | 3475187d | bellard | } |
905 | 3475187d | bellard | |
906 | 905fdcb5 | blueswir1 | enum {
|
907 | 905fdcb5 | blueswir1 | sun4u_id = 0,
|
908 | 905fdcb5 | blueswir1 | sun4v_id = 64,
|
909 | e87231d4 | blueswir1 | niagara_id, |
910 | 905fdcb5 | blueswir1 | }; |
911 | 905fdcb5 | blueswir1 | |
912 | c7ba218d | blueswir1 | static const struct hwdef hwdefs[] = { |
913 | c7ba218d | blueswir1 | /* Sun4u generic PC-like machine */
|
914 | c7ba218d | blueswir1 | { |
915 | 5910b047 | Igor V. Kovalenko | .default_cpu_model = "TI UltraSparc IIi",
|
916 | 905fdcb5 | blueswir1 | .machine_id = sun4u_id, |
917 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
918 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
919 | c7ba218d | blueswir1 | }, |
920 | c7ba218d | blueswir1 | /* Sun4v generic PC-like machine */
|
921 | c7ba218d | blueswir1 | { |
922 | c7ba218d | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
923 | 905fdcb5 | blueswir1 | .machine_id = sun4v_id, |
924 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
925 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
926 | e87231d4 | blueswir1 | }, |
927 | e87231d4 | blueswir1 | /* Sun4v generic Niagara machine */
|
928 | e87231d4 | blueswir1 | { |
929 | e87231d4 | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
930 | e87231d4 | blueswir1 | .machine_id = niagara_id, |
931 | e87231d4 | blueswir1 | .prom_addr = 0xfff0000000ULL,
|
932 | e87231d4 | blueswir1 | .console_serial_base = 0xfff0c2c000ULL,
|
933 | c7ba218d | blueswir1 | }, |
934 | c7ba218d | blueswir1 | }; |
935 | c7ba218d | blueswir1 | |
936 | c7ba218d | blueswir1 | /* Sun4u hardware initialisation */
|
937 | 5f072e1f | Eduardo Habkost | static void sun4u_init(QEMUMachineInitArgs *args) |
938 | 5f072e1f | Eduardo Habkost | { |
939 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
940 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
941 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
942 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
943 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
944 | 5f072e1f | Eduardo Habkost | const char *boot_devices = args->boot_device; |
945 | 38bc50f7 | Richard Henderson | sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
946 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
|
947 | c7ba218d | blueswir1 | } |
948 | c7ba218d | blueswir1 | |
949 | c7ba218d | blueswir1 | /* Sun4v hardware initialisation */
|
950 | 5f072e1f | Eduardo Habkost | static void sun4v_init(QEMUMachineInitArgs *args) |
951 | 5f072e1f | Eduardo Habkost | { |
952 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
953 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
954 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
955 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
956 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
957 | 5f072e1f | Eduardo Habkost | const char *boot_devices = args->boot_device; |
958 | 38bc50f7 | Richard Henderson | sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
959 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
|
960 | c7ba218d | blueswir1 | } |
961 | c7ba218d | blueswir1 | |
962 | e87231d4 | blueswir1 | /* Niagara hardware initialisation */
|
963 | 5f072e1f | Eduardo Habkost | static void niagara_init(QEMUMachineInitArgs *args) |
964 | 5f072e1f | Eduardo Habkost | { |
965 | 5f072e1f | Eduardo Habkost | ram_addr_t RAM_size = args->ram_size; |
966 | 5f072e1f | Eduardo Habkost | const char *cpu_model = args->cpu_model; |
967 | 5f072e1f | Eduardo Habkost | const char *kernel_filename = args->kernel_filename; |
968 | 5f072e1f | Eduardo Habkost | const char *kernel_cmdline = args->kernel_cmdline; |
969 | 5f072e1f | Eduardo Habkost | const char *initrd_filename = args->initrd_filename; |
970 | 5f072e1f | Eduardo Habkost | const char *boot_devices = args->boot_device; |
971 | 38bc50f7 | Richard Henderson | sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename, |
972 | e87231d4 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
|
973 | e87231d4 | blueswir1 | } |
974 | e87231d4 | blueswir1 | |
975 | f80f9ec9 | Anthony Liguori | static QEMUMachine sun4u_machine = {
|
976 | 66de733b | blueswir1 | .name = "sun4u",
|
977 | 66de733b | blueswir1 | .desc = "Sun4u platform",
|
978 | 66de733b | blueswir1 | .init = sun4u_init, |
979 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
980 | 0c257437 | Anthony Liguori | .is_default = 1,
|
981 | 3475187d | bellard | }; |
982 | c7ba218d | blueswir1 | |
983 | f80f9ec9 | Anthony Liguori | static QEMUMachine sun4v_machine = {
|
984 | 66de733b | blueswir1 | .name = "sun4v",
|
985 | 66de733b | blueswir1 | .desc = "Sun4v platform",
|
986 | 66de733b | blueswir1 | .init = sun4v_init, |
987 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
988 | c7ba218d | blueswir1 | }; |
989 | e87231d4 | blueswir1 | |
990 | f80f9ec9 | Anthony Liguori | static QEMUMachine niagara_machine = {
|
991 | e87231d4 | blueswir1 | .name = "Niagara",
|
992 | e87231d4 | blueswir1 | .desc = "Sun4v platform, Niagara",
|
993 | e87231d4 | blueswir1 | .init = niagara_init, |
994 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
995 | e87231d4 | blueswir1 | }; |
996 | f80f9ec9 | Anthony Liguori | |
997 | 83f7d43a | Andreas Färber | static void sun4u_register_types(void) |
998 | 83f7d43a | Andreas Färber | { |
999 | 83f7d43a | Andreas Färber | type_register_static(&ebus_info); |
1000 | 83f7d43a | Andreas Färber | type_register_static(&prom_info); |
1001 | 83f7d43a | Andreas Färber | type_register_static(&ram_info); |
1002 | 83f7d43a | Andreas Färber | } |
1003 | 83f7d43a | Andreas Färber | |
1004 | f80f9ec9 | Anthony Liguori | static void sun4u_machine_init(void) |
1005 | f80f9ec9 | Anthony Liguori | { |
1006 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sun4u_machine); |
1007 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&sun4v_machine); |
1008 | f80f9ec9 | Anthony Liguori | qemu_register_machine(&niagara_machine); |
1009 | f80f9ec9 | Anthony Liguori | } |
1010 | f80f9ec9 | Anthony Liguori | |
1011 | 83f7d43a | Andreas Färber | type_init(sun4u_register_types) |
1012 | f80f9ec9 | Anthony Liguori | machine_init(sun4u_machine_init); |