Archipelago » qemu

/*

 *  PowerPC emulation for qemu: main translation routines.

 *

 *  Copyright (c) 2003-2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "exec-all.h"

#include "disas.h"

#include "tcg-op.h"

#include "qemu-common.h"

#include "helper.h"

#define GEN_HELPER 1

#include "helper.h"

#define CPU_SINGLE_STEP 0x1

#define CPU_BRANCH_STEP 0x2

#define GDBSTUB_SINGLE_STEP 0x4

/* Include definitions for instructions classes and implementations flags */

//#define DO_SINGLE_STEP

//#define PPC_DEBUG_DISAS

//#define DO_PPC_STATISTICS

//#define OPTIMIZE_FPRF_UPDATE

/*****************************************************************************/

/* Code translation helpers                                                  */

/* global register indexes */

static TCGv_ptr cpu_env;

static char cpu_reg_names[10*3 + 22*4 /* GPR */

#if !defined(TARGET_PPC64)

    + 10*4 + 22*5 /* SPE GPRh */

#endif

    + 10*4 + 22*5 /* FPR */

    + 2*(10*6 + 22*7) /* AVRh, AVRl */

    + 8*5 /* CRF */];

static TCGv cpu_gpr[32];

#if !defined(TARGET_PPC64)

static TCGv cpu_gprh[32];

#endif

static TCGv_i64 cpu_fpr[32];

static TCGv_i64 cpu_avrh[32], cpu_avrl[32];

static TCGv_i32 cpu_crf[8];

static TCGv cpu_nip;

static TCGv cpu_ctr;

static TCGv cpu_lr;

static TCGv cpu_xer;

static TCGv_i32 cpu_fpscr;

/* dyngen register indexes */

static TCGv cpu_T[3];

#if defined(TARGET_PPC64)

#define cpu_T64 cpu_T

#else

static TCGv_i64 cpu_T64[3];

#endif

static TCGv_i64 cpu_FT[3];

static TCGv_i64 cpu_AVRh[3], cpu_AVRl[3];

#include "gen-icount.h"

void ppc_translate_init(void)

{

    int i;

    char* p;

    static int done_init = 0;

    if (done_init)

        return;

    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");

#if TARGET_LONG_BITS > HOST_LONG_BITS

    cpu_T[0] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t0), "T0");

    cpu_T[1] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t1), "T1");

    cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");

#else

    cpu_T[0] = tcg_global_reg_new(TCG_AREG1, "T0");

    cpu_T[1] = tcg_global_reg_new(TCG_AREG2, "T1");

#ifdef HOST_I386

    /* XXX: This is a temporary workaround for i386.

     *      On i386 qemu_st32 runs out of registers.

     *      The proper fix is to remove cpu_T.

     */

    cpu_T[2] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, t2), "T2");

#else

    cpu_T[2] = tcg_global_reg_new(TCG_AREG3, "T2");

#endif

#endif

#if !defined(TARGET_PPC64)

    cpu_T64[0] = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, t0_64),

                                        "T0_64");

    cpu_T64[1] = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, t1_64),

                                        "T1_64");

    cpu_T64[2] = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, t2_64),

                                        "T2_64");

#endif

    cpu_FT[0] = tcg_global_mem_new_i64(TCG_AREG0,

                                       offsetof(CPUState, ft0), "FT0");

    cpu_FT[1] = tcg_global_mem_new_i64(TCG_AREG0,

                                       offsetof(CPUState, ft1), "FT1");

    cpu_FT[2] = tcg_global_mem_new_i64(TCG_AREG0,

                                       offsetof(CPUState, ft2), "FT2");

    cpu_AVRh[0] = tcg_global_mem_new_i64(TCG_AREG0,

                                     offsetof(CPUState, avr0.u64[0]), "AVR0H");

    cpu_AVRl[0] = tcg_global_mem_new_i64(TCG_AREG0,

                                     offsetof(CPUState, avr0.u64[1]), "AVR0L");

    cpu_AVRh[1] = tcg_global_mem_new_i64(TCG_AREG0,

                                     offsetof(CPUState, avr1.u64[0]), "AVR1H");

    cpu_AVRl[1] = tcg_global_mem_new_i64(TCG_AREG0,

                                     offsetof(CPUState, avr1.u64[1]), "AVR1L");

    cpu_AVRh[2] = tcg_global_mem_new_i64(TCG_AREG0,

                                     offsetof(CPUState, avr2.u64[0]), "AVR2H");

    cpu_AVRl[2] = tcg_global_mem_new_i64(TCG_AREG0,

                                     offsetof(CPUState, avr2.u64[1]), "AVR2L");

    p = cpu_reg_names;

    for (i = 0; i < 8; i++) {

        sprintf(p, "crf%d", i);

        cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,

                                            offsetof(CPUState, crf[i]), p);

        p += 5;

    }

    for (i = 0; i < 32; i++) {

        sprintf(p, "r%d", i);

        cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,

                                        offsetof(CPUState, gpr[i]), p);

        p += (i < 10) ? 3 : 4;

#if !defined(TARGET_PPC64)

        sprintf(p, "r%dH", i);

        cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,

                                             offsetof(CPUState, gprh[i]), p);

        p += (i < 10) ? 4 : 5;

#endif

        sprintf(p, "fp%d", i);

        cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,

                                            offsetof(CPUState, fpr[i]), p);

        p += (i < 10) ? 4 : 5;

        sprintf(p, "avr%dH", i);

        cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,

                                         offsetof(CPUState, avr[i].u64[0]), p);

        p += (i < 10) ? 6 : 7;

        sprintf(p, "avr%dL", i);

        cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,

                                         offsetof(CPUState, avr[i].u64[1]), p);

        p += (i < 10) ? 6 : 7;

    }

    cpu_nip = tcg_global_mem_new(TCG_AREG0,

                                 offsetof(CPUState, nip), "nip");

    cpu_ctr = tcg_global_mem_new(TCG_AREG0,

                                 offsetof(CPUState, ctr), "ctr");

    cpu_lr = tcg_global_mem_new(TCG_AREG0,

                                offsetof(CPUState, lr), "lr");

    cpu_xer = tcg_global_mem_new(TCG_AREG0,

                                 offsetof(CPUState, xer), "xer");

    cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,

                                       offsetof(CPUState, fpscr), "fpscr");

    /* register helpers */

#define GEN_HELPER 2

#include "helper.h"

    done_init = 1;

}

#if defined(OPTIMIZE_FPRF_UPDATE)

static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];

static uint16_t **gen_fprf_ptr;

#endif

/* internal defines */

typedef struct DisasContext {

    struct TranslationBlock *tb;

    target_ulong nip;

    uint32_t opcode;

    uint32_t exception;

    /* Routine used to access memory */

    int mem_idx;

    /* Translation flags */

#if !defined(CONFIG_USER_ONLY)

    int supervisor;

#endif

#if defined(TARGET_PPC64)

    int sf_mode;

#endif

    int fpu_enabled;

    int altivec_enabled;

    int spe_enabled;

    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */

    int singlestep_enabled;

    int dcache_line_size;

} DisasContext;

struct opc_handler_t {

    /* invalid bits */

    uint32_t inval;

    /* instruction type */

    uint64_t type;

    /* handler */

    void (*handler)(DisasContext *ctx);

#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)

    const char *oname;

#endif

#if defined(DO_PPC_STATISTICS)

    uint64_t count;

#endif

};

static always_inline void gen_reset_fpstatus (void)

{

#ifdef CONFIG_SOFTFLOAT

    gen_op_reset_fpstatus();

#endif

}

static always_inline void gen_compute_fprf (int set_fprf, int set_rc)

{

    if (set_fprf != 0) {

        /* This case might be optimized later */

#if defined(OPTIMIZE_FPRF_UPDATE)

        *gen_fprf_ptr++ = gen_opc_ptr;

#endif

        gen_op_compute_fprf(1);

        if (unlikely(set_rc)) {

            tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_T[0]);

            tcg_gen_andi_i32(cpu_crf[1], cpu_crf[1], 0xf);

        }

        gen_op_float_check_status();

    } else if (unlikely(set_rc)) {

        /* We always need to compute fpcc */

        gen_op_compute_fprf(0);

        tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_T[0]);

        tcg_gen_andi_i32(cpu_crf[1], cpu_crf[1], 0xf);

        if (set_fprf)

            gen_op_float_check_status();

    }

}

static always_inline void gen_optimize_fprf (void)

{

#if defined(OPTIMIZE_FPRF_UPDATE)

    uint16_t **ptr;

    for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)

        *ptr = INDEX_op_nop1;

    gen_fprf_ptr = gen_fprf_buf;

#endif

}

static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)

{

#if defined(TARGET_PPC64)

    if (ctx->sf_mode)

        tcg_gen_movi_tl(cpu_nip, nip);

    else

#endif

        tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);

}

#define GEN_EXCP(ctx, excp, error)                                            \

do {                                                                          \

    if ((ctx)->exception == POWERPC_EXCP_NONE) {                              \

        gen_update_nip(ctx, (ctx)->nip);                                      \

    }                                                                         \

    gen_op_raise_exception_err((excp), (error));                              \

    ctx->exception = (excp);                                                  \

} while (0)

#define GEN_EXCP_INVAL(ctx)                                                   \

GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \

         POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)

#define GEN_EXCP_PRIVOPC(ctx)                                                 \

GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \

         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)

#define GEN_EXCP_PRIVREG(ctx)                                                 \

GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \

         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)

#define GEN_EXCP_NO_FP(ctx)                                                   \

GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)

#define GEN_EXCP_NO_AP(ctx)                                                   \

GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)

#define GEN_EXCP_NO_VR(ctx)                                                   \

GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)

/* Stop translation */

static always_inline void GEN_STOP (DisasContext *ctx)

{

    gen_update_nip(ctx, ctx->nip);

    ctx->exception = POWERPC_EXCP_STOP;

}

/* No need to update nip here, as execution flow will change */

static always_inline void GEN_SYNC (DisasContext *ctx)

{

    ctx->exception = POWERPC_EXCP_SYNC;

}

#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \

static void gen_##name (DisasContext *ctx);                                   \

GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \

static void gen_##name (DisasContext *ctx)

#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \

static void gen_##name (DisasContext *ctx);                                   \

GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type);                       \

static void gen_##name (DisasContext *ctx)

typedef struct opcode_t {

    unsigned char opc1, opc2, opc3;

#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */

    unsigned char pad[5];

#else

    unsigned char pad[1];

#endif

    opc_handler_t handler;

    const char *oname;

} opcode_t;

/*****************************************************************************/

/***                           Instruction decoding                        ***/

#define EXTRACT_HELPER(name, shift, nb)                                       \

static always_inline uint32_t name (uint32_t opcode)                          \

{                                                                             \

    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \

}

#define EXTRACT_SHELPER(name, shift, nb)                                      \

static always_inline int32_t name (uint32_t opcode)                           \

{                                                                             \

    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \

}

/* Opcode part 1 */

EXTRACT_HELPER(opc1, 26, 6);

/* Opcode part 2 */

EXTRACT_HELPER(opc2, 1, 5);

/* Opcode part 3 */

EXTRACT_HELPER(opc3, 6, 5);

/* Update Cr0 flags */

EXTRACT_HELPER(Rc, 0, 1);

/* Destination */

EXTRACT_HELPER(rD, 21, 5);

/* Source */

EXTRACT_HELPER(rS, 21, 5);

/* First operand */

EXTRACT_HELPER(rA, 16, 5);

/* Second operand */

EXTRACT_HELPER(rB, 11, 5);

/* Third operand */

EXTRACT_HELPER(rC, 6, 5);

/***                               Get CRn                                 ***/

EXTRACT_HELPER(crfD, 23, 3);

EXTRACT_HELPER(crfS, 18, 3);

EXTRACT_HELPER(crbD, 21, 5);

EXTRACT_HELPER(crbA, 16, 5);

EXTRACT_HELPER(crbB, 11, 5);

/* SPR / TBL */

EXTRACT_HELPER(_SPR, 11, 10);

static always_inline uint32_t SPR (uint32_t opcode)

{

    uint32_t sprn = _SPR(opcode);

    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);

}

/***                              Get constants                            ***/

EXTRACT_HELPER(IMM, 12, 8);

/* 16 bits signed immediate value */

EXTRACT_SHELPER(SIMM, 0, 16);

/* 16 bits unsigned immediate value */

EXTRACT_HELPER(UIMM, 0, 16);

/* Bit count */

EXTRACT_HELPER(NB, 11, 5);

/* Shift count */

EXTRACT_HELPER(SH, 11, 5);

/* Mask start */

EXTRACT_HELPER(MB, 6, 5);

/* Mask end */

EXTRACT_HELPER(ME, 1, 5);

/* Trap operand */

EXTRACT_HELPER(TO, 21, 5);

EXTRACT_HELPER(CRM, 12, 8);

EXTRACT_HELPER(FM, 17, 8);

EXTRACT_HELPER(SR, 16, 4);

EXTRACT_HELPER(FPIMM, 12, 4);

/***                            Jump target decoding                       ***/

/* Displacement */

EXTRACT_SHELPER(d, 0, 16);

/* Immediate address */

static always_inline target_ulong LI (uint32_t opcode)

{

    return (opcode >> 0) & 0x03FFFFFC;

}

static always_inline uint32_t BD (uint32_t opcode)

{

    return (opcode >> 0) & 0xFFFC;

}

EXTRACT_HELPER(BO, 21, 5);

EXTRACT_HELPER(BI, 16, 5);

/* Absolute/relative address */

EXTRACT_HELPER(AA, 1, 1);

/* Link */

EXTRACT_HELPER(LK, 0, 1);

/* Create a mask between <start> and <end> bits */

static always_inline target_ulong MASK (uint32_t start, uint32_t end)

{

    target_ulong ret;

#if defined(TARGET_PPC64)

    if (likely(start == 0)) {

        ret = UINT64_MAX << (63 - end);

    } else if (likely(end == 63)) {

        ret = UINT64_MAX >> start;

    }

#else

    if (likely(start == 0)) {

        ret = UINT32_MAX << (31  - end);

    } else if (likely(end == 31)) {

        ret = UINT32_MAX >> start;

    }

#endif

    else {

        ret = (((target_ulong)(-1ULL)) >> (start)) ^

            (((target_ulong)(-1ULL) >> (end)) >> 1);

        if (unlikely(start > end))

            return ~ret;

    }

    return ret;

}

/*****************************************************************************/

/* PowerPC Instructions types definitions                                    */

enum {

    PPC_NONE           = 0x0000000000000000ULL,

    /* PowerPC base instructions set                                         */

    PPC_INSNS_BASE     = 0x0000000000000001ULL,

    /*   integer operations instructions                                     */

#define PPC_INTEGER PPC_INSNS_BASE

    /*   flow control instructions                                           */

#define PPC_FLOW    PPC_INSNS_BASE

    /*   virtual memory instructions                                         */

#define PPC_MEM     PPC_INSNS_BASE

    /*   ld/st with reservation instructions                                 */

#define PPC_RES     PPC_INSNS_BASE

    /*   spr/msr access instructions                                         */

#define PPC_MISC    PPC_INSNS_BASE

    /* Deprecated instruction sets                                           */

    /*   Original POWER instruction set                                      */

    PPC_POWER          = 0x0000000000000002ULL,

    /*   POWER2 instruction set extension                                    */

    PPC_POWER2         = 0x0000000000000004ULL,

    /*   Power RTC support                                                   */

    PPC_POWER_RTC      = 0x0000000000000008ULL,

    /*   Power-to-PowerPC bridge (601)                                       */

    PPC_POWER_BR       = 0x0000000000000010ULL,

    /* 64 bits PowerPC instruction set                                       */

    PPC_64B            = 0x0000000000000020ULL,

    /*   New 64 bits extensions (PowerPC 2.0x)                               */

    PPC_64BX           = 0x0000000000000040ULL,

    /*   64 bits hypervisor extensions                                       */

    PPC_64H            = 0x0000000000000080ULL,

    /*   New wait instruction (PowerPC 2.0x)                                 */

    PPC_WAIT           = 0x0000000000000100ULL,

    /*   Time base mftb instruction                                          */

    PPC_MFTB           = 0x0000000000000200ULL,

    /* Fixed-point unit extensions                                           */

    /*   PowerPC 602 specific                                                */

    PPC_602_SPEC       = 0x0000000000000400ULL,

    /*   isel instruction                                                    */

    PPC_ISEL           = 0x0000000000000800ULL,

    /*   popcntb instruction                                                 */

    PPC_POPCNTB        = 0x0000000000001000ULL,

    /*   string load / store                                                 */

    PPC_STRING         = 0x0000000000002000ULL,

    /* Floating-point unit extensions                                        */

    /*   Optional floating point instructions                                */

    PPC_FLOAT          = 0x0000000000010000ULL,

    /* New floating-point extensions (PowerPC 2.0x)                          */

    PPC_FLOAT_EXT      = 0x0000000000020000ULL,

    PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,

    PPC_FLOAT_FRES     = 0x0000000000080000ULL,

    PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,

    PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,

    PPC_FLOAT_FSEL     = 0x0000000000400000ULL,

    PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,

    /* Vector/SIMD extensions                                                */

    /*   Altivec support                                                     */

    PPC_ALTIVEC        = 0x0000000001000000ULL,

    /*   PowerPC 2.03 SPE extension                                          */

    PPC_SPE            = 0x0000000002000000ULL,

    /*   PowerPC 2.03 SPE floating-point extension                           */

    PPC_SPEFPU         = 0x0000000004000000ULL,

    /* Optional memory control instructions                                  */

    PPC_MEM_TLBIA      = 0x0000000010000000ULL,

    PPC_MEM_TLBIE      = 0x0000000020000000ULL,

    PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,

    /*   sync instruction                                                    */

    PPC_MEM_SYNC       = 0x0000000080000000ULL,

    /*   eieio instruction                                                   */

    PPC_MEM_EIEIO      = 0x0000000100000000ULL,

    /* Cache control instructions                                            */

    PPC_CACHE          = 0x0000000200000000ULL,

    /*   icbi instruction                                                    */

    PPC_CACHE_ICBI     = 0x0000000400000000ULL,

    /*   dcbz instruction with fixed cache line size                         */

    PPC_CACHE_DCBZ     = 0x0000000800000000ULL,

    /*   dcbz instruction with tunable cache line size                       */

    PPC_CACHE_DCBZT    = 0x0000001000000000ULL,

    /*   dcba instruction                                                    */

    PPC_CACHE_DCBA     = 0x0000002000000000ULL,

    /*   Freescale cache locking instructions                                */

    PPC_CACHE_LOCK     = 0x0000004000000000ULL,

    /* MMU related extensions                                                */

    /*   external control instructions                                       */

    PPC_EXTERN         = 0x0000010000000000ULL,

    /*   segment register access instructions                                */

    PPC_SEGMENT        = 0x0000020000000000ULL,

    /*   PowerPC 6xx TLB management instructions                             */

    PPC_6xx_TLB        = 0x0000040000000000ULL,

    /* PowerPC 74xx TLB management instructions                              */

    PPC_74xx_TLB       = 0x0000080000000000ULL,

    /*   PowerPC 40x TLB management instructions                             */

    PPC_40x_TLB        = 0x0000100000000000ULL,

    /*   segment register access instructions for PowerPC 64 "bridge"        */

    PPC_SEGMENT_64B    = 0x0000200000000000ULL,

    /*   SLB management                                                      */

    PPC_SLBI           = 0x0000400000000000ULL,

    /* Embedded PowerPC dedicated instructions                               */

    PPC_WRTEE          = 0x0001000000000000ULL,

    /* PowerPC 40x exception model                                           */

    PPC_40x_EXCP       = 0x0002000000000000ULL,

    /* PowerPC 405 Mac instructions                                          */

    PPC_405_MAC        = 0x0004000000000000ULL,

    /* PowerPC 440 specific instructions                                     */

    PPC_440_SPEC       = 0x0008000000000000ULL,

    /* BookE (embedded) PowerPC specification                                */

    PPC_BOOKE          = 0x0010000000000000ULL,

    /* mfapidi instruction                                                   */

    PPC_MFAPIDI        = 0x0020000000000000ULL,

    /* tlbiva instruction                                                    */

    PPC_TLBIVA         = 0x0040000000000000ULL,

    /* tlbivax instruction                                                   */

    PPC_TLBIVAX        = 0x0080000000000000ULL,

    /* PowerPC 4xx dedicated instructions                                    */

    PPC_4xx_COMMON     = 0x0100000000000000ULL,

    /* PowerPC 40x ibct instructions                                         */

    PPC_40x_ICBT       = 0x0200000000000000ULL,

    /* rfmci is not implemented in all BookE PowerPC                         */

    PPC_RFMCI          = 0x0400000000000000ULL,

    /* rfdi instruction                                                      */

    PPC_RFDI           = 0x0800000000000000ULL,

    /* DCR accesses                                                          */

    PPC_DCR            = 0x1000000000000000ULL,

    /* DCR extended accesse                                                  */

    PPC_DCRX           = 0x2000000000000000ULL,

    /* user-mode DCR access, implemented in PowerPC 460                      */

    PPC_DCRUX          = 0x4000000000000000ULL,

};

/*****************************************************************************/

/* PowerPC instructions table                                                */

#if HOST_LONG_BITS == 64

#define OPC_ALIGN 8

#else

#define OPC_ALIGN 4

#endif

#if defined(__APPLE__)

#define OPCODES_SECTION                                                       \

    __attribute__ ((section("__TEXT,__opcodes"), unused, aligned (OPC_ALIGN) ))

#else

#define OPCODES_SECTION                                                       \

    __attribute__ ((section(".opcodes"), unused, aligned (OPC_ALIGN) ))

#endif

#if defined(DO_PPC_STATISTICS)

#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \

OPCODES_SECTION opcode_t opc_##name = {                                       \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval   = invl,                                                      \

        .type = _typ,                                                         \

        .handler = &gen_##name,                                               \

        .oname = stringify(name),                                             \

    },                                                                        \

    .oname = stringify(name),                                                 \

}

#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \

OPCODES_SECTION opcode_t opc_##name = {                                       \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval   = invl,                                                      \

        .type = _typ,                                                         \

        .handler = &gen_##name,                                               \

        .oname = onam,                                                        \

    },                                                                        \

    .oname = onam,                                                            \

}

#else

#define GEN_OPCODE(name, op1, op2, op3, invl, _typ)                           \

OPCODES_SECTION opcode_t opc_##name = {                                       \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval   = invl,                                                      \

        .type = _typ,                                                         \

        .handler = &gen_##name,                                               \

    },                                                                        \

    .oname = stringify(name),                                                 \

}

#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ)                    \

OPCODES_SECTION opcode_t opc_##name = {                                       \

    .opc1 = op1,                                                              \

    .opc2 = op2,                                                              \

    .opc3 = op3,                                                              \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval   = invl,                                                      \

        .type = _typ,                                                         \

        .handler = &gen_##name,                                               \

    },                                                                        \

    .oname = onam,                                                            \

}

#endif

#define GEN_OPCODE_MARK(name)                                                 \

OPCODES_SECTION opcode_t opc_##name = {                                       \

    .opc1 = 0xFF,                                                             \

    .opc2 = 0xFF,                                                             \

    .opc3 = 0xFF,                                                             \

    .pad  = { 0, },                                                           \

    .handler = {                                                              \

        .inval   = 0x00000000,                                                \

        .type = 0x00,                                                         \

        .handler = NULL,                                                      \

    },                                                                        \

    .oname = stringify(name),                                                 \

}

/* Start opcode list */

GEN_OPCODE_MARK(start);

/* Invalid instruction */

GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)

{

    GEN_EXCP_INVAL(ctx);

}

static opc_handler_t invalid_handler = {

    .inval   = 0xFFFFFFFF,

    .type    = PPC_NONE,

    .handler = gen_invalid,

};

/***                           Integer comparison                          ***/

static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)

{

    int l1, l2, l3;

    tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_xer);

    tcg_gen_shri_i32(cpu_crf[crf], cpu_crf[crf], XER_SO);

    tcg_gen_andi_i32(cpu_crf[crf], cpu_crf[crf], 1);

    l1 = gen_new_label();

    l2 = gen_new_label();

    l3 = gen_new_label();

    if (s) {

        tcg_gen_brcond_tl(TCG_COND_LT, arg0, arg1, l1);

        tcg_gen_brcond_tl(TCG_COND_GT, arg0, arg1, l2);

    } else {

        tcg_gen_brcond_tl(TCG_COND_LTU, arg0, arg1, l1);

        tcg_gen_brcond_tl(TCG_COND_GTU, arg0, arg1, l2);

    }

    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_EQ);

    tcg_gen_br(l3);

    gen_set_label(l1);

    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_LT);

    tcg_gen_br(l3);

    gen_set_label(l2);

    tcg_gen_ori_i32(cpu_crf[crf], cpu_crf[crf], 1 << CRF_GT);

    gen_set_label(l3);

}

static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)

{

    TCGv t0 = tcg_const_local_tl(arg1);

    gen_op_cmp(arg0, t0, s, crf);

    tcg_temp_free(t0);

}

#if defined(TARGET_PPC64)

static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)

{

    TCGv t0, t1;

    t0 = tcg_temp_local_new();

    t1 = tcg_temp_local_new();

    if (s) {

        tcg_gen_ext32s_tl(t0, arg0);

        tcg_gen_ext32s_tl(t1, arg1);

    } else {

        tcg_gen_ext32u_tl(t0, arg0);

        tcg_gen_ext32u_tl(t1, arg1);

    }

    gen_op_cmp(t0, t1, s, crf);

    tcg_temp_free(t1);

    tcg_temp_free(t0);

}

static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)

{

    TCGv t0 = tcg_const_local_tl(arg1);

    gen_op_cmp32(arg0, t0, s, crf);

    tcg_temp_free(t0);

}

#endif

static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)

{

#if defined(TARGET_PPC64)

    if (!(ctx->sf_mode))

        gen_op_cmpi32(reg, 0, 1, 0);

    else

#endif

        gen_op_cmpi(reg, 0, 1, 0);

}

/* cmp */

GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER)

{

#if defined(TARGET_PPC64)

    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))

        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

                     1, crfD(ctx->opcode));

    else

#endif

        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

                   1, crfD(ctx->opcode));

}

/* cmpi */

GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)

{

#if defined(TARGET_PPC64)

    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))

        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),

                      1, crfD(ctx->opcode));

    else

#endif

        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),

                    1, crfD(ctx->opcode));

}

/* cmpl */

GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER)

{

#if defined(TARGET_PPC64)

    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))

        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

                     0, crfD(ctx->opcode));

    else

#endif

        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],

                   0, crfD(ctx->opcode));

}

/* cmpli */

GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)

{

#if defined(TARGET_PPC64)

    if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))

        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),

                      0, crfD(ctx->opcode));

    else

#endif

        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),

                    0, crfD(ctx->opcode));

}

/* isel (PowerPC 2.03 specification) */

GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)

{

    int l1, l2;

    uint32_t bi = rC(ctx->opcode);

    uint32_t mask;

    TCGv_i32 t0;

    l1 = gen_new_label();

    l2 = gen_new_label();

    mask = 1 << (3 - (bi & 0x03));

    t0 = tcg_temp_new_i32();

    tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);

    tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);

    if (rA(ctx->opcode) == 0)

        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);

    else

        tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);

    tcg_gen_br(l2);

    gen_set_label(l1);

    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);

    gen_set_label(l2);

    tcg_temp_free_i32(t0);

}

/***                           Integer arithmetic                          ***/

static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)

{

    int l1;

    TCGv t0;

    l1 = gen_new_label();

    /* Start with XER OV disabled, the most likely case */

    tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));

    t0 = tcg_temp_local_new();

    tcg_gen_xor_tl(t0, arg0, arg1);

#if defined(TARGET_PPC64)

    if (!ctx->sf_mode)

        tcg_gen_ext32s_tl(t0, t0);

#endif

    if (sub)