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1 | 0824d6fc | bellard | /*
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2 | 1df912cf | bellard | * QEMU PC System Emulator
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3 | 0824d6fc | bellard | *
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4 | 1df912cf | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 0824d6fc | bellard | *
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6 | 1df912cf | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 1df912cf | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 1df912cf | bellard | * in the Software without restriction, including without limitation the rights
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9 | 1df912cf | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 1df912cf | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 1df912cf | bellard | * furnished to do so, subject to the following conditions:
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12 | 1df912cf | bellard | *
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13 | 1df912cf | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 1df912cf | bellard | * all copies or substantial portions of the Software.
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15 | 1df912cf | bellard | *
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16 | 1df912cf | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 1df912cf | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 1df912cf | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 1df912cf | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 1df912cf | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 1df912cf | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 1df912cf | bellard | * THE SOFTWARE.
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23 | 0824d6fc | bellard | */
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24 | 0824d6fc | bellard | #include <stdlib.h> |
25 | 0824d6fc | bellard | #include <stdio.h> |
26 | 1df912cf | bellard | #include <stdarg.h> |
27 | 0824d6fc | bellard | #include <string.h> |
28 | 0824d6fc | bellard | #include <getopt.h> |
29 | 0824d6fc | bellard | #include <inttypes.h> |
30 | 0824d6fc | bellard | #include <unistd.h> |
31 | 0824d6fc | bellard | #include <sys/mman.h> |
32 | 0824d6fc | bellard | #include <fcntl.h> |
33 | 0824d6fc | bellard | #include <signal.h> |
34 | 0824d6fc | bellard | #include <time.h> |
35 | 0824d6fc | bellard | #include <sys/time.h> |
36 | 0824d6fc | bellard | #include <malloc.h> |
37 | 0824d6fc | bellard | #include <termios.h> |
38 | 0824d6fc | bellard | #include <sys/poll.h> |
39 | 0824d6fc | bellard | #include <errno.h> |
40 | f1510b2c | bellard | #include <sys/wait.h> |
41 | f1510b2c | bellard | |
42 | f1510b2c | bellard | #include <sys/ioctl.h> |
43 | f1510b2c | bellard | #include <sys/socket.h> |
44 | f1510b2c | bellard | #include <linux/if.h> |
45 | f1510b2c | bellard | #include <linux/if_tun.h> |
46 | 0824d6fc | bellard | |
47 | 0824d6fc | bellard | #include "cpu-i386.h" |
48 | 0824d6fc | bellard | #include "disas.h" |
49 | fc01f7e7 | bellard | #include "thunk.h" |
50 | fc01f7e7 | bellard | |
51 | fc01f7e7 | bellard | #include "vl.h" |
52 | 0824d6fc | bellard | |
53 | 0824d6fc | bellard | #define DEBUG_LOGFILE "/tmp/vl.log" |
54 | f1510b2c | bellard | #define DEFAULT_NETWORK_SCRIPT "/etc/vl-ifup" |
55 | f1510b2c | bellard | |
56 | 0824d6fc | bellard | //#define DEBUG_UNUSED_IOPORT
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57 | c9159e53 | bellard | //#define DEBUG_IRQ_LATENCY
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58 | 0824d6fc | bellard | |
59 | 7916e224 | bellard | #define PHYS_RAM_BASE 0xac000000 |
60 | 7916e224 | bellard | #define PHYS_RAM_MAX_SIZE (256 * 1024 * 1024) |
61 | 7916e224 | bellard | |
62 | 0824d6fc | bellard | #define KERNEL_LOAD_ADDR 0x00100000 |
63 | 0824d6fc | bellard | #define INITRD_LOAD_ADDR 0x00400000 |
64 | 0824d6fc | bellard | #define KERNEL_PARAMS_ADDR 0x00090000 |
65 | 0824d6fc | bellard | |
66 | 33e3963e | bellard | #define MAX_DISKS 2 |
67 | 33e3963e | bellard | |
68 | 0824d6fc | bellard | /* from plex86 (BSD license) */
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69 | 0824d6fc | bellard | struct __attribute__ ((packed)) linux_params {
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70 | 0824d6fc | bellard | // For 0x00..0x3f, see 'struct screen_info' in linux/include/linux/tty.h.
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71 | 0824d6fc | bellard | // I just padded out the VESA parts, rather than define them.
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72 | 0824d6fc | bellard | |
73 | 0824d6fc | bellard | /* 0x000 */ uint8_t orig_x;
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74 | 0824d6fc | bellard | /* 0x001 */ uint8_t orig_y;
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75 | 0824d6fc | bellard | /* 0x002 */ uint16_t ext_mem_k;
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76 | 0824d6fc | bellard | /* 0x004 */ uint16_t orig_video_page;
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77 | 0824d6fc | bellard | /* 0x006 */ uint8_t orig_video_mode;
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78 | 0824d6fc | bellard | /* 0x007 */ uint8_t orig_video_cols;
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79 | 0824d6fc | bellard | /* 0x008 */ uint16_t unused1;
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80 | 0824d6fc | bellard | /* 0x00a */ uint16_t orig_video_ega_bx;
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81 | 0824d6fc | bellard | /* 0x00c */ uint16_t unused2;
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82 | 0824d6fc | bellard | /* 0x00e */ uint8_t orig_video_lines;
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83 | 0824d6fc | bellard | /* 0x00f */ uint8_t orig_video_isVGA;
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84 | 0824d6fc | bellard | /* 0x010 */ uint16_t orig_video_points;
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85 | 0824d6fc | bellard | /* 0x012 */ uint8_t pad0[0x20 - 0x12]; // VESA info. |
86 | 0824d6fc | bellard | /* 0x020 */ uint16_t cl_magic; // Commandline magic number (0xA33F) |
87 | 0824d6fc | bellard | /* 0x022 */ uint16_t cl_offset; // Commandline offset. Address of commandline |
88 | 0824d6fc | bellard | // is calculated as 0x90000 + cl_offset, bu
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89 | 0824d6fc | bellard | // only if cl_magic == 0xA33F.
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90 | 0824d6fc | bellard | /* 0x024 */ uint8_t pad1[0x40 - 0x24]; // VESA info. |
91 | 0824d6fc | bellard | |
92 | 0824d6fc | bellard | /* 0x040 */ uint8_t apm_bios_info[20]; // struct apm_bios_info |
93 | 0824d6fc | bellard | /* 0x054 */ uint8_t pad2[0x80 - 0x54]; |
94 | 0824d6fc | bellard | |
95 | 0824d6fc | bellard | // Following 2 from 'struct drive_info_struct' in drivers/block/cciss.h.
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96 | 0824d6fc | bellard | // Might be truncated?
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97 | 0824d6fc | bellard | /* 0x080 */ uint8_t hd0_info[16]; // hd0-disk-parameter from intvector 0x41 |
98 | 0824d6fc | bellard | /* 0x090 */ uint8_t hd1_info[16]; // hd1-disk-parameter from intvector 0x46 |
99 | 0824d6fc | bellard | |
100 | 0824d6fc | bellard | // System description table truncated to 16 bytes
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101 | 0824d6fc | bellard | // From 'struct sys_desc_table_struct' in linux/arch/i386/kernel/setup.c.
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102 | 0824d6fc | bellard | /* 0x0a0 */ uint16_t sys_description_len;
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103 | 0824d6fc | bellard | /* 0x0a2 */ uint8_t sys_description_table[14]; |
104 | 0824d6fc | bellard | // [0] machine id
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105 | 0824d6fc | bellard | // [1] machine submodel id
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106 | 0824d6fc | bellard | // [2] BIOS revision
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107 | 0824d6fc | bellard | // [3] bit1: MCA bus
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108 | 0824d6fc | bellard | |
109 | 0824d6fc | bellard | /* 0x0b0 */ uint8_t pad3[0x1e0 - 0xb0]; |
110 | 0824d6fc | bellard | /* 0x1e0 */ uint32_t alt_mem_k;
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111 | 0824d6fc | bellard | /* 0x1e4 */ uint8_t pad4[4]; |
112 | 0824d6fc | bellard | /* 0x1e8 */ uint8_t e820map_entries;
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113 | 0824d6fc | bellard | /* 0x1e9 */ uint8_t eddbuf_entries; // EDD_NR |
114 | 0824d6fc | bellard | /* 0x1ea */ uint8_t pad5[0x1f1 - 0x1ea]; |
115 | 0824d6fc | bellard | /* 0x1f1 */ uint8_t setup_sects; // size of setup.S, number of sectors |
116 | 0824d6fc | bellard | /* 0x1f2 */ uint16_t mount_root_rdonly; // MOUNT_ROOT_RDONLY (if !=0) |
117 | 0824d6fc | bellard | /* 0x1f4 */ uint16_t sys_size; // size of compressed kernel-part in the |
118 | 0824d6fc | bellard | // (b)zImage-file (in 16 byte units, rounded up)
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119 | 0824d6fc | bellard | /* 0x1f6 */ uint16_t swap_dev; // (unused AFAIK) |
120 | 0824d6fc | bellard | /* 0x1f8 */ uint16_t ramdisk_flags;
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121 | 0824d6fc | bellard | /* 0x1fa */ uint16_t vga_mode; // (old one) |
122 | 0824d6fc | bellard | /* 0x1fc */ uint16_t orig_root_dev; // (high=Major, low=minor) |
123 | 0824d6fc | bellard | /* 0x1fe */ uint8_t pad6[1]; |
124 | 0824d6fc | bellard | /* 0x1ff */ uint8_t aux_device_info;
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125 | 0824d6fc | bellard | /* 0x200 */ uint16_t jump_setup; // Jump to start of setup code, |
126 | 0824d6fc | bellard | // aka "reserved" field.
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127 | 0824d6fc | bellard | /* 0x202 */ uint8_t setup_signature[4]; // Signature for SETUP-header, ="HdrS" |
128 | 0824d6fc | bellard | /* 0x206 */ uint16_t header_format_version; // Version number of header format; |
129 | 0824d6fc | bellard | /* 0x208 */ uint8_t setup_S_temp0[8]; // Used by setup.S for communication with |
130 | 0824d6fc | bellard | // boot loaders, look there.
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131 | 0824d6fc | bellard | /* 0x210 */ uint8_t loader_type;
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132 | 0824d6fc | bellard | // 0 for old one.
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133 | 0824d6fc | bellard | // else 0xTV:
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134 | 0824d6fc | bellard | // T=0: LILO
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135 | 0824d6fc | bellard | // T=1: Loadlin
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136 | 0824d6fc | bellard | // T=2: bootsect-loader
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137 | 0824d6fc | bellard | // T=3: SYSLINUX
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138 | 0824d6fc | bellard | // T=4: ETHERBOOT
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139 | 0824d6fc | bellard | // V=version
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140 | 0824d6fc | bellard | /* 0x211 */ uint8_t loadflags;
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141 | 0824d6fc | bellard | // bit0 = 1: kernel is loaded high (bzImage)
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142 | 0824d6fc | bellard | // bit7 = 1: Heap and pointer (see below) set by boot
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143 | 0824d6fc | bellard | // loader.
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144 | 0824d6fc | bellard | /* 0x212 */ uint16_t setup_S_temp1;
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145 | 0824d6fc | bellard | /* 0x214 */ uint32_t kernel_start;
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146 | 0824d6fc | bellard | /* 0x218 */ uint32_t initrd_start;
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147 | 0824d6fc | bellard | /* 0x21c */ uint32_t initrd_size;
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148 | 0824d6fc | bellard | /* 0x220 */ uint8_t setup_S_temp2[4]; |
149 | 0824d6fc | bellard | /* 0x224 */ uint16_t setup_S_heap_end_pointer;
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150 | 0824d6fc | bellard | /* 0x226 */ uint8_t pad7[0x2d0 - 0x226]; |
151 | 0824d6fc | bellard | |
152 | 0824d6fc | bellard | /* 0x2d0 : Int 15, ax=e820 memory map. */
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153 | 0824d6fc | bellard | // (linux/include/asm-i386/e820.h, 'struct e820entry')
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154 | 0824d6fc | bellard | #define E820MAX 32 |
155 | 0824d6fc | bellard | #define E820_RAM 1 |
156 | 0824d6fc | bellard | #define E820_RESERVED 2 |
157 | 0824d6fc | bellard | #define E820_ACPI 3 /* usable as RAM once ACPI tables have been read */ |
158 | 0824d6fc | bellard | #define E820_NVS 4 |
159 | 0824d6fc | bellard | struct {
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160 | 0824d6fc | bellard | uint64_t addr; |
161 | 0824d6fc | bellard | uint64_t size; |
162 | 0824d6fc | bellard | uint32_t type; |
163 | 0824d6fc | bellard | } e820map[E820MAX]; |
164 | 0824d6fc | bellard | |
165 | 0824d6fc | bellard | /* 0x550 */ uint8_t pad8[0x600 - 0x550]; |
166 | 0824d6fc | bellard | |
167 | 0824d6fc | bellard | // BIOS Enhanced Disk Drive Services.
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168 | 0824d6fc | bellard | // (From linux/include/asm-i386/edd.h, 'struct edd_info')
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169 | 0824d6fc | bellard | // Each 'struct edd_info is 78 bytes, times a max of 6 structs in array.
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170 | 0824d6fc | bellard | /* 0x600 */ uint8_t eddbuf[0x7d4 - 0x600]; |
171 | 0824d6fc | bellard | |
172 | 0824d6fc | bellard | /* 0x7d4 */ uint8_t pad9[0x800 - 0x7d4]; |
173 | 0824d6fc | bellard | /* 0x800 */ uint8_t commandline[0x800]; |
174 | 0824d6fc | bellard | |
175 | 0824d6fc | bellard | /* 0x1000 */
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176 | 0824d6fc | bellard | uint64_t gdt_table[256];
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177 | 0824d6fc | bellard | uint64_t idt_table[48];
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178 | 0824d6fc | bellard | }; |
179 | 0824d6fc | bellard | |
180 | 0824d6fc | bellard | #define KERNEL_CS 0x10 |
181 | 0824d6fc | bellard | #define KERNEL_DS 0x18 |
182 | 0824d6fc | bellard | |
183 | 0824d6fc | bellard | typedef void (IOPortWriteFunc)(CPUX86State *env, uint32_t address, uint32_t data); |
184 | 0824d6fc | bellard | typedef uint32_t (IOPortReadFunc)(CPUX86State *env, uint32_t address);
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185 | 0824d6fc | bellard | |
186 | fc01f7e7 | bellard | #define MAX_IOPORTS 4096 |
187 | 0824d6fc | bellard | |
188 | 0824d6fc | bellard | char phys_ram_file[1024]; |
189 | 0824d6fc | bellard | CPUX86State *global_env; |
190 | 1df912cf | bellard | CPUX86State *cpu_single_env; |
191 | 0824d6fc | bellard | FILE *logfile = NULL;
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192 | 0824d6fc | bellard | int loglevel;
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193 | fc01f7e7 | bellard | IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
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194 | fc01f7e7 | bellard | IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
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195 | 33e3963e | bellard | BlockDriverState *bs_table[MAX_DISKS]; |
196 | 0824d6fc | bellard | |
197 | 0824d6fc | bellard | /***********************************************************/
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198 | 0824d6fc | bellard | /* x86 io ports */
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199 | 0824d6fc | bellard | |
200 | 0824d6fc | bellard | uint32_t default_ioport_readb(CPUX86State *env, uint32_t address) |
201 | 0824d6fc | bellard | { |
202 | 0824d6fc | bellard | #ifdef DEBUG_UNUSED_IOPORT
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203 | 0824d6fc | bellard | fprintf(stderr, "inb: port=0x%04x\n", address);
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204 | 0824d6fc | bellard | #endif
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205 | fc01f7e7 | bellard | return 0xff; |
206 | 0824d6fc | bellard | } |
207 | 0824d6fc | bellard | |
208 | 0824d6fc | bellard | void default_ioport_writeb(CPUX86State *env, uint32_t address, uint32_t data)
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209 | 0824d6fc | bellard | { |
210 | 0824d6fc | bellard | #ifdef DEBUG_UNUSED_IOPORT
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211 | 0824d6fc | bellard | fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
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212 | 0824d6fc | bellard | #endif
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213 | 0824d6fc | bellard | } |
214 | 0824d6fc | bellard | |
215 | 0824d6fc | bellard | /* default is to make two byte accesses */
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216 | 0824d6fc | bellard | uint32_t default_ioport_readw(CPUX86State *env, uint32_t address) |
217 | 0824d6fc | bellard | { |
218 | 0824d6fc | bellard | uint32_t data; |
219 | fc01f7e7 | bellard | data = ioport_read_table[0][address](env, address);
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220 | fc01f7e7 | bellard | data |= ioport_read_table[0][address + 1](env, address + 1) << 8; |
221 | 0824d6fc | bellard | return data;
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222 | 0824d6fc | bellard | } |
223 | 0824d6fc | bellard | |
224 | 0824d6fc | bellard | void default_ioport_writew(CPUX86State *env, uint32_t address, uint32_t data)
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225 | 0824d6fc | bellard | { |
226 | fc01f7e7 | bellard | ioport_write_table[0][address](env, address, data & 0xff); |
227 | fc01f7e7 | bellard | ioport_write_table[0][address + 1](env, address + 1, (data >> 8) & 0xff); |
228 | 0824d6fc | bellard | } |
229 | 0824d6fc | bellard | |
230 | fc01f7e7 | bellard | uint32_t default_ioport_readl(CPUX86State *env, uint32_t address) |
231 | 0824d6fc | bellard | { |
232 | fc01f7e7 | bellard | #ifdef DEBUG_UNUSED_IOPORT
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233 | fc01f7e7 | bellard | fprintf(stderr, "inl: port=0x%04x\n", address);
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234 | fc01f7e7 | bellard | #endif
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235 | fc01f7e7 | bellard | return 0xffffffff; |
236 | 0824d6fc | bellard | } |
237 | 0824d6fc | bellard | |
238 | fc01f7e7 | bellard | void default_ioport_writel(CPUX86State *env, uint32_t address, uint32_t data)
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239 | 0824d6fc | bellard | { |
240 | fc01f7e7 | bellard | #ifdef DEBUG_UNUSED_IOPORT
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241 | fc01f7e7 | bellard | fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
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242 | fc01f7e7 | bellard | #endif
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243 | 0824d6fc | bellard | } |
244 | 0824d6fc | bellard | |
245 | fc01f7e7 | bellard | void init_ioports(void) |
246 | 0824d6fc | bellard | { |
247 | 0824d6fc | bellard | int i;
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248 | 0824d6fc | bellard | |
249 | fc01f7e7 | bellard | for(i = 0; i < MAX_IOPORTS; i++) { |
250 | fc01f7e7 | bellard | ioport_read_table[0][i] = default_ioport_readb;
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251 | fc01f7e7 | bellard | ioport_write_table[0][i] = default_ioport_writeb;
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252 | fc01f7e7 | bellard | ioport_read_table[1][i] = default_ioport_readw;
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253 | fc01f7e7 | bellard | ioport_write_table[1][i] = default_ioport_writew;
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254 | fc01f7e7 | bellard | ioport_read_table[2][i] = default_ioport_readl;
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255 | fc01f7e7 | bellard | ioport_write_table[2][i] = default_ioport_writel;
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256 | fc01f7e7 | bellard | } |
257 | 0824d6fc | bellard | } |
258 | 0824d6fc | bellard | |
259 | fc01f7e7 | bellard | /* size is the word size in byte */
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260 | fc01f7e7 | bellard | int register_ioport_read(int start, int length, IOPortReadFunc *func, int size) |
261 | f1510b2c | bellard | { |
262 | fc01f7e7 | bellard | int i, bsize;
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263 | f1510b2c | bellard | |
264 | fc01f7e7 | bellard | if (size == 1) |
265 | fc01f7e7 | bellard | bsize = 0;
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266 | fc01f7e7 | bellard | else if (size == 2) |
267 | fc01f7e7 | bellard | bsize = 1;
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268 | fc01f7e7 | bellard | else if (size == 4) |
269 | fc01f7e7 | bellard | bsize = 2;
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270 | fc01f7e7 | bellard | else
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271 | fc01f7e7 | bellard | return -1; |
272 | fc01f7e7 | bellard | for(i = start; i < start + length; i += size)
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273 | fc01f7e7 | bellard | ioport_read_table[bsize][i] = func; |
274 | f1510b2c | bellard | return 0; |
275 | f1510b2c | bellard | } |
276 | f1510b2c | bellard | |
277 | fc01f7e7 | bellard | /* size is the word size in byte */
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278 | fc01f7e7 | bellard | int register_ioport_write(int start, int length, IOPortWriteFunc *func, int size) |
279 | f1510b2c | bellard | { |
280 | fc01f7e7 | bellard | int i, bsize;
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281 | f1510b2c | bellard | |
282 | fc01f7e7 | bellard | if (size == 1) |
283 | fc01f7e7 | bellard | bsize = 0;
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284 | fc01f7e7 | bellard | else if (size == 2) |
285 | fc01f7e7 | bellard | bsize = 1;
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286 | fc01f7e7 | bellard | else if (size == 4) |
287 | fc01f7e7 | bellard | bsize = 2;
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288 | fc01f7e7 | bellard | else
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289 | fc01f7e7 | bellard | return -1; |
290 | fc01f7e7 | bellard | for(i = start; i < start + length; i += size)
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291 | fc01f7e7 | bellard | ioport_write_table[bsize][i] = func; |
292 | f1510b2c | bellard | return 0; |
293 | f1510b2c | bellard | } |
294 | f1510b2c | bellard | |
295 | 0824d6fc | bellard | void pstrcpy(char *buf, int buf_size, const char *str) |
296 | 0824d6fc | bellard | { |
297 | 0824d6fc | bellard | int c;
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298 | 0824d6fc | bellard | char *q = buf;
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299 | 0824d6fc | bellard | |
300 | 0824d6fc | bellard | if (buf_size <= 0) |
301 | 0824d6fc | bellard | return;
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302 | 0824d6fc | bellard | |
303 | 0824d6fc | bellard | for(;;) {
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304 | 0824d6fc | bellard | c = *str++; |
305 | 0824d6fc | bellard | if (c == 0 || q >= buf + buf_size - 1) |
306 | 0824d6fc | bellard | break;
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307 | 0824d6fc | bellard | *q++ = c; |
308 | 0824d6fc | bellard | } |
309 | 0824d6fc | bellard | *q = '\0';
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310 | 0824d6fc | bellard | } |
311 | 0824d6fc | bellard | |
312 | 0824d6fc | bellard | /* strcat and truncate. */
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313 | 0824d6fc | bellard | char *pstrcat(char *buf, int buf_size, const char *s) |
314 | 0824d6fc | bellard | { |
315 | 0824d6fc | bellard | int len;
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316 | 0824d6fc | bellard | len = strlen(buf); |
317 | 0824d6fc | bellard | if (len < buf_size)
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318 | 0824d6fc | bellard | pstrcpy(buf + len, buf_size - len, s); |
319 | 0824d6fc | bellard | return buf;
|
320 | 0824d6fc | bellard | } |
321 | 0824d6fc | bellard | |
322 | 0824d6fc | bellard | int load_kernel(const char *filename, uint8_t *addr) |
323 | 0824d6fc | bellard | { |
324 | 0824d6fc | bellard | int fd, size, setup_sects;
|
325 | 0824d6fc | bellard | uint8_t bootsect[512];
|
326 | 0824d6fc | bellard | |
327 | 0824d6fc | bellard | fd = open(filename, O_RDONLY); |
328 | 0824d6fc | bellard | if (fd < 0) |
329 | 0824d6fc | bellard | return -1; |
330 | 0824d6fc | bellard | if (read(fd, bootsect, 512) != 512) |
331 | 0824d6fc | bellard | goto fail;
|
332 | 0824d6fc | bellard | setup_sects = bootsect[0x1F1];
|
333 | 0824d6fc | bellard | if (!setup_sects)
|
334 | 0824d6fc | bellard | setup_sects = 4;
|
335 | 0824d6fc | bellard | /* skip 16 bit setup code */
|
336 | 0824d6fc | bellard | lseek(fd, (setup_sects + 1) * 512, SEEK_SET); |
337 | 0824d6fc | bellard | size = read(fd, addr, 16 * 1024 * 1024); |
338 | 0824d6fc | bellard | if (size < 0) |
339 | 0824d6fc | bellard | goto fail;
|
340 | 0824d6fc | bellard | close(fd); |
341 | 0824d6fc | bellard | return size;
|
342 | 0824d6fc | bellard | fail:
|
343 | 0824d6fc | bellard | close(fd); |
344 | 0824d6fc | bellard | return -1; |
345 | 0824d6fc | bellard | } |
346 | 0824d6fc | bellard | |
347 | 0824d6fc | bellard | /* return the size or -1 if error */
|
348 | 0824d6fc | bellard | int load_image(const char *filename, uint8_t *addr) |
349 | 0824d6fc | bellard | { |
350 | 0824d6fc | bellard | int fd, size;
|
351 | 0824d6fc | bellard | fd = open(filename, O_RDONLY); |
352 | 0824d6fc | bellard | if (fd < 0) |
353 | 0824d6fc | bellard | return -1; |
354 | 0824d6fc | bellard | size = lseek(fd, 0, SEEK_END);
|
355 | 0824d6fc | bellard | lseek(fd, 0, SEEK_SET);
|
356 | 0824d6fc | bellard | if (read(fd, addr, size) != size) {
|
357 | 0824d6fc | bellard | close(fd); |
358 | 0824d6fc | bellard | return -1; |
359 | 0824d6fc | bellard | } |
360 | 0824d6fc | bellard | close(fd); |
361 | 0824d6fc | bellard | return size;
|
362 | 0824d6fc | bellard | } |
363 | 0824d6fc | bellard | |
364 | 0824d6fc | bellard | void cpu_x86_outb(CPUX86State *env, int addr, int val) |
365 | 0824d6fc | bellard | { |
366 | fc01f7e7 | bellard | ioport_write_table[0][addr & (MAX_IOPORTS - 1)](env, addr, val); |
367 | 0824d6fc | bellard | } |
368 | 0824d6fc | bellard | |
369 | 0824d6fc | bellard | void cpu_x86_outw(CPUX86State *env, int addr, int val) |
370 | 0824d6fc | bellard | { |
371 | fc01f7e7 | bellard | ioport_write_table[1][addr & (MAX_IOPORTS - 1)](env, addr, val); |
372 | 0824d6fc | bellard | } |
373 | 0824d6fc | bellard | |
374 | 0824d6fc | bellard | void cpu_x86_outl(CPUX86State *env, int addr, int val) |
375 | 0824d6fc | bellard | { |
376 | fc01f7e7 | bellard | ioport_write_table[2][addr & (MAX_IOPORTS - 1)](env, addr, val); |
377 | 0824d6fc | bellard | } |
378 | 0824d6fc | bellard | |
379 | 0824d6fc | bellard | int cpu_x86_inb(CPUX86State *env, int addr) |
380 | 0824d6fc | bellard | { |
381 | fc01f7e7 | bellard | return ioport_read_table[0][addr & (MAX_IOPORTS - 1)](env, addr); |
382 | 0824d6fc | bellard | } |
383 | 0824d6fc | bellard | |
384 | 0824d6fc | bellard | int cpu_x86_inw(CPUX86State *env, int addr) |
385 | 0824d6fc | bellard | { |
386 | fc01f7e7 | bellard | return ioport_read_table[1][addr & (MAX_IOPORTS - 1)](env, addr); |
387 | 0824d6fc | bellard | } |
388 | 0824d6fc | bellard | |
389 | 0824d6fc | bellard | int cpu_x86_inl(CPUX86State *env, int addr) |
390 | 0824d6fc | bellard | { |
391 | fc01f7e7 | bellard | return ioport_read_table[2][addr & (MAX_IOPORTS - 1)](env, addr); |
392 | 0824d6fc | bellard | } |
393 | 0824d6fc | bellard | |
394 | 0824d6fc | bellard | /***********************************************************/
|
395 | 0824d6fc | bellard | void ioport80_write(CPUX86State *env, uint32_t addr, uint32_t data)
|
396 | 0824d6fc | bellard | { |
397 | 0824d6fc | bellard | } |
398 | 0824d6fc | bellard | |
399 | 0824d6fc | bellard | void hw_error(const char *fmt, ...) |
400 | 0824d6fc | bellard | { |
401 | 0824d6fc | bellard | va_list ap; |
402 | 0824d6fc | bellard | |
403 | 0824d6fc | bellard | va_start(ap, fmt); |
404 | 0824d6fc | bellard | fprintf(stderr, "qemu: hardware error: ");
|
405 | 0824d6fc | bellard | vfprintf(stderr, fmt, ap); |
406 | 0824d6fc | bellard | fprintf(stderr, "\n");
|
407 | 0824d6fc | bellard | #ifdef TARGET_I386
|
408 | 0824d6fc | bellard | cpu_x86_dump_state(global_env, stderr, X86_DUMP_FPU | X86_DUMP_CCOP); |
409 | 0824d6fc | bellard | #endif
|
410 | 0824d6fc | bellard | va_end(ap); |
411 | 0824d6fc | bellard | abort(); |
412 | 0824d6fc | bellard | } |
413 | 0824d6fc | bellard | |
414 | 0824d6fc | bellard | /***********************************************************/
|
415 | 0824d6fc | bellard | /* vga emulation */
|
416 | 0824d6fc | bellard | static uint8_t vga_index;
|
417 | 0824d6fc | bellard | static uint8_t vga_regs[256]; |
418 | 0824d6fc | bellard | static int last_cursor_pos; |
419 | 0824d6fc | bellard | |
420 | 0824d6fc | bellard | void update_console_messages(void) |
421 | 0824d6fc | bellard | { |
422 | 0824d6fc | bellard | int c, i, cursor_pos, eol;
|
423 | 0824d6fc | bellard | |
424 | 0824d6fc | bellard | cursor_pos = vga_regs[0x0f] | (vga_regs[0x0e] << 8); |
425 | 0824d6fc | bellard | eol = 0;
|
426 | 0824d6fc | bellard | for(i = last_cursor_pos; i < cursor_pos; i++) {
|
427 | 0824d6fc | bellard | c = phys_ram_base[0xb8000 + (i) * 2]; |
428 | 0824d6fc | bellard | if (c >= ' ') { |
429 | 0824d6fc | bellard | putchar(c); |
430 | 0824d6fc | bellard | eol = 0;
|
431 | 0824d6fc | bellard | } else {
|
432 | 0824d6fc | bellard | if (!eol)
|
433 | 0824d6fc | bellard | putchar('\n');
|
434 | 0824d6fc | bellard | eol = 1;
|
435 | 0824d6fc | bellard | } |
436 | 0824d6fc | bellard | } |
437 | 0824d6fc | bellard | fflush(stdout); |
438 | 0824d6fc | bellard | last_cursor_pos = cursor_pos; |
439 | 0824d6fc | bellard | } |
440 | 0824d6fc | bellard | |
441 | 0824d6fc | bellard | /* just to see first Linux console messages, we intercept cursor position */
|
442 | 0824d6fc | bellard | void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
|
443 | 0824d6fc | bellard | { |
444 | 0824d6fc | bellard | switch(addr) {
|
445 | 0824d6fc | bellard | case 0x3d4: |
446 | 0824d6fc | bellard | vga_index = data; |
447 | 0824d6fc | bellard | break;
|
448 | 0824d6fc | bellard | case 0x3d5: |
449 | 0824d6fc | bellard | vga_regs[vga_index] = data; |
450 | 0824d6fc | bellard | if (vga_index == 0x0f) |
451 | 0824d6fc | bellard | update_console_messages(); |
452 | 0824d6fc | bellard | break;
|
453 | 0824d6fc | bellard | } |
454 | 0824d6fc | bellard | |
455 | 0824d6fc | bellard | } |
456 | 0824d6fc | bellard | |
457 | 0824d6fc | bellard | /***********************************************************/
|
458 | 0824d6fc | bellard | /* cmos emulation */
|
459 | 0824d6fc | bellard | |
460 | 0824d6fc | bellard | #define RTC_SECONDS 0 |
461 | 0824d6fc | bellard | #define RTC_SECONDS_ALARM 1 |
462 | 0824d6fc | bellard | #define RTC_MINUTES 2 |
463 | 0824d6fc | bellard | #define RTC_MINUTES_ALARM 3 |
464 | 0824d6fc | bellard | #define RTC_HOURS 4 |
465 | 0824d6fc | bellard | #define RTC_HOURS_ALARM 5 |
466 | 0824d6fc | bellard | #define RTC_ALARM_DONT_CARE 0xC0 |
467 | 0824d6fc | bellard | |
468 | 0824d6fc | bellard | #define RTC_DAY_OF_WEEK 6 |
469 | 0824d6fc | bellard | #define RTC_DAY_OF_MONTH 7 |
470 | 0824d6fc | bellard | #define RTC_MONTH 8 |
471 | 0824d6fc | bellard | #define RTC_YEAR 9 |
472 | 0824d6fc | bellard | |
473 | 0824d6fc | bellard | #define RTC_REG_A 10 |
474 | 0824d6fc | bellard | #define RTC_REG_B 11 |
475 | 0824d6fc | bellard | #define RTC_REG_C 12 |
476 | 0824d6fc | bellard | #define RTC_REG_D 13 |
477 | 0824d6fc | bellard | |
478 | 0824d6fc | bellard | /* PC cmos mappings */
|
479 | 0824d6fc | bellard | #define REG_EQUIPMENT_BYTE 0x14 |
480 | 0824d6fc | bellard | |
481 | 0824d6fc | bellard | uint8_t cmos_data[128];
|
482 | 0824d6fc | bellard | uint8_t cmos_index; |
483 | 0824d6fc | bellard | |
484 | 0824d6fc | bellard | void cmos_ioport_write(CPUX86State *env, uint32_t addr, uint32_t data)
|
485 | 0824d6fc | bellard | { |
486 | 0824d6fc | bellard | if (addr == 0x70) { |
487 | 0824d6fc | bellard | cmos_index = data & 0x7f;
|
488 | 0824d6fc | bellard | } |
489 | 0824d6fc | bellard | } |
490 | 0824d6fc | bellard | |
491 | 0824d6fc | bellard | uint32_t cmos_ioport_read(CPUX86State *env, uint32_t addr) |
492 | 0824d6fc | bellard | { |
493 | 0824d6fc | bellard | int ret;
|
494 | 0824d6fc | bellard | |
495 | 0824d6fc | bellard | if (addr == 0x70) { |
496 | 0824d6fc | bellard | return 0xff; |
497 | 0824d6fc | bellard | } else {
|
498 | 0824d6fc | bellard | /* toggle update-in-progress bit for Linux (same hack as
|
499 | 0824d6fc | bellard | plex86) */
|
500 | 0824d6fc | bellard | ret = cmos_data[cmos_index]; |
501 | 0824d6fc | bellard | if (cmos_index == RTC_REG_A)
|
502 | 0824d6fc | bellard | cmos_data[RTC_REG_A] ^= 0x80;
|
503 | 0824d6fc | bellard | else if (cmos_index == RTC_REG_C) |
504 | 0824d6fc | bellard | cmos_data[RTC_REG_C] = 0x00;
|
505 | 0824d6fc | bellard | return ret;
|
506 | 0824d6fc | bellard | } |
507 | 0824d6fc | bellard | } |
508 | 0824d6fc | bellard | |
509 | 0824d6fc | bellard | |
510 | 0824d6fc | bellard | static inline int to_bcd(int a) |
511 | 0824d6fc | bellard | { |
512 | 0824d6fc | bellard | return ((a / 10) << 4) | (a % 10); |
513 | 0824d6fc | bellard | } |
514 | 0824d6fc | bellard | |
515 | 0824d6fc | bellard | void cmos_init(void) |
516 | 0824d6fc | bellard | { |
517 | 0824d6fc | bellard | struct tm *tm;
|
518 | 0824d6fc | bellard | time_t ti; |
519 | 0824d6fc | bellard | |
520 | 0824d6fc | bellard | ti = time(NULL);
|
521 | 0824d6fc | bellard | tm = gmtime(&ti); |
522 | 0824d6fc | bellard | cmos_data[RTC_SECONDS] = to_bcd(tm->tm_sec); |
523 | 0824d6fc | bellard | cmos_data[RTC_MINUTES] = to_bcd(tm->tm_min); |
524 | 0824d6fc | bellard | cmos_data[RTC_HOURS] = to_bcd(tm->tm_hour); |
525 | 0824d6fc | bellard | cmos_data[RTC_DAY_OF_WEEK] = to_bcd(tm->tm_wday); |
526 | 0824d6fc | bellard | cmos_data[RTC_DAY_OF_MONTH] = to_bcd(tm->tm_mday); |
527 | abd0aaff | bellard | cmos_data[RTC_MONTH] = to_bcd(tm->tm_mon + 1);
|
528 | 0824d6fc | bellard | cmos_data[RTC_YEAR] = to_bcd(tm->tm_year % 100);
|
529 | 0824d6fc | bellard | |
530 | 0824d6fc | bellard | cmos_data[RTC_REG_A] = 0x26;
|
531 | 0824d6fc | bellard | cmos_data[RTC_REG_B] = 0x02;
|
532 | 0824d6fc | bellard | cmos_data[RTC_REG_C] = 0x00;
|
533 | 0824d6fc | bellard | cmos_data[RTC_REG_D] = 0x80;
|
534 | 0824d6fc | bellard | |
535 | 0824d6fc | bellard | cmos_data[REG_EQUIPMENT_BYTE] = 0x02; /* FPU is there */ |
536 | 0824d6fc | bellard | |
537 | fc01f7e7 | bellard | register_ioport_write(0x70, 2, cmos_ioport_write, 1); |
538 | fc01f7e7 | bellard | register_ioport_read(0x70, 2, cmos_ioport_read, 1); |
539 | 0824d6fc | bellard | } |
540 | 0824d6fc | bellard | |
541 | 0824d6fc | bellard | /***********************************************************/
|
542 | 0824d6fc | bellard | /* 8259 pic emulation */
|
543 | 0824d6fc | bellard | |
544 | b118d61e | bellard | //#define DEBUG_PIC
|
545 | b118d61e | bellard | |
546 | 0824d6fc | bellard | typedef struct PicState { |
547 | 0824d6fc | bellard | uint8_t last_irr; /* edge detection */
|
548 | 0824d6fc | bellard | uint8_t irr; /* interrupt request register */
|
549 | 0824d6fc | bellard | uint8_t imr; /* interrupt mask register */
|
550 | 0824d6fc | bellard | uint8_t isr; /* interrupt service register */
|
551 | 0824d6fc | bellard | uint8_t priority_add; /* used to compute irq priority */
|
552 | 0824d6fc | bellard | uint8_t irq_base; |
553 | 0824d6fc | bellard | uint8_t read_reg_select; |
554 | 0824d6fc | bellard | uint8_t special_mask; |
555 | 0824d6fc | bellard | uint8_t init_state; |
556 | 0824d6fc | bellard | uint8_t auto_eoi; |
557 | 0824d6fc | bellard | uint8_t rotate_on_autoeoi; |
558 | 0824d6fc | bellard | uint8_t init4; /* true if 4 byte init */
|
559 | 0824d6fc | bellard | } PicState; |
560 | 0824d6fc | bellard | |
561 | 0824d6fc | bellard | /* 0 is master pic, 1 is slave pic */
|
562 | 0824d6fc | bellard | PicState pics[2];
|
563 | 0824d6fc | bellard | int pic_irq_requested;
|
564 | 0824d6fc | bellard | |
565 | 0824d6fc | bellard | /* set irq level. If an edge is detected, then the IRR is set to 1 */
|
566 | 0824d6fc | bellard | static inline void pic_set_irq1(PicState *s, int irq, int level) |
567 | 0824d6fc | bellard | { |
568 | 0824d6fc | bellard | int mask;
|
569 | 0824d6fc | bellard | mask = 1 << irq;
|
570 | 0824d6fc | bellard | if (level) {
|
571 | 0824d6fc | bellard | if ((s->last_irr & mask) == 0) |
572 | 0824d6fc | bellard | s->irr |= mask; |
573 | 0824d6fc | bellard | s->last_irr |= mask; |
574 | 0824d6fc | bellard | } else {
|
575 | 0824d6fc | bellard | s->last_irr &= ~mask; |
576 | 0824d6fc | bellard | } |
577 | 0824d6fc | bellard | } |
578 | 0824d6fc | bellard | |
579 | 0824d6fc | bellard | static inline int get_priority(PicState *s, int mask) |
580 | 0824d6fc | bellard | { |
581 | 0824d6fc | bellard | int priority;
|
582 | 0824d6fc | bellard | if (mask == 0) |
583 | 0824d6fc | bellard | return -1; |
584 | 0824d6fc | bellard | priority = 7;
|
585 | 0824d6fc | bellard | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) |
586 | 0824d6fc | bellard | priority--; |
587 | 0824d6fc | bellard | return priority;
|
588 | 0824d6fc | bellard | } |
589 | 0824d6fc | bellard | |
590 | 0824d6fc | bellard | /* return the pic wanted interrupt. return -1 if none */
|
591 | 0824d6fc | bellard | static int pic_get_irq(PicState *s) |
592 | 0824d6fc | bellard | { |
593 | 0824d6fc | bellard | int mask, cur_priority, priority;
|
594 | 0824d6fc | bellard | |
595 | 0824d6fc | bellard | mask = s->irr & ~s->imr; |
596 | 0824d6fc | bellard | priority = get_priority(s, mask); |
597 | 0824d6fc | bellard | if (priority < 0) |
598 | 0824d6fc | bellard | return -1; |
599 | 0824d6fc | bellard | /* compute current priority */
|
600 | 0824d6fc | bellard | cur_priority = get_priority(s, s->isr); |
601 | 0824d6fc | bellard | if (priority > cur_priority) {
|
602 | 0824d6fc | bellard | /* higher priority found: an irq should be generated */
|
603 | 0824d6fc | bellard | return priority;
|
604 | 0824d6fc | bellard | } else {
|
605 | 0824d6fc | bellard | return -1; |
606 | 0824d6fc | bellard | } |
607 | 0824d6fc | bellard | } |
608 | 0824d6fc | bellard | |
609 | c9159e53 | bellard | /* raise irq to CPU if necessary. must be called every time the active
|
610 | c9159e53 | bellard | irq may change */
|
611 | c9159e53 | bellard | static void pic_update_irq(void) |
612 | 0824d6fc | bellard | { |
613 | 0824d6fc | bellard | int irq2, irq;
|
614 | 0824d6fc | bellard | |
615 | 0824d6fc | bellard | /* first look at slave pic */
|
616 | 0824d6fc | bellard | irq2 = pic_get_irq(&pics[1]);
|
617 | 0824d6fc | bellard | if (irq2 >= 0) { |
618 | 0824d6fc | bellard | /* if irq request by slave pic, signal master PIC */
|
619 | 0824d6fc | bellard | pic_set_irq1(&pics[0], 2, 1); |
620 | 0824d6fc | bellard | pic_set_irq1(&pics[0], 2, 0); |
621 | 0824d6fc | bellard | } |
622 | 0824d6fc | bellard | /* look at requested irq */
|
623 | 0824d6fc | bellard | irq = pic_get_irq(&pics[0]);
|
624 | 0824d6fc | bellard | if (irq >= 0) { |
625 | 0824d6fc | bellard | if (irq == 2) { |
626 | 0824d6fc | bellard | /* from slave pic */
|
627 | 0824d6fc | bellard | pic_irq_requested = 8 + irq2;
|
628 | 0824d6fc | bellard | } else {
|
629 | 0824d6fc | bellard | /* from master pic */
|
630 | 0824d6fc | bellard | pic_irq_requested = irq; |
631 | 0824d6fc | bellard | } |
632 | c9159e53 | bellard | cpu_x86_interrupt(global_env, CPU_INTERRUPT_HARD); |
633 | 0824d6fc | bellard | } |
634 | 0824d6fc | bellard | } |
635 | 0824d6fc | bellard | |
636 | c9159e53 | bellard | #ifdef DEBUG_IRQ_LATENCY
|
637 | c9159e53 | bellard | int64_t irq_time[16];
|
638 | c9159e53 | bellard | int64_t cpu_get_ticks(void);
|
639 | c9159e53 | bellard | #endif
|
640 | b118d61e | bellard | #ifdef DEBUG_PIC
|
641 | b118d61e | bellard | int irq_level[16]; |
642 | b118d61e | bellard | #endif
|
643 | c9159e53 | bellard | |
644 | c9159e53 | bellard | void pic_set_irq(int irq, int level) |
645 | c9159e53 | bellard | { |
646 | b118d61e | bellard | #ifdef DEBUG_PIC
|
647 | b118d61e | bellard | if (level != irq_level[irq]) {
|
648 | b118d61e | bellard | printf("pic_set_irq: irq=%d level=%d\n", irq, level);
|
649 | b118d61e | bellard | irq_level[irq] = level; |
650 | b118d61e | bellard | } |
651 | b118d61e | bellard | #endif
|
652 | c9159e53 | bellard | #ifdef DEBUG_IRQ_LATENCY
|
653 | c9159e53 | bellard | if (level) {
|
654 | c9159e53 | bellard | irq_time[irq] = cpu_get_ticks(); |
655 | c9159e53 | bellard | } |
656 | c9159e53 | bellard | #endif
|
657 | c9159e53 | bellard | pic_set_irq1(&pics[irq >> 3], irq & 7, level); |
658 | c9159e53 | bellard | pic_update_irq(); |
659 | c9159e53 | bellard | } |
660 | c9159e53 | bellard | |
661 | 0824d6fc | bellard | int cpu_x86_get_pic_interrupt(CPUX86State *env)
|
662 | 0824d6fc | bellard | { |
663 | 0824d6fc | bellard | int irq, irq2, intno;
|
664 | 0824d6fc | bellard | |
665 | 0824d6fc | bellard | /* signal the pic that the irq was acked by the CPU */
|
666 | 0824d6fc | bellard | irq = pic_irq_requested; |
667 | c9159e53 | bellard | #ifdef DEBUG_IRQ_LATENCY
|
668 | c9159e53 | bellard | printf("IRQ%d latency=%Ld\n", irq, cpu_get_ticks() - irq_time[irq]);
|
669 | c9159e53 | bellard | #endif
|
670 | b118d61e | bellard | #ifdef DEBUG_PIC
|
671 | b118d61e | bellard | printf("pic_interrupt: irq=%d\n", irq);
|
672 | b118d61e | bellard | #endif
|
673 | c9159e53 | bellard | |
674 | 0824d6fc | bellard | if (irq >= 8) { |
675 | 0824d6fc | bellard | irq2 = irq & 7;
|
676 | 0824d6fc | bellard | pics[1].isr |= (1 << irq2); |
677 | 0824d6fc | bellard | pics[1].irr &= ~(1 << irq2); |
678 | 0824d6fc | bellard | irq = 2;
|
679 | 0824d6fc | bellard | intno = pics[1].irq_base + irq2;
|
680 | 0824d6fc | bellard | } else {
|
681 | 0824d6fc | bellard | intno = pics[0].irq_base + irq;
|
682 | 0824d6fc | bellard | } |
683 | 0824d6fc | bellard | pics[0].isr |= (1 << irq); |
684 | 0824d6fc | bellard | pics[0].irr &= ~(1 << irq); |
685 | 0824d6fc | bellard | return intno;
|
686 | 0824d6fc | bellard | } |
687 | 0824d6fc | bellard | |
688 | 0824d6fc | bellard | void pic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
689 | 0824d6fc | bellard | { |
690 | 0824d6fc | bellard | PicState *s; |
691 | 0824d6fc | bellard | int priority;
|
692 | 0824d6fc | bellard | |
693 | b118d61e | bellard | #ifdef DEBUG_PIC
|
694 | b118d61e | bellard | printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
|
695 | b118d61e | bellard | #endif
|
696 | 0824d6fc | bellard | s = &pics[addr >> 7];
|
697 | 0824d6fc | bellard | addr &= 1;
|
698 | 0824d6fc | bellard | if (addr == 0) { |
699 | 0824d6fc | bellard | if (val & 0x10) { |
700 | 0824d6fc | bellard | /* init */
|
701 | 0824d6fc | bellard | memset(s, 0, sizeof(PicState)); |
702 | 0824d6fc | bellard | s->init_state = 1;
|
703 | 0824d6fc | bellard | s->init4 = val & 1;
|
704 | 0824d6fc | bellard | if (val & 0x02) |
705 | 0824d6fc | bellard | hw_error("single mode not supported");
|
706 | 0824d6fc | bellard | if (val & 0x08) |
707 | 0824d6fc | bellard | hw_error("level sensitive irq not supported");
|
708 | 0824d6fc | bellard | } else if (val & 0x08) { |
709 | 0824d6fc | bellard | if (val & 0x02) |
710 | 0824d6fc | bellard | s->read_reg_select = val & 1;
|
711 | 0824d6fc | bellard | if (val & 0x40) |
712 | 0824d6fc | bellard | s->special_mask = (val >> 5) & 1; |
713 | 0824d6fc | bellard | } else {
|
714 | 0824d6fc | bellard | switch(val) {
|
715 | 0824d6fc | bellard | case 0x00: |
716 | 0824d6fc | bellard | case 0x80: |
717 | 0824d6fc | bellard | s->rotate_on_autoeoi = val >> 7;
|
718 | 0824d6fc | bellard | break;
|
719 | 0824d6fc | bellard | case 0x20: /* end of interrupt */ |
720 | 0824d6fc | bellard | case 0xa0: |
721 | 0824d6fc | bellard | priority = get_priority(s, s->isr); |
722 | 0824d6fc | bellard | if (priority >= 0) { |
723 | 0824d6fc | bellard | s->isr &= ~(1 << ((priority + s->priority_add) & 7)); |
724 | 0824d6fc | bellard | } |
725 | 0824d6fc | bellard | if (val == 0xa0) |
726 | 0824d6fc | bellard | s->priority_add = (s->priority_add + 1) & 7; |
727 | 0824d6fc | bellard | break;
|
728 | 0824d6fc | bellard | case 0x60 ... 0x67: |
729 | 0824d6fc | bellard | priority = val & 7;
|
730 | 0824d6fc | bellard | s->isr &= ~(1 << priority);
|
731 | 0824d6fc | bellard | break;
|
732 | 0824d6fc | bellard | case 0xc0 ... 0xc7: |
733 | 0824d6fc | bellard | s->priority_add = (val + 1) & 7; |
734 | 0824d6fc | bellard | break;
|
735 | 0824d6fc | bellard | case 0xe0 ... 0xe7: |
736 | 0824d6fc | bellard | priority = val & 7;
|
737 | 0824d6fc | bellard | s->isr &= ~(1 << priority);
|
738 | 0824d6fc | bellard | s->priority_add = (priority + 1) & 7; |
739 | 0824d6fc | bellard | break;
|
740 | 0824d6fc | bellard | } |
741 | 0824d6fc | bellard | } |
742 | 0824d6fc | bellard | } else {
|
743 | 0824d6fc | bellard | switch(s->init_state) {
|
744 | 0824d6fc | bellard | case 0: |
745 | 0824d6fc | bellard | /* normal mode */
|
746 | 0824d6fc | bellard | s->imr = val; |
747 | c9159e53 | bellard | pic_update_irq(); |
748 | 0824d6fc | bellard | break;
|
749 | 0824d6fc | bellard | case 1: |
750 | 0824d6fc | bellard | s->irq_base = val & 0xf8;
|
751 | 0824d6fc | bellard | s->init_state = 2;
|
752 | 0824d6fc | bellard | break;
|
753 | 0824d6fc | bellard | case 2: |
754 | 0824d6fc | bellard | if (s->init4) {
|
755 | 0824d6fc | bellard | s->init_state = 3;
|
756 | 0824d6fc | bellard | } else {
|
757 | 0824d6fc | bellard | s->init_state = 0;
|
758 | 0824d6fc | bellard | } |
759 | 0824d6fc | bellard | break;
|
760 | 0824d6fc | bellard | case 3: |
761 | 0824d6fc | bellard | s->auto_eoi = (val >> 1) & 1; |
762 | 0824d6fc | bellard | s->init_state = 0;
|
763 | 0824d6fc | bellard | break;
|
764 | 0824d6fc | bellard | } |
765 | 0824d6fc | bellard | } |
766 | 0824d6fc | bellard | } |
767 | 0824d6fc | bellard | |
768 | b118d61e | bellard | uint32_t pic_ioport_read(CPUX86State *env, uint32_t addr1) |
769 | 0824d6fc | bellard | { |
770 | 0824d6fc | bellard | PicState *s; |
771 | b118d61e | bellard | unsigned int addr; |
772 | b118d61e | bellard | int ret;
|
773 | b118d61e | bellard | |
774 | b118d61e | bellard | addr = addr1; |
775 | 0824d6fc | bellard | s = &pics[addr >> 7];
|
776 | 0824d6fc | bellard | addr &= 1;
|
777 | 0824d6fc | bellard | if (addr == 0) { |
778 | 0824d6fc | bellard | if (s->read_reg_select)
|
779 | b118d61e | bellard | ret = s->isr; |
780 | 0824d6fc | bellard | else
|
781 | b118d61e | bellard | ret = s->irr; |
782 | 0824d6fc | bellard | } else {
|
783 | b118d61e | bellard | ret = s->imr; |
784 | 0824d6fc | bellard | } |
785 | b118d61e | bellard | #ifdef DEBUG_PIC
|
786 | b118d61e | bellard | printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
|
787 | b118d61e | bellard | #endif
|
788 | b118d61e | bellard | return ret;
|
789 | 0824d6fc | bellard | } |
790 | 0824d6fc | bellard | |
791 | 0824d6fc | bellard | void pic_init(void) |
792 | 0824d6fc | bellard | { |
793 | fc01f7e7 | bellard | register_ioport_write(0x20, 2, pic_ioport_write, 1); |
794 | fc01f7e7 | bellard | register_ioport_read(0x20, 2, pic_ioport_read, 1); |
795 | fc01f7e7 | bellard | register_ioport_write(0xa0, 2, pic_ioport_write, 1); |
796 | fc01f7e7 | bellard | register_ioport_read(0xa0, 2, pic_ioport_read, 1); |
797 | 0824d6fc | bellard | } |
798 | 0824d6fc | bellard | |
799 | 0824d6fc | bellard | /***********************************************************/
|
800 | 0824d6fc | bellard | /* 8253 PIT emulation */
|
801 | 0824d6fc | bellard | |
802 | 0824d6fc | bellard | #define PIT_FREQ 1193182 |
803 | 0824d6fc | bellard | |
804 | 0824d6fc | bellard | #define RW_STATE_LSB 0 |
805 | 0824d6fc | bellard | #define RW_STATE_MSB 1 |
806 | 0824d6fc | bellard | #define RW_STATE_WORD0 2 |
807 | 0824d6fc | bellard | #define RW_STATE_WORD1 3 |
808 | 0824d6fc | bellard | #define RW_STATE_LATCHED_WORD0 4 |
809 | 0824d6fc | bellard | #define RW_STATE_LATCHED_WORD1 5 |
810 | 0824d6fc | bellard | |
811 | 0824d6fc | bellard | typedef struct PITChannelState { |
812 | 87858c89 | bellard | int count; /* can be 65536 */ |
813 | 0824d6fc | bellard | uint16_t latched_count; |
814 | 0824d6fc | bellard | uint8_t rw_state; |
815 | 0824d6fc | bellard | uint8_t mode; |
816 | 0824d6fc | bellard | uint8_t bcd; /* not supported */
|
817 | 0824d6fc | bellard | uint8_t gate; /* timer start */
|
818 | 0824d6fc | bellard | int64_t count_load_time; |
819 | 87858c89 | bellard | int64_t count_last_edge_check_time; |
820 | 0824d6fc | bellard | } PITChannelState; |
821 | 0824d6fc | bellard | |
822 | 0824d6fc | bellard | PITChannelState pit_channels[3];
|
823 | 0824d6fc | bellard | int speaker_data_on;
|
824 | 87858c89 | bellard | int pit_min_timer_count = 0; |
825 | 0824d6fc | bellard | |
826 | 0824d6fc | bellard | int64_t ticks_per_sec; |
827 | 0824d6fc | bellard | |
828 | 0824d6fc | bellard | int64_t get_clock(void)
|
829 | 0824d6fc | bellard | { |
830 | 0824d6fc | bellard | struct timeval tv;
|
831 | 0824d6fc | bellard | gettimeofday(&tv, NULL);
|
832 | 0824d6fc | bellard | return tv.tv_sec * 1000000LL + tv.tv_usec; |
833 | 0824d6fc | bellard | } |
834 | 0824d6fc | bellard | |
835 | 0824d6fc | bellard | int64_t cpu_get_ticks(void)
|
836 | 0824d6fc | bellard | { |
837 | 0824d6fc | bellard | int64_t val; |
838 | 0824d6fc | bellard | asm("rdtsc" : "=A" (val)); |
839 | 0824d6fc | bellard | return val;
|
840 | 0824d6fc | bellard | } |
841 | 0824d6fc | bellard | |
842 | 0824d6fc | bellard | void cpu_calibrate_ticks(void) |
843 | 0824d6fc | bellard | { |
844 | 0824d6fc | bellard | int64_t usec, ticks; |
845 | 0824d6fc | bellard | |
846 | 0824d6fc | bellard | usec = get_clock(); |
847 | 0824d6fc | bellard | ticks = cpu_get_ticks(); |
848 | 0824d6fc | bellard | usleep(50 * 1000); |
849 | 0824d6fc | bellard | usec = get_clock() - usec; |
850 | 0824d6fc | bellard | ticks = cpu_get_ticks() - ticks; |
851 | 0824d6fc | bellard | ticks_per_sec = (ticks * 1000000LL + (usec >> 1)) / usec; |
852 | 0824d6fc | bellard | } |
853 | 0824d6fc | bellard | |
854 | 87858c89 | bellard | /* compute with 96 bit intermediate result: (a*b)/c */
|
855 | 87858c89 | bellard | static uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c)
|
856 | 87858c89 | bellard | { |
857 | 87858c89 | bellard | union {
|
858 | 87858c89 | bellard | uint64_t ll; |
859 | 87858c89 | bellard | struct {
|
860 | 87858c89 | bellard | #ifdef WORDS_BIGENDIAN
|
861 | 87858c89 | bellard | uint32_t high, low; |
862 | 87858c89 | bellard | #else
|
863 | 87858c89 | bellard | uint32_t low, high; |
864 | 87858c89 | bellard | #endif
|
865 | 87858c89 | bellard | } l; |
866 | 87858c89 | bellard | } u, res; |
867 | 87858c89 | bellard | uint64_t rl, rh; |
868 | 87858c89 | bellard | |
869 | 87858c89 | bellard | u.ll = a; |
870 | 87858c89 | bellard | rl = (uint64_t)u.l.low * (uint64_t)b; |
871 | 87858c89 | bellard | rh = (uint64_t)u.l.high * (uint64_t)b; |
872 | 87858c89 | bellard | rh += (rl >> 32);
|
873 | 87858c89 | bellard | res.l.high = rh / c; |
874 | 87858c89 | bellard | res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c; |
875 | 87858c89 | bellard | return res.ll;
|
876 | 87858c89 | bellard | } |
877 | 87858c89 | bellard | |
878 | 0824d6fc | bellard | static int pit_get_count(PITChannelState *s) |
879 | 0824d6fc | bellard | { |
880 | 87858c89 | bellard | uint64_t d; |
881 | 0824d6fc | bellard | int counter;
|
882 | 0824d6fc | bellard | |
883 | 87858c89 | bellard | d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec); |
884 | 0824d6fc | bellard | switch(s->mode) {
|
885 | 0824d6fc | bellard | case 0: |
886 | 0824d6fc | bellard | case 1: |
887 | 0824d6fc | bellard | case 4: |
888 | 0824d6fc | bellard | case 5: |
889 | 0824d6fc | bellard | counter = (s->count - d) & 0xffff;
|
890 | 0824d6fc | bellard | break;
|
891 | 0824d6fc | bellard | default:
|
892 | 0824d6fc | bellard | counter = s->count - (d % s->count); |
893 | 0824d6fc | bellard | break;
|
894 | 0824d6fc | bellard | } |
895 | 0824d6fc | bellard | return counter;
|
896 | 0824d6fc | bellard | } |
897 | 0824d6fc | bellard | |
898 | 0824d6fc | bellard | /* get pit output bit */
|
899 | 0824d6fc | bellard | static int pit_get_out(PITChannelState *s) |
900 | 0824d6fc | bellard | { |
901 | 87858c89 | bellard | uint64_t d; |
902 | 0824d6fc | bellard | int out;
|
903 | 0824d6fc | bellard | |
904 | 87858c89 | bellard | d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec); |
905 | 0824d6fc | bellard | switch(s->mode) {
|
906 | 0824d6fc | bellard | default:
|
907 | 0824d6fc | bellard | case 0: |
908 | 0824d6fc | bellard | out = (d >= s->count); |
909 | 0824d6fc | bellard | break;
|
910 | 0824d6fc | bellard | case 1: |
911 | 0824d6fc | bellard | out = (d < s->count); |
912 | 0824d6fc | bellard | break;
|
913 | 0824d6fc | bellard | case 2: |
914 | 0824d6fc | bellard | if ((d % s->count) == 0 && d != 0) |
915 | 0824d6fc | bellard | out = 1;
|
916 | 0824d6fc | bellard | else
|
917 | 0824d6fc | bellard | out = 0;
|
918 | 0824d6fc | bellard | break;
|
919 | 0824d6fc | bellard | case 3: |
920 | 0824d6fc | bellard | out = (d % s->count) < (s->count >> 1);
|
921 | 0824d6fc | bellard | break;
|
922 | 0824d6fc | bellard | case 4: |
923 | 0824d6fc | bellard | case 5: |
924 | 0824d6fc | bellard | out = (d == s->count); |
925 | 0824d6fc | bellard | break;
|
926 | 0824d6fc | bellard | } |
927 | 0824d6fc | bellard | return out;
|
928 | 0824d6fc | bellard | } |
929 | 0824d6fc | bellard | |
930 | 87858c89 | bellard | /* get the number of 0 to 1 transitions we had since we call this
|
931 | 87858c89 | bellard | function */
|
932 | 87858c89 | bellard | /* XXX: maybe better to use ticks precision to avoid getting edges
|
933 | 87858c89 | bellard | twice if checks are done at very small intervals */
|
934 | 87858c89 | bellard | static int pit_get_out_edges(PITChannelState *s) |
935 | 87858c89 | bellard | { |
936 | 87858c89 | bellard | uint64_t d1, d2; |
937 | 87858c89 | bellard | int64_t ticks; |
938 | 87858c89 | bellard | int ret, v;
|
939 | 87858c89 | bellard | |
940 | 87858c89 | bellard | ticks = cpu_get_ticks(); |
941 | 87858c89 | bellard | d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time, |
942 | 87858c89 | bellard | PIT_FREQ, ticks_per_sec); |
943 | 87858c89 | bellard | d2 = muldiv64(ticks - s->count_load_time, |
944 | 87858c89 | bellard | PIT_FREQ, ticks_per_sec); |
945 | 87858c89 | bellard | s->count_last_edge_check_time = ticks; |
946 | 87858c89 | bellard | switch(s->mode) {
|
947 | 87858c89 | bellard | default:
|
948 | 87858c89 | bellard | case 0: |
949 | 87858c89 | bellard | if (d1 < s->count && d2 >= s->count)
|
950 | 87858c89 | bellard | ret = 1;
|
951 | 87858c89 | bellard | else
|
952 | 87858c89 | bellard | ret = 0;
|
953 | 87858c89 | bellard | break;
|
954 | 87858c89 | bellard | case 1: |
955 | 87858c89 | bellard | ret = 0;
|
956 | 87858c89 | bellard | break;
|
957 | 87858c89 | bellard | case 2: |
958 | 87858c89 | bellard | d1 /= s->count; |
959 | 87858c89 | bellard | d2 /= s->count; |
960 | 87858c89 | bellard | ret = d2 - d1; |
961 | 87858c89 | bellard | break;
|
962 | 87858c89 | bellard | case 3: |
963 | 87858c89 | bellard | v = s->count - (s->count >> 1);
|
964 | 87858c89 | bellard | d1 = (d1 + v) / s->count; |
965 | 87858c89 | bellard | d2 = (d2 + v) / s->count; |
966 | 87858c89 | bellard | ret = d2 - d1; |
967 | 87858c89 | bellard | break;
|
968 | 87858c89 | bellard | case 4: |
969 | 87858c89 | bellard | case 5: |
970 | 87858c89 | bellard | if (d1 < s->count && d2 >= s->count)
|
971 | 87858c89 | bellard | ret = 1;
|
972 | 87858c89 | bellard | else
|
973 | 87858c89 | bellard | ret = 0;
|
974 | 87858c89 | bellard | break;
|
975 | 87858c89 | bellard | } |
976 | 87858c89 | bellard | return ret;
|
977 | 87858c89 | bellard | } |
978 | 87858c89 | bellard | |
979 | 87858c89 | bellard | static inline void pit_load_count(PITChannelState *s, int val) |
980 | 87858c89 | bellard | { |
981 | 87858c89 | bellard | if (val == 0) |
982 | 87858c89 | bellard | val = 0x10000;
|
983 | 87858c89 | bellard | s->count_load_time = cpu_get_ticks(); |
984 | 87858c89 | bellard | s->count_last_edge_check_time = s->count_load_time; |
985 | 87858c89 | bellard | s->count = val; |
986 | 87858c89 | bellard | if (s == &pit_channels[0] && val <= pit_min_timer_count) { |
987 | 87858c89 | bellard | fprintf(stderr, |
988 | 87858c89 | bellard | "\nWARNING: vl: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.5.xx Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
|
989 | 87858c89 | bellard | PIT_FREQ / pit_min_timer_count); |
990 | 87858c89 | bellard | } |
991 | 87858c89 | bellard | } |
992 | 87858c89 | bellard | |
993 | 0824d6fc | bellard | void pit_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
994 | 0824d6fc | bellard | { |
995 | 0824d6fc | bellard | int channel, access;
|
996 | 0824d6fc | bellard | PITChannelState *s; |
997 | 87858c89 | bellard | |
998 | 0824d6fc | bellard | addr &= 3;
|
999 | 0824d6fc | bellard | if (addr == 3) { |
1000 | 0824d6fc | bellard | channel = val >> 6;
|
1001 | 0824d6fc | bellard | if (channel == 3) |
1002 | 0824d6fc | bellard | return;
|
1003 | 0824d6fc | bellard | s = &pit_channels[channel]; |
1004 | 0824d6fc | bellard | access = (val >> 4) & 3; |
1005 | 0824d6fc | bellard | switch(access) {
|
1006 | 0824d6fc | bellard | case 0: |
1007 | 0824d6fc | bellard | s->latched_count = pit_get_count(s); |
1008 | 0824d6fc | bellard | s->rw_state = RW_STATE_LATCHED_WORD0; |
1009 | 0824d6fc | bellard | break;
|
1010 | 0824d6fc | bellard | default:
|
1011 | 87858c89 | bellard | s->mode = (val >> 1) & 7; |
1012 | 87858c89 | bellard | s->bcd = val & 1;
|
1013 | 0824d6fc | bellard | s->rw_state = access - 1 + RW_STATE_LSB;
|
1014 | 0824d6fc | bellard | break;
|
1015 | 0824d6fc | bellard | } |
1016 | 0824d6fc | bellard | } else {
|
1017 | 0824d6fc | bellard | s = &pit_channels[addr]; |
1018 | 0824d6fc | bellard | switch(s->rw_state) {
|
1019 | 0824d6fc | bellard | case RW_STATE_LSB:
|
1020 | 87858c89 | bellard | pit_load_count(s, val); |
1021 | 0824d6fc | bellard | break;
|
1022 | 0824d6fc | bellard | case RW_STATE_MSB:
|
1023 | 87858c89 | bellard | pit_load_count(s, val << 8);
|
1024 | 0824d6fc | bellard | break;
|
1025 | 0824d6fc | bellard | case RW_STATE_WORD0:
|
1026 | 0824d6fc | bellard | case RW_STATE_WORD1:
|
1027 | 0824d6fc | bellard | if (s->rw_state & 1) { |
1028 | 87858c89 | bellard | pit_load_count(s, (s->latched_count & 0xff) | (val << 8)); |
1029 | 0824d6fc | bellard | } else {
|
1030 | 0824d6fc | bellard | s->latched_count = val; |
1031 | 0824d6fc | bellard | } |
1032 | 0824d6fc | bellard | s->rw_state ^= 1;
|
1033 | 0824d6fc | bellard | break;
|
1034 | 0824d6fc | bellard | } |
1035 | 0824d6fc | bellard | } |
1036 | 0824d6fc | bellard | } |
1037 | 0824d6fc | bellard | |
1038 | 0824d6fc | bellard | uint32_t pit_ioport_read(CPUX86State *env, uint32_t addr) |
1039 | 0824d6fc | bellard | { |
1040 | 0824d6fc | bellard | int ret, count;
|
1041 | 0824d6fc | bellard | PITChannelState *s; |
1042 | 0824d6fc | bellard | |
1043 | 0824d6fc | bellard | addr &= 3;
|
1044 | 0824d6fc | bellard | s = &pit_channels[addr]; |
1045 | 0824d6fc | bellard | switch(s->rw_state) {
|
1046 | 0824d6fc | bellard | case RW_STATE_LSB:
|
1047 | 0824d6fc | bellard | case RW_STATE_MSB:
|
1048 | 0824d6fc | bellard | case RW_STATE_WORD0:
|
1049 | 0824d6fc | bellard | case RW_STATE_WORD1:
|
1050 | 0824d6fc | bellard | count = pit_get_count(s); |
1051 | 0824d6fc | bellard | if (s->rw_state & 1) |
1052 | 0824d6fc | bellard | ret = (count >> 8) & 0xff; |
1053 | 0824d6fc | bellard | else
|
1054 | 0824d6fc | bellard | ret = count & 0xff;
|
1055 | 0824d6fc | bellard | if (s->rw_state & 2) |
1056 | 0824d6fc | bellard | s->rw_state ^= 1;
|
1057 | 0824d6fc | bellard | break;
|
1058 | 0824d6fc | bellard | default:
|
1059 | 0824d6fc | bellard | case RW_STATE_LATCHED_WORD0:
|
1060 | 0824d6fc | bellard | case RW_STATE_LATCHED_WORD1:
|
1061 | 0824d6fc | bellard | if (s->rw_state & 1) |
1062 | 0824d6fc | bellard | ret = s->latched_count >> 8;
|
1063 | 0824d6fc | bellard | else
|
1064 | 0824d6fc | bellard | ret = s->latched_count & 0xff;
|
1065 | 0824d6fc | bellard | s->rw_state ^= 1;
|
1066 | 0824d6fc | bellard | break;
|
1067 | 0824d6fc | bellard | } |
1068 | 0824d6fc | bellard | return ret;
|
1069 | 0824d6fc | bellard | } |
1070 | 0824d6fc | bellard | |
1071 | 0824d6fc | bellard | void speaker_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1072 | 0824d6fc | bellard | { |
1073 | 0824d6fc | bellard | speaker_data_on = (val >> 1) & 1; |
1074 | 0824d6fc | bellard | pit_channels[2].gate = val & 1; |
1075 | 0824d6fc | bellard | } |
1076 | 0824d6fc | bellard | |
1077 | 0824d6fc | bellard | uint32_t speaker_ioport_read(CPUX86State *env, uint32_t addr) |
1078 | 0824d6fc | bellard | { |
1079 | 0824d6fc | bellard | int out;
|
1080 | 0824d6fc | bellard | out = pit_get_out(&pit_channels[2]);
|
1081 | 0824d6fc | bellard | return (speaker_data_on << 1) | pit_channels[2].gate | (out << 5); |
1082 | 0824d6fc | bellard | } |
1083 | 0824d6fc | bellard | |
1084 | 0824d6fc | bellard | void pit_init(void) |
1085 | 0824d6fc | bellard | { |
1086 | 87858c89 | bellard | PITChannelState *s; |
1087 | 87858c89 | bellard | int i;
|
1088 | 87858c89 | bellard | |
1089 | 87858c89 | bellard | cpu_calibrate_ticks(); |
1090 | 87858c89 | bellard | |
1091 | 87858c89 | bellard | for(i = 0;i < 3; i++) { |
1092 | 87858c89 | bellard | s = &pit_channels[i]; |
1093 | 87858c89 | bellard | s->mode = 3;
|
1094 | 87858c89 | bellard | s->gate = (i != 2);
|
1095 | 87858c89 | bellard | pit_load_count(s, 0);
|
1096 | 87858c89 | bellard | } |
1097 | 87858c89 | bellard | |
1098 | fc01f7e7 | bellard | register_ioport_write(0x40, 4, pit_ioport_write, 1); |
1099 | fc01f7e7 | bellard | register_ioport_read(0x40, 3, pit_ioport_read, 1); |
1100 | 0824d6fc | bellard | |
1101 | fc01f7e7 | bellard | register_ioport_read(0x61, 1, speaker_ioport_read, 1); |
1102 | fc01f7e7 | bellard | register_ioport_write(0x61, 1, speaker_ioport_write, 1); |
1103 | 0824d6fc | bellard | } |
1104 | 0824d6fc | bellard | |
1105 | 0824d6fc | bellard | /***********************************************************/
|
1106 | 0824d6fc | bellard | /* serial port emulation */
|
1107 | 0824d6fc | bellard | |
1108 | 0824d6fc | bellard | #define UART_IRQ 4 |
1109 | 0824d6fc | bellard | |
1110 | 0824d6fc | bellard | #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
1111 | 0824d6fc | bellard | |
1112 | 0824d6fc | bellard | #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
1113 | 0824d6fc | bellard | #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
1114 | 0824d6fc | bellard | #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
1115 | 0824d6fc | bellard | #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
1116 | 0824d6fc | bellard | |
1117 | 0824d6fc | bellard | #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
1118 | 0824d6fc | bellard | #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
1119 | 0824d6fc | bellard | |
1120 | 0824d6fc | bellard | #define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
1121 | 0824d6fc | bellard | #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
1122 | 0824d6fc | bellard | #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
1123 | 0824d6fc | bellard | #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
1124 | 0824d6fc | bellard | |
1125 | 0824d6fc | bellard | #define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
1126 | 0824d6fc | bellard | #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
1127 | 0824d6fc | bellard | #define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
1128 | 0824d6fc | bellard | #define UART_LSR_FE 0x08 /* Frame error indicator */ |
1129 | 0824d6fc | bellard | #define UART_LSR_PE 0x04 /* Parity error indicator */ |
1130 | 0824d6fc | bellard | #define UART_LSR_OE 0x02 /* Overrun error indicator */ |
1131 | 0824d6fc | bellard | #define UART_LSR_DR 0x01 /* Receiver data ready */ |
1132 | 0824d6fc | bellard | |
1133 | 0824d6fc | bellard | typedef struct SerialState { |
1134 | 0824d6fc | bellard | uint8_t divider; |
1135 | 0824d6fc | bellard | uint8_t rbr; /* receive register */
|
1136 | 0824d6fc | bellard | uint8_t ier; |
1137 | 0824d6fc | bellard | uint8_t iir; /* read only */
|
1138 | 0824d6fc | bellard | uint8_t lcr; |
1139 | 0824d6fc | bellard | uint8_t mcr; |
1140 | 0824d6fc | bellard | uint8_t lsr; /* read only */
|
1141 | 0824d6fc | bellard | uint8_t msr; |
1142 | 0824d6fc | bellard | uint8_t scr; |
1143 | 0824d6fc | bellard | } SerialState; |
1144 | 0824d6fc | bellard | |
1145 | 0824d6fc | bellard | SerialState serial_ports[1];
|
1146 | 0824d6fc | bellard | |
1147 | 0824d6fc | bellard | void serial_update_irq(void) |
1148 | 0824d6fc | bellard | { |
1149 | 0824d6fc | bellard | SerialState *s = &serial_ports[0];
|
1150 | 0824d6fc | bellard | |
1151 | 0824d6fc | bellard | if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
|
1152 | 0824d6fc | bellard | s->iir = UART_IIR_RDI; |
1153 | 0824d6fc | bellard | } else if ((s->lsr & UART_LSR_THRE) && (s->ier & UART_IER_THRI)) { |
1154 | 0824d6fc | bellard | s->iir = UART_IIR_THRI; |
1155 | 0824d6fc | bellard | } else {
|
1156 | 0824d6fc | bellard | s->iir = UART_IIR_NO_INT; |
1157 | 0824d6fc | bellard | } |
1158 | 0824d6fc | bellard | if (s->iir != UART_IIR_NO_INT) {
|
1159 | 0824d6fc | bellard | pic_set_irq(UART_IRQ, 1);
|
1160 | 0824d6fc | bellard | } else {
|
1161 | 0824d6fc | bellard | pic_set_irq(UART_IRQ, 0);
|
1162 | 0824d6fc | bellard | } |
1163 | 0824d6fc | bellard | } |
1164 | 0824d6fc | bellard | |
1165 | 0824d6fc | bellard | void serial_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1166 | 0824d6fc | bellard | { |
1167 | 0824d6fc | bellard | SerialState *s = &serial_ports[0];
|
1168 | 0824d6fc | bellard | unsigned char ch; |
1169 | 0824d6fc | bellard | int ret;
|
1170 | 0824d6fc | bellard | |
1171 | 0824d6fc | bellard | addr &= 7;
|
1172 | 0824d6fc | bellard | switch(addr) {
|
1173 | 0824d6fc | bellard | default:
|
1174 | 0824d6fc | bellard | case 0: |
1175 | 0824d6fc | bellard | if (s->lcr & UART_LCR_DLAB) {
|
1176 | 0824d6fc | bellard | s->divider = (s->divider & 0xff00) | val;
|
1177 | 0824d6fc | bellard | } else {
|
1178 | 0824d6fc | bellard | s->lsr &= ~UART_LSR_THRE; |
1179 | 0824d6fc | bellard | serial_update_irq(); |
1180 | 0824d6fc | bellard | |
1181 | 0824d6fc | bellard | ch = val; |
1182 | 0824d6fc | bellard | do {
|
1183 | 0824d6fc | bellard | ret = write(1, &ch, 1); |
1184 | 0824d6fc | bellard | } while (ret != 1); |
1185 | 0824d6fc | bellard | s->lsr |= UART_LSR_THRE; |
1186 | 0824d6fc | bellard | s->lsr |= UART_LSR_TEMT; |
1187 | 0824d6fc | bellard | serial_update_irq(); |
1188 | 0824d6fc | bellard | } |
1189 | 0824d6fc | bellard | break;
|
1190 | 0824d6fc | bellard | case 1: |
1191 | 0824d6fc | bellard | if (s->lcr & UART_LCR_DLAB) {
|
1192 | 0824d6fc | bellard | s->divider = (s->divider & 0x00ff) | (val << 8); |
1193 | 0824d6fc | bellard | } else {
|
1194 | 0824d6fc | bellard | s->ier = val; |
1195 | 0824d6fc | bellard | serial_update_irq(); |
1196 | 0824d6fc | bellard | } |
1197 | 0824d6fc | bellard | break;
|
1198 | 0824d6fc | bellard | case 2: |
1199 | 0824d6fc | bellard | break;
|
1200 | 0824d6fc | bellard | case 3: |
1201 | 0824d6fc | bellard | s->lcr = val; |
1202 | 0824d6fc | bellard | break;
|
1203 | 0824d6fc | bellard | case 4: |
1204 | 0824d6fc | bellard | s->mcr = val; |
1205 | 0824d6fc | bellard | break;
|
1206 | 0824d6fc | bellard | case 5: |
1207 | 0824d6fc | bellard | break;
|
1208 | 0824d6fc | bellard | case 6: |
1209 | 0824d6fc | bellard | s->msr = val; |
1210 | 0824d6fc | bellard | break;
|
1211 | 0824d6fc | bellard | case 7: |
1212 | 0824d6fc | bellard | s->scr = val; |
1213 | 0824d6fc | bellard | break;
|
1214 | 0824d6fc | bellard | } |
1215 | 0824d6fc | bellard | } |
1216 | 0824d6fc | bellard | |
1217 | 0824d6fc | bellard | uint32_t serial_ioport_read(CPUX86State *env, uint32_t addr) |
1218 | 0824d6fc | bellard | { |
1219 | 0824d6fc | bellard | SerialState *s = &serial_ports[0];
|
1220 | 0824d6fc | bellard | uint32_t ret; |
1221 | 0824d6fc | bellard | |
1222 | 0824d6fc | bellard | addr &= 7;
|
1223 | 0824d6fc | bellard | switch(addr) {
|
1224 | 0824d6fc | bellard | default:
|
1225 | 0824d6fc | bellard | case 0: |
1226 | 0824d6fc | bellard | if (s->lcr & UART_LCR_DLAB) {
|
1227 | 0824d6fc | bellard | ret = s->divider & 0xff;
|
1228 | 0824d6fc | bellard | } else {
|
1229 | 0824d6fc | bellard | ret = s->rbr; |
1230 | 0824d6fc | bellard | s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); |
1231 | 0824d6fc | bellard | serial_update_irq(); |
1232 | 0824d6fc | bellard | } |
1233 | 0824d6fc | bellard | break;
|
1234 | 0824d6fc | bellard | case 1: |
1235 | 0824d6fc | bellard | if (s->lcr & UART_LCR_DLAB) {
|
1236 | 0824d6fc | bellard | ret = (s->divider >> 8) & 0xff; |
1237 | 0824d6fc | bellard | } else {
|
1238 | 0824d6fc | bellard | ret = s->ier; |
1239 | 0824d6fc | bellard | } |
1240 | 0824d6fc | bellard | break;
|
1241 | 0824d6fc | bellard | case 2: |
1242 | 0824d6fc | bellard | ret = s->iir; |
1243 | 0824d6fc | bellard | break;
|
1244 | 0824d6fc | bellard | case 3: |
1245 | 0824d6fc | bellard | ret = s->lcr; |
1246 | 0824d6fc | bellard | break;
|
1247 | 0824d6fc | bellard | case 4: |
1248 | 0824d6fc | bellard | ret = s->mcr; |
1249 | 0824d6fc | bellard | break;
|
1250 | 0824d6fc | bellard | case 5: |
1251 | 0824d6fc | bellard | ret = s->lsr; |
1252 | 0824d6fc | bellard | break;
|
1253 | 0824d6fc | bellard | case 6: |
1254 | 0824d6fc | bellard | ret = s->msr; |
1255 | 0824d6fc | bellard | break;
|
1256 | 0824d6fc | bellard | case 7: |
1257 | 0824d6fc | bellard | ret = s->scr; |
1258 | 0824d6fc | bellard | break;
|
1259 | 0824d6fc | bellard | } |
1260 | 0824d6fc | bellard | return ret;
|
1261 | 0824d6fc | bellard | } |
1262 | 0824d6fc | bellard | |
1263 | 0824d6fc | bellard | #define TERM_ESCAPE 0x01 /* ctrl-a is used for escape */ |
1264 | 0824d6fc | bellard | static int term_got_escape; |
1265 | 0824d6fc | bellard | |
1266 | 0824d6fc | bellard | void term_print_help(void) |
1267 | 0824d6fc | bellard | { |
1268 | 0824d6fc | bellard | printf("\n"
|
1269 | 0824d6fc | bellard | "C-a h print this help\n"
|
1270 | 0824d6fc | bellard | "C-a x exit emulatior\n"
|
1271 | 33e3963e | bellard | "C-a s save disk data back to file (if -snapshot)\n"
|
1272 | 0824d6fc | bellard | "C-a b send break (magic sysrq)\n"
|
1273 | 0824d6fc | bellard | "C-a C-a send C-a\n"
|
1274 | 0824d6fc | bellard | ); |
1275 | 0824d6fc | bellard | } |
1276 | 0824d6fc | bellard | |
1277 | 0824d6fc | bellard | /* called when a char is received */
|
1278 | 0824d6fc | bellard | void serial_received_byte(SerialState *s, int ch) |
1279 | 0824d6fc | bellard | { |
1280 | 0824d6fc | bellard | if (term_got_escape) {
|
1281 | 0824d6fc | bellard | term_got_escape = 0;
|
1282 | 0824d6fc | bellard | switch(ch) {
|
1283 | 0824d6fc | bellard | case 'h': |
1284 | 0824d6fc | bellard | term_print_help(); |
1285 | 0824d6fc | bellard | break;
|
1286 | 0824d6fc | bellard | case 'x': |
1287 | 0824d6fc | bellard | exit(0);
|
1288 | 0824d6fc | bellard | break;
|
1289 | 33e3963e | bellard | case 's': |
1290 | 33e3963e | bellard | { |
1291 | 33e3963e | bellard | int i;
|
1292 | 33e3963e | bellard | for (i = 0; i < MAX_DISKS; i++) { |
1293 | 33e3963e | bellard | if (bs_table[i])
|
1294 | 33e3963e | bellard | bdrv_commit(bs_table[i]); |
1295 | 33e3963e | bellard | } |
1296 | 33e3963e | bellard | } |
1297 | 33e3963e | bellard | break;
|
1298 | 0824d6fc | bellard | case 'b': |
1299 | 0824d6fc | bellard | /* send break */
|
1300 | 0824d6fc | bellard | s->rbr = 0;
|
1301 | 0824d6fc | bellard | s->lsr |= UART_LSR_BI | UART_LSR_DR; |
1302 | 0824d6fc | bellard | serial_update_irq(); |
1303 | 0824d6fc | bellard | break;
|
1304 | 0824d6fc | bellard | case TERM_ESCAPE:
|
1305 | 0824d6fc | bellard | goto send_char;
|
1306 | 0824d6fc | bellard | } |
1307 | 0824d6fc | bellard | } else if (ch == TERM_ESCAPE) { |
1308 | 0824d6fc | bellard | term_got_escape = 1;
|
1309 | 0824d6fc | bellard | } else {
|
1310 | 0824d6fc | bellard | send_char:
|
1311 | 0824d6fc | bellard | s->rbr = ch; |
1312 | 0824d6fc | bellard | s->lsr |= UART_LSR_DR; |
1313 | 0824d6fc | bellard | serial_update_irq(); |
1314 | 0824d6fc | bellard | } |
1315 | 0824d6fc | bellard | } |
1316 | 0824d6fc | bellard | |
1317 | 0824d6fc | bellard | /* init terminal so that we can grab keys */
|
1318 | 0824d6fc | bellard | static struct termios oldtty; |
1319 | 0824d6fc | bellard | |
1320 | 0824d6fc | bellard | static void term_exit(void) |
1321 | 0824d6fc | bellard | { |
1322 | 0824d6fc | bellard | tcsetattr (0, TCSANOW, &oldtty);
|
1323 | 0824d6fc | bellard | } |
1324 | 0824d6fc | bellard | |
1325 | 0824d6fc | bellard | static void term_init(void) |
1326 | 0824d6fc | bellard | { |
1327 | 0824d6fc | bellard | struct termios tty;
|
1328 | 0824d6fc | bellard | |
1329 | 0824d6fc | bellard | tcgetattr (0, &tty);
|
1330 | 0824d6fc | bellard | oldtty = tty; |
1331 | 0824d6fc | bellard | |
1332 | 0824d6fc | bellard | tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP |
1333 | 0824d6fc | bellard | |INLCR|IGNCR|ICRNL|IXON); |
1334 | 0824d6fc | bellard | tty.c_oflag |= OPOST; |
1335 | 0824d6fc | bellard | tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN|ISIG); |
1336 | 0824d6fc | bellard | tty.c_cflag &= ~(CSIZE|PARENB); |
1337 | 0824d6fc | bellard | tty.c_cflag |= CS8; |
1338 | 0824d6fc | bellard | tty.c_cc[VMIN] = 1;
|
1339 | 0824d6fc | bellard | tty.c_cc[VTIME] = 0;
|
1340 | 0824d6fc | bellard | |
1341 | 0824d6fc | bellard | tcsetattr (0, TCSANOW, &tty);
|
1342 | 0824d6fc | bellard | |
1343 | 0824d6fc | bellard | atexit(term_exit); |
1344 | 0824d6fc | bellard | |
1345 | 0824d6fc | bellard | fcntl(0, F_SETFL, O_NONBLOCK);
|
1346 | 0824d6fc | bellard | } |
1347 | 0824d6fc | bellard | |
1348 | 0824d6fc | bellard | void serial_init(void) |
1349 | 0824d6fc | bellard | { |
1350 | 0824d6fc | bellard | SerialState *s = &serial_ports[0];
|
1351 | 0824d6fc | bellard | |
1352 | 0824d6fc | bellard | s->lsr = UART_LSR_TEMT | UART_LSR_THRE; |
1353 | 0824d6fc | bellard | |
1354 | fc01f7e7 | bellard | register_ioport_write(0x3f8, 8, serial_ioport_write, 1); |
1355 | fc01f7e7 | bellard | register_ioport_read(0x3f8, 8, serial_ioport_read, 1); |
1356 | 0824d6fc | bellard | |
1357 | 0824d6fc | bellard | term_init(); |
1358 | 0824d6fc | bellard | } |
1359 | 0824d6fc | bellard | |
1360 | f1510b2c | bellard | /***********************************************************/
|
1361 | f1510b2c | bellard | /* ne2000 emulation */
|
1362 | f1510b2c | bellard | |
1363 | f1510b2c | bellard | //#define DEBUG_NE2000
|
1364 | f1510b2c | bellard | |
1365 | f1510b2c | bellard | #define NE2000_IOPORT 0x300 |
1366 | f1510b2c | bellard | #define NE2000_IRQ 9 |
1367 | f1510b2c | bellard | |
1368 | f1510b2c | bellard | #define MAX_ETH_FRAME_SIZE 1514 |
1369 | f1510b2c | bellard | |
1370 | f1510b2c | bellard | #define E8390_CMD 0x00 /* The command register (for all pages) */ |
1371 | f1510b2c | bellard | /* Page 0 register offsets. */
|
1372 | f1510b2c | bellard | #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
1373 | f1510b2c | bellard | #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
1374 | f1510b2c | bellard | #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
1375 | f1510b2c | bellard | #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
1376 | f1510b2c | bellard | #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
1377 | f1510b2c | bellard | #define EN0_TSR 0x04 /* Transmit status reg RD */ |
1378 | f1510b2c | bellard | #define EN0_TPSR 0x04 /* Transmit starting page WR */ |
1379 | f1510b2c | bellard | #define EN0_NCR 0x05 /* Number of collision reg RD */ |
1380 | f1510b2c | bellard | #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
1381 | f1510b2c | bellard | #define EN0_FIFO 0x06 /* FIFO RD */ |
1382 | f1510b2c | bellard | #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
1383 | f1510b2c | bellard | #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
1384 | f1510b2c | bellard | #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
1385 | f1510b2c | bellard | #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
1386 | f1510b2c | bellard | #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
1387 | f1510b2c | bellard | #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
1388 | f1510b2c | bellard | #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
1389 | f1510b2c | bellard | #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
1390 | f1510b2c | bellard | #define EN0_RSR 0x0c /* rx status reg RD */ |
1391 | f1510b2c | bellard | #define EN0_RXCR 0x0c /* RX configuration reg WR */ |
1392 | f1510b2c | bellard | #define EN0_TXCR 0x0d /* TX configuration reg WR */ |
1393 | f1510b2c | bellard | #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
1394 | f1510b2c | bellard | #define EN0_DCFG 0x0e /* Data configuration reg WR */ |
1395 | f1510b2c | bellard | #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
1396 | f1510b2c | bellard | #define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
1397 | f1510b2c | bellard | #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
1398 | f1510b2c | bellard | |
1399 | f1510b2c | bellard | #define EN1_PHYS 0x11 |
1400 | f1510b2c | bellard | #define EN1_CURPAG 0x17 |
1401 | f1510b2c | bellard | #define EN1_MULT 0x18 |
1402 | f1510b2c | bellard | |
1403 | f1510b2c | bellard | /* Register accessed at EN_CMD, the 8390 base addr. */
|
1404 | f1510b2c | bellard | #define E8390_STOP 0x01 /* Stop and reset the chip */ |
1405 | f1510b2c | bellard | #define E8390_START 0x02 /* Start the chip, clear reset */ |
1406 | f1510b2c | bellard | #define E8390_TRANS 0x04 /* Transmit a frame */ |
1407 | f1510b2c | bellard | #define E8390_RREAD 0x08 /* Remote read */ |
1408 | f1510b2c | bellard | #define E8390_RWRITE 0x10 /* Remote write */ |
1409 | f1510b2c | bellard | #define E8390_NODMA 0x20 /* Remote DMA */ |
1410 | f1510b2c | bellard | #define E8390_PAGE0 0x00 /* Select page chip registers */ |
1411 | f1510b2c | bellard | #define E8390_PAGE1 0x40 /* using the two high-order bits */ |
1412 | f1510b2c | bellard | #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
1413 | f1510b2c | bellard | |
1414 | f1510b2c | bellard | /* Bits in EN0_ISR - Interrupt status register */
|
1415 | f1510b2c | bellard | #define ENISR_RX 0x01 /* Receiver, no error */ |
1416 | f1510b2c | bellard | #define ENISR_TX 0x02 /* Transmitter, no error */ |
1417 | f1510b2c | bellard | #define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
1418 | f1510b2c | bellard | #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
1419 | f1510b2c | bellard | #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
1420 | f1510b2c | bellard | #define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
1421 | f1510b2c | bellard | #define ENISR_RDC 0x40 /* remote dma complete */ |
1422 | f1510b2c | bellard | #define ENISR_RESET 0x80 /* Reset completed */ |
1423 | f1510b2c | bellard | #define ENISR_ALL 0x3f /* Interrupts we will enable */ |
1424 | f1510b2c | bellard | |
1425 | f1510b2c | bellard | /* Bits in received packet status byte and EN0_RSR*/
|
1426 | f1510b2c | bellard | #define ENRSR_RXOK 0x01 /* Received a good packet */ |
1427 | f1510b2c | bellard | #define ENRSR_CRC 0x02 /* CRC error */ |
1428 | f1510b2c | bellard | #define ENRSR_FAE 0x04 /* frame alignment error */ |
1429 | f1510b2c | bellard | #define ENRSR_FO 0x08 /* FIFO overrun */ |
1430 | f1510b2c | bellard | #define ENRSR_MPA 0x10 /* missed pkt */ |
1431 | f1510b2c | bellard | #define ENRSR_PHY 0x20 /* physical/multicast address */ |
1432 | f1510b2c | bellard | #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
1433 | f1510b2c | bellard | #define ENRSR_DEF 0x80 /* deferring */ |
1434 | f1510b2c | bellard | |
1435 | f1510b2c | bellard | /* Transmitted packet status, EN0_TSR. */
|
1436 | f1510b2c | bellard | #define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
1437 | f1510b2c | bellard | #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
1438 | f1510b2c | bellard | #define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
1439 | f1510b2c | bellard | #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
1440 | f1510b2c | bellard | #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
1441 | f1510b2c | bellard | #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
1442 | f1510b2c | bellard | #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
1443 | f1510b2c | bellard | #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
1444 | f1510b2c | bellard | |
1445 | f1510b2c | bellard | #define NE2000_MEM_SIZE 32768 |
1446 | f1510b2c | bellard | |
1447 | f1510b2c | bellard | typedef struct NE2000State { |
1448 | f1510b2c | bellard | uint8_t cmd; |
1449 | f1510b2c | bellard | uint32_t start; |
1450 | f1510b2c | bellard | uint32_t stop; |
1451 | f1510b2c | bellard | uint8_t boundary; |
1452 | f1510b2c | bellard | uint8_t tsr; |
1453 | f1510b2c | bellard | uint8_t tpsr; |
1454 | f1510b2c | bellard | uint16_t tcnt; |
1455 | f1510b2c | bellard | uint16_t rcnt; |
1456 | f1510b2c | bellard | uint32_t rsar; |
1457 | f1510b2c | bellard | uint8_t isr; |
1458 | f1510b2c | bellard | uint8_t dcfg; |
1459 | f1510b2c | bellard | uint8_t imr; |
1460 | f1510b2c | bellard | uint8_t phys[6]; /* mac address */ |
1461 | f1510b2c | bellard | uint8_t curpag; |
1462 | f1510b2c | bellard | uint8_t mult[8]; /* multicast mask array */ |
1463 | f1510b2c | bellard | uint8_t mem[NE2000_MEM_SIZE]; |
1464 | f1510b2c | bellard | } NE2000State; |
1465 | f1510b2c | bellard | |
1466 | f1510b2c | bellard | NE2000State ne2000_state; |
1467 | f1510b2c | bellard | int net_fd = -1; |
1468 | f1510b2c | bellard | char network_script[1024]; |
1469 | f1510b2c | bellard | |
1470 | f1510b2c | bellard | void ne2000_reset(void) |
1471 | f1510b2c | bellard | { |
1472 | f1510b2c | bellard | NE2000State *s = &ne2000_state; |
1473 | f1510b2c | bellard | int i;
|
1474 | f1510b2c | bellard | |
1475 | f1510b2c | bellard | s->isr = ENISR_RESET; |
1476 | f1510b2c | bellard | s->mem[0] = 0x52; |
1477 | f1510b2c | bellard | s->mem[1] = 0x54; |
1478 | f1510b2c | bellard | s->mem[2] = 0x00; |
1479 | f1510b2c | bellard | s->mem[3] = 0x12; |
1480 | f1510b2c | bellard | s->mem[4] = 0x34; |
1481 | f1510b2c | bellard | s->mem[5] = 0x56; |
1482 | f1510b2c | bellard | s->mem[14] = 0x57; |
1483 | f1510b2c | bellard | s->mem[15] = 0x57; |
1484 | f1510b2c | bellard | |
1485 | f1510b2c | bellard | /* duplicate prom data */
|
1486 | f1510b2c | bellard | for(i = 15;i >= 0; i--) { |
1487 | f1510b2c | bellard | s->mem[2 * i] = s->mem[i];
|
1488 | f1510b2c | bellard | s->mem[2 * i + 1] = s->mem[i]; |
1489 | f1510b2c | bellard | } |
1490 | f1510b2c | bellard | } |
1491 | f1510b2c | bellard | |
1492 | f1510b2c | bellard | void ne2000_update_irq(NE2000State *s)
|
1493 | f1510b2c | bellard | { |
1494 | f1510b2c | bellard | int isr;
|
1495 | f1510b2c | bellard | isr = s->isr & s->imr; |
1496 | f1510b2c | bellard | if (isr)
|
1497 | f1510b2c | bellard | pic_set_irq(NE2000_IRQ, 1);
|
1498 | f1510b2c | bellard | else
|
1499 | f1510b2c | bellard | pic_set_irq(NE2000_IRQ, 0);
|
1500 | f1510b2c | bellard | } |
1501 | f1510b2c | bellard | |
1502 | f1510b2c | bellard | int net_init(void) |
1503 | f1510b2c | bellard | { |
1504 | f1510b2c | bellard | struct ifreq ifr;
|
1505 | f1510b2c | bellard | int fd, ret, pid, status;
|
1506 | f1510b2c | bellard | |
1507 | f1510b2c | bellard | fd = open("/dev/net/tun", O_RDWR);
|
1508 | f1510b2c | bellard | if (fd < 0) { |
1509 | f1510b2c | bellard | fprintf(stderr, "warning: could not open /dev/net/tun: no virtual network emulation\n");
|
1510 | f1510b2c | bellard | return -1; |
1511 | f1510b2c | bellard | } |
1512 | f1510b2c | bellard | memset(&ifr, 0, sizeof(ifr)); |
1513 | f1510b2c | bellard | ifr.ifr_flags = IFF_TAP | IFF_NO_PI; |
1514 | f1510b2c | bellard | pstrcpy(ifr.ifr_name, IFNAMSIZ, "tun%d");
|
1515 | f1510b2c | bellard | ret = ioctl(fd, TUNSETIFF, (void *) &ifr);
|
1516 | f1510b2c | bellard | if (ret != 0) { |
1517 | f1510b2c | bellard | fprintf(stderr, "warning: could not configure /dev/net/tun: no virtual network emulation\n");
|
1518 | f1510b2c | bellard | close(fd); |
1519 | f1510b2c | bellard | return -1; |
1520 | f1510b2c | bellard | } |
1521 | fc01f7e7 | bellard | printf("Connected to host network interface: %s\n", ifr.ifr_name);
|
1522 | f1510b2c | bellard | fcntl(fd, F_SETFL, O_NONBLOCK); |
1523 | f1510b2c | bellard | net_fd = fd; |
1524 | f1510b2c | bellard | |
1525 | f1510b2c | bellard | /* try to launch network init script */
|
1526 | f1510b2c | bellard | pid = fork(); |
1527 | f1510b2c | bellard | if (pid >= 0) { |
1528 | f1510b2c | bellard | if (pid == 0) { |
1529 | f1510b2c | bellard | execl(network_script, network_script, ifr.ifr_name, NULL);
|
1530 | f1510b2c | bellard | exit(1);
|
1531 | f1510b2c | bellard | } |
1532 | f1510b2c | bellard | while (waitpid(pid, &status, 0) != pid); |
1533 | f1510b2c | bellard | if (!WIFEXITED(status) ||
|
1534 | f1510b2c | bellard | WEXITSTATUS(status) != 0) {
|
1535 | f1510b2c | bellard | fprintf(stderr, "%s: could not launch network script for '%s'\n",
|
1536 | f1510b2c | bellard | network_script, ifr.ifr_name); |
1537 | f1510b2c | bellard | } |
1538 | f1510b2c | bellard | } |
1539 | f1510b2c | bellard | return 0; |
1540 | f1510b2c | bellard | } |
1541 | f1510b2c | bellard | |
1542 | f1510b2c | bellard | void net_send_packet(NE2000State *s, const uint8_t *buf, int size) |
1543 | f1510b2c | bellard | { |
1544 | f1510b2c | bellard | #ifdef DEBUG_NE2000
|
1545 | f1510b2c | bellard | printf("NE2000: sending packet size=%d\n", size);
|
1546 | f1510b2c | bellard | #endif
|
1547 | f1510b2c | bellard | write(net_fd, buf, size); |
1548 | f1510b2c | bellard | } |
1549 | f1510b2c | bellard | |
1550 | f1510b2c | bellard | /* return true if the NE2000 can receive more data */
|
1551 | f1510b2c | bellard | int ne2000_can_receive(NE2000State *s)
|
1552 | f1510b2c | bellard | { |
1553 | f1510b2c | bellard | int avail, index, boundary;
|
1554 | f1510b2c | bellard | |
1555 | f1510b2c | bellard | if (s->cmd & E8390_STOP)
|
1556 | f1510b2c | bellard | return 0; |
1557 | f1510b2c | bellard | index = s->curpag << 8;
|
1558 | f1510b2c | bellard | boundary = s->boundary << 8;
|
1559 | f1510b2c | bellard | if (index < boundary)
|
1560 | f1510b2c | bellard | avail = boundary - index; |
1561 | f1510b2c | bellard | else
|
1562 | f1510b2c | bellard | avail = (s->stop - s->start) - (index - boundary); |
1563 | f1510b2c | bellard | if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
1564 | f1510b2c | bellard | return 0; |
1565 | f1510b2c | bellard | return 1; |
1566 | f1510b2c | bellard | } |
1567 | f1510b2c | bellard | |
1568 | f1510b2c | bellard | void ne2000_receive(NE2000State *s, uint8_t *buf, int size) |
1569 | f1510b2c | bellard | { |
1570 | f1510b2c | bellard | uint8_t *p; |
1571 | f1510b2c | bellard | int total_len, next, avail, len, index;
|
1572 | f1510b2c | bellard | |
1573 | f1510b2c | bellard | #if defined(DEBUG_NE2000)
|
1574 | f1510b2c | bellard | printf("NE2000: received len=%d\n", size);
|
1575 | f1510b2c | bellard | #endif
|
1576 | f1510b2c | bellard | |
1577 | f1510b2c | bellard | index = s->curpag << 8;
|
1578 | f1510b2c | bellard | /* 4 bytes for header */
|
1579 | f1510b2c | bellard | total_len = size + 4;
|
1580 | f1510b2c | bellard | /* address for next packet (4 bytes for CRC) */
|
1581 | f1510b2c | bellard | next = index + ((total_len + 4 + 255) & ~0xff); |
1582 | f1510b2c | bellard | if (next >= s->stop)
|
1583 | f1510b2c | bellard | next -= (s->stop - s->start); |
1584 | f1510b2c | bellard | /* prepare packet header */
|
1585 | f1510b2c | bellard | p = s->mem + index; |
1586 | f1510b2c | bellard | p[0] = ENRSR_RXOK; /* receive status */ |
1587 | f1510b2c | bellard | p[1] = next >> 8; |
1588 | f1510b2c | bellard | p[2] = total_len;
|
1589 | f1510b2c | bellard | p[3] = total_len >> 8; |
1590 | f1510b2c | bellard | index += 4;
|
1591 | f1510b2c | bellard | |
1592 | f1510b2c | bellard | /* write packet data */
|
1593 | f1510b2c | bellard | while (size > 0) { |
1594 | f1510b2c | bellard | avail = s->stop - index; |
1595 | f1510b2c | bellard | len = size; |
1596 | f1510b2c | bellard | if (len > avail)
|
1597 | f1510b2c | bellard | len = avail; |
1598 | f1510b2c | bellard | memcpy(s->mem + index, buf, len); |
1599 | f1510b2c | bellard | buf += len; |
1600 | f1510b2c | bellard | index += len; |
1601 | f1510b2c | bellard | if (index == s->stop)
|
1602 | f1510b2c | bellard | index = s->start; |
1603 | f1510b2c | bellard | size -= len; |
1604 | f1510b2c | bellard | } |
1605 | f1510b2c | bellard | s->curpag = next >> 8;
|
1606 | f1510b2c | bellard | |
1607 | f1510b2c | bellard | /* now we can signal we have receive something */
|
1608 | f1510b2c | bellard | s->isr |= ENISR_RX; |
1609 | f1510b2c | bellard | ne2000_update_irq(s); |
1610 | f1510b2c | bellard | } |
1611 | f1510b2c | bellard | |
1612 | f1510b2c | bellard | void ne2000_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1613 | f1510b2c | bellard | { |
1614 | f1510b2c | bellard | NE2000State *s = &ne2000_state; |
1615 | f1510b2c | bellard | int offset, page;
|
1616 | f1510b2c | bellard | |
1617 | f1510b2c | bellard | addr &= 0xf;
|
1618 | f1510b2c | bellard | #ifdef DEBUG_NE2000
|
1619 | f1510b2c | bellard | printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
|
1620 | f1510b2c | bellard | #endif
|
1621 | f1510b2c | bellard | if (addr == E8390_CMD) {
|
1622 | f1510b2c | bellard | /* control register */
|
1623 | f1510b2c | bellard | s->cmd = val; |
1624 | f1510b2c | bellard | if (val & E8390_START) {
|
1625 | f1510b2c | bellard | /* test specific case: zero length transfert */
|
1626 | f1510b2c | bellard | if ((val & (E8390_RREAD | E8390_RWRITE)) &&
|
1627 | f1510b2c | bellard | s->rcnt == 0) {
|
1628 | f1510b2c | bellard | s->isr |= ENISR_RDC; |
1629 | f1510b2c | bellard | ne2000_update_irq(s); |
1630 | f1510b2c | bellard | } |
1631 | f1510b2c | bellard | if (val & E8390_TRANS) {
|
1632 | f1510b2c | bellard | net_send_packet(s, s->mem + (s->tpsr << 8), s->tcnt);
|
1633 | f1510b2c | bellard | /* signal end of transfert */
|
1634 | f1510b2c | bellard | s->tsr = ENTSR_PTX; |
1635 | f1510b2c | bellard | s->isr |= ENISR_TX; |
1636 | f1510b2c | bellard | ne2000_update_irq(s); |
1637 | f1510b2c | bellard | } |
1638 | f1510b2c | bellard | } |
1639 | f1510b2c | bellard | } else {
|
1640 | f1510b2c | bellard | page = s->cmd >> 6;
|
1641 | f1510b2c | bellard | offset = addr | (page << 4);
|
1642 | f1510b2c | bellard | switch(offset) {
|
1643 | f1510b2c | bellard | case EN0_STARTPG:
|
1644 | f1510b2c | bellard | s->start = val << 8;
|
1645 | f1510b2c | bellard | break;
|
1646 | f1510b2c | bellard | case EN0_STOPPG:
|
1647 | f1510b2c | bellard | s->stop = val << 8;
|
1648 | f1510b2c | bellard | break;
|
1649 | f1510b2c | bellard | case EN0_BOUNDARY:
|
1650 | f1510b2c | bellard | s->boundary = val; |
1651 | f1510b2c | bellard | break;
|
1652 | f1510b2c | bellard | case EN0_IMR:
|
1653 | f1510b2c | bellard | s->imr = val; |
1654 | f1510b2c | bellard | ne2000_update_irq(s); |
1655 | f1510b2c | bellard | break;
|
1656 | f1510b2c | bellard | case EN0_TPSR:
|
1657 | f1510b2c | bellard | s->tpsr = val; |
1658 | f1510b2c | bellard | break;
|
1659 | f1510b2c | bellard | case EN0_TCNTLO:
|
1660 | f1510b2c | bellard | s->tcnt = (s->tcnt & 0xff00) | val;
|
1661 | f1510b2c | bellard | break;
|
1662 | f1510b2c | bellard | case EN0_TCNTHI:
|
1663 | f1510b2c | bellard | s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
1664 | f1510b2c | bellard | break;
|
1665 | f1510b2c | bellard | case EN0_RSARLO:
|
1666 | f1510b2c | bellard | s->rsar = (s->rsar & 0xff00) | val;
|
1667 | f1510b2c | bellard | break;
|
1668 | f1510b2c | bellard | case EN0_RSARHI:
|
1669 | f1510b2c | bellard | s->rsar = (s->rsar & 0x00ff) | (val << 8); |
1670 | f1510b2c | bellard | break;
|
1671 | f1510b2c | bellard | case EN0_RCNTLO:
|
1672 | f1510b2c | bellard | s->rcnt = (s->rcnt & 0xff00) | val;
|
1673 | f1510b2c | bellard | break;
|
1674 | f1510b2c | bellard | case EN0_RCNTHI:
|
1675 | f1510b2c | bellard | s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
1676 | f1510b2c | bellard | break;
|
1677 | f1510b2c | bellard | case EN0_DCFG:
|
1678 | f1510b2c | bellard | s->dcfg = val; |
1679 | f1510b2c | bellard | break;
|
1680 | f1510b2c | bellard | case EN0_ISR:
|
1681 | f1510b2c | bellard | s->isr &= ~val; |
1682 | f1510b2c | bellard | ne2000_update_irq(s); |
1683 | f1510b2c | bellard | break;
|
1684 | f1510b2c | bellard | case EN1_PHYS ... EN1_PHYS + 5: |
1685 | f1510b2c | bellard | s->phys[offset - EN1_PHYS] = val; |
1686 | f1510b2c | bellard | break;
|
1687 | f1510b2c | bellard | case EN1_CURPAG:
|
1688 | f1510b2c | bellard | s->curpag = val; |
1689 | f1510b2c | bellard | break;
|
1690 | f1510b2c | bellard | case EN1_MULT ... EN1_MULT + 7: |
1691 | f1510b2c | bellard | s->mult[offset - EN1_MULT] = val; |
1692 | f1510b2c | bellard | break;
|
1693 | f1510b2c | bellard | } |
1694 | f1510b2c | bellard | } |
1695 | f1510b2c | bellard | } |
1696 | f1510b2c | bellard | |
1697 | f1510b2c | bellard | uint32_t ne2000_ioport_read(CPUX86State *env, uint32_t addr) |
1698 | f1510b2c | bellard | { |
1699 | f1510b2c | bellard | NE2000State *s = &ne2000_state; |
1700 | f1510b2c | bellard | int offset, page, ret;
|
1701 | f1510b2c | bellard | |
1702 | f1510b2c | bellard | addr &= 0xf;
|
1703 | f1510b2c | bellard | if (addr == E8390_CMD) {
|
1704 | f1510b2c | bellard | ret = s->cmd; |
1705 | f1510b2c | bellard | } else {
|
1706 | f1510b2c | bellard | page = s->cmd >> 6;
|
1707 | f1510b2c | bellard | offset = addr | (page << 4);
|
1708 | f1510b2c | bellard | switch(offset) {
|
1709 | f1510b2c | bellard | case EN0_TSR:
|
1710 | f1510b2c | bellard | ret = s->tsr; |
1711 | f1510b2c | bellard | break;
|
1712 | f1510b2c | bellard | case EN0_BOUNDARY:
|
1713 | f1510b2c | bellard | ret = s->boundary; |
1714 | f1510b2c | bellard | break;
|
1715 | f1510b2c | bellard | case EN0_ISR:
|
1716 | f1510b2c | bellard | ret = s->isr; |
1717 | f1510b2c | bellard | break;
|
1718 | f1510b2c | bellard | case EN1_PHYS ... EN1_PHYS + 5: |
1719 | f1510b2c | bellard | ret = s->phys[offset - EN1_PHYS]; |
1720 | f1510b2c | bellard | break;
|
1721 | f1510b2c | bellard | case EN1_CURPAG:
|
1722 | f1510b2c | bellard | ret = s->curpag; |
1723 | f1510b2c | bellard | break;
|
1724 | f1510b2c | bellard | case EN1_MULT ... EN1_MULT + 7: |
1725 | f1510b2c | bellard | ret = s->mult[offset - EN1_MULT]; |
1726 | f1510b2c | bellard | break;
|
1727 | f1510b2c | bellard | default:
|
1728 | f1510b2c | bellard | ret = 0x00;
|
1729 | f1510b2c | bellard | break;
|
1730 | f1510b2c | bellard | } |
1731 | f1510b2c | bellard | } |
1732 | f1510b2c | bellard | #ifdef DEBUG_NE2000
|
1733 | f1510b2c | bellard | printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
|
1734 | f1510b2c | bellard | #endif
|
1735 | f1510b2c | bellard | return ret;
|
1736 | f1510b2c | bellard | } |
1737 | f1510b2c | bellard | |
1738 | f1510b2c | bellard | void ne2000_asic_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1739 | f1510b2c | bellard | { |
1740 | f1510b2c | bellard | NE2000State *s = &ne2000_state; |
1741 | f1510b2c | bellard | uint8_t *p; |
1742 | f1510b2c | bellard | |
1743 | f1510b2c | bellard | #ifdef DEBUG_NE2000
|
1744 | f1510b2c | bellard | printf("NE2000: asic write val=0x%04x\n", val);
|
1745 | f1510b2c | bellard | #endif
|
1746 | f1510b2c | bellard | p = s->mem + s->rsar; |
1747 | f1510b2c | bellard | if (s->dcfg & 0x01) { |
1748 | f1510b2c | bellard | /* 16 bit access */
|
1749 | f1510b2c | bellard | p[0] = val;
|
1750 | f1510b2c | bellard | p[1] = val >> 8; |
1751 | f1510b2c | bellard | s->rsar += 2;
|
1752 | f1510b2c | bellard | s->rcnt -= 2;
|
1753 | f1510b2c | bellard | } else {
|
1754 | f1510b2c | bellard | /* 8 bit access */
|
1755 | f1510b2c | bellard | p[0] = val;
|
1756 | f1510b2c | bellard | s->rsar++; |
1757 | f1510b2c | bellard | s->rcnt--; |
1758 | f1510b2c | bellard | } |
1759 | f1510b2c | bellard | /* wrap */
|
1760 | f1510b2c | bellard | if (s->rsar == s->stop)
|
1761 | f1510b2c | bellard | s->rsar = s->start; |
1762 | f1510b2c | bellard | if (s->rcnt == 0) { |
1763 | f1510b2c | bellard | /* signal end of transfert */
|
1764 | f1510b2c | bellard | s->isr |= ENISR_RDC; |
1765 | f1510b2c | bellard | ne2000_update_irq(s); |
1766 | f1510b2c | bellard | } |
1767 | f1510b2c | bellard | } |
1768 | f1510b2c | bellard | |
1769 | f1510b2c | bellard | uint32_t ne2000_asic_ioport_read(CPUX86State *env, uint32_t addr) |
1770 | f1510b2c | bellard | { |
1771 | f1510b2c | bellard | NE2000State *s = &ne2000_state; |
1772 | f1510b2c | bellard | uint8_t *p; |
1773 | f1510b2c | bellard | int ret;
|
1774 | f1510b2c | bellard | |
1775 | f1510b2c | bellard | p = s->mem + s->rsar; |
1776 | f1510b2c | bellard | if (s->dcfg & 0x01) { |
1777 | f1510b2c | bellard | /* 16 bit access */
|
1778 | f1510b2c | bellard | ret = p[0] | (p[1] << 8); |
1779 | f1510b2c | bellard | s->rsar += 2;
|
1780 | f1510b2c | bellard | s->rcnt -= 2;
|
1781 | f1510b2c | bellard | } else {
|
1782 | f1510b2c | bellard | /* 8 bit access */
|
1783 | f1510b2c | bellard | ret = p[0];
|
1784 | f1510b2c | bellard | s->rsar++; |
1785 | f1510b2c | bellard | s->rcnt--; |
1786 | f1510b2c | bellard | } |
1787 | f1510b2c | bellard | /* wrap */
|
1788 | f1510b2c | bellard | if (s->rsar == s->stop)
|
1789 | f1510b2c | bellard | s->rsar = s->start; |
1790 | f1510b2c | bellard | if (s->rcnt == 0) { |
1791 | f1510b2c | bellard | /* signal end of transfert */
|
1792 | f1510b2c | bellard | s->isr |= ENISR_RDC; |
1793 | f1510b2c | bellard | ne2000_update_irq(s); |
1794 | f1510b2c | bellard | } |
1795 | f1510b2c | bellard | #ifdef DEBUG_NE2000
|
1796 | f1510b2c | bellard | printf("NE2000: asic read val=0x%04x\n", ret);
|
1797 | f1510b2c | bellard | #endif
|
1798 | f1510b2c | bellard | return ret;
|
1799 | f1510b2c | bellard | } |
1800 | f1510b2c | bellard | |
1801 | f1510b2c | bellard | void ne2000_reset_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
1802 | f1510b2c | bellard | { |
1803 | f1510b2c | bellard | /* nothing to do (end of reset pulse) */
|
1804 | f1510b2c | bellard | } |
1805 | f1510b2c | bellard | |
1806 | f1510b2c | bellard | uint32_t ne2000_reset_ioport_read(CPUX86State *env, uint32_t addr) |
1807 | f1510b2c | bellard | { |
1808 | f1510b2c | bellard | ne2000_reset(); |
1809 | f1510b2c | bellard | return 0; |
1810 | f1510b2c | bellard | } |
1811 | f1510b2c | bellard | |
1812 | f1510b2c | bellard | void ne2000_init(void) |
1813 | f1510b2c | bellard | { |
1814 | fc01f7e7 | bellard | register_ioport_write(NE2000_IOPORT, 16, ne2000_ioport_write, 1); |
1815 | fc01f7e7 | bellard | register_ioport_read(NE2000_IOPORT, 16, ne2000_ioport_read, 1); |
1816 | f1510b2c | bellard | |
1817 | fc01f7e7 | bellard | register_ioport_write(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_write, 1); |
1818 | fc01f7e7 | bellard | register_ioport_read(NE2000_IOPORT + 0x10, 1, ne2000_asic_ioport_read, 1); |
1819 | fc01f7e7 | bellard | register_ioport_write(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_write, 2); |
1820 | fc01f7e7 | bellard | register_ioport_read(NE2000_IOPORT + 0x10, 2, ne2000_asic_ioport_read, 2); |
1821 | f1510b2c | bellard | |
1822 | fc01f7e7 | bellard | register_ioport_write(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_write, 1); |
1823 | fc01f7e7 | bellard | register_ioport_read(NE2000_IOPORT + 0x1f, 1, ne2000_reset_ioport_read, 1); |
1824 | f1510b2c | bellard | ne2000_reset(); |
1825 | f1510b2c | bellard | } |
1826 | f1510b2c | bellard | |
1827 | f1510b2c | bellard | /***********************************************************/
|
1828 | fc01f7e7 | bellard | /* ide emulation */
|
1829 | fc01f7e7 | bellard | |
1830 | fc01f7e7 | bellard | //#define DEBUG_IDE
|
1831 | fc01f7e7 | bellard | |
1832 | fc01f7e7 | bellard | /* Bits of HD_STATUS */
|
1833 | fc01f7e7 | bellard | #define ERR_STAT 0x01 |
1834 | fc01f7e7 | bellard | #define INDEX_STAT 0x02 |
1835 | fc01f7e7 | bellard | #define ECC_STAT 0x04 /* Corrected error */ |
1836 | fc01f7e7 | bellard | #define DRQ_STAT 0x08 |
1837 | fc01f7e7 | bellard | #define SEEK_STAT 0x10 |
1838 | fc01f7e7 | bellard | #define SRV_STAT 0x10 |
1839 | fc01f7e7 | bellard | #define WRERR_STAT 0x20 |
1840 | fc01f7e7 | bellard | #define READY_STAT 0x40 |
1841 | fc01f7e7 | bellard | #define BUSY_STAT 0x80 |
1842 | fc01f7e7 | bellard | |
1843 | fc01f7e7 | bellard | /* Bits for HD_ERROR */
|
1844 | fc01f7e7 | bellard | #define MARK_ERR 0x01 /* Bad address mark */ |
1845 | fc01f7e7 | bellard | #define TRK0_ERR 0x02 /* couldn't find track 0 */ |
1846 | fc01f7e7 | bellard | #define ABRT_ERR 0x04 /* Command aborted */ |
1847 | fc01f7e7 | bellard | #define MCR_ERR 0x08 /* media change request */ |
1848 | fc01f7e7 | bellard | #define ID_ERR 0x10 /* ID field not found */ |
1849 | fc01f7e7 | bellard | #define MC_ERR 0x20 /* media changed */ |
1850 | fc01f7e7 | bellard | #define ECC_ERR 0x40 /* Uncorrectable ECC error */ |
1851 | fc01f7e7 | bellard | #define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */ |
1852 | fc01f7e7 | bellard | #define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */ |
1853 | fc01f7e7 | bellard | |
1854 | fc01f7e7 | bellard | /* Bits of HD_NSECTOR */
|
1855 | fc01f7e7 | bellard | #define CD 0x01 |
1856 | fc01f7e7 | bellard | #define IO 0x02 |
1857 | fc01f7e7 | bellard | #define REL 0x04 |
1858 | fc01f7e7 | bellard | #define TAG_MASK 0xf8 |
1859 | fc01f7e7 | bellard | |
1860 | fc01f7e7 | bellard | #define IDE_CMD_RESET 0x04 |
1861 | fc01f7e7 | bellard | #define IDE_CMD_DISABLE_IRQ 0x02 |
1862 | fc01f7e7 | bellard | |
1863 | fc01f7e7 | bellard | /* ATA/ATAPI Commands pre T13 Spec */
|
1864 | fc01f7e7 | bellard | #define WIN_NOP 0x00 |
1865 | fc01f7e7 | bellard | /*
|
1866 | fc01f7e7 | bellard | * 0x01->0x02 Reserved
|
1867 | fc01f7e7 | bellard | */
|
1868 | fc01f7e7 | bellard | #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */ |
1869 | fc01f7e7 | bellard | /*
|
1870 | fc01f7e7 | bellard | * 0x04->0x07 Reserved
|
1871 | fc01f7e7 | bellard | */
|
1872 | fc01f7e7 | bellard | #define WIN_SRST 0x08 /* ATAPI soft reset command */ |
1873 | fc01f7e7 | bellard | #define WIN_DEVICE_RESET 0x08 |
1874 | fc01f7e7 | bellard | /*
|
1875 | fc01f7e7 | bellard | * 0x09->0x0F Reserved
|
1876 | fc01f7e7 | bellard | */
|
1877 | fc01f7e7 | bellard | #define WIN_RECAL 0x10 |
1878 | fc01f7e7 | bellard | #define WIN_RESTORE WIN_RECAL
|
1879 | fc01f7e7 | bellard | /*
|
1880 | fc01f7e7 | bellard | * 0x10->0x1F Reserved
|
1881 | fc01f7e7 | bellard | */
|
1882 | fc01f7e7 | bellard | #define WIN_READ 0x20 /* 28-Bit */ |
1883 | fc01f7e7 | bellard | #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */ |
1884 | fc01f7e7 | bellard | #define WIN_READ_LONG 0x22 /* 28-Bit */ |
1885 | fc01f7e7 | bellard | #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */ |
1886 | fc01f7e7 | bellard | #define WIN_READ_EXT 0x24 /* 48-Bit */ |
1887 | fc01f7e7 | bellard | #define WIN_READDMA_EXT 0x25 /* 48-Bit */ |
1888 | fc01f7e7 | bellard | #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */ |
1889 | fc01f7e7 | bellard | #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */ |
1890 | fc01f7e7 | bellard | /*
|
1891 | fc01f7e7 | bellard | * 0x28
|
1892 | fc01f7e7 | bellard | */
|
1893 | fc01f7e7 | bellard | #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */ |
1894 | fc01f7e7 | bellard | /*
|
1895 | fc01f7e7 | bellard | * 0x2A->0x2F Reserved
|
1896 | fc01f7e7 | bellard | */
|
1897 | fc01f7e7 | bellard | #define WIN_WRITE 0x30 /* 28-Bit */ |
1898 | fc01f7e7 | bellard | #define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */ |
1899 | fc01f7e7 | bellard | #define WIN_WRITE_LONG 0x32 /* 28-Bit */ |
1900 | fc01f7e7 | bellard | #define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */ |
1901 | fc01f7e7 | bellard | #define WIN_WRITE_EXT 0x34 /* 48-Bit */ |
1902 | fc01f7e7 | bellard | #define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */ |
1903 | fc01f7e7 | bellard | #define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */ |
1904 | fc01f7e7 | bellard | #define WIN_SET_MAX_EXT 0x37 /* 48-Bit */ |
1905 | fc01f7e7 | bellard | #define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */ |
1906 | fc01f7e7 | bellard | #define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */ |
1907 | fc01f7e7 | bellard | /*
|
1908 | fc01f7e7 | bellard | * 0x3A->0x3B Reserved
|
1909 | fc01f7e7 | bellard | */
|
1910 | fc01f7e7 | bellard | #define WIN_WRITE_VERIFY 0x3C /* 28-Bit */ |
1911 | fc01f7e7 | bellard | /*
|
1912 | fc01f7e7 | bellard | * 0x3D->0x3F Reserved
|
1913 | fc01f7e7 | bellard | */
|
1914 | fc01f7e7 | bellard | #define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */ |
1915 | fc01f7e7 | bellard | #define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */ |
1916 | fc01f7e7 | bellard | #define WIN_VERIFY_EXT 0x42 /* 48-Bit */ |
1917 | fc01f7e7 | bellard | /*
|
1918 | fc01f7e7 | bellard | * 0x43->0x4F Reserved
|
1919 | fc01f7e7 | bellard | */
|
1920 | fc01f7e7 | bellard | #define WIN_FORMAT 0x50 |
1921 | fc01f7e7 | bellard | /*
|
1922 | fc01f7e7 | bellard | * 0x51->0x5F Reserved
|
1923 | fc01f7e7 | bellard | */
|
1924 | fc01f7e7 | bellard | #define WIN_INIT 0x60 |
1925 | fc01f7e7 | bellard | /*
|
1926 | fc01f7e7 | bellard | * 0x61->0x5F Reserved
|
1927 | fc01f7e7 | bellard | */
|
1928 | fc01f7e7 | bellard | #define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */ |
1929 | fc01f7e7 | bellard | #define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */ |
1930 | fc01f7e7 | bellard | #define WIN_DIAGNOSE 0x90 |
1931 | fc01f7e7 | bellard | #define WIN_SPECIFY 0x91 /* set drive geometry translation */ |
1932 | fc01f7e7 | bellard | #define WIN_DOWNLOAD_MICROCODE 0x92 |
1933 | fc01f7e7 | bellard | #define WIN_STANDBYNOW2 0x94 |
1934 | fc01f7e7 | bellard | #define WIN_STANDBY2 0x96 |
1935 | fc01f7e7 | bellard | #define WIN_SETIDLE2 0x97 |
1936 | fc01f7e7 | bellard | #define WIN_CHECKPOWERMODE2 0x98 |
1937 | fc01f7e7 | bellard | #define WIN_SLEEPNOW2 0x99 |
1938 | fc01f7e7 | bellard | /*
|
1939 | fc01f7e7 | bellard | * 0x9A VENDOR
|
1940 | fc01f7e7 | bellard | */
|
1941 | fc01f7e7 | bellard | #define WIN_PACKETCMD 0xA0 /* Send a packet command. */ |
1942 | fc01f7e7 | bellard | #define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */ |
1943 | fc01f7e7 | bellard | #define WIN_QUEUED_SERVICE 0xA2 |
1944 | fc01f7e7 | bellard | #define WIN_SMART 0xB0 /* self-monitoring and reporting */ |
1945 | fc01f7e7 | bellard | #define CFA_ERASE_SECTORS 0xC0 |
1946 | fc01f7e7 | bellard | #define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/ |
1947 | fc01f7e7 | bellard | #define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */ |
1948 | fc01f7e7 | bellard | #define WIN_SETMULT 0xC6 /* enable/disable multiple mode */ |
1949 | fc01f7e7 | bellard | #define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */ |
1950 | fc01f7e7 | bellard | #define WIN_READDMA 0xC8 /* read sectors using DMA transfers */ |
1951 | fc01f7e7 | bellard | #define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */ |
1952 | fc01f7e7 | bellard | #define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */ |
1953 | fc01f7e7 | bellard | #define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */ |
1954 | fc01f7e7 | bellard | #define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */ |
1955 | fc01f7e7 | bellard | #define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */ |
1956 | fc01f7e7 | bellard | #define WIN_GETMEDIASTATUS 0xDA |
1957 | fc01f7e7 | bellard | #define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */ |
1958 | fc01f7e7 | bellard | #define WIN_POSTBOOT 0xDC |
1959 | fc01f7e7 | bellard | #define WIN_PREBOOT 0xDD |
1960 | fc01f7e7 | bellard | #define WIN_DOORLOCK 0xDE /* lock door on removable drives */ |
1961 | fc01f7e7 | bellard | #define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */ |
1962 | fc01f7e7 | bellard | #define WIN_STANDBYNOW1 0xE0 |
1963 | fc01f7e7 | bellard | #define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */ |
1964 | fc01f7e7 | bellard | #define WIN_STANDBY 0xE2 /* Set device in Standby Mode */ |
1965 | fc01f7e7 | bellard | #define WIN_SETIDLE1 0xE3 |
1966 | fc01f7e7 | bellard | #define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */ |
1967 | fc01f7e7 | bellard | #define WIN_CHECKPOWERMODE1 0xE5 |
1968 | fc01f7e7 | bellard | #define WIN_SLEEPNOW1 0xE6 |
1969 | fc01f7e7 | bellard | #define WIN_FLUSH_CACHE 0xE7 |
1970 | fc01f7e7 | bellard | #define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */ |
1971 | fc01f7e7 | bellard | #define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */ |
1972 | fc01f7e7 | bellard | /* SET_FEATURES 0x22 or 0xDD */
|
1973 | fc01f7e7 | bellard | #define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */ |
1974 | fc01f7e7 | bellard | #define WIN_IDENTIFY 0xEC /* ask drive to identify itself */ |
1975 | fc01f7e7 | bellard | #define WIN_MEDIAEJECT 0xED |
1976 | fc01f7e7 | bellard | #define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */ |
1977 | fc01f7e7 | bellard | #define WIN_SETFEATURES 0xEF /* set special drive features */ |
1978 | fc01f7e7 | bellard | #define EXABYTE_ENABLE_NEST 0xF0 |
1979 | fc01f7e7 | bellard | #define WIN_SECURITY_SET_PASS 0xF1 |
1980 | fc01f7e7 | bellard | #define WIN_SECURITY_UNLOCK 0xF2 |
1981 | fc01f7e7 | bellard | #define WIN_SECURITY_ERASE_PREPARE 0xF3 |
1982 | fc01f7e7 | bellard | #define WIN_SECURITY_ERASE_UNIT 0xF4 |
1983 | fc01f7e7 | bellard | #define WIN_SECURITY_FREEZE_LOCK 0xF5 |
1984 | fc01f7e7 | bellard | #define WIN_SECURITY_DISABLE 0xF6 |
1985 | fc01f7e7 | bellard | #define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */ |
1986 | fc01f7e7 | bellard | #define WIN_SET_MAX 0xF9 |
1987 | fc01f7e7 | bellard | #define DISABLE_SEAGATE 0xFB |
1988 | fc01f7e7 | bellard | |
1989 | c9159e53 | bellard | /* set to 1 set disable mult support */
|
1990 | c9159e53 | bellard | #define MAX_MULT_SECTORS 8 |
1991 | fc01f7e7 | bellard | |
1992 | fc01f7e7 | bellard | struct IDEState;
|
1993 | fc01f7e7 | bellard | |
1994 | fc01f7e7 | bellard | typedef void EndTransferFunc(struct IDEState *); |
1995 | fc01f7e7 | bellard | |
1996 | fc01f7e7 | bellard | typedef struct IDEState { |
1997 | fc01f7e7 | bellard | /* ide config */
|
1998 | fc01f7e7 | bellard | int cylinders, heads, sectors;
|
1999 | fc01f7e7 | bellard | int64_t nb_sectors; |
2000 | fc01f7e7 | bellard | int mult_sectors;
|
2001 | fc01f7e7 | bellard | int irq;
|
2002 | fc01f7e7 | bellard | /* ide regs */
|
2003 | fc01f7e7 | bellard | uint8_t feature; |
2004 | fc01f7e7 | bellard | uint8_t error; |
2005 | c9159e53 | bellard | uint16_t nsector; /* 0 is 256 to ease computations */
|
2006 | fc01f7e7 | bellard | uint8_t sector; |
2007 | fc01f7e7 | bellard | uint8_t lcyl; |
2008 | fc01f7e7 | bellard | uint8_t hcyl; |
2009 | fc01f7e7 | bellard | uint8_t select; |
2010 | fc01f7e7 | bellard | uint8_t status; |
2011 | fc01f7e7 | bellard | /* 0x3f6 command, only meaningful for drive 0 */
|
2012 | fc01f7e7 | bellard | uint8_t cmd; |
2013 | fc01f7e7 | bellard | /* depends on bit 4 in select, only meaningful for drive 0 */
|
2014 | fc01f7e7 | bellard | struct IDEState *cur_drive;
|
2015 | fc01f7e7 | bellard | BlockDriverState *bs; |
2016 | c9159e53 | bellard | int req_nb_sectors; /* number of sectors per interrupt */ |
2017 | fc01f7e7 | bellard | EndTransferFunc *end_transfer_func; |
2018 | fc01f7e7 | bellard | uint8_t *data_ptr; |
2019 | fc01f7e7 | bellard | uint8_t *data_end; |
2020 | fc01f7e7 | bellard | uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4]; |
2021 | fc01f7e7 | bellard | } IDEState; |
2022 | fc01f7e7 | bellard | |
2023 | fc01f7e7 | bellard | IDEState ide_state[MAX_DISKS]; |
2024 | fc01f7e7 | bellard | |
2025 | fc01f7e7 | bellard | static void padstr(char *str, const char *src, int len) |
2026 | fc01f7e7 | bellard | { |
2027 | fc01f7e7 | bellard | int i, v;
|
2028 | fc01f7e7 | bellard | for(i = 0; i < len; i++) { |
2029 | fc01f7e7 | bellard | if (*src)
|
2030 | fc01f7e7 | bellard | v = *src++; |
2031 | fc01f7e7 | bellard | else
|
2032 | fc01f7e7 | bellard | v = ' ';
|
2033 | fc01f7e7 | bellard | *(char *)((long)str ^ 1) = v; |
2034 | fc01f7e7 | bellard | str++; |
2035 | fc01f7e7 | bellard | } |
2036 | fc01f7e7 | bellard | } |
2037 | fc01f7e7 | bellard | |
2038 | fc01f7e7 | bellard | static void ide_identify(IDEState *s) |
2039 | fc01f7e7 | bellard | { |
2040 | fc01f7e7 | bellard | uint16_t *p; |
2041 | fc01f7e7 | bellard | unsigned int oldsize; |
2042 | fc01f7e7 | bellard | |
2043 | fc01f7e7 | bellard | memset(s->io_buffer, 0, 512); |
2044 | fc01f7e7 | bellard | p = (uint16_t *)s->io_buffer; |
2045 | fc01f7e7 | bellard | stw(p + 0, 0x0040); |
2046 | fc01f7e7 | bellard | stw(p + 1, s->cylinders);
|
2047 | fc01f7e7 | bellard | stw(p + 3, s->heads);
|
2048 | fc01f7e7 | bellard | stw(p + 4, 512 * s->sectors); /* sectors */ |
2049 | fc01f7e7 | bellard | stw(p + 5, 512); /* sector size */ |
2050 | fc01f7e7 | bellard | stw(p + 6, s->sectors);
|
2051 | fc01f7e7 | bellard | stw(p + 20, 3); /* buffer type */ |
2052 | fc01f7e7 | bellard | stw(p + 21, 512); /* cache size in sectors */ |
2053 | fc01f7e7 | bellard | stw(p + 22, 4); /* ecc bytes */ |
2054 | fc01f7e7 | bellard | padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40); |
2055 | c9159e53 | bellard | #if MAX_MULT_SECTORS > 1 |
2056 | c9159e53 | bellard | stw(p + 47, MAX_MULT_SECTORS);
|
2057 | c9159e53 | bellard | #endif
|
2058 | fc01f7e7 | bellard | stw(p + 48, 1); /* dword I/O */ |
2059 | fc01f7e7 | bellard | stw(p + 49, 1 << 9); /* LBA supported, no DMA */ |
2060 | fc01f7e7 | bellard | stw(p + 51, 0x200); /* PIO transfer cycle */ |
2061 | fc01f7e7 | bellard | stw(p + 52, 0x200); /* DMA transfer cycle */ |
2062 | fc01f7e7 | bellard | stw(p + 54, s->cylinders);
|
2063 | fc01f7e7 | bellard | stw(p + 55, s->heads);
|
2064 | fc01f7e7 | bellard | stw(p + 56, s->sectors);
|
2065 | fc01f7e7 | bellard | oldsize = s->cylinders * s->heads * s->sectors; |
2066 | fc01f7e7 | bellard | stw(p + 57, oldsize);
|
2067 | fc01f7e7 | bellard | stw(p + 58, oldsize >> 16); |
2068 | fc01f7e7 | bellard | if (s->mult_sectors)
|
2069 | fc01f7e7 | bellard | stw(p + 59, 0x100 | s->mult_sectors); |
2070 | fc01f7e7 | bellard | stw(p + 60, s->nb_sectors);
|
2071 | fc01f7e7 | bellard | stw(p + 61, s->nb_sectors >> 16); |
2072 | fc01f7e7 | bellard | stw(p + 80, (1 << 1) | (1 << 2)); |
2073 | fc01f7e7 | bellard | stw(p + 82, (1 << 14)); |
2074 | fc01f7e7 | bellard | stw(p + 83, (1 << 14)); |
2075 | fc01f7e7 | bellard | stw(p + 84, (1 << 14)); |
2076 | fc01f7e7 | bellard | stw(p + 85, (1 << 14)); |
2077 | fc01f7e7 | bellard | stw(p + 86, 0); |
2078 | fc01f7e7 | bellard | stw(p + 87, (1 << 14)); |
2079 | fc01f7e7 | bellard | } |
2080 | fc01f7e7 | bellard | |
2081 | fc01f7e7 | bellard | static inline void ide_abort_command(IDEState *s) |
2082 | fc01f7e7 | bellard | { |
2083 | fc01f7e7 | bellard | s->status = READY_STAT | ERR_STAT; |
2084 | fc01f7e7 | bellard | s->error = ABRT_ERR; |
2085 | fc01f7e7 | bellard | } |
2086 | fc01f7e7 | bellard | |
2087 | fc01f7e7 | bellard | static inline void ide_set_irq(IDEState *s) |
2088 | fc01f7e7 | bellard | { |
2089 | fc01f7e7 | bellard | if (!(ide_state[0].cmd & IDE_CMD_DISABLE_IRQ)) { |
2090 | fc01f7e7 | bellard | pic_set_irq(s->irq, 1);
|
2091 | fc01f7e7 | bellard | } |
2092 | fc01f7e7 | bellard | } |
2093 | fc01f7e7 | bellard | |
2094 | fc01f7e7 | bellard | /* prepare data transfer and tell what to do after */
|
2095 | fc01f7e7 | bellard | static void ide_transfer_start(IDEState *s, int size, |
2096 | fc01f7e7 | bellard | EndTransferFunc *end_transfer_func) |
2097 | fc01f7e7 | bellard | { |
2098 | fc01f7e7 | bellard | s->end_transfer_func = end_transfer_func; |
2099 | fc01f7e7 | bellard | s->data_ptr = s->io_buffer; |
2100 | fc01f7e7 | bellard | s->data_end = s->io_buffer + size; |
2101 | fc01f7e7 | bellard | s->status |= DRQ_STAT; |
2102 | fc01f7e7 | bellard | } |
2103 | fc01f7e7 | bellard | |
2104 | fc01f7e7 | bellard | static void ide_transfer_stop(IDEState *s) |
2105 | fc01f7e7 | bellard | { |
2106 | fc01f7e7 | bellard | s->end_transfer_func = ide_transfer_stop; |
2107 | fc01f7e7 | bellard | s->data_ptr = s->io_buffer; |
2108 | fc01f7e7 | bellard | s->data_end = s->io_buffer; |
2109 | fc01f7e7 | bellard | s->status &= ~DRQ_STAT; |
2110 | fc01f7e7 | bellard | } |
2111 | fc01f7e7 | bellard | |
2112 | fc01f7e7 | bellard | static int64_t ide_get_sector(IDEState *s)
|
2113 | fc01f7e7 | bellard | { |
2114 | fc01f7e7 | bellard | int64_t sector_num; |
2115 | fc01f7e7 | bellard | if (s->select & 0x40) { |
2116 | fc01f7e7 | bellard | /* lba */
|
2117 | fc01f7e7 | bellard | sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) | |
2118 | fc01f7e7 | bellard | (s->lcyl << 8) | s->sector;
|
2119 | fc01f7e7 | bellard | } else {
|
2120 | fc01f7e7 | bellard | sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
|
2121 | fc01f7e7 | bellard | (s->select & 0x0f) * s->sectors +
|
2122 | fc01f7e7 | bellard | (s->sector - 1);
|
2123 | fc01f7e7 | bellard | } |
2124 | fc01f7e7 | bellard | return sector_num;
|
2125 | fc01f7e7 | bellard | } |
2126 | fc01f7e7 | bellard | |
2127 | fc01f7e7 | bellard | static void ide_set_sector(IDEState *s, int64_t sector_num) |
2128 | fc01f7e7 | bellard | { |
2129 | fc01f7e7 | bellard | unsigned int cyl, r; |
2130 | fc01f7e7 | bellard | if (s->select & 0x40) { |
2131 | fc01f7e7 | bellard | s->select = (s->select & 0xf0) | (sector_num >> 24); |
2132 | fc01f7e7 | bellard | s->hcyl = (sector_num >> 16);
|
2133 | fc01f7e7 | bellard | s->lcyl = (sector_num >> 8);
|
2134 | fc01f7e7 | bellard | s->sector = (sector_num); |
2135 | fc01f7e7 | bellard | } else {
|
2136 | fc01f7e7 | bellard | cyl = sector_num / (s->heads * s->sectors); |
2137 | fc01f7e7 | bellard | r = sector_num % (s->heads * s->sectors); |
2138 | fc01f7e7 | bellard | s->hcyl = cyl >> 8;
|
2139 | fc01f7e7 | bellard | s->lcyl = cyl; |
2140 | fc01f7e7 | bellard | s->select = (s->select & 0xf0) | (r / s->sectors);
|
2141 | fc01f7e7 | bellard | s->sector = (r % s->sectors) + 1;
|
2142 | fc01f7e7 | bellard | } |
2143 | fc01f7e7 | bellard | } |
2144 | fc01f7e7 | bellard | |
2145 | fc01f7e7 | bellard | static void ide_sector_read(IDEState *s) |
2146 | fc01f7e7 | bellard | { |
2147 | fc01f7e7 | bellard | int64_t sector_num; |
2148 | c9159e53 | bellard | int ret, n;
|
2149 | fc01f7e7 | bellard | |
2150 | fc01f7e7 | bellard | s->status = READY_STAT | SEEK_STAT; |
2151 | fc01f7e7 | bellard | sector_num = ide_get_sector(s); |
2152 | c9159e53 | bellard | n = s->nsector; |
2153 | c9159e53 | bellard | if (n == 0) { |
2154 | fc01f7e7 | bellard | /* no more sector to read from disk */
|
2155 | fc01f7e7 | bellard | ide_transfer_stop(s); |
2156 | fc01f7e7 | bellard | } else {
|
2157 | fc01f7e7 | bellard | #if defined(DEBUG_IDE)
|
2158 | fc01f7e7 | bellard | printf("read sector=%Ld\n", sector_num);
|
2159 | fc01f7e7 | bellard | #endif
|
2160 | c9159e53 | bellard | if (n > s->req_nb_sectors)
|
2161 | c9159e53 | bellard | n = s->req_nb_sectors; |
2162 | c9159e53 | bellard | ret = bdrv_read(s->bs, sector_num, s->io_buffer, n); |
2163 | c9159e53 | bellard | ide_transfer_start(s, 512 * n, ide_sector_read);
|
2164 | fc01f7e7 | bellard | ide_set_irq(s); |
2165 | c9159e53 | bellard | ide_set_sector(s, sector_num + n); |
2166 | c9159e53 | bellard | s->nsector -= n; |
2167 | fc01f7e7 | bellard | } |
2168 | fc01f7e7 | bellard | } |
2169 | fc01f7e7 | bellard | |
2170 | fc01f7e7 | bellard | static void ide_sector_write(IDEState *s) |
2171 | fc01f7e7 | bellard | { |
2172 | fc01f7e7 | bellard | int64_t sector_num; |
2173 | c9159e53 | bellard | int ret, n, n1;
|
2174 | fc01f7e7 | bellard | |
2175 | fc01f7e7 | bellard | s->status = READY_STAT | SEEK_STAT; |
2176 | fc01f7e7 | bellard | sector_num = ide_get_sector(s); |
2177 | fc01f7e7 | bellard | #if defined(DEBUG_IDE)
|
2178 | fc01f7e7 | bellard | printf("write sector=%Ld\n", sector_num);
|
2179 | fc01f7e7 | bellard | #endif
|
2180 | c9159e53 | bellard | n = s->nsector; |
2181 | c9159e53 | bellard | if (n > s->req_nb_sectors)
|
2182 | c9159e53 | bellard | n = s->req_nb_sectors; |
2183 | c9159e53 | bellard | ret = bdrv_write(s->bs, sector_num, s->io_buffer, n); |
2184 | c9159e53 | bellard | s->nsector -= n; |
2185 | fc01f7e7 | bellard | if (s->nsector == 0) { |
2186 | fc01f7e7 | bellard | /* no more sector to write */
|
2187 | fc01f7e7 | bellard | ide_transfer_stop(s); |
2188 | fc01f7e7 | bellard | } else {
|
2189 | c9159e53 | bellard | n1 = s->nsector; |
2190 | c9159e53 | bellard | if (n1 > s->req_nb_sectors)
|
2191 | c9159e53 | bellard | n1 = s->req_nb_sectors; |
2192 | c9159e53 | bellard | ide_transfer_start(s, 512 * n1, ide_sector_write);
|
2193 | fc01f7e7 | bellard | } |
2194 | c9159e53 | bellard | ide_set_sector(s, sector_num + n); |
2195 | fc01f7e7 | bellard | ide_set_irq(s); |
2196 | fc01f7e7 | bellard | } |
2197 | fc01f7e7 | bellard | |
2198 | fc01f7e7 | bellard | void ide_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
2199 | fc01f7e7 | bellard | { |
2200 | fc01f7e7 | bellard | IDEState *s = ide_state[0].cur_drive;
|
2201 | c9159e53 | bellard | int unit, n;
|
2202 | fc01f7e7 | bellard | |
2203 | fc01f7e7 | bellard | addr &= 7;
|
2204 | fc01f7e7 | bellard | #ifdef DEBUG_IDE
|
2205 | fc01f7e7 | bellard | printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
|
2206 | fc01f7e7 | bellard | #endif
|
2207 | fc01f7e7 | bellard | switch(addr) {
|
2208 | fc01f7e7 | bellard | case 0: |
2209 | fc01f7e7 | bellard | break;
|
2210 | fc01f7e7 | bellard | case 1: |
2211 | fc01f7e7 | bellard | s->feature = val; |
2212 | fc01f7e7 | bellard | break;
|
2213 | fc01f7e7 | bellard | case 2: |
2214 | c9159e53 | bellard | if (val == 0) |
2215 | c9159e53 | bellard | val = 256;
|
2216 | fc01f7e7 | bellard | s->nsector = val; |
2217 | fc01f7e7 | bellard | break;
|
2218 | fc01f7e7 | bellard | case 3: |
2219 | fc01f7e7 | bellard | s->sector = val; |
2220 | fc01f7e7 | bellard | break;
|
2221 | fc01f7e7 | bellard | case 4: |
2222 | fc01f7e7 | bellard | s->lcyl = val; |
2223 | fc01f7e7 | bellard | break;
|
2224 | fc01f7e7 | bellard | case 5: |
2225 | fc01f7e7 | bellard | s->hcyl = val; |
2226 | fc01f7e7 | bellard | break;
|
2227 | fc01f7e7 | bellard | case 6: |
2228 | fc01f7e7 | bellard | /* select drive */
|
2229 | fc01f7e7 | bellard | unit = (val >> 4) & 1; |
2230 | fc01f7e7 | bellard | s = &ide_state[unit]; |
2231 | fc01f7e7 | bellard | ide_state[0].cur_drive = s;
|
2232 | fc01f7e7 | bellard | s->select = val; |
2233 | fc01f7e7 | bellard | break;
|
2234 | fc01f7e7 | bellard | default:
|
2235 | fc01f7e7 | bellard | case 7: |
2236 | fc01f7e7 | bellard | /* command */
|
2237 | fc01f7e7 | bellard | #if defined(DEBUG_IDE)
|
2238 | fc01f7e7 | bellard | printf("ide: CMD=%02x\n", val);
|
2239 | fc01f7e7 | bellard | #endif
|
2240 | fc01f7e7 | bellard | switch(val) {
|
2241 | fc01f7e7 | bellard | case WIN_PIDENTIFY:
|
2242 | fc01f7e7 | bellard | case WIN_IDENTIFY:
|
2243 | fc01f7e7 | bellard | if (s->bs) {
|
2244 | fc01f7e7 | bellard | ide_identify(s); |
2245 | fc01f7e7 | bellard | s->status = READY_STAT; |
2246 | fc01f7e7 | bellard | ide_transfer_start(s, 512, ide_transfer_stop);
|
2247 | fc01f7e7 | bellard | } else {
|
2248 | fc01f7e7 | bellard | ide_abort_command(s); |
2249 | fc01f7e7 | bellard | } |
2250 | fc01f7e7 | bellard | ide_set_irq(s); |
2251 | fc01f7e7 | bellard | break;
|
2252 | fc01f7e7 | bellard | case WIN_SPECIFY:
|
2253 | fc01f7e7 | bellard | case WIN_RECAL:
|
2254 | fc01f7e7 | bellard | s->status = READY_STAT; |
2255 | fc01f7e7 | bellard | ide_set_irq(s); |
2256 | fc01f7e7 | bellard | break;
|
2257 | fc01f7e7 | bellard | case WIN_SETMULT:
|
2258 | fc01f7e7 | bellard | if (s->nsector > MAX_MULT_SECTORS ||
|
2259 | fc01f7e7 | bellard | s->nsector == 0 ||
|
2260 | fc01f7e7 | bellard | (s->nsector & (s->nsector - 1)) != 0) { |
2261 | fc01f7e7 | bellard | ide_abort_command(s); |
2262 | fc01f7e7 | bellard | } else {
|
2263 | fc01f7e7 | bellard | s->mult_sectors = s->nsector; |
2264 | fc01f7e7 | bellard | s->status = READY_STAT; |
2265 | fc01f7e7 | bellard | } |
2266 | fc01f7e7 | bellard | ide_set_irq(s); |
2267 | fc01f7e7 | bellard | break;
|
2268 | fc01f7e7 | bellard | case WIN_READ:
|
2269 | fc01f7e7 | bellard | case WIN_READ_ONCE:
|
2270 | c9159e53 | bellard | s->req_nb_sectors = 1;
|
2271 | fc01f7e7 | bellard | ide_sector_read(s); |
2272 | fc01f7e7 | bellard | break;
|
2273 | fc01f7e7 | bellard | case WIN_WRITE:
|
2274 | fc01f7e7 | bellard | case WIN_WRITE_ONCE:
|
2275 | fc01f7e7 | bellard | s->status = SEEK_STAT; |
2276 | c9159e53 | bellard | s->req_nb_sectors = 1;
|
2277 | fc01f7e7 | bellard | ide_transfer_start(s, 512, ide_sector_write);
|
2278 | fc01f7e7 | bellard | break;
|
2279 | c9159e53 | bellard | case WIN_MULTREAD:
|
2280 | c9159e53 | bellard | if (!s->mult_sectors)
|
2281 | c9159e53 | bellard | goto abort_cmd;
|
2282 | c9159e53 | bellard | s->req_nb_sectors = s->mult_sectors; |
2283 | c9159e53 | bellard | ide_sector_read(s); |
2284 | c9159e53 | bellard | break;
|
2285 | c9159e53 | bellard | case WIN_MULTWRITE:
|
2286 | c9159e53 | bellard | if (!s->mult_sectors)
|
2287 | c9159e53 | bellard | goto abort_cmd;
|
2288 | c9159e53 | bellard | s->status = SEEK_STAT; |
2289 | c9159e53 | bellard | s->req_nb_sectors = s->mult_sectors; |
2290 | c9159e53 | bellard | n = s->nsector; |
2291 | c9159e53 | bellard | if (n > s->req_nb_sectors)
|
2292 | c9159e53 | bellard | n = s->req_nb_sectors; |
2293 | c9159e53 | bellard | ide_transfer_start(s, 512 * n, ide_sector_write);
|
2294 | c9159e53 | bellard | break;
|
2295 | cd4c3e88 | bellard | case WIN_READ_NATIVE_MAX:
|
2296 | cd4c3e88 | bellard | ide_set_sector(s, s->nb_sectors - 1);
|
2297 | cd4c3e88 | bellard | s->status = READY_STAT; |
2298 | cd4c3e88 | bellard | ide_set_irq(s); |
2299 | cd4c3e88 | bellard | break;
|
2300 | fc01f7e7 | bellard | default:
|
2301 | c9159e53 | bellard | abort_cmd:
|
2302 | fc01f7e7 | bellard | ide_abort_command(s); |
2303 | fc01f7e7 | bellard | ide_set_irq(s); |
2304 | fc01f7e7 | bellard | break;
|
2305 | fc01f7e7 | bellard | } |
2306 | fc01f7e7 | bellard | } |
2307 | fc01f7e7 | bellard | } |
2308 | fc01f7e7 | bellard | |
2309 | fc01f7e7 | bellard | uint32_t ide_ioport_read(CPUX86State *env, uint32_t addr) |
2310 | fc01f7e7 | bellard | { |
2311 | fc01f7e7 | bellard | IDEState *s = ide_state[0].cur_drive;
|
2312 | fc01f7e7 | bellard | int ret;
|
2313 | fc01f7e7 | bellard | |
2314 | fc01f7e7 | bellard | addr &= 7;
|
2315 | fc01f7e7 | bellard | switch(addr) {
|
2316 | fc01f7e7 | bellard | case 0: |
2317 | fc01f7e7 | bellard | ret = 0xff;
|
2318 | fc01f7e7 | bellard | break;
|
2319 | fc01f7e7 | bellard | case 1: |
2320 | fc01f7e7 | bellard | ret = s->error; |
2321 | fc01f7e7 | bellard | break;
|
2322 | fc01f7e7 | bellard | case 2: |
2323 | c9159e53 | bellard | ret = s->nsector & 0xff;
|
2324 | fc01f7e7 | bellard | break;
|
2325 | fc01f7e7 | bellard | case 3: |
2326 | fc01f7e7 | bellard | ret = s->sector; |
2327 | fc01f7e7 | bellard | break;
|
2328 | fc01f7e7 | bellard | case 4: |
2329 | fc01f7e7 | bellard | ret = s->lcyl; |
2330 | fc01f7e7 | bellard | break;
|
2331 | fc01f7e7 | bellard | case 5: |
2332 | fc01f7e7 | bellard | ret = s->hcyl; |
2333 | fc01f7e7 | bellard | break;
|
2334 | fc01f7e7 | bellard | case 6: |
2335 | fc01f7e7 | bellard | ret = s->select; |
2336 | fc01f7e7 | bellard | break;
|
2337 | fc01f7e7 | bellard | default:
|
2338 | fc01f7e7 | bellard | case 7: |
2339 | fc01f7e7 | bellard | ret = s->status; |
2340 | fc01f7e7 | bellard | pic_set_irq(s->irq, 0);
|
2341 | fc01f7e7 | bellard | break;
|
2342 | fc01f7e7 | bellard | } |
2343 | fc01f7e7 | bellard | #ifdef DEBUG_IDE
|
2344 | fc01f7e7 | bellard | printf("ide: read addr=0x%x val=%02x\n", addr, ret);
|
2345 | fc01f7e7 | bellard | #endif
|
2346 | fc01f7e7 | bellard | return ret;
|
2347 | fc01f7e7 | bellard | } |
2348 | fc01f7e7 | bellard | |
2349 | fc01f7e7 | bellard | uint32_t ide_status_read(CPUX86State *env, uint32_t addr) |
2350 | fc01f7e7 | bellard | { |
2351 | fc01f7e7 | bellard | IDEState *s = ide_state[0].cur_drive;
|
2352 | fc01f7e7 | bellard | int ret;
|
2353 | fc01f7e7 | bellard | ret = s->status; |
2354 | fc01f7e7 | bellard | #ifdef DEBUG_IDE
|
2355 | fc01f7e7 | bellard | printf("ide: read addr=0x%x val=%02x\n", addr, ret);
|
2356 | fc01f7e7 | bellard | #endif
|
2357 | fc01f7e7 | bellard | return ret;
|
2358 | fc01f7e7 | bellard | } |
2359 | fc01f7e7 | bellard | |
2360 | fc01f7e7 | bellard | void ide_cmd_write(CPUX86State *env, uint32_t addr, uint32_t val)
|
2361 | fc01f7e7 | bellard | { |
2362 | fc01f7e7 | bellard | IDEState *s = &ide_state[0];
|
2363 | fc01f7e7 | bellard | /* common for both drives */
|
2364 | fc01f7e7 | bellard | s->cmd = val; |
2365 | fc01f7e7 | bellard | } |
2366 | fc01f7e7 | bellard | |
2367 | fc01f7e7 | bellard | void ide_data_writew(CPUX86State *env, uint32_t addr, uint32_t val)
|
2368 | fc01f7e7 | bellard | { |
2369 | fc01f7e7 | bellard | IDEState *s = ide_state[0].cur_drive;
|
2370 | fc01f7e7 | bellard | uint8_t *p; |
2371 | fc01f7e7 | bellard | |
2372 | fc01f7e7 | bellard | p = s->data_ptr; |
2373 | fc01f7e7 | bellard | *(uint16_t *)p = tswap16(val); |
2374 | fc01f7e7 | bellard | p += 2;
|
2375 | fc01f7e7 | bellard | s->data_ptr = p; |
2376 | fc01f7e7 | bellard | if (p >= s->data_end)
|
2377 | fc01f7e7 | bellard | s->end_transfer_func(s); |
2378 | fc01f7e7 | bellard | } |
2379 | fc01f7e7 | bellard | |
2380 | fc01f7e7 | bellard | uint32_t ide_data_readw(CPUX86State *env, uint32_t addr) |
2381 | fc01f7e7 | bellard | { |
2382 | fc01f7e7 | bellard | IDEState *s = ide_state[0].cur_drive;
|
2383 | fc01f7e7 | bellard | uint8_t *p; |
2384 | fc01f7e7 | bellard | int ret;
|
2385 | fc01f7e7 | bellard | |
2386 | fc01f7e7 | bellard | p = s->data_ptr; |
2387 | fc01f7e7 | bellard | ret = tswap16(*(uint16_t *)p); |
2388 | fc01f7e7 | bellard | p += 2;
|
2389 | fc01f7e7 | bellard | s->data_ptr = p; |
2390 | fc01f7e7 | bellard | if (p >= s->data_end)
|
2391 | fc01f7e7 | bellard | s->end_transfer_func(s); |
2392 | fc01f7e7 | bellard | return ret;
|
2393 | fc01f7e7 | bellard | } |
2394 | fc01f7e7 | bellard | |
2395 | fc01f7e7 | bellard | void ide_data_writel(CPUX86State *env, uint32_t addr, uint32_t val)
|
2396 | fc01f7e7 | bellard | { |
2397 | fc01f7e7 | bellard | IDEState *s = ide_state[0].cur_drive;
|
2398 | fc01f7e7 | bellard | uint8_t *p; |
2399 | fc01f7e7 | bellard | |
2400 | fc01f7e7 | bellard | p = s->data_ptr; |
2401 | fc01f7e7 | bellard | *(uint32_t *)p = tswap32(val); |
2402 | fc01f7e7 | bellard | p += 4;
|
2403 | fc01f7e7 | bellard | s->data_ptr = p; |
2404 | fc01f7e7 | bellard | if (p >= s->data_end)
|
2405 | fc01f7e7 | bellard | s->end_transfer_func(s); |
2406 | fc01f7e7 | bellard | } |
2407 | fc01f7e7 | bellard | |
2408 | fc01f7e7 | bellard | uint32_t ide_data_readl(CPUX86State *env, uint32_t addr) |
2409 | fc01f7e7 | bellard | { |
2410 | fc01f7e7 | bellard | IDEState *s = ide_state[0].cur_drive;
|
2411 | fc01f7e7 | bellard | uint8_t *p; |
2412 | fc01f7e7 | bellard | int ret;
|
2413 | fc01f7e7 | bellard | |
2414 | fc01f7e7 | bellard | p = s->data_ptr; |
2415 | fc01f7e7 | bellard | ret = tswap32(*(uint32_t *)p); |
2416 | fc01f7e7 | bellard | p += 4;
|
2417 | fc01f7e7 | bellard | s->data_ptr = p; |
2418 | fc01f7e7 | bellard | if (p >= s->data_end)
|
2419 | fc01f7e7 | bellard | s->end_transfer_func(s); |
2420 | fc01f7e7 | bellard | return ret;
|
2421 | fc01f7e7 | bellard | } |
2422 | fc01f7e7 | bellard | |
2423 | fc01f7e7 | bellard | void ide_reset(IDEState *s)
|
2424 | fc01f7e7 | bellard | { |
2425 | fc01f7e7 | bellard | s->mult_sectors = MAX_MULT_SECTORS; |
2426 | fc01f7e7 | bellard | s->status = READY_STAT; |
2427 | fc01f7e7 | bellard | s->cur_drive = s; |
2428 | fc01f7e7 | bellard | s->select = 0xa0;
|
2429 | fc01f7e7 | bellard | } |
2430 | fc01f7e7 | bellard | |
2431 | fc01f7e7 | bellard | void ide_init(void) |
2432 | fc01f7e7 | bellard | { |
2433 | fc01f7e7 | bellard | IDEState *s; |
2434 | fc01f7e7 | bellard | int i, cylinders;
|
2435 | fc01f7e7 | bellard | int64_t nb_sectors; |
2436 | fc01f7e7 | bellard | |
2437 | fc01f7e7 | bellard | for(i = 0; i < MAX_DISKS; i++) { |
2438 | fc01f7e7 | bellard | s = &ide_state[i]; |
2439 | fc01f7e7 | bellard | s->bs = bs_table[i]; |
2440 | fc01f7e7 | bellard | if (s->bs) {
|
2441 | fc01f7e7 | bellard | bdrv_get_geometry(s->bs, &nb_sectors); |
2442 | fc01f7e7 | bellard | cylinders = nb_sectors / (16 * 63); |
2443 | fc01f7e7 | bellard | if (cylinders > 16383) |
2444 | fc01f7e7 | bellard | cylinders = 16383;
|
2445 | fc01f7e7 | bellard | else if (cylinders < 2) |
2446 | fc01f7e7 | bellard | cylinders = 2;
|
2447 | fc01f7e7 | bellard | s->cylinders = cylinders; |
2448 | fc01f7e7 | bellard | s->heads = 16;
|
2449 | fc01f7e7 | bellard | s->sectors = 63;
|
2450 | fc01f7e7 | bellard | s->nb_sectors = nb_sectors; |
2451 | fc01f7e7 | bellard | } |
2452 | fc01f7e7 | bellard | s->irq = 14;
|
2453 | fc01f7e7 | bellard | ide_reset(s); |
2454 | fc01f7e7 | bellard | } |
2455 | fc01f7e7 | bellard | register_ioport_write(0x1f0, 8, ide_ioport_write, 1); |
2456 | fc01f7e7 | bellard | register_ioport_read(0x1f0, 8, ide_ioport_read, 1); |
2457 | fc01f7e7 | bellard | register_ioport_read(0x3f6, 1, ide_status_read, 1); |
2458 | fc01f7e7 | bellard | register_ioport_write(0x3f6, 1, ide_cmd_write, 1); |
2459 | fc01f7e7 | bellard | |
2460 | fc01f7e7 | bellard | /* data ports */
|
2461 | fc01f7e7 | bellard | register_ioport_write(0x1f0, 2, ide_data_writew, 2); |
2462 | fc01f7e7 | bellard | register_ioport_read(0x1f0, 2, ide_data_readw, 2); |
2463 | fc01f7e7 | bellard | register_ioport_write(0x1f0, 4, ide_data_writel, 4); |
2464 | fc01f7e7 | bellard | register_ioport_read(0x1f0, 4, ide_data_readl, 4); |
2465 | fc01f7e7 | bellard | } |
2466 | fc01f7e7 | bellard | |
2467 | fc01f7e7 | bellard | /***********************************************************/
|
2468 | cd4c3e88 | bellard | /* simulate reset (stop qemu) */
|
2469 | cd4c3e88 | bellard | |
2470 | cd4c3e88 | bellard | int reset_requested;
|
2471 | cd4c3e88 | bellard | |
2472 | cd4c3e88 | bellard | uint32_t kbd_read_status(CPUX86State *env, uint32_t addr) |
2473 | cd4c3e88 | bellard | { |
2474 | cd4c3e88 | bellard | return 0; |
2475 | cd4c3e88 | bellard | } |
2476 | cd4c3e88 | bellard | |
2477 | cd4c3e88 | bellard | void kbd_write_command(CPUX86State *env, uint32_t addr, uint32_t val)
|
2478 | cd4c3e88 | bellard | { |
2479 | cd4c3e88 | bellard | switch(val) {
|
2480 | cd4c3e88 | bellard | case 0xfe: |
2481 | cd4c3e88 | bellard | reset_requested = 1;
|
2482 | cd4c3e88 | bellard | cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT); |
2483 | cd4c3e88 | bellard | break;
|
2484 | cd4c3e88 | bellard | default:
|
2485 | cd4c3e88 | bellard | break;
|
2486 | cd4c3e88 | bellard | } |
2487 | cd4c3e88 | bellard | } |
2488 | cd4c3e88 | bellard | |
2489 | cd4c3e88 | bellard | void kbd_init(void) |
2490 | cd4c3e88 | bellard | { |
2491 | cd4c3e88 | bellard | register_ioport_read(0x64, 1, kbd_read_status, 1); |
2492 | cd4c3e88 | bellard | register_ioport_write(0x64, 1, kbd_write_command, 1); |
2493 | cd4c3e88 | bellard | } |
2494 | cd4c3e88 | bellard | |
2495 | cd4c3e88 | bellard | /***********************************************************/
|
2496 | 0824d6fc | bellard | /* cpu signal handler */
|
2497 | 0824d6fc | bellard | static void host_segv_handler(int host_signum, siginfo_t *info, |
2498 | 0824d6fc | bellard | void *puc)
|
2499 | 0824d6fc | bellard | { |
2500 | 0824d6fc | bellard | if (cpu_signal_handler(host_signum, info, puc))
|
2501 | 0824d6fc | bellard | return;
|
2502 | 0824d6fc | bellard | term_exit(); |
2503 | 0824d6fc | bellard | abort(); |
2504 | 0824d6fc | bellard | } |
2505 | 0824d6fc | bellard | |
2506 | 0824d6fc | bellard | static int timer_irq_pending; |
2507 | 87858c89 | bellard | static int timer_irq_count; |
2508 | 0824d6fc | bellard | |
2509 | 0824d6fc | bellard | static void host_alarm_handler(int host_signum, siginfo_t *info, |
2510 | 0824d6fc | bellard | void *puc)
|
2511 | 0824d6fc | bellard | { |
2512 | 87858c89 | bellard | /* NOTE: since usually the OS asks a 100 Hz clock, there can be
|
2513 | 87858c89 | bellard | some drift between cpu_get_ticks() and the interrupt time. So
|
2514 | 87858c89 | bellard | we queue some interrupts to avoid missing some */
|
2515 | 87858c89 | bellard | timer_irq_count += pit_get_out_edges(&pit_channels[0]);
|
2516 | 87858c89 | bellard | if (timer_irq_count) {
|
2517 | 87858c89 | bellard | if (timer_irq_count > 2) |
2518 | 87858c89 | bellard | timer_irq_count = 2;
|
2519 | 87858c89 | bellard | timer_irq_count--; |
2520 | 87858c89 | bellard | /* just exit from the cpu to have a chance to handle timers */
|
2521 | c9159e53 | bellard | cpu_x86_interrupt(global_env, CPU_INTERRUPT_EXIT); |
2522 | 87858c89 | bellard | timer_irq_pending = 1;
|
2523 | 87858c89 | bellard | } |
2524 | 0824d6fc | bellard | } |
2525 | 0824d6fc | bellard | |
2526 | 33e3963e | bellard | unsigned long mmap_addr = PHYS_RAM_BASE; |
2527 | 33e3963e | bellard | |
2528 | 33e3963e | bellard | void *get_mmap_addr(unsigned long size) |
2529 | 33e3963e | bellard | { |
2530 | 33e3963e | bellard | unsigned long addr; |
2531 | 33e3963e | bellard | addr = mmap_addr; |
2532 | 33e3963e | bellard | mmap_addr += ((size + 4095) & ~4095) + 4096; |
2533 | 33e3963e | bellard | return (void *)addr; |
2534 | 33e3963e | bellard | } |
2535 | 33e3963e | bellard | |
2536 | b4608c04 | bellard | /* main execution loop */
|
2537 | b4608c04 | bellard | |
2538 | b4608c04 | bellard | CPUState *cpu_gdbstub_get_env(void *opaque)
|
2539 | b4608c04 | bellard | { |
2540 | b4608c04 | bellard | return global_env;
|
2541 | b4608c04 | bellard | } |
2542 | b4608c04 | bellard | |
2543 | 4c3a88a2 | bellard | int main_loop(void *opaque) |
2544 | b4608c04 | bellard | { |
2545 | b4608c04 | bellard | struct pollfd ufds[2], *pf, *serial_ufd, *net_ufd, *gdb_ufd; |
2546 | b4608c04 | bellard | int ret, n, timeout;
|
2547 | b4608c04 | bellard | uint8_t ch; |
2548 | b4608c04 | bellard | CPUState *env = global_env; |
2549 | b4608c04 | bellard | |
2550 | b4608c04 | bellard | for(;;) {
|
2551 | b4608c04 | bellard | |
2552 | b4608c04 | bellard | ret = cpu_x86_exec(env); |
2553 | cd4c3e88 | bellard | if (reset_requested)
|
2554 | cd4c3e88 | bellard | break;
|
2555 | 4c3a88a2 | bellard | if (ret == EXCP_DEBUG)
|
2556 | 4c3a88a2 | bellard | return EXCP_DEBUG;
|
2557 | b4608c04 | bellard | /* if hlt instruction, we wait until the next IRQ */
|
2558 | b4608c04 | bellard | if (ret == EXCP_HLT)
|
2559 | b4608c04 | bellard | timeout = 10;
|
2560 | b4608c04 | bellard | else
|
2561 | b4608c04 | bellard | timeout = 0;
|
2562 | b4608c04 | bellard | /* poll any events */
|
2563 | b4608c04 | bellard | serial_ufd = NULL;
|
2564 | b4608c04 | bellard | pf = ufds; |
2565 | b4608c04 | bellard | if (!(serial_ports[0].lsr & UART_LSR_DR)) { |
2566 | b4608c04 | bellard | serial_ufd = pf; |
2567 | b4608c04 | bellard | pf->fd = 0;
|
2568 | b4608c04 | bellard | pf->events = POLLIN; |
2569 | b4608c04 | bellard | pf++; |
2570 | b4608c04 | bellard | } |
2571 | b4608c04 | bellard | net_ufd = NULL;
|
2572 | b4608c04 | bellard | if (net_fd > 0 && ne2000_can_receive(&ne2000_state)) { |
2573 | b4608c04 | bellard | net_ufd = pf; |
2574 | b4608c04 | bellard | pf->fd = net_fd; |
2575 | b4608c04 | bellard | pf->events = POLLIN; |
2576 | b4608c04 | bellard | pf++; |
2577 | b4608c04 | bellard | } |
2578 | b4608c04 | bellard | gdb_ufd = NULL;
|
2579 | b4608c04 | bellard | if (gdbstub_fd > 0) { |
2580 | b4608c04 | bellard | gdb_ufd = pf; |
2581 | b4608c04 | bellard | pf->fd = gdbstub_fd; |
2582 | b4608c04 | bellard | pf->events = POLLIN; |
2583 | b4608c04 | bellard | pf++; |
2584 | b4608c04 | bellard | } |
2585 | b4608c04 | bellard | |
2586 | b4608c04 | bellard | ret = poll(ufds, pf - ufds, timeout); |
2587 | b4608c04 | bellard | if (ret > 0) { |
2588 | b4608c04 | bellard | if (serial_ufd && (serial_ufd->revents & POLLIN)) {
|
2589 | b4608c04 | bellard | n = read(0, &ch, 1); |
2590 | b4608c04 | bellard | if (n == 1) { |
2591 | b4608c04 | bellard | serial_received_byte(&serial_ports[0], ch);
|
2592 | b4608c04 | bellard | } |
2593 | b4608c04 | bellard | } |
2594 | b4608c04 | bellard | if (net_ufd && (net_ufd->revents & POLLIN)) {
|
2595 | b4608c04 | bellard | uint8_t buf[MAX_ETH_FRAME_SIZE]; |
2596 | b4608c04 | bellard | |
2597 | b4608c04 | bellard | n = read(net_fd, buf, MAX_ETH_FRAME_SIZE); |
2598 | b4608c04 | bellard | if (n > 0) { |
2599 | b4608c04 | bellard | if (n < 60) { |
2600 | b4608c04 | bellard | memset(buf + n, 0, 60 - n); |
2601 | b4608c04 | bellard | n = 60;
|
2602 | b4608c04 | bellard | } |
2603 | b4608c04 | bellard | ne2000_receive(&ne2000_state, buf, n); |
2604 | b4608c04 | bellard | } |
2605 | b4608c04 | bellard | } |
2606 | b4608c04 | bellard | if (gdb_ufd && (gdb_ufd->revents & POLLIN)) {
|
2607 | b4608c04 | bellard | uint8_t buf[1];
|
2608 | b4608c04 | bellard | /* stop emulation if requested by gdb */
|
2609 | b4608c04 | bellard | n = read(gdbstub_fd, buf, 1);
|
2610 | b4608c04 | bellard | if (n == 1) |
2611 | b4608c04 | bellard | break;
|
2612 | b4608c04 | bellard | } |
2613 | b4608c04 | bellard | } |
2614 | b4608c04 | bellard | |
2615 | b4608c04 | bellard | /* timer IRQ */
|
2616 | b4608c04 | bellard | if (timer_irq_pending) {
|
2617 | b4608c04 | bellard | pic_set_irq(0, 1); |
2618 | b4608c04 | bellard | pic_set_irq(0, 0); |
2619 | b4608c04 | bellard | timer_irq_pending = 0;
|
2620 | b4608c04 | bellard | } |
2621 | b4608c04 | bellard | } |
2622 | 4c3a88a2 | bellard | return EXCP_INTERRUPT;
|
2623 | b4608c04 | bellard | } |
2624 | b4608c04 | bellard | |
2625 | 0824d6fc | bellard | void help(void) |
2626 | 0824d6fc | bellard | { |
2627 | 0824d6fc | bellard | printf("Virtual Linux version " QEMU_VERSION ", Copyright (c) 2003 Fabrice Bellard\n" |
2628 | fc01f7e7 | bellard | "usage: vl [options] bzImage [kernel parameters...]\n"
|
2629 | 0824d6fc | bellard | "\n"
|
2630 | 0824d6fc | bellard | "'bzImage' is a Linux kernel image (PAGE_OFFSET must be defined\n"
|
2631 | 0824d6fc | bellard | "to 0x90000000 in asm/page.h and arch/i386/vmlinux.lds)\n"
|
2632 | fc01f7e7 | bellard | "\n"
|
2633 | fc01f7e7 | bellard | "General options:\n"
|
2634 | fc01f7e7 | bellard | "-initrd file use 'file' as initial ram disk\n"
|
2635 | fc01f7e7 | bellard | "-hda file use 'file' as hard disk 0 image\n"
|
2636 | fc01f7e7 | bellard | "-hdb file use 'file' as hard disk 1 image\n"
|
2637 | 33e3963e | bellard | "-snapshot write to temporary files instead of disk image files\n"
|
2638 | fc01f7e7 | bellard | "-m megs set virtual RAM size to megs MB\n"
|
2639 | fc01f7e7 | bellard | "-n script set network init script [default=%s]\n"
|
2640 | fc01f7e7 | bellard | "\n"
|
2641 | fc01f7e7 | bellard | "Debug options:\n"
|
2642 | fc01f7e7 | bellard | "-s wait gdb connection to port %d\n"
|
2643 | fc01f7e7 | bellard | "-p port change gdb connection port\n"
|
2644 | fc01f7e7 | bellard | "-d output log in /tmp/vl.log\n"
|
2645 | 0824d6fc | bellard | "\n"
|
2646 | f1510b2c | bellard | "During emulation, use C-a h to get terminal commands:\n",
|
2647 | b4608c04 | bellard | DEFAULT_NETWORK_SCRIPT, DEFAULT_GDBSTUB_PORT); |
2648 | 0824d6fc | bellard | term_print_help(); |
2649 | 0824d6fc | bellard | exit(1);
|
2650 | 0824d6fc | bellard | } |
2651 | 0824d6fc | bellard | |
2652 | fc01f7e7 | bellard | struct option long_options[] = {
|
2653 | fc01f7e7 | bellard | { "initrd", 1, NULL, 0, }, |
2654 | fc01f7e7 | bellard | { "hda", 1, NULL, 0, }, |
2655 | fc01f7e7 | bellard | { "hdb", 1, NULL, 0, }, |
2656 | 33e3963e | bellard | { "snapshot", 0, NULL, 0, }, |
2657 | fc01f7e7 | bellard | { NULL, 0, NULL, 0 }, |
2658 | fc01f7e7 | bellard | }; |
2659 | fc01f7e7 | bellard | |
2660 | 0824d6fc | bellard | int main(int argc, char **argv) |
2661 | 0824d6fc | bellard | { |
2662 | fc01f7e7 | bellard | int c, ret, initrd_size, i, use_gdbstub, gdbstub_port, long_index;
|
2663 | 33e3963e | bellard | int snapshot;
|
2664 | 0824d6fc | bellard | struct linux_params *params;
|
2665 | 0824d6fc | bellard | struct sigaction act;
|
2666 | 0824d6fc | bellard | struct itimerval itv;
|
2667 | 0824d6fc | bellard | CPUX86State *env; |
2668 | fc01f7e7 | bellard | const char *tmpdir, *initrd_filename; |
2669 | fc01f7e7 | bellard | const char *hd_filename[MAX_DISKS]; |
2670 | 87858c89 | bellard | |
2671 | 0824d6fc | bellard | /* we never want that malloc() uses mmap() */
|
2672 | 0824d6fc | bellard | mallopt(M_MMAP_THRESHOLD, 4096 * 1024); |
2673 | fc01f7e7 | bellard | initrd_filename = NULL;
|
2674 | fc01f7e7 | bellard | for(i = 0; i < MAX_DISKS; i++) |
2675 | fc01f7e7 | bellard | hd_filename[i] = NULL;
|
2676 | 0824d6fc | bellard | phys_ram_size = 32 * 1024 * 1024; |
2677 | f1510b2c | bellard | pstrcpy(network_script, sizeof(network_script), DEFAULT_NETWORK_SCRIPT);
|
2678 | b4608c04 | bellard | use_gdbstub = 0;
|
2679 | b4608c04 | bellard | gdbstub_port = DEFAULT_GDBSTUB_PORT; |
2680 | 33e3963e | bellard | snapshot = 0;
|
2681 | 0824d6fc | bellard | for(;;) {
|
2682 | fc01f7e7 | bellard | c = getopt_long_only(argc, argv, "hm:dn:sp:", long_options, &long_index);
|
2683 | 0824d6fc | bellard | if (c == -1) |
2684 | 0824d6fc | bellard | break;
|
2685 | 0824d6fc | bellard | switch(c) {
|
2686 | fc01f7e7 | bellard | case 0: |
2687 | fc01f7e7 | bellard | switch(long_index) {
|
2688 | fc01f7e7 | bellard | case 0: |
2689 | fc01f7e7 | bellard | initrd_filename = optarg; |
2690 | fc01f7e7 | bellard | break;
|
2691 | fc01f7e7 | bellard | case 1: |
2692 | fc01f7e7 | bellard | hd_filename[0] = optarg;
|
2693 | fc01f7e7 | bellard | break;
|
2694 | fc01f7e7 | bellard | case 2: |
2695 | fc01f7e7 | bellard | hd_filename[1] = optarg;
|
2696 | fc01f7e7 | bellard | break;
|
2697 | 33e3963e | bellard | case 3: |
2698 | 33e3963e | bellard | snapshot = 1;
|
2699 | 33e3963e | bellard | break;
|
2700 | fc01f7e7 | bellard | } |
2701 | fc01f7e7 | bellard | break;
|
2702 | 0824d6fc | bellard | case 'h': |
2703 | 0824d6fc | bellard | help(); |
2704 | 0824d6fc | bellard | break;
|
2705 | 0824d6fc | bellard | case 'm': |
2706 | 0824d6fc | bellard | phys_ram_size = atoi(optarg) * 1024 * 1024; |
2707 | 0824d6fc | bellard | if (phys_ram_size <= 0) |
2708 | 0824d6fc | bellard | help(); |
2709 | 7916e224 | bellard | if (phys_ram_size > PHYS_RAM_MAX_SIZE) {
|
2710 | 7916e224 | bellard | fprintf(stderr, "vl: at most %d MB RAM can be simulated\n",
|
2711 | 7916e224 | bellard | PHYS_RAM_MAX_SIZE / (1024 * 1024)); |
2712 | 7916e224 | bellard | exit(1);
|
2713 | 7916e224 | bellard | } |
2714 | 0824d6fc | bellard | break;
|
2715 | 0824d6fc | bellard | case 'd': |
2716 | 0824d6fc | bellard | loglevel = 1;
|
2717 | 0824d6fc | bellard | break;
|
2718 | f1510b2c | bellard | case 'n': |
2719 | f1510b2c | bellard | pstrcpy(network_script, sizeof(network_script), optarg);
|
2720 | f1510b2c | bellard | break;
|
2721 | b4608c04 | bellard | case 's': |
2722 | b4608c04 | bellard | use_gdbstub = 1;
|
2723 | b4608c04 | bellard | break;
|
2724 | b4608c04 | bellard | case 'p': |
2725 | b4608c04 | bellard | gdbstub_port = atoi(optarg); |
2726 | b4608c04 | bellard | break;
|
2727 | 0824d6fc | bellard | } |
2728 | 0824d6fc | bellard | } |
2729 | fc01f7e7 | bellard | if (optind >= argc)
|
2730 | 0824d6fc | bellard | help(); |
2731 | 0824d6fc | bellard | |
2732 | 0824d6fc | bellard | /* init debug */
|
2733 | b118d61e | bellard | setvbuf(stdout, NULL, _IOLBF, 0); |
2734 | 0824d6fc | bellard | if (loglevel) {
|
2735 | 0824d6fc | bellard | logfile = fopen(DEBUG_LOGFILE, "w");
|
2736 | 0824d6fc | bellard | if (!logfile) {
|
2737 | 0824d6fc | bellard | perror(DEBUG_LOGFILE); |
2738 | 0824d6fc | bellard | _exit(1);
|
2739 | 0824d6fc | bellard | } |
2740 | 0824d6fc | bellard | setvbuf(logfile, NULL, _IOLBF, 0); |
2741 | 0824d6fc | bellard | } |
2742 | 0824d6fc | bellard | |
2743 | f1510b2c | bellard | /* init network tun interface */
|
2744 | f1510b2c | bellard | net_init(); |
2745 | f1510b2c | bellard | |
2746 | 0824d6fc | bellard | /* init the memory */
|
2747 | 87858c89 | bellard | tmpdir = getenv("VLTMPDIR");
|
2748 | 87858c89 | bellard | if (!tmpdir)
|
2749 | 87858c89 | bellard | tmpdir = "/tmp";
|
2750 | 87858c89 | bellard | snprintf(phys_ram_file, sizeof(phys_ram_file), "%s/vlXXXXXX", tmpdir); |
2751 | 0824d6fc | bellard | if (mkstemp(phys_ram_file) < 0) { |
2752 | 87858c89 | bellard | fprintf(stderr, "Could not create temporary memory file '%s'\n",
|
2753 | 87858c89 | bellard | phys_ram_file); |
2754 | 0824d6fc | bellard | exit(1);
|
2755 | 0824d6fc | bellard | } |
2756 | 0824d6fc | bellard | phys_ram_fd = open(phys_ram_file, O_CREAT | O_TRUNC | O_RDWR, 0600);
|
2757 | 0824d6fc | bellard | if (phys_ram_fd < 0) { |
2758 | 87858c89 | bellard | fprintf(stderr, "Could not open temporary memory file '%s'\n",
|
2759 | 87858c89 | bellard | phys_ram_file); |
2760 | 0824d6fc | bellard | exit(1);
|
2761 | 0824d6fc | bellard | } |
2762 | 0824d6fc | bellard | ftruncate(phys_ram_fd, phys_ram_size); |
2763 | 0824d6fc | bellard | unlink(phys_ram_file); |
2764 | 33e3963e | bellard | phys_ram_base = mmap(get_mmap_addr(phys_ram_size), phys_ram_size, |
2765 | 0824d6fc | bellard | PROT_WRITE | PROT_READ, MAP_SHARED | MAP_FIXED, |
2766 | 0824d6fc | bellard | phys_ram_fd, 0);
|
2767 | 0824d6fc | bellard | if (phys_ram_base == MAP_FAILED) {
|
2768 | 0824d6fc | bellard | fprintf(stderr, "Could not map physical memory\n");
|
2769 | 0824d6fc | bellard | exit(1);
|
2770 | 0824d6fc | bellard | } |
2771 | 0824d6fc | bellard | |
2772 | 33e3963e | bellard | /* open the virtual block devices */
|
2773 | 33e3963e | bellard | for(i = 0; i < MAX_DISKS; i++) { |
2774 | 33e3963e | bellard | if (hd_filename[i]) {
|
2775 | 33e3963e | bellard | bs_table[i] = bdrv_open(hd_filename[i], snapshot); |
2776 | 33e3963e | bellard | if (!bs_table[i]) {
|
2777 | 33e3963e | bellard | fprintf(stderr, "vl: could not open hard disk image '%s\n",
|
2778 | 33e3963e | bellard | hd_filename[i]); |
2779 | 33e3963e | bellard | exit(1);
|
2780 | 33e3963e | bellard | } |
2781 | 33e3963e | bellard | } |
2782 | 33e3963e | bellard | } |
2783 | 33e3963e | bellard | |
2784 | 0824d6fc | bellard | /* now we can load the kernel */
|
2785 | 0824d6fc | bellard | ret = load_kernel(argv[optind], phys_ram_base + KERNEL_LOAD_ADDR); |
2786 | 0824d6fc | bellard | if (ret < 0) { |
2787 | fc01f7e7 | bellard | fprintf(stderr, "vl: could not load kernel '%s'\n", argv[optind]);
|
2788 | 0824d6fc | bellard | exit(1);
|
2789 | 0824d6fc | bellard | } |
2790 | 0824d6fc | bellard | |
2791 | 0824d6fc | bellard | /* load initrd */
|
2792 | fc01f7e7 | bellard | initrd_size = 0;
|
2793 | fc01f7e7 | bellard | if (initrd_filename) {
|
2794 | fc01f7e7 | bellard | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
2795 | fc01f7e7 | bellard | if (initrd_size < 0) { |
2796 | fc01f7e7 | bellard | fprintf(stderr, "vl: could not load initial ram disk '%s'\n",
|
2797 | fc01f7e7 | bellard | initrd_filename); |
2798 | fc01f7e7 | bellard | exit(1);
|
2799 | fc01f7e7 | bellard | } |
2800 | 0824d6fc | bellard | } |
2801 | 0824d6fc | bellard | |
2802 | 0824d6fc | bellard | /* init kernel params */
|
2803 | 0824d6fc | bellard | params = (void *)(phys_ram_base + KERNEL_PARAMS_ADDR);
|
2804 | 0824d6fc | bellard | memset(params, 0, sizeof(struct linux_params)); |
2805 | 0824d6fc | bellard | params->mount_root_rdonly = 0;
|
2806 | 0824d6fc | bellard | params->cl_magic = 0xA33F;
|
2807 | 0824d6fc | bellard | params->cl_offset = params->commandline - (uint8_t *)params; |
2808 | 7916e224 | bellard | params->alt_mem_k = (phys_ram_size / 1024) - 1024; |
2809 | fc01f7e7 | bellard | for(i = optind + 1; i < argc; i++) { |
2810 | fc01f7e7 | bellard | if (i != optind + 1) |
2811 | 0824d6fc | bellard | pstrcat(params->commandline, sizeof(params->commandline), " "); |
2812 | 0824d6fc | bellard | pstrcat(params->commandline, sizeof(params->commandline), argv[i]);
|
2813 | 0824d6fc | bellard | } |
2814 | 0824d6fc | bellard | params->loader_type = 0x01;
|
2815 | 0824d6fc | bellard | if (initrd_size > 0) { |
2816 | 0824d6fc | bellard | params->initrd_start = INITRD_LOAD_ADDR; |
2817 | 0824d6fc | bellard | params->initrd_size = initrd_size; |
2818 | 0824d6fc | bellard | } |
2819 | 0824d6fc | bellard | params->orig_video_lines = 25;
|
2820 | 0824d6fc | bellard | params->orig_video_cols = 80;
|
2821 | 0824d6fc | bellard | |
2822 | 0824d6fc | bellard | /* init basic PC hardware */
|
2823 | 0824d6fc | bellard | init_ioports(); |
2824 | fc01f7e7 | bellard | register_ioport_write(0x80, 1, ioport80_write, 1); |
2825 | 0824d6fc | bellard | |
2826 | fc01f7e7 | bellard | register_ioport_write(0x3d4, 2, vga_ioport_write, 1); |
2827 | 0824d6fc | bellard | |
2828 | 0824d6fc | bellard | cmos_init(); |
2829 | 0824d6fc | bellard | pic_init(); |
2830 | 0824d6fc | bellard | pit_init(); |
2831 | 0824d6fc | bellard | serial_init(); |
2832 | f1510b2c | bellard | ne2000_init(); |
2833 | fc01f7e7 | bellard | ide_init(); |
2834 | cd4c3e88 | bellard | kbd_init(); |
2835 | 0824d6fc | bellard | |
2836 | 0824d6fc | bellard | /* setup cpu signal handlers for MMU / self modifying code handling */
|
2837 | 0824d6fc | bellard | sigfillset(&act.sa_mask); |
2838 | 0824d6fc | bellard | act.sa_flags = SA_SIGINFO; |
2839 | 0824d6fc | bellard | act.sa_sigaction = host_segv_handler; |
2840 | 0824d6fc | bellard | sigaction(SIGSEGV, &act, NULL);
|
2841 | 0824d6fc | bellard | sigaction(SIGBUS, &act, NULL);
|
2842 | 0824d6fc | bellard | |
2843 | 0824d6fc | bellard | act.sa_sigaction = host_alarm_handler; |
2844 | 0824d6fc | bellard | sigaction(SIGALRM, &act, NULL);
|
2845 | 0824d6fc | bellard | |
2846 | 0824d6fc | bellard | /* init CPU state */
|
2847 | 0824d6fc | bellard | env = cpu_init(); |
2848 | 0824d6fc | bellard | global_env = env; |
2849 | 1df912cf | bellard | cpu_single_env = env; |
2850 | 0824d6fc | bellard | |
2851 | 0824d6fc | bellard | /* setup basic memory access */
|
2852 | 0824d6fc | bellard | env->cr[0] = 0x00000033; |
2853 | 0824d6fc | bellard | cpu_x86_init_mmu(env); |
2854 | 0824d6fc | bellard | |
2855 | 0824d6fc | bellard | memset(params->idt_table, 0, sizeof(params->idt_table)); |
2856 | 0824d6fc | bellard | |
2857 | 0824d6fc | bellard | params->gdt_table[2] = 0x00cf9a000000ffffLL; /* KERNEL_CS */ |
2858 | 0824d6fc | bellard | params->gdt_table[3] = 0x00cf92000000ffffLL; /* KERNEL_DS */ |
2859 | 0824d6fc | bellard | |
2860 | 0824d6fc | bellard | env->idt.base = (void *)params->idt_table;
|
2861 | 0824d6fc | bellard | env->idt.limit = sizeof(params->idt_table) - 1; |
2862 | 0824d6fc | bellard | env->gdt.base = (void *)params->gdt_table;
|
2863 | 0824d6fc | bellard | env->gdt.limit = sizeof(params->gdt_table) - 1; |
2864 | 0824d6fc | bellard | |
2865 | 0824d6fc | bellard | cpu_x86_load_seg(env, R_CS, KERNEL_CS); |
2866 | 0824d6fc | bellard | cpu_x86_load_seg(env, R_DS, KERNEL_DS); |
2867 | 0824d6fc | bellard | cpu_x86_load_seg(env, R_ES, KERNEL_DS); |
2868 | 0824d6fc | bellard | cpu_x86_load_seg(env, R_SS, KERNEL_DS); |
2869 | 0824d6fc | bellard | cpu_x86_load_seg(env, R_FS, KERNEL_DS); |
2870 | 0824d6fc | bellard | cpu_x86_load_seg(env, R_GS, KERNEL_DS); |
2871 | 0824d6fc | bellard | |
2872 | 0824d6fc | bellard | env->eip = KERNEL_LOAD_ADDR; |
2873 | 0824d6fc | bellard | env->regs[R_ESI] = KERNEL_PARAMS_ADDR; |
2874 | 0824d6fc | bellard | env->eflags = 0x2;
|
2875 | 0824d6fc | bellard | |
2876 | 0824d6fc | bellard | itv.it_interval.tv_sec = 0;
|
2877 | 87858c89 | bellard | itv.it_interval.tv_usec = 1000;
|
2878 | 0824d6fc | bellard | itv.it_value.tv_sec = 0;
|
2879 | 0824d6fc | bellard | itv.it_value.tv_usec = 10 * 1000; |
2880 | 0824d6fc | bellard | setitimer(ITIMER_REAL, &itv, NULL);
|
2881 | 87858c89 | bellard | /* we probe the tick duration of the kernel to inform the user if
|
2882 | 87858c89 | bellard | the emulated kernel requested a too high timer frequency */
|
2883 | 87858c89 | bellard | getitimer(ITIMER_REAL, &itv); |
2884 | 87858c89 | bellard | pit_min_timer_count = ((uint64_t)itv.it_interval.tv_usec * PIT_FREQ) / |
2885 | 87858c89 | bellard | 1000000;
|
2886 | b4608c04 | bellard | |
2887 | b4608c04 | bellard | if (use_gdbstub) {
|
2888 | b4608c04 | bellard | cpu_gdbstub(NULL, main_loop, gdbstub_port);
|
2889 | b4608c04 | bellard | } else {
|
2890 | b4608c04 | bellard | main_loop(NULL);
|
2891 | 0824d6fc | bellard | } |
2892 | 0824d6fc | bellard | return 0; |
2893 | 0824d6fc | bellard | } |