root / hw / mc146818rtc.c @ a4d5f62c
History | View | Annotate | Download (18.4 kB)
1 | 80cabfad | bellard | /*
|
---|---|---|---|
2 | 80cabfad | bellard | * QEMU MC146818 RTC emulation
|
3 | 5fafdf24 | ths | *
|
4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
|
5 | 5fafdf24 | ths | *
|
6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
|
9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
|
12 | 80cabfad | bellard | *
|
13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
|
15 | 80cabfad | bellard | *
|
16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 80cabfad | bellard | * THE SOFTWARE.
|
23 | 80cabfad | bellard | */
|
24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "qemu-timer.h" |
26 | 87ecb68b | pbrook | #include "sysemu.h" |
27 | 87ecb68b | pbrook | #include "pc.h" |
28 | 87ecb68b | pbrook | #include "isa.h" |
29 | 16b29ae1 | aliguori | #include "hpet_emul.h" |
30 | 80cabfad | bellard | |
31 | 80cabfad | bellard | //#define DEBUG_CMOS
|
32 | 80cabfad | bellard | |
33 | dd17765b | Gleb Natapov | #define RTC_REINJECT_ON_ACK_COUNT 20 |
34 | ba32edab | Gleb Natapov | |
35 | 80cabfad | bellard | #define RTC_SECONDS 0 |
36 | 80cabfad | bellard | #define RTC_SECONDS_ALARM 1 |
37 | 80cabfad | bellard | #define RTC_MINUTES 2 |
38 | 80cabfad | bellard | #define RTC_MINUTES_ALARM 3 |
39 | 80cabfad | bellard | #define RTC_HOURS 4 |
40 | 80cabfad | bellard | #define RTC_HOURS_ALARM 5 |
41 | 80cabfad | bellard | #define RTC_ALARM_DONT_CARE 0xC0 |
42 | 80cabfad | bellard | |
43 | 80cabfad | bellard | #define RTC_DAY_OF_WEEK 6 |
44 | 80cabfad | bellard | #define RTC_DAY_OF_MONTH 7 |
45 | 80cabfad | bellard | #define RTC_MONTH 8 |
46 | 80cabfad | bellard | #define RTC_YEAR 9 |
47 | 80cabfad | bellard | |
48 | 80cabfad | bellard | #define RTC_REG_A 10 |
49 | 80cabfad | bellard | #define RTC_REG_B 11 |
50 | 80cabfad | bellard | #define RTC_REG_C 12 |
51 | 80cabfad | bellard | #define RTC_REG_D 13 |
52 | 80cabfad | bellard | |
53 | dff38e7b | bellard | #define REG_A_UIP 0x80 |
54 | 80cabfad | bellard | |
55 | 100d9891 | aurel32 | #define REG_B_SET 0x80 |
56 | 100d9891 | aurel32 | #define REG_B_PIE 0x40 |
57 | 100d9891 | aurel32 | #define REG_B_AIE 0x20 |
58 | 100d9891 | aurel32 | #define REG_B_UIE 0x10 |
59 | 100d9891 | aurel32 | #define REG_B_SQWE 0x08 |
60 | 100d9891 | aurel32 | #define REG_B_DM 0x04 |
61 | dff38e7b | bellard | |
62 | 72716184 | Anthony Liguori | #define REG_C_UF 0x10 |
63 | 72716184 | Anthony Liguori | #define REG_C_IRQF 0x80 |
64 | 72716184 | Anthony Liguori | #define REG_C_PF 0x40 |
65 | 72716184 | Anthony Liguori | #define REG_C_AF 0x20 |
66 | 72716184 | Anthony Liguori | |
67 | dff38e7b | bellard | struct RTCState {
|
68 | 32e0c826 | Gerd Hoffmann | ISADevice dev; |
69 | dff38e7b | bellard | uint8_t cmos_data[128];
|
70 | dff38e7b | bellard | uint8_t cmos_index; |
71 | 43f493af | bellard | struct tm current_tm;
|
72 | 32e0c826 | Gerd Hoffmann | int32_t base_year; |
73 | d537cf6c | pbrook | qemu_irq irq; |
74 | 100d9891 | aurel32 | qemu_irq sqw_irq; |
75 | 18c6e2ff | ths | int it_shift;
|
76 | dff38e7b | bellard | /* periodic timer */
|
77 | dff38e7b | bellard | QEMUTimer *periodic_timer; |
78 | dff38e7b | bellard | int64_t next_periodic_time; |
79 | dff38e7b | bellard | /* second update */
|
80 | dff38e7b | bellard | int64_t next_second_time; |
81 | ba32edab | Gleb Natapov | uint16_t irq_reinject_on_ack_count; |
82 | 73822ec8 | aliguori | uint32_t irq_coalesced; |
83 | 73822ec8 | aliguori | uint32_t period; |
84 | 93b66569 | aliguori | QEMUTimer *coalesced_timer; |
85 | dff38e7b | bellard | QEMUTimer *second_timer; |
86 | dff38e7b | bellard | QEMUTimer *second_timer2; |
87 | dff38e7b | bellard | }; |
88 | dff38e7b | bellard | |
89 | e0ca7b94 | Juan Quintela | static void rtc_irq_raise(qemu_irq irq) |
90 | e0ca7b94 | Juan Quintela | { |
91 | c50c2d68 | aurel32 | /* When HPET is operating in legacy mode, RTC interrupts are disabled
|
92 | 16b29ae1 | aliguori | * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
|
93 | c50c2d68 | aurel32 | * mode is established while interrupt is raised. We want it to
|
94 | 16b29ae1 | aliguori | * be lowered in any case
|
95 | c50c2d68 | aurel32 | */
|
96 | ce88f890 | Juan Quintela | #if defined TARGET_I386
|
97 | c50c2d68 | aurel32 | if (!hpet_in_legacy_mode())
|
98 | 16b29ae1 | aliguori | #endif
|
99 | 16b29ae1 | aliguori | qemu_irq_raise(irq); |
100 | 16b29ae1 | aliguori | } |
101 | 16b29ae1 | aliguori | |
102 | dff38e7b | bellard | static void rtc_set_time(RTCState *s); |
103 | dff38e7b | bellard | static void rtc_copy_date(RTCState *s); |
104 | dff38e7b | bellard | |
105 | 93b66569 | aliguori | #ifdef TARGET_I386
|
106 | 93b66569 | aliguori | static void rtc_coalesced_timer_update(RTCState *s) |
107 | 93b66569 | aliguori | { |
108 | 93b66569 | aliguori | if (s->irq_coalesced == 0) { |
109 | 93b66569 | aliguori | qemu_del_timer(s->coalesced_timer); |
110 | 93b66569 | aliguori | } else {
|
111 | 93b66569 | aliguori | /* divide each RTC interval to 2 - 8 smaller intervals */
|
112 | 93b66569 | aliguori | int c = MIN(s->irq_coalesced, 7) + 1; |
113 | 6875204c | Jan Kiszka | int64_t next_clock = qemu_get_clock(rtc_clock) + |
114 | 6875204c | Jan Kiszka | muldiv64(s->period / c, get_ticks_per_sec(), 32768);
|
115 | 93b66569 | aliguori | qemu_mod_timer(s->coalesced_timer, next_clock); |
116 | 93b66569 | aliguori | } |
117 | 93b66569 | aliguori | } |
118 | 93b66569 | aliguori | |
119 | 93b66569 | aliguori | static void rtc_coalesced_timer(void *opaque) |
120 | 93b66569 | aliguori | { |
121 | 93b66569 | aliguori | RTCState *s = opaque; |
122 | 93b66569 | aliguori | |
123 | 93b66569 | aliguori | if (s->irq_coalesced != 0) { |
124 | 93b66569 | aliguori | apic_reset_irq_delivered(); |
125 | 93b66569 | aliguori | s->cmos_data[RTC_REG_C] |= 0xc0;
|
126 | 93b66569 | aliguori | rtc_irq_raise(s->irq); |
127 | 93b66569 | aliguori | if (apic_get_irq_delivered()) {
|
128 | 93b66569 | aliguori | s->irq_coalesced--; |
129 | 93b66569 | aliguori | } |
130 | 93b66569 | aliguori | } |
131 | 93b66569 | aliguori | |
132 | 93b66569 | aliguori | rtc_coalesced_timer_update(s); |
133 | 93b66569 | aliguori | } |
134 | 93b66569 | aliguori | #endif
|
135 | 93b66569 | aliguori | |
136 | dff38e7b | bellard | static void rtc_timer_update(RTCState *s, int64_t current_time) |
137 | dff38e7b | bellard | { |
138 | dff38e7b | bellard | int period_code, period;
|
139 | dff38e7b | bellard | int64_t cur_clock, next_irq_clock; |
140 | 100d9891 | aurel32 | int enable_pie;
|
141 | dff38e7b | bellard | |
142 | dff38e7b | bellard | period_code = s->cmos_data[RTC_REG_A] & 0x0f;
|
143 | ce88f890 | Juan Quintela | #if defined TARGET_I386
|
144 | c50c2d68 | aurel32 | /* disable periodic timer if hpet is in legacy mode, since interrupts are
|
145 | 16b29ae1 | aliguori | * disabled anyway.
|
146 | 16b29ae1 | aliguori | */
|
147 | a8b01dd8 | pbrook | enable_pie = !hpet_in_legacy_mode(); |
148 | 16b29ae1 | aliguori | #else
|
149 | 100d9891 | aurel32 | enable_pie = 1;
|
150 | 16b29ae1 | aliguori | #endif
|
151 | 100d9891 | aurel32 | if (period_code != 0 |
152 | 100d9891 | aurel32 | && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie) |
153 | 100d9891 | aurel32 | || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) { |
154 | dff38e7b | bellard | if (period_code <= 2) |
155 | dff38e7b | bellard | period_code += 7;
|
156 | dff38e7b | bellard | /* period in 32 Khz cycles */
|
157 | dff38e7b | bellard | period = 1 << (period_code - 1); |
158 | 73822ec8 | aliguori | #ifdef TARGET_I386
|
159 | 73822ec8 | aliguori | if(period != s->period)
|
160 | 73822ec8 | aliguori | s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
161 | 73822ec8 | aliguori | s->period = period; |
162 | 73822ec8 | aliguori | #endif
|
163 | dff38e7b | bellard | /* compute 32 khz clock */
|
164 | 6ee093c9 | Juan Quintela | cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
|
165 | dff38e7b | bellard | next_irq_clock = (cur_clock & ~(period - 1)) + period;
|
166 | 6875204c | Jan Kiszka | s->next_periodic_time = |
167 | 6875204c | Jan Kiszka | muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1; |
168 | dff38e7b | bellard | qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
169 | dff38e7b | bellard | } else {
|
170 | 73822ec8 | aliguori | #ifdef TARGET_I386
|
171 | 73822ec8 | aliguori | s->irq_coalesced = 0;
|
172 | 73822ec8 | aliguori | #endif
|
173 | dff38e7b | bellard | qemu_del_timer(s->periodic_timer); |
174 | dff38e7b | bellard | } |
175 | dff38e7b | bellard | } |
176 | dff38e7b | bellard | |
177 | dff38e7b | bellard | static void rtc_periodic_timer(void *opaque) |
178 | dff38e7b | bellard | { |
179 | dff38e7b | bellard | RTCState *s = opaque; |
180 | dff38e7b | bellard | |
181 | dff38e7b | bellard | rtc_timer_update(s, s->next_periodic_time); |
182 | 100d9891 | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
|
183 | 100d9891 | aurel32 | s->cmos_data[RTC_REG_C] |= 0xc0;
|
184 | 93b66569 | aliguori | #ifdef TARGET_I386
|
185 | 93b66569 | aliguori | if(rtc_td_hack) {
|
186 | ba32edab | Gleb Natapov | if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
|
187 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count = 0;
|
188 | 93b66569 | aliguori | apic_reset_irq_delivered(); |
189 | 93b66569 | aliguori | rtc_irq_raise(s->irq); |
190 | 93b66569 | aliguori | if (!apic_get_irq_delivered()) {
|
191 | 93b66569 | aliguori | s->irq_coalesced++; |
192 | 93b66569 | aliguori | rtc_coalesced_timer_update(s); |
193 | 93b66569 | aliguori | } |
194 | 93b66569 | aliguori | } else
|
195 | 93b66569 | aliguori | #endif
|
196 | 100d9891 | aurel32 | rtc_irq_raise(s->irq); |
197 | 100d9891 | aurel32 | } |
198 | 100d9891 | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
|
199 | 100d9891 | aurel32 | /* Not square wave at all but we don't want 2048Hz interrupts!
|
200 | 100d9891 | aurel32 | Must be seen as a pulse. */
|
201 | 100d9891 | aurel32 | qemu_irq_raise(s->sqw_irq); |
202 | 100d9891 | aurel32 | } |
203 | dff38e7b | bellard | } |
204 | 80cabfad | bellard | |
205 | b41a2cd1 | bellard | static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
206 | 80cabfad | bellard | { |
207 | b41a2cd1 | bellard | RTCState *s = opaque; |
208 | 80cabfad | bellard | |
209 | 80cabfad | bellard | if ((addr & 1) == 0) { |
210 | 80cabfad | bellard | s->cmos_index = data & 0x7f;
|
211 | 80cabfad | bellard | } else {
|
212 | 80cabfad | bellard | #ifdef DEBUG_CMOS
|
213 | 80cabfad | bellard | printf("cmos: write index=0x%02x val=0x%02x\n",
|
214 | 80cabfad | bellard | s->cmos_index, data); |
215 | 3b46e624 | ths | #endif
|
216 | dff38e7b | bellard | switch(s->cmos_index) {
|
217 | 80cabfad | bellard | case RTC_SECONDS_ALARM:
|
218 | 80cabfad | bellard | case RTC_MINUTES_ALARM:
|
219 | 80cabfad | bellard | case RTC_HOURS_ALARM:
|
220 | 80cabfad | bellard | /* XXX: not supported */
|
221 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
222 | 80cabfad | bellard | break;
|
223 | 80cabfad | bellard | case RTC_SECONDS:
|
224 | 80cabfad | bellard | case RTC_MINUTES:
|
225 | 80cabfad | bellard | case RTC_HOURS:
|
226 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
|
227 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
|
228 | 80cabfad | bellard | case RTC_MONTH:
|
229 | 80cabfad | bellard | case RTC_YEAR:
|
230 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
231 | dff38e7b | bellard | /* if in set mode, do not update the time */
|
232 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
233 | dff38e7b | bellard | rtc_set_time(s); |
234 | dff38e7b | bellard | } |
235 | 80cabfad | bellard | break;
|
236 | 80cabfad | bellard | case RTC_REG_A:
|
237 | dff38e7b | bellard | /* UIP bit is read only */
|
238 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
239 | dff38e7b | bellard | (s->cmos_data[RTC_REG_A] & REG_A_UIP); |
240 | 6875204c | Jan Kiszka | rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
241 | dff38e7b | bellard | break;
|
242 | 80cabfad | bellard | case RTC_REG_B:
|
243 | dff38e7b | bellard | if (data & REG_B_SET) {
|
244 | dff38e7b | bellard | /* set mode: reset UIP mode */
|
245 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
246 | dff38e7b | bellard | data &= ~REG_B_UIE; |
247 | dff38e7b | bellard | } else {
|
248 | dff38e7b | bellard | /* if disabling set mode, update the time */
|
249 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
|
250 | dff38e7b | bellard | rtc_set_time(s); |
251 | dff38e7b | bellard | } |
252 | dff38e7b | bellard | } |
253 | dff38e7b | bellard | s->cmos_data[RTC_REG_B] = data; |
254 | 6875204c | Jan Kiszka | rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
255 | 80cabfad | bellard | break;
|
256 | 80cabfad | bellard | case RTC_REG_C:
|
257 | 80cabfad | bellard | case RTC_REG_D:
|
258 | 80cabfad | bellard | /* cannot write to them */
|
259 | 80cabfad | bellard | break;
|
260 | 80cabfad | bellard | default:
|
261 | 80cabfad | bellard | s->cmos_data[s->cmos_index] = data; |
262 | 80cabfad | bellard | break;
|
263 | 80cabfad | bellard | } |
264 | 80cabfad | bellard | } |
265 | 80cabfad | bellard | } |
266 | 80cabfad | bellard | |
267 | abd0c6bd | Paul Brook | static inline int rtc_to_bcd(RTCState *s, int a) |
268 | 80cabfad | bellard | { |
269 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
|
270 | dff38e7b | bellard | return a;
|
271 | dff38e7b | bellard | } else {
|
272 | dff38e7b | bellard | return ((a / 10) << 4) | (a % 10); |
273 | dff38e7b | bellard | } |
274 | 80cabfad | bellard | } |
275 | 80cabfad | bellard | |
276 | abd0c6bd | Paul Brook | static inline int rtc_from_bcd(RTCState *s, int a) |
277 | 80cabfad | bellard | { |
278 | 6f1bf24d | aurel32 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
|
279 | dff38e7b | bellard | return a;
|
280 | dff38e7b | bellard | } else {
|
281 | dff38e7b | bellard | return ((a >> 4) * 10) + (a & 0x0f); |
282 | dff38e7b | bellard | } |
283 | dff38e7b | bellard | } |
284 | dff38e7b | bellard | |
285 | dff38e7b | bellard | static void rtc_set_time(RTCState *s) |
286 | dff38e7b | bellard | { |
287 | 43f493af | bellard | struct tm *tm = &s->current_tm;
|
288 | dff38e7b | bellard | |
289 | abd0c6bd | Paul Brook | tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
290 | abd0c6bd | Paul Brook | tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); |
291 | abd0c6bd | Paul Brook | tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
|
292 | 43f493af | bellard | if (!(s->cmos_data[RTC_REG_B] & 0x02) && |
293 | 43f493af | bellard | (s->cmos_data[RTC_HOURS] & 0x80)) {
|
294 | 43f493af | bellard | tm->tm_hour += 12;
|
295 | 43f493af | bellard | } |
296 | abd0c6bd | Paul Brook | tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
|
297 | abd0c6bd | Paul Brook | tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
298 | abd0c6bd | Paul Brook | tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
|
299 | abd0c6bd | Paul Brook | tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
|
300 | 43f493af | bellard | } |
301 | 43f493af | bellard | |
302 | 43f493af | bellard | static void rtc_copy_date(RTCState *s) |
303 | 43f493af | bellard | { |
304 | 43f493af | bellard | const struct tm *tm = &s->current_tm; |
305 | 42fc73a1 | aurel32 | int year;
|
306 | dff38e7b | bellard | |
307 | abd0c6bd | Paul Brook | s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
308 | abd0c6bd | Paul Brook | s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); |
309 | 43f493af | bellard | if (s->cmos_data[RTC_REG_B] & 0x02) { |
310 | 43f493af | bellard | /* 24 hour format */
|
311 | abd0c6bd | Paul Brook | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
312 | 43f493af | bellard | } else {
|
313 | 43f493af | bellard | /* 12 hour format */
|
314 | abd0c6bd | Paul Brook | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour % 12);
|
315 | 43f493af | bellard | if (tm->tm_hour >= 12) |
316 | 43f493af | bellard | s->cmos_data[RTC_HOURS] |= 0x80;
|
317 | 43f493af | bellard | } |
318 | abd0c6bd | Paul Brook | s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
|
319 | abd0c6bd | Paul Brook | s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); |
320 | abd0c6bd | Paul Brook | s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
|
321 | 42fc73a1 | aurel32 | year = (tm->tm_year - s->base_year) % 100;
|
322 | 42fc73a1 | aurel32 | if (year < 0) |
323 | 42fc73a1 | aurel32 | year += 100;
|
324 | abd0c6bd | Paul Brook | s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year); |
325 | 43f493af | bellard | } |
326 | 43f493af | bellard | |
327 | 43f493af | bellard | /* month is between 0 and 11. */
|
328 | 43f493af | bellard | static int get_days_in_month(int month, int year) |
329 | 43f493af | bellard | { |
330 | 5fafdf24 | ths | static const int days_tab[12] = { |
331 | 5fafdf24 | ths | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
332 | 43f493af | bellard | }; |
333 | 43f493af | bellard | int d;
|
334 | 43f493af | bellard | if ((unsigned )month >= 12) |
335 | 43f493af | bellard | return 31; |
336 | 43f493af | bellard | d = days_tab[month]; |
337 | 43f493af | bellard | if (month == 1) { |
338 | 43f493af | bellard | if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) |
339 | 43f493af | bellard | d++; |
340 | 43f493af | bellard | } |
341 | 43f493af | bellard | return d;
|
342 | 43f493af | bellard | } |
343 | 43f493af | bellard | |
344 | 43f493af | bellard | /* update 'tm' to the next second */
|
345 | 43f493af | bellard | static void rtc_next_second(struct tm *tm) |
346 | 43f493af | bellard | { |
347 | 43f493af | bellard | int days_in_month;
|
348 | 43f493af | bellard | |
349 | 43f493af | bellard | tm->tm_sec++; |
350 | 43f493af | bellard | if ((unsigned)tm->tm_sec >= 60) { |
351 | 43f493af | bellard | tm->tm_sec = 0;
|
352 | 43f493af | bellard | tm->tm_min++; |
353 | 43f493af | bellard | if ((unsigned)tm->tm_min >= 60) { |
354 | 43f493af | bellard | tm->tm_min = 0;
|
355 | 43f493af | bellard | tm->tm_hour++; |
356 | 43f493af | bellard | if ((unsigned)tm->tm_hour >= 24) { |
357 | 43f493af | bellard | tm->tm_hour = 0;
|
358 | 43f493af | bellard | /* next day */
|
359 | 43f493af | bellard | tm->tm_wday++; |
360 | 43f493af | bellard | if ((unsigned)tm->tm_wday >= 7) |
361 | 43f493af | bellard | tm->tm_wday = 0;
|
362 | 5fafdf24 | ths | days_in_month = get_days_in_month(tm->tm_mon, |
363 | 43f493af | bellard | tm->tm_year + 1900);
|
364 | 43f493af | bellard | tm->tm_mday++; |
365 | 43f493af | bellard | if (tm->tm_mday < 1) { |
366 | 43f493af | bellard | tm->tm_mday = 1;
|
367 | 43f493af | bellard | } else if (tm->tm_mday > days_in_month) { |
368 | 43f493af | bellard | tm->tm_mday = 1;
|
369 | 43f493af | bellard | tm->tm_mon++; |
370 | 43f493af | bellard | if (tm->tm_mon >= 12) { |
371 | 43f493af | bellard | tm->tm_mon = 0;
|
372 | 43f493af | bellard | tm->tm_year++; |
373 | 43f493af | bellard | } |
374 | 43f493af | bellard | } |
375 | 43f493af | bellard | } |
376 | 43f493af | bellard | } |
377 | 43f493af | bellard | } |
378 | dff38e7b | bellard | } |
379 | dff38e7b | bellard | |
380 | 43f493af | bellard | |
381 | dff38e7b | bellard | static void rtc_update_second(void *opaque) |
382 | dff38e7b | bellard | { |
383 | dff38e7b | bellard | RTCState *s = opaque; |
384 | 4721c457 | bellard | int64_t delay; |
385 | dff38e7b | bellard | |
386 | dff38e7b | bellard | /* if the oscillator is not in normal operation, we do not update */
|
387 | dff38e7b | bellard | if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { |
388 | 6ee093c9 | Juan Quintela | s->next_second_time += get_ticks_per_sec(); |
389 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
390 | dff38e7b | bellard | } else {
|
391 | 43f493af | bellard | rtc_next_second(&s->current_tm); |
392 | 3b46e624 | ths | |
393 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
394 | dff38e7b | bellard | /* update in progress bit */
|
395 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
396 | dff38e7b | bellard | } |
397 | 4721c457 | bellard | /* should be 244 us = 8 / 32768 seconds, but currently the
|
398 | 4721c457 | bellard | timers do not have the necessary resolution. */
|
399 | 6ee093c9 | Juan Quintela | delay = (get_ticks_per_sec() * 1) / 100; |
400 | 4721c457 | bellard | if (delay < 1) |
401 | 4721c457 | bellard | delay = 1;
|
402 | 5fafdf24 | ths | qemu_mod_timer(s->second_timer2, |
403 | 4721c457 | bellard | s->next_second_time + delay); |
404 | dff38e7b | bellard | } |
405 | dff38e7b | bellard | } |
406 | dff38e7b | bellard | |
407 | dff38e7b | bellard | static void rtc_update_second2(void *opaque) |
408 | dff38e7b | bellard | { |
409 | dff38e7b | bellard | RTCState *s = opaque; |
410 | dff38e7b | bellard | |
411 | dff38e7b | bellard | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
412 | dff38e7b | bellard | rtc_copy_date(s); |
413 | dff38e7b | bellard | } |
414 | dff38e7b | bellard | |
415 | dff38e7b | bellard | /* check alarm */
|
416 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
|
417 | dff38e7b | bellard | if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
418 | 43f493af | bellard | s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) && |
419 | dff38e7b | bellard | ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
420 | 43f493af | bellard | s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) && |
421 | dff38e7b | bellard | ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
422 | 43f493af | bellard | s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) { |
423 | dff38e7b | bellard | |
424 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] |= 0xa0;
|
425 | 16b29ae1 | aliguori | rtc_irq_raise(s->irq); |
426 | dff38e7b | bellard | } |
427 | dff38e7b | bellard | } |
428 | dff38e7b | bellard | |
429 | dff38e7b | bellard | /* update ended interrupt */
|
430 | 98815437 | Bernhard Kauer | s->cmos_data[RTC_REG_C] |= REG_C_UF; |
431 | dff38e7b | bellard | if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
|
432 | 98815437 | Bernhard Kauer | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
433 | 98815437 | Bernhard Kauer | rtc_irq_raise(s->irq); |
434 | dff38e7b | bellard | } |
435 | dff38e7b | bellard | |
436 | dff38e7b | bellard | /* clear update in progress bit */
|
437 | dff38e7b | bellard | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
438 | dff38e7b | bellard | |
439 | 6ee093c9 | Juan Quintela | s->next_second_time += get_ticks_per_sec(); |
440 | dff38e7b | bellard | qemu_mod_timer(s->second_timer, s->next_second_time); |
441 | 80cabfad | bellard | } |
442 | 80cabfad | bellard | |
443 | b41a2cd1 | bellard | static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
444 | 80cabfad | bellard | { |
445 | b41a2cd1 | bellard | RTCState *s = opaque; |
446 | 80cabfad | bellard | int ret;
|
447 | 80cabfad | bellard | if ((addr & 1) == 0) { |
448 | 80cabfad | bellard | return 0xff; |
449 | 80cabfad | bellard | } else {
|
450 | 80cabfad | bellard | switch(s->cmos_index) {
|
451 | 80cabfad | bellard | case RTC_SECONDS:
|
452 | 80cabfad | bellard | case RTC_MINUTES:
|
453 | 80cabfad | bellard | case RTC_HOURS:
|
454 | 80cabfad | bellard | case RTC_DAY_OF_WEEK:
|
455 | 80cabfad | bellard | case RTC_DAY_OF_MONTH:
|
456 | 80cabfad | bellard | case RTC_MONTH:
|
457 | 80cabfad | bellard | case RTC_YEAR:
|
458 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
459 | 80cabfad | bellard | break;
|
460 | 80cabfad | bellard | case RTC_REG_A:
|
461 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
462 | 80cabfad | bellard | break;
|
463 | 80cabfad | bellard | case RTC_REG_C:
|
464 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
465 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
466 | ba32edab | Gleb Natapov | #ifdef TARGET_I386
|
467 | ba32edab | Gleb Natapov | if(s->irq_coalesced &&
|
468 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) { |
469 | ba32edab | Gleb Natapov | s->irq_reinject_on_ack_count++; |
470 | ba32edab | Gleb Natapov | apic_reset_irq_delivered(); |
471 | ba32edab | Gleb Natapov | qemu_irq_raise(s->irq); |
472 | ba32edab | Gleb Natapov | if (apic_get_irq_delivered())
|
473 | ba32edab | Gleb Natapov | s->irq_coalesced--; |
474 | ba32edab | Gleb Natapov | break;
|
475 | ba32edab | Gleb Natapov | } |
476 | ba32edab | Gleb Natapov | #endif
|
477 | ba32edab | Gleb Natapov | |
478 | 5fafdf24 | ths | s->cmos_data[RTC_REG_C] = 0x00;
|
479 | 80cabfad | bellard | break;
|
480 | 80cabfad | bellard | default:
|
481 | 80cabfad | bellard | ret = s->cmos_data[s->cmos_index]; |
482 | 80cabfad | bellard | break;
|
483 | 80cabfad | bellard | } |
484 | 80cabfad | bellard | #ifdef DEBUG_CMOS
|
485 | 80cabfad | bellard | printf("cmos: read index=0x%02x val=0x%02x\n",
|
486 | 80cabfad | bellard | s->cmos_index, ret); |
487 | 80cabfad | bellard | #endif
|
488 | 80cabfad | bellard | return ret;
|
489 | 80cabfad | bellard | } |
490 | 80cabfad | bellard | } |
491 | 80cabfad | bellard | |
492 | dff38e7b | bellard | void rtc_set_memory(RTCState *s, int addr, int val) |
493 | dff38e7b | bellard | { |
494 | dff38e7b | bellard | if (addr >= 0 && addr <= 127) |
495 | dff38e7b | bellard | s->cmos_data[addr] = val; |
496 | dff38e7b | bellard | } |
497 | dff38e7b | bellard | |
498 | dff38e7b | bellard | void rtc_set_date(RTCState *s, const struct tm *tm) |
499 | dff38e7b | bellard | { |
500 | 43f493af | bellard | s->current_tm = *tm; |
501 | dff38e7b | bellard | rtc_copy_date(s); |
502 | dff38e7b | bellard | } |
503 | dff38e7b | bellard | |
504 | ea55ffb3 | ths | /* PC cmos mappings */
|
505 | ea55ffb3 | ths | #define REG_IBM_CENTURY_BYTE 0x32 |
506 | ea55ffb3 | ths | #define REG_IBM_PS2_CENTURY_BYTE 0x37 |
507 | ea55ffb3 | ths | |
508 | 9596ebb7 | pbrook | static void rtc_set_date_from_host(RTCState *s) |
509 | ea55ffb3 | ths | { |
510 | f6503059 | balrog | struct tm tm;
|
511 | ea55ffb3 | ths | int val;
|
512 | ea55ffb3 | ths | |
513 | ea55ffb3 | ths | /* set the CMOS date */
|
514 | f6503059 | balrog | qemu_get_timedate(&tm, 0);
|
515 | f6503059 | balrog | rtc_set_date(s, &tm); |
516 | ea55ffb3 | ths | |
517 | abd0c6bd | Paul Brook | val = rtc_to_bcd(s, (tm.tm_year / 100) + 19); |
518 | ea55ffb3 | ths | rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val); |
519 | ea55ffb3 | ths | rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val); |
520 | ea55ffb3 | ths | } |
521 | ea55ffb3 | ths | |
522 | 6b075b8a | Juan Quintela | static int rtc_post_load(void *opaque, int version_id) |
523 | 80cabfad | bellard | { |
524 | 6b075b8a | Juan Quintela | #ifdef TARGET_I386
|
525 | dff38e7b | bellard | RTCState *s = opaque; |
526 | dff38e7b | bellard | |
527 | 048c74c4 | Juan Quintela | if (version_id >= 2) { |
528 | 048c74c4 | Juan Quintela | if (rtc_td_hack) {
|
529 | 048c74c4 | Juan Quintela | rtc_coalesced_timer_update(s); |
530 | 048c74c4 | Juan Quintela | } |
531 | 048c74c4 | Juan Quintela | } |
532 | 6b075b8a | Juan Quintela | #endif
|
533 | 73822ec8 | aliguori | return 0; |
534 | 73822ec8 | aliguori | } |
535 | 73822ec8 | aliguori | |
536 | 6b075b8a | Juan Quintela | static const VMStateDescription vmstate_rtc = { |
537 | 6b075b8a | Juan Quintela | .name = "mc146818rtc",
|
538 | 6b075b8a | Juan Quintela | .version_id = 2,
|
539 | 6b075b8a | Juan Quintela | .minimum_version_id = 1,
|
540 | 6b075b8a | Juan Quintela | .minimum_version_id_old = 1,
|
541 | 6b075b8a | Juan Quintela | .post_load = rtc_post_load, |
542 | 6b075b8a | Juan Quintela | .fields = (VMStateField []) { |
543 | 6b075b8a | Juan Quintela | VMSTATE_BUFFER(cmos_data, RTCState), |
544 | 6b075b8a | Juan Quintela | VMSTATE_UINT8(cmos_index, RTCState), |
545 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_sec, RTCState), |
546 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_min, RTCState), |
547 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_hour, RTCState), |
548 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_wday, RTCState), |
549 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_mday, RTCState), |
550 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_mon, RTCState), |
551 | 6b075b8a | Juan Quintela | VMSTATE_INT32(current_tm.tm_year, RTCState), |
552 | 6b075b8a | Juan Quintela | VMSTATE_TIMER(periodic_timer, RTCState), |
553 | 6b075b8a | Juan Quintela | VMSTATE_INT64(next_periodic_time, RTCState), |
554 | 6b075b8a | Juan Quintela | VMSTATE_INT64(next_second_time, RTCState), |
555 | 6b075b8a | Juan Quintela | VMSTATE_TIMER(second_timer, RTCState), |
556 | 6b075b8a | Juan Quintela | VMSTATE_TIMER(second_timer2, RTCState), |
557 | 6b075b8a | Juan Quintela | VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
|
558 | 6b075b8a | Juan Quintela | VMSTATE_UINT32_V(period, RTCState, 2),
|
559 | 6b075b8a | Juan Quintela | VMSTATE_END_OF_LIST() |
560 | 6b075b8a | Juan Quintela | } |
561 | 6b075b8a | Juan Quintela | }; |
562 | 6b075b8a | Juan Quintela | |
563 | eeb7c03c | Gleb Natapov | static void rtc_reset(void *opaque) |
564 | eeb7c03c | Gleb Natapov | { |
565 | eeb7c03c | Gleb Natapov | RTCState *s = opaque; |
566 | eeb7c03c | Gleb Natapov | |
567 | 72716184 | Anthony Liguori | s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
568 | 72716184 | Anthony Liguori | s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); |
569 | eeb7c03c | Gleb Natapov | |
570 | 72716184 | Anthony Liguori | qemu_irq_lower(s->irq); |
571 | eeb7c03c | Gleb Natapov | |
572 | eeb7c03c | Gleb Natapov | #ifdef TARGET_I386
|
573 | eeb7c03c | Gleb Natapov | if (rtc_td_hack)
|
574 | eeb7c03c | Gleb Natapov | s->irq_coalesced = 0;
|
575 | eeb7c03c | Gleb Natapov | #endif
|
576 | eeb7c03c | Gleb Natapov | } |
577 | eeb7c03c | Gleb Natapov | |
578 | 32e0c826 | Gerd Hoffmann | static int rtc_initfn(ISADevice *dev) |
579 | dff38e7b | bellard | { |
580 | 32e0c826 | Gerd Hoffmann | RTCState *s = DO_UPCAST(RTCState, dev, dev); |
581 | 32e0c826 | Gerd Hoffmann | int base = 0x70; |
582 | 32e0c826 | Gerd Hoffmann | int isairq = 8; |
583 | dff38e7b | bellard | |
584 | 32e0c826 | Gerd Hoffmann | isa_init_irq(dev, &s->irq, isairq); |
585 | 80cabfad | bellard | |
586 | 80cabfad | bellard | s->cmos_data[RTC_REG_A] = 0x26;
|
587 | 80cabfad | bellard | s->cmos_data[RTC_REG_B] = 0x02;
|
588 | 80cabfad | bellard | s->cmos_data[RTC_REG_C] = 0x00;
|
589 | 80cabfad | bellard | s->cmos_data[RTC_REG_D] = 0x80;
|
590 | 80cabfad | bellard | |
591 | ea55ffb3 | ths | rtc_set_date_from_host(s); |
592 | ea55ffb3 | ths | |
593 | 6875204c | Jan Kiszka | s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s); |
594 | 93b66569 | aliguori | #ifdef TARGET_I386
|
595 | 93b66569 | aliguori | if (rtc_td_hack)
|
596 | 6875204c | Jan Kiszka | s->coalesced_timer = |
597 | 6875204c | Jan Kiszka | qemu_new_timer(rtc_clock, rtc_coalesced_timer, s); |
598 | 93b66569 | aliguori | #endif
|
599 | 6875204c | Jan Kiszka | s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s); |
600 | 6875204c | Jan Kiszka | s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s); |
601 | dff38e7b | bellard | |
602 | 6875204c | Jan Kiszka | s->next_second_time = |
603 | 6875204c | Jan Kiszka | qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100; |
604 | dff38e7b | bellard | qemu_mod_timer(s->second_timer2, s->next_second_time); |
605 | dff38e7b | bellard | |
606 | b41a2cd1 | bellard | register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
607 | b41a2cd1 | bellard | register_ioport_read(base, 2, 1, cmos_ioport_read, s); |
608 | dff38e7b | bellard | |
609 | 6b075b8a | Juan Quintela | vmstate_register(base, &vmstate_rtc, s); |
610 | a08d4367 | Jan Kiszka | qemu_register_reset(rtc_reset, s); |
611 | 32e0c826 | Gerd Hoffmann | return 0; |
612 | 32e0c826 | Gerd Hoffmann | } |
613 | 32e0c826 | Gerd Hoffmann | |
614 | 32e0c826 | Gerd Hoffmann | RTCState *rtc_init(int base_year)
|
615 | 32e0c826 | Gerd Hoffmann | { |
616 | 32e0c826 | Gerd Hoffmann | ISADevice *dev; |
617 | eeb7c03c | Gleb Natapov | |
618 | 32e0c826 | Gerd Hoffmann | dev = isa_create("mc146818rtc");
|
619 | 32e0c826 | Gerd Hoffmann | qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
|
620 | e23a1b33 | Markus Armbruster | qdev_init_nofail(&dev->qdev); |
621 | 32e0c826 | Gerd Hoffmann | return DO_UPCAST(RTCState, dev, dev);
|
622 | 80cabfad | bellard | } |
623 | 80cabfad | bellard | |
624 | 32e0c826 | Gerd Hoffmann | static ISADeviceInfo mc146818rtc_info = {
|
625 | 32e0c826 | Gerd Hoffmann | .qdev.name = "mc146818rtc",
|
626 | 32e0c826 | Gerd Hoffmann | .qdev.size = sizeof(RTCState),
|
627 | 32e0c826 | Gerd Hoffmann | .qdev.no_user = 1,
|
628 | 32e0c826 | Gerd Hoffmann | .init = rtc_initfn, |
629 | 32e0c826 | Gerd Hoffmann | .qdev.props = (Property[]) { |
630 | 32e0c826 | Gerd Hoffmann | DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), |
631 | 32e0c826 | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
632 | 32e0c826 | Gerd Hoffmann | } |
633 | 32e0c826 | Gerd Hoffmann | }; |
634 | 32e0c826 | Gerd Hoffmann | |
635 | 32e0c826 | Gerd Hoffmann | static void mc146818rtc_register(void) |
636 | 100d9891 | aurel32 | { |
637 | 32e0c826 | Gerd Hoffmann | isa_qdev_register(&mc146818rtc_info); |
638 | 100d9891 | aurel32 | } |
639 | 32e0c826 | Gerd Hoffmann | device_init(mc146818rtc_register) |