root / hw / cuda.c @ a6307b08
History | View | Annotate | Download (21.1 kB)
1 | 267002cd | bellard | /*
|
---|---|---|---|
2 | 3cbee15b | j_mayer | * QEMU PowerMac CUDA device support
|
3 | 5fafdf24 | ths | *
|
4 | 3cbee15b | j_mayer | * Copyright (c) 2004-2007 Fabrice Bellard
|
5 | 3cbee15b | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
|
6 | 5fafdf24 | ths | *
|
7 | 267002cd | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
8 | 267002cd | bellard | * of this software and associated documentation files (the "Software"), to deal
|
9 | 267002cd | bellard | * in the Software without restriction, including without limitation the rights
|
10 | 267002cd | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
11 | 267002cd | bellard | * copies of the Software, and to permit persons to whom the Software is
|
12 | 267002cd | bellard | * furnished to do so, subject to the following conditions:
|
13 | 267002cd | bellard | *
|
14 | 267002cd | bellard | * The above copyright notice and this permission notice shall be included in
|
15 | 267002cd | bellard | * all copies or substantial portions of the Software.
|
16 | 267002cd | bellard | *
|
17 | 267002cd | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
18 | 267002cd | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
19 | 267002cd | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
20 | 267002cd | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
21 | 267002cd | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
22 | 267002cd | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
23 | 267002cd | bellard | * THE SOFTWARE.
|
24 | 267002cd | bellard | */
|
25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 3cbee15b | j_mayer | #include "ppc_mac.h" |
27 | 87ecb68b | pbrook | #include "qemu-timer.h" |
28 | 87ecb68b | pbrook | #include "sysemu.h" |
29 | 267002cd | bellard | |
30 | 61271e5c | bellard | /* XXX: implement all timer modes */
|
31 | 61271e5c | bellard | |
32 | ea026b2f | blueswir1 | /* debug CUDA */
|
33 | 819e712b | bellard | //#define DEBUG_CUDA
|
34 | ea026b2f | blueswir1 | |
35 | ea026b2f | blueswir1 | /* debug CUDA packets */
|
36 | 819e712b | bellard | //#define DEBUG_CUDA_PACKET
|
37 | 819e712b | bellard | |
38 | ea026b2f | blueswir1 | #ifdef DEBUG_CUDA
|
39 | 001faf32 | Blue Swirl | #define CUDA_DPRINTF(fmt, ...) \
|
40 | 001faf32 | Blue Swirl | do { printf("CUDA: " fmt , ## __VA_ARGS__); } while (0) |
41 | ea026b2f | blueswir1 | #else
|
42 | 001faf32 | Blue Swirl | #define CUDA_DPRINTF(fmt, ...)
|
43 | ea026b2f | blueswir1 | #endif
|
44 | ea026b2f | blueswir1 | |
45 | 267002cd | bellard | /* Bits in B data register: all active low */
|
46 | 267002cd | bellard | #define TREQ 0x08 /* Transfer request (input) */ |
47 | 267002cd | bellard | #define TACK 0x10 /* Transfer acknowledge (output) */ |
48 | 267002cd | bellard | #define TIP 0x20 /* Transfer in progress (output) */ |
49 | 267002cd | bellard | |
50 | 267002cd | bellard | /* Bits in ACR */
|
51 | 267002cd | bellard | #define SR_CTRL 0x1c /* Shift register control bits */ |
52 | 267002cd | bellard | #define SR_EXT 0x0c /* Shift on external clock */ |
53 | 267002cd | bellard | #define SR_OUT 0x10 /* Shift out if 1 */ |
54 | 267002cd | bellard | |
55 | 267002cd | bellard | /* Bits in IFR and IER */
|
56 | 267002cd | bellard | #define IER_SET 0x80 /* set bits in IER */ |
57 | 267002cd | bellard | #define IER_CLR 0 /* clear bits in IER */ |
58 | 267002cd | bellard | #define SR_INT 0x04 /* Shift register full/empty */ |
59 | 267002cd | bellard | #define T1_INT 0x40 /* Timer 1 interrupt */ |
60 | 61271e5c | bellard | #define T2_INT 0x20 /* Timer 2 interrupt */ |
61 | 267002cd | bellard | |
62 | 267002cd | bellard | /* Bits in ACR */
|
63 | 267002cd | bellard | #define T1MODE 0xc0 /* Timer 1 mode */ |
64 | 267002cd | bellard | #define T1MODE_CONT 0x40 /* continuous interrupts */ |
65 | 267002cd | bellard | |
66 | 267002cd | bellard | /* commands (1st byte) */
|
67 | 267002cd | bellard | #define ADB_PACKET 0 |
68 | 267002cd | bellard | #define CUDA_PACKET 1 |
69 | 267002cd | bellard | #define ERROR_PACKET 2 |
70 | 267002cd | bellard | #define TIMER_PACKET 3 |
71 | 267002cd | bellard | #define POWER_PACKET 4 |
72 | 267002cd | bellard | #define MACIIC_PACKET 5 |
73 | 267002cd | bellard | #define PMU_PACKET 6 |
74 | 267002cd | bellard | |
75 | 267002cd | bellard | |
76 | 267002cd | bellard | /* CUDA commands (2nd byte) */
|
77 | 267002cd | bellard | #define CUDA_WARM_START 0x0 |
78 | 267002cd | bellard | #define CUDA_AUTOPOLL 0x1 |
79 | 267002cd | bellard | #define CUDA_GET_6805_ADDR 0x2 |
80 | 267002cd | bellard | #define CUDA_GET_TIME 0x3 |
81 | 267002cd | bellard | #define CUDA_GET_PRAM 0x7 |
82 | 267002cd | bellard | #define CUDA_SET_6805_ADDR 0x8 |
83 | 267002cd | bellard | #define CUDA_SET_TIME 0x9 |
84 | 267002cd | bellard | #define CUDA_POWERDOWN 0xa |
85 | 267002cd | bellard | #define CUDA_POWERUP_TIME 0xb |
86 | 267002cd | bellard | #define CUDA_SET_PRAM 0xc |
87 | 267002cd | bellard | #define CUDA_MS_RESET 0xd |
88 | 267002cd | bellard | #define CUDA_SEND_DFAC 0xe |
89 | 267002cd | bellard | #define CUDA_BATTERY_SWAP_SENSE 0x10 |
90 | 267002cd | bellard | #define CUDA_RESET_SYSTEM 0x11 |
91 | 267002cd | bellard | #define CUDA_SET_IPL 0x12 |
92 | 267002cd | bellard | #define CUDA_FILE_SERVER_FLAG 0x13 |
93 | 267002cd | bellard | #define CUDA_SET_AUTO_RATE 0x14 |
94 | 267002cd | bellard | #define CUDA_GET_AUTO_RATE 0x16 |
95 | 267002cd | bellard | #define CUDA_SET_DEVICE_LIST 0x19 |
96 | 267002cd | bellard | #define CUDA_GET_DEVICE_LIST 0x1a |
97 | 267002cd | bellard | #define CUDA_SET_ONE_SECOND_MODE 0x1b |
98 | 267002cd | bellard | #define CUDA_SET_POWER_MESSAGES 0x21 |
99 | 267002cd | bellard | #define CUDA_GET_SET_IIC 0x22 |
100 | 267002cd | bellard | #define CUDA_WAKEUP 0x23 |
101 | 267002cd | bellard | #define CUDA_TIMER_TICKLE 0x24 |
102 | 267002cd | bellard | #define CUDA_COMBINED_FORMAT_IIC 0x25 |
103 | 267002cd | bellard | |
104 | 267002cd | bellard | #define CUDA_TIMER_FREQ (4700000 / 6) |
105 | e2733d20 | bellard | #define CUDA_ADB_POLL_FREQ 50 |
106 | 267002cd | bellard | |
107 | d7ce296f | bellard | /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
|
108 | d7ce296f | bellard | #define RTC_OFFSET 2082844800 |
109 | d7ce296f | bellard | |
110 | 267002cd | bellard | typedef struct CUDATimer { |
111 | 5fafdf24 | ths | int index;
|
112 | 61271e5c | bellard | uint16_t latch; |
113 | 267002cd | bellard | uint16_t counter_value; /* counter value at load time */
|
114 | 267002cd | bellard | int64_t load_time; |
115 | 267002cd | bellard | int64_t next_irq_time; |
116 | 267002cd | bellard | QEMUTimer *timer; |
117 | 267002cd | bellard | } CUDATimer; |
118 | 267002cd | bellard | |
119 | 267002cd | bellard | typedef struct CUDAState { |
120 | 267002cd | bellard | /* cuda registers */
|
121 | 267002cd | bellard | uint8_t b; /* B-side data */
|
122 | 267002cd | bellard | uint8_t a; /* A-side data */
|
123 | 267002cd | bellard | uint8_t dirb; /* B-side direction (1=output) */
|
124 | 267002cd | bellard | uint8_t dira; /* A-side direction (1=output) */
|
125 | 267002cd | bellard | uint8_t sr; /* Shift register */
|
126 | 267002cd | bellard | uint8_t acr; /* Auxiliary control register */
|
127 | 267002cd | bellard | uint8_t pcr; /* Peripheral control register */
|
128 | 267002cd | bellard | uint8_t ifr; /* Interrupt flag register */
|
129 | 267002cd | bellard | uint8_t ier; /* Interrupt enable register */
|
130 | 267002cd | bellard | uint8_t anh; /* A-side data, no handshake */
|
131 | 267002cd | bellard | |
132 | 267002cd | bellard | CUDATimer timers[2];
|
133 | 3b46e624 | ths | |
134 | 5703c174 | aurel32 | uint32_t tick_offset; |
135 | 5703c174 | aurel32 | |
136 | 267002cd | bellard | uint8_t last_b; /* last value of B register */
|
137 | 267002cd | bellard | uint8_t last_acr; /* last value of B register */
|
138 | 3b46e624 | ths | |
139 | 267002cd | bellard | int data_in_size;
|
140 | 267002cd | bellard | int data_in_index;
|
141 | 267002cd | bellard | int data_out_index;
|
142 | 267002cd | bellard | |
143 | d537cf6c | pbrook | qemu_irq irq; |
144 | 267002cd | bellard | uint8_t autopoll; |
145 | 267002cd | bellard | uint8_t data_in[128];
|
146 | 267002cd | bellard | uint8_t data_out[16];
|
147 | e2733d20 | bellard | QEMUTimer *adb_poll_timer; |
148 | 267002cd | bellard | } CUDAState; |
149 | 267002cd | bellard | |
150 | 267002cd | bellard | static CUDAState cuda_state;
|
151 | 267002cd | bellard | ADBBusState adb_bus; |
152 | 267002cd | bellard | |
153 | 267002cd | bellard | static void cuda_update(CUDAState *s); |
154 | 5fafdf24 | ths | static void cuda_receive_packet_from_host(CUDAState *s, |
155 | 267002cd | bellard | const uint8_t *data, int len); |
156 | 5fafdf24 | ths | static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
157 | 819e712b | bellard | int64_t current_time); |
158 | 267002cd | bellard | |
159 | 267002cd | bellard | static void cuda_update_irq(CUDAState *s) |
160 | 267002cd | bellard | { |
161 | 819e712b | bellard | if (s->ifr & s->ier & (SR_INT | T1_INT)) {
|
162 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
163 | 267002cd | bellard | } else {
|
164 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
165 | 267002cd | bellard | } |
166 | 267002cd | bellard | } |
167 | 267002cd | bellard | |
168 | 267002cd | bellard | static unsigned int get_counter(CUDATimer *s) |
169 | 267002cd | bellard | { |
170 | 267002cd | bellard | int64_t d; |
171 | 267002cd | bellard | unsigned int counter; |
172 | 267002cd | bellard | |
173 | 5fafdf24 | ths | d = muldiv64(qemu_get_clock(vm_clock) - s->load_time, |
174 | 267002cd | bellard | CUDA_TIMER_FREQ, ticks_per_sec); |
175 | 61271e5c | bellard | if (s->index == 0) { |
176 | 61271e5c | bellard | /* the timer goes down from latch to -1 (period of latch + 2) */
|
177 | 61271e5c | bellard | if (d <= (s->counter_value + 1)) { |
178 | 61271e5c | bellard | counter = (s->counter_value - d) & 0xffff;
|
179 | 61271e5c | bellard | } else {
|
180 | 61271e5c | bellard | counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
181 | 5fafdf24 | ths | counter = (s->latch - counter) & 0xffff;
|
182 | 61271e5c | bellard | } |
183 | 267002cd | bellard | } else {
|
184 | 61271e5c | bellard | counter = (s->counter_value - d) & 0xffff;
|
185 | 267002cd | bellard | } |
186 | 267002cd | bellard | return counter;
|
187 | 267002cd | bellard | } |
188 | 267002cd | bellard | |
189 | 819e712b | bellard | static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) |
190 | 267002cd | bellard | { |
191 | ea026b2f | blueswir1 | CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val); |
192 | 819e712b | bellard | ti->load_time = qemu_get_clock(vm_clock); |
193 | 819e712b | bellard | ti->counter_value = val; |
194 | 819e712b | bellard | cuda_timer_update(s, ti, ti->load_time); |
195 | 267002cd | bellard | } |
196 | 267002cd | bellard | |
197 | 267002cd | bellard | static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
|
198 | 267002cd | bellard | { |
199 | 61271e5c | bellard | int64_t d, next_time; |
200 | 61271e5c | bellard | unsigned int counter; |
201 | 61271e5c | bellard | |
202 | 267002cd | bellard | /* current counter value */
|
203 | 5fafdf24 | ths | d = muldiv64(current_time - s->load_time, |
204 | 267002cd | bellard | CUDA_TIMER_FREQ, ticks_per_sec); |
205 | 61271e5c | bellard | /* the timer goes down from latch to -1 (period of latch + 2) */
|
206 | 61271e5c | bellard | if (d <= (s->counter_value + 1)) { |
207 | 61271e5c | bellard | counter = (s->counter_value - d) & 0xffff;
|
208 | 61271e5c | bellard | } else {
|
209 | 61271e5c | bellard | counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
210 | 5fafdf24 | ths | counter = (s->latch - counter) & 0xffff;
|
211 | 61271e5c | bellard | } |
212 | 3b46e624 | ths | |
213 | 61271e5c | bellard | /* Note: we consider the irq is raised on 0 */
|
214 | 61271e5c | bellard | if (counter == 0xffff) { |
215 | 61271e5c | bellard | next_time = d + s->latch + 1;
|
216 | 61271e5c | bellard | } else if (counter == 0) { |
217 | 61271e5c | bellard | next_time = d + s->latch + 2;
|
218 | 61271e5c | bellard | } else {
|
219 | 61271e5c | bellard | next_time = d + counter; |
220 | 267002cd | bellard | } |
221 | ea026b2f | blueswir1 | CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n", |
222 | ea026b2f | blueswir1 | s->latch, d, next_time - d); |
223 | 5fafdf24 | ths | next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) + |
224 | 267002cd | bellard | s->load_time; |
225 | 267002cd | bellard | if (next_time <= current_time)
|
226 | 267002cd | bellard | next_time = current_time + 1;
|
227 | 267002cd | bellard | return next_time;
|
228 | 267002cd | bellard | } |
229 | 267002cd | bellard | |
230 | 5fafdf24 | ths | static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
231 | 819e712b | bellard | int64_t current_time) |
232 | 819e712b | bellard | { |
233 | 819e712b | bellard | if (!ti->timer)
|
234 | 819e712b | bellard | return;
|
235 | 819e712b | bellard | if ((s->acr & T1MODE) != T1MODE_CONT) {
|
236 | 819e712b | bellard | qemu_del_timer(ti->timer); |
237 | 819e712b | bellard | } else {
|
238 | 819e712b | bellard | ti->next_irq_time = get_next_irq_time(ti, current_time); |
239 | 819e712b | bellard | qemu_mod_timer(ti->timer, ti->next_irq_time); |
240 | 819e712b | bellard | } |
241 | 819e712b | bellard | } |
242 | 819e712b | bellard | |
243 | 267002cd | bellard | static void cuda_timer1(void *opaque) |
244 | 267002cd | bellard | { |
245 | 267002cd | bellard | CUDAState *s = opaque; |
246 | 267002cd | bellard | CUDATimer *ti = &s->timers[0];
|
247 | 267002cd | bellard | |
248 | 819e712b | bellard | cuda_timer_update(s, ti, ti->next_irq_time); |
249 | 267002cd | bellard | s->ifr |= T1_INT; |
250 | 267002cd | bellard | cuda_update_irq(s); |
251 | 267002cd | bellard | } |
252 | 267002cd | bellard | |
253 | 267002cd | bellard | static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr) |
254 | 267002cd | bellard | { |
255 | 267002cd | bellard | CUDAState *s = opaque; |
256 | 267002cd | bellard | uint32_t val; |
257 | 267002cd | bellard | |
258 | 267002cd | bellard | addr = (addr >> 9) & 0xf; |
259 | 267002cd | bellard | switch(addr) {
|
260 | 267002cd | bellard | case 0: |
261 | 267002cd | bellard | val = s->b; |
262 | 267002cd | bellard | break;
|
263 | 267002cd | bellard | case 1: |
264 | 267002cd | bellard | val = s->a; |
265 | 267002cd | bellard | break;
|
266 | 267002cd | bellard | case 2: |
267 | 267002cd | bellard | val = s->dirb; |
268 | 267002cd | bellard | break;
|
269 | 267002cd | bellard | case 3: |
270 | 267002cd | bellard | val = s->dira; |
271 | 267002cd | bellard | break;
|
272 | 267002cd | bellard | case 4: |
273 | 267002cd | bellard | val = get_counter(&s->timers[0]) & 0xff; |
274 | 267002cd | bellard | s->ifr &= ~T1_INT; |
275 | 267002cd | bellard | cuda_update_irq(s); |
276 | 267002cd | bellard | break;
|
277 | 267002cd | bellard | case 5: |
278 | 267002cd | bellard | val = get_counter(&s->timers[0]) >> 8; |
279 | 267002cd | bellard | cuda_update_irq(s); |
280 | 267002cd | bellard | break;
|
281 | 267002cd | bellard | case 6: |
282 | 267002cd | bellard | val = s->timers[0].latch & 0xff; |
283 | 267002cd | bellard | break;
|
284 | 267002cd | bellard | case 7: |
285 | 61271e5c | bellard | /* XXX: check this */
|
286 | 267002cd | bellard | val = (s->timers[0].latch >> 8) & 0xff; |
287 | 267002cd | bellard | break;
|
288 | 267002cd | bellard | case 8: |
289 | 267002cd | bellard | val = get_counter(&s->timers[1]) & 0xff; |
290 | 61271e5c | bellard | s->ifr &= ~T2_INT; |
291 | 267002cd | bellard | break;
|
292 | 267002cd | bellard | case 9: |
293 | 267002cd | bellard | val = get_counter(&s->timers[1]) >> 8; |
294 | 267002cd | bellard | break;
|
295 | 267002cd | bellard | case 10: |
296 | 819e712b | bellard | val = s->sr; |
297 | 819e712b | bellard | s->ifr &= ~SR_INT; |
298 | 819e712b | bellard | cuda_update_irq(s); |
299 | 267002cd | bellard | break;
|
300 | 267002cd | bellard | case 11: |
301 | 267002cd | bellard | val = s->acr; |
302 | 267002cd | bellard | break;
|
303 | 267002cd | bellard | case 12: |
304 | 267002cd | bellard | val = s->pcr; |
305 | 267002cd | bellard | break;
|
306 | 267002cd | bellard | case 13: |
307 | 267002cd | bellard | val = s->ifr; |
308 | 5fafdf24 | ths | if (s->ifr & s->ier)
|
309 | b7c7b181 | bellard | val |= 0x80;
|
310 | 267002cd | bellard | break;
|
311 | 267002cd | bellard | case 14: |
312 | b7c7b181 | bellard | val = s->ier | 0x80;
|
313 | 267002cd | bellard | break;
|
314 | 267002cd | bellard | default:
|
315 | 267002cd | bellard | case 15: |
316 | 267002cd | bellard | val = s->anh; |
317 | 267002cd | bellard | break;
|
318 | 267002cd | bellard | } |
319 | 819e712b | bellard | if (addr != 13 || val != 0) |
320 | ea026b2f | blueswir1 | CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr, val); |
321 | 267002cd | bellard | return val;
|
322 | 267002cd | bellard | } |
323 | 267002cd | bellard | |
324 | 267002cd | bellard | static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
325 | 267002cd | bellard | { |
326 | 267002cd | bellard | CUDAState *s = opaque; |
327 | 3b46e624 | ths | |
328 | 267002cd | bellard | addr = (addr >> 9) & 0xf; |
329 | ea026b2f | blueswir1 | CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr, val); |
330 | 267002cd | bellard | |
331 | 267002cd | bellard | switch(addr) {
|
332 | 267002cd | bellard | case 0: |
333 | 267002cd | bellard | s->b = val; |
334 | 267002cd | bellard | cuda_update(s); |
335 | 267002cd | bellard | break;
|
336 | 267002cd | bellard | case 1: |
337 | 267002cd | bellard | s->a = val; |
338 | 267002cd | bellard | break;
|
339 | 267002cd | bellard | case 2: |
340 | 267002cd | bellard | s->dirb = val; |
341 | 267002cd | bellard | break;
|
342 | 267002cd | bellard | case 3: |
343 | 267002cd | bellard | s->dira = val; |
344 | 267002cd | bellard | break;
|
345 | 267002cd | bellard | case 4: |
346 | 61271e5c | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
347 | 61271e5c | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
|
348 | 267002cd | bellard | break;
|
349 | 267002cd | bellard | case 5: |
350 | 61271e5c | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
351 | 61271e5c | bellard | s->ifr &= ~T1_INT; |
352 | 61271e5c | bellard | set_counter(s, &s->timers[0], s->timers[0].latch); |
353 | 267002cd | bellard | break;
|
354 | 267002cd | bellard | case 6: |
355 | 267002cd | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
356 | 819e712b | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
|
357 | 267002cd | bellard | break;
|
358 | 267002cd | bellard | case 7: |
359 | 267002cd | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
360 | 61271e5c | bellard | s->ifr &= ~T1_INT; |
361 | 819e712b | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
|
362 | 267002cd | bellard | break;
|
363 | 267002cd | bellard | case 8: |
364 | 61271e5c | bellard | s->timers[1].latch = val;
|
365 | 819e712b | bellard | set_counter(s, &s->timers[1], val);
|
366 | 267002cd | bellard | break;
|
367 | 267002cd | bellard | case 9: |
368 | 61271e5c | bellard | set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch); |
369 | 267002cd | bellard | break;
|
370 | 267002cd | bellard | case 10: |
371 | 267002cd | bellard | s->sr = val; |
372 | 267002cd | bellard | break;
|
373 | 267002cd | bellard | case 11: |
374 | 267002cd | bellard | s->acr = val; |
375 | 819e712b | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
|
376 | 267002cd | bellard | cuda_update(s); |
377 | 267002cd | bellard | break;
|
378 | 267002cd | bellard | case 12: |
379 | 267002cd | bellard | s->pcr = val; |
380 | 267002cd | bellard | break;
|
381 | 267002cd | bellard | case 13: |
382 | 267002cd | bellard | /* reset bits */
|
383 | 267002cd | bellard | s->ifr &= ~val; |
384 | 267002cd | bellard | cuda_update_irq(s); |
385 | 267002cd | bellard | break;
|
386 | 267002cd | bellard | case 14: |
387 | 267002cd | bellard | if (val & IER_SET) {
|
388 | 267002cd | bellard | /* set bits */
|
389 | 267002cd | bellard | s->ier |= val & 0x7f;
|
390 | 267002cd | bellard | } else {
|
391 | 267002cd | bellard | /* reset bits */
|
392 | 267002cd | bellard | s->ier &= ~val; |
393 | 267002cd | bellard | } |
394 | 267002cd | bellard | cuda_update_irq(s); |
395 | 267002cd | bellard | break;
|
396 | 267002cd | bellard | default:
|
397 | 267002cd | bellard | case 15: |
398 | 267002cd | bellard | s->anh = val; |
399 | 267002cd | bellard | break;
|
400 | 267002cd | bellard | } |
401 | 267002cd | bellard | } |
402 | 267002cd | bellard | |
403 | 267002cd | bellard | /* NOTE: TIP and TREQ are negated */
|
404 | 267002cd | bellard | static void cuda_update(CUDAState *s) |
405 | 267002cd | bellard | { |
406 | 819e712b | bellard | int packet_received, len;
|
407 | 819e712b | bellard | |
408 | 819e712b | bellard | packet_received = 0;
|
409 | 819e712b | bellard | if (!(s->b & TIP)) {
|
410 | 819e712b | bellard | /* transfer requested from host */
|
411 | 267002cd | bellard | |
412 | 819e712b | bellard | if (s->acr & SR_OUT) {
|
413 | 819e712b | bellard | /* data output */
|
414 | 819e712b | bellard | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
415 | 819e712b | bellard | if (s->data_out_index < sizeof(s->data_out)) { |
416 | ea026b2f | blueswir1 | CUDA_DPRINTF("send: %02x\n", s->sr);
|
417 | 819e712b | bellard | s->data_out[s->data_out_index++] = s->sr; |
418 | 819e712b | bellard | s->ifr |= SR_INT; |
419 | 819e712b | bellard | cuda_update_irq(s); |
420 | 819e712b | bellard | } |
421 | 819e712b | bellard | } |
422 | 819e712b | bellard | } else {
|
423 | 819e712b | bellard | if (s->data_in_index < s->data_in_size) {
|
424 | 819e712b | bellard | /* data input */
|
425 | 819e712b | bellard | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
426 | 819e712b | bellard | s->sr = s->data_in[s->data_in_index++]; |
427 | ea026b2f | blueswir1 | CUDA_DPRINTF("recv: %02x\n", s->sr);
|
428 | 819e712b | bellard | /* indicate end of transfer */
|
429 | 819e712b | bellard | if (s->data_in_index >= s->data_in_size) {
|
430 | 819e712b | bellard | s->b = (s->b | TREQ); |
431 | 819e712b | bellard | } |
432 | 819e712b | bellard | s->ifr |= SR_INT; |
433 | 819e712b | bellard | cuda_update_irq(s); |
434 | 819e712b | bellard | } |
435 | 267002cd | bellard | } |
436 | 819e712b | bellard | } |
437 | 819e712b | bellard | } else {
|
438 | 819e712b | bellard | /* no transfer requested: handle sync case */
|
439 | 819e712b | bellard | if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
|
440 | 819e712b | bellard | /* update TREQ state each time TACK change state */
|
441 | 819e712b | bellard | if (s->b & TACK)
|
442 | 819e712b | bellard | s->b = (s->b | TREQ); |
443 | 819e712b | bellard | else
|
444 | 819e712b | bellard | s->b = (s->b & ~TREQ); |
445 | 267002cd | bellard | s->ifr |= SR_INT; |
446 | 267002cd | bellard | cuda_update_irq(s); |
447 | 819e712b | bellard | } else {
|
448 | 819e712b | bellard | if (!(s->last_b & TIP)) {
|
449 | e91c8a77 | ths | /* handle end of host to cuda transfer */
|
450 | 819e712b | bellard | packet_received = (s->data_out_index > 0);
|
451 | e91c8a77 | ths | /* always an IRQ at the end of transfer */
|
452 | 819e712b | bellard | s->ifr |= SR_INT; |
453 | 819e712b | bellard | cuda_update_irq(s); |
454 | 819e712b | bellard | } |
455 | 819e712b | bellard | /* signal if there is data to read */
|
456 | 819e712b | bellard | if (s->data_in_index < s->data_in_size) {
|
457 | 819e712b | bellard | s->b = (s->b & ~TREQ); |
458 | 819e712b | bellard | } |
459 | 267002cd | bellard | } |
460 | 267002cd | bellard | } |
461 | 267002cd | bellard | |
462 | 267002cd | bellard | s->last_acr = s->acr; |
463 | 267002cd | bellard | s->last_b = s->b; |
464 | 819e712b | bellard | |
465 | 819e712b | bellard | /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
|
466 | 819e712b | bellard | recursively */
|
467 | 819e712b | bellard | if (packet_received) {
|
468 | 819e712b | bellard | len = s->data_out_index; |
469 | 819e712b | bellard | s->data_out_index = 0;
|
470 | 819e712b | bellard | cuda_receive_packet_from_host(s, s->data_out, len); |
471 | 819e712b | bellard | } |
472 | 267002cd | bellard | } |
473 | 267002cd | bellard | |
474 | 5fafdf24 | ths | static void cuda_send_packet_to_host(CUDAState *s, |
475 | 267002cd | bellard | const uint8_t *data, int len) |
476 | 267002cd | bellard | { |
477 | 819e712b | bellard | #ifdef DEBUG_CUDA_PACKET
|
478 | 819e712b | bellard | { |
479 | 819e712b | bellard | int i;
|
480 | 819e712b | bellard | printf("cuda_send_packet_to_host:\n");
|
481 | 819e712b | bellard | for(i = 0; i < len; i++) |
482 | 819e712b | bellard | printf(" %02x", data[i]);
|
483 | 819e712b | bellard | printf("\n");
|
484 | 819e712b | bellard | } |
485 | 819e712b | bellard | #endif
|
486 | 267002cd | bellard | memcpy(s->data_in, data, len); |
487 | 267002cd | bellard | s->data_in_size = len; |
488 | 267002cd | bellard | s->data_in_index = 0;
|
489 | 267002cd | bellard | cuda_update(s); |
490 | 267002cd | bellard | s->ifr |= SR_INT; |
491 | 267002cd | bellard | cuda_update_irq(s); |
492 | 267002cd | bellard | } |
493 | 267002cd | bellard | |
494 | 7db4eea6 | bellard | static void cuda_adb_poll(void *opaque) |
495 | e2733d20 | bellard | { |
496 | e2733d20 | bellard | CUDAState *s = opaque; |
497 | e2733d20 | bellard | uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
498 | e2733d20 | bellard | int olen;
|
499 | e2733d20 | bellard | |
500 | e2733d20 | bellard | olen = adb_poll(&adb_bus, obuf + 2);
|
501 | e2733d20 | bellard | if (olen > 0) { |
502 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
503 | e2733d20 | bellard | obuf[1] = 0x40; /* polled data */ |
504 | e2733d20 | bellard | cuda_send_packet_to_host(s, obuf, olen + 2);
|
505 | e2733d20 | bellard | } |
506 | 5fafdf24 | ths | qemu_mod_timer(s->adb_poll_timer, |
507 | 5fafdf24 | ths | qemu_get_clock(vm_clock) + |
508 | e2733d20 | bellard | (ticks_per_sec / CUDA_ADB_POLL_FREQ)); |
509 | e2733d20 | bellard | } |
510 | e2733d20 | bellard | |
511 | 5fafdf24 | ths | static void cuda_receive_packet(CUDAState *s, |
512 | 267002cd | bellard | const uint8_t *data, int len) |
513 | 267002cd | bellard | { |
514 | 267002cd | bellard | uint8_t obuf[16];
|
515 | 5703c174 | aurel32 | int autopoll;
|
516 | 5703c174 | aurel32 | uint32_t ti; |
517 | 267002cd | bellard | |
518 | 267002cd | bellard | switch(data[0]) { |
519 | 267002cd | bellard | case CUDA_AUTOPOLL:
|
520 | e2733d20 | bellard | autopoll = (data[1] != 0); |
521 | e2733d20 | bellard | if (autopoll != s->autopoll) {
|
522 | e2733d20 | bellard | s->autopoll = autopoll; |
523 | e2733d20 | bellard | if (autopoll) {
|
524 | 5fafdf24 | ths | qemu_mod_timer(s->adb_poll_timer, |
525 | 5fafdf24 | ths | qemu_get_clock(vm_clock) + |
526 | e2733d20 | bellard | (ticks_per_sec / CUDA_ADB_POLL_FREQ)); |
527 | e2733d20 | bellard | } else {
|
528 | e2733d20 | bellard | qemu_del_timer(s->adb_poll_timer); |
529 | e2733d20 | bellard | } |
530 | e2733d20 | bellard | } |
531 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
532 | 267002cd | bellard | obuf[1] = data[1]; |
533 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
534 | 267002cd | bellard | break;
|
535 | dccfafc4 | bellard | case CUDA_SET_TIME:
|
536 | 5703c174 | aurel32 | ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4]; |
537 | 5703c174 | aurel32 | s->tick_offset = ti - (qemu_get_clock(vm_clock) / ticks_per_sec); |
538 | 5703c174 | aurel32 | obuf[0] = CUDA_PACKET;
|
539 | 5703c174 | aurel32 | obuf[1] = 0; |
540 | 5703c174 | aurel32 | obuf[2] = 0; |
541 | 5703c174 | aurel32 | cuda_send_packet_to_host(s, obuf, 3);
|
542 | 5703c174 | aurel32 | break;
|
543 | 5703c174 | aurel32 | case CUDA_GET_TIME:
|
544 | 5703c174 | aurel32 | ti = s->tick_offset + (qemu_get_clock(vm_clock) / ticks_per_sec); |
545 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
546 | 267002cd | bellard | obuf[1] = 0; |
547 | 267002cd | bellard | obuf[2] = 0; |
548 | 267002cd | bellard | obuf[3] = ti >> 24; |
549 | 267002cd | bellard | obuf[4] = ti >> 16; |
550 | 267002cd | bellard | obuf[5] = ti >> 8; |
551 | 267002cd | bellard | obuf[6] = ti;
|
552 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 7);
|
553 | 267002cd | bellard | break;
|
554 | 267002cd | bellard | case CUDA_FILE_SERVER_FLAG:
|
555 | 267002cd | bellard | case CUDA_SET_DEVICE_LIST:
|
556 | 267002cd | bellard | case CUDA_SET_AUTO_RATE:
|
557 | 267002cd | bellard | case CUDA_SET_POWER_MESSAGES:
|
558 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
559 | 267002cd | bellard | obuf[1] = 0; |
560 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
561 | 267002cd | bellard | break;
|
562 | d7ce296f | bellard | case CUDA_POWERDOWN:
|
563 | d7ce296f | bellard | obuf[0] = CUDA_PACKET;
|
564 | d7ce296f | bellard | obuf[1] = 0; |
565 | d7ce296f | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
566 | c76ee25d | aurel32 | qemu_system_shutdown_request(); |
567 | c76ee25d | aurel32 | break;
|
568 | 0686970f | j_mayer | case CUDA_RESET_SYSTEM:
|
569 | 0686970f | j_mayer | obuf[0] = CUDA_PACKET;
|
570 | 0686970f | j_mayer | obuf[1] = 0; |
571 | 0686970f | j_mayer | cuda_send_packet_to_host(s, obuf, 2);
|
572 | 0686970f | j_mayer | qemu_system_reset_request(); |
573 | 0686970f | j_mayer | break;
|
574 | 267002cd | bellard | default:
|
575 | 267002cd | bellard | break;
|
576 | 267002cd | bellard | } |
577 | 267002cd | bellard | } |
578 | 267002cd | bellard | |
579 | 5fafdf24 | ths | static void cuda_receive_packet_from_host(CUDAState *s, |
580 | 267002cd | bellard | const uint8_t *data, int len) |
581 | 267002cd | bellard | { |
582 | 819e712b | bellard | #ifdef DEBUG_CUDA_PACKET
|
583 | 819e712b | bellard | { |
584 | 819e712b | bellard | int i;
|
585 | cadae95f | bellard | printf("cuda_receive_packet_from_host:\n");
|
586 | 819e712b | bellard | for(i = 0; i < len; i++) |
587 | 819e712b | bellard | printf(" %02x", data[i]);
|
588 | 819e712b | bellard | printf("\n");
|
589 | 819e712b | bellard | } |
590 | 819e712b | bellard | #endif
|
591 | 267002cd | bellard | switch(data[0]) { |
592 | 267002cd | bellard | case ADB_PACKET:
|
593 | e2733d20 | bellard | { |
594 | e2733d20 | bellard | uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
595 | e2733d20 | bellard | int olen;
|
596 | e2733d20 | bellard | olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1); |
597 | 38f0b147 | bellard | if (olen > 0) { |
598 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
599 | e2733d20 | bellard | obuf[1] = 0x00; |
600 | e2733d20 | bellard | } else {
|
601 | 38f0b147 | bellard | /* error */
|
602 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
603 | 38f0b147 | bellard | obuf[1] = -olen;
|
604 | 38f0b147 | bellard | olen = 0;
|
605 | e2733d20 | bellard | } |
606 | e2733d20 | bellard | cuda_send_packet_to_host(s, obuf, olen + 2);
|
607 | e2733d20 | bellard | } |
608 | 267002cd | bellard | break;
|
609 | 267002cd | bellard | case CUDA_PACKET:
|
610 | 267002cd | bellard | cuda_receive_packet(s, data + 1, len - 1); |
611 | 267002cd | bellard | break;
|
612 | 267002cd | bellard | } |
613 | 267002cd | bellard | } |
614 | 267002cd | bellard | |
615 | 267002cd | bellard | static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
616 | 267002cd | bellard | { |
617 | 267002cd | bellard | } |
618 | 267002cd | bellard | |
619 | 267002cd | bellard | static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
620 | 267002cd | bellard | { |
621 | 267002cd | bellard | } |
622 | 267002cd | bellard | |
623 | 267002cd | bellard | static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr) |
624 | 267002cd | bellard | { |
625 | 267002cd | bellard | return 0; |
626 | 267002cd | bellard | } |
627 | 267002cd | bellard | |
628 | 267002cd | bellard | static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr) |
629 | 267002cd | bellard | { |
630 | 267002cd | bellard | return 0; |
631 | 267002cd | bellard | } |
632 | 267002cd | bellard | |
633 | 267002cd | bellard | static CPUWriteMemoryFunc *cuda_write[] = {
|
634 | 267002cd | bellard | &cuda_writeb, |
635 | 267002cd | bellard | &cuda_writew, |
636 | 267002cd | bellard | &cuda_writel, |
637 | 267002cd | bellard | }; |
638 | 267002cd | bellard | |
639 | 267002cd | bellard | static CPUReadMemoryFunc *cuda_read[] = {
|
640 | 267002cd | bellard | &cuda_readb, |
641 | 267002cd | bellard | &cuda_readw, |
642 | 267002cd | bellard | &cuda_readl, |
643 | 267002cd | bellard | }; |
644 | 267002cd | bellard | |
645 | 9b64997f | blueswir1 | static void cuda_save_timer(QEMUFile *f, CUDATimer *s) |
646 | 9b64997f | blueswir1 | { |
647 | 9b64997f | blueswir1 | qemu_put_be16s(f, &s->latch); |
648 | 9b64997f | blueswir1 | qemu_put_be16s(f, &s->counter_value); |
649 | 9b64997f | blueswir1 | qemu_put_sbe64s(f, &s->load_time); |
650 | 9b64997f | blueswir1 | qemu_put_sbe64s(f, &s->next_irq_time); |
651 | 9b64997f | blueswir1 | if (s->timer)
|
652 | 9b64997f | blueswir1 | qemu_put_timer(f, s->timer); |
653 | 9b64997f | blueswir1 | } |
654 | 9b64997f | blueswir1 | |
655 | 9b64997f | blueswir1 | static void cuda_save(QEMUFile *f, void *opaque) |
656 | 9b64997f | blueswir1 | { |
657 | 9b64997f | blueswir1 | CUDAState *s = (CUDAState *)opaque; |
658 | 9b64997f | blueswir1 | |
659 | 9b64997f | blueswir1 | qemu_put_ubyte(f, s->b); |
660 | 9b64997f | blueswir1 | qemu_put_ubyte(f, s->a); |
661 | 9b64997f | blueswir1 | qemu_put_ubyte(f, s->dirb); |
662 | 9b64997f | blueswir1 | qemu_put_ubyte(f, s->dira); |
663 | 9b64997f | blueswir1 | qemu_put_ubyte(f, s->sr); |
664 | 9b64997f | blueswir1 | qemu_put_ubyte(f, s->acr); |
665 | 9b64997f | blueswir1 | qemu_put_ubyte(f, s->pcr); |
666 | 9b64997f | blueswir1 | qemu_put_ubyte(f, s->ifr); |
667 | 9b64997f | blueswir1 | qemu_put_ubyte(f, s->ier); |
668 | 9b64997f | blueswir1 | qemu_put_ubyte(f, s->anh); |
669 | 9b64997f | blueswir1 | qemu_put_sbe32s(f, &s->data_in_size); |
670 | 9b64997f | blueswir1 | qemu_put_sbe32s(f, &s->data_in_index); |
671 | 9b64997f | blueswir1 | qemu_put_sbe32s(f, &s->data_out_index); |
672 | 9b64997f | blueswir1 | qemu_put_ubyte(f, s->autopoll); |
673 | 9b64997f | blueswir1 | qemu_put_buffer(f, s->data_in, sizeof(s->data_in));
|
674 | 9b64997f | blueswir1 | qemu_put_buffer(f, s->data_out, sizeof(s->data_out));
|
675 | 5703c174 | aurel32 | qemu_put_be32s(f, &s->tick_offset); |
676 | 9b64997f | blueswir1 | cuda_save_timer(f, &s->timers[0]);
|
677 | 9b64997f | blueswir1 | cuda_save_timer(f, &s->timers[1]);
|
678 | 9b64997f | blueswir1 | } |
679 | 9b64997f | blueswir1 | |
680 | 9b64997f | blueswir1 | static void cuda_load_timer(QEMUFile *f, CUDATimer *s) |
681 | 9b64997f | blueswir1 | { |
682 | 9b64997f | blueswir1 | qemu_get_be16s(f, &s->latch); |
683 | 9b64997f | blueswir1 | qemu_get_be16s(f, &s->counter_value); |
684 | 9b64997f | blueswir1 | qemu_get_sbe64s(f, &s->load_time); |
685 | 9b64997f | blueswir1 | qemu_get_sbe64s(f, &s->next_irq_time); |
686 | 9b64997f | blueswir1 | if (s->timer)
|
687 | 9b64997f | blueswir1 | qemu_get_timer(f, s->timer); |
688 | 9b64997f | blueswir1 | } |
689 | 9b64997f | blueswir1 | |
690 | 9b64997f | blueswir1 | static int cuda_load(QEMUFile *f, void *opaque, int version_id) |
691 | 9b64997f | blueswir1 | { |
692 | 9b64997f | blueswir1 | CUDAState *s = (CUDAState *)opaque; |
693 | 9b64997f | blueswir1 | |
694 | 9b64997f | blueswir1 | if (version_id != 1) |
695 | 9b64997f | blueswir1 | return -EINVAL;
|
696 | 9b64997f | blueswir1 | |
697 | 9b64997f | blueswir1 | s->b = qemu_get_ubyte(f); |
698 | 9b64997f | blueswir1 | s->a = qemu_get_ubyte(f); |
699 | 9b64997f | blueswir1 | s->dirb = qemu_get_ubyte(f); |
700 | 9b64997f | blueswir1 | s->dira = qemu_get_ubyte(f); |
701 | 9b64997f | blueswir1 | s->sr = qemu_get_ubyte(f); |
702 | 9b64997f | blueswir1 | s->acr = qemu_get_ubyte(f); |
703 | 9b64997f | blueswir1 | s->pcr = qemu_get_ubyte(f); |
704 | 9b64997f | blueswir1 | s->ifr = qemu_get_ubyte(f); |
705 | 9b64997f | blueswir1 | s->ier = qemu_get_ubyte(f); |
706 | 9b64997f | blueswir1 | s->anh = qemu_get_ubyte(f); |
707 | 9b64997f | blueswir1 | qemu_get_sbe32s(f, &s->data_in_size); |
708 | 9b64997f | blueswir1 | qemu_get_sbe32s(f, &s->data_in_index); |
709 | 9b64997f | blueswir1 | qemu_get_sbe32s(f, &s->data_out_index); |
710 | 9b64997f | blueswir1 | s->autopoll = qemu_get_ubyte(f); |
711 | 9b64997f | blueswir1 | qemu_get_buffer(f, s->data_in, sizeof(s->data_in));
|
712 | 9b64997f | blueswir1 | qemu_get_buffer(f, s->data_out, sizeof(s->data_out));
|
713 | 5703c174 | aurel32 | qemu_get_be32s(f, &s->tick_offset); |
714 | 9b64997f | blueswir1 | cuda_load_timer(f, &s->timers[0]);
|
715 | 9b64997f | blueswir1 | cuda_load_timer(f, &s->timers[1]);
|
716 | 9b64997f | blueswir1 | |
717 | 9b64997f | blueswir1 | return 0; |
718 | 9b64997f | blueswir1 | } |
719 | 9b64997f | blueswir1 | |
720 | 6e6b7363 | blueswir1 | static void cuda_reset(void *opaque) |
721 | 6e6b7363 | blueswir1 | { |
722 | 6e6b7363 | blueswir1 | CUDAState *s = opaque; |
723 | 6e6b7363 | blueswir1 | |
724 | 6e6b7363 | blueswir1 | s->b = 0;
|
725 | 6e6b7363 | blueswir1 | s->a = 0;
|
726 | 6e6b7363 | blueswir1 | s->dirb = 0;
|
727 | 6e6b7363 | blueswir1 | s->dira = 0;
|
728 | 6e6b7363 | blueswir1 | s->sr = 0;
|
729 | 6e6b7363 | blueswir1 | s->acr = 0;
|
730 | 6e6b7363 | blueswir1 | s->pcr = 0;
|
731 | 6e6b7363 | blueswir1 | s->ifr = 0;
|
732 | 6e6b7363 | blueswir1 | s->ier = 0;
|
733 | 6e6b7363 | blueswir1 | // s->ier = T1_INT | SR_INT;
|
734 | 6e6b7363 | blueswir1 | s->anh = 0;
|
735 | 6e6b7363 | blueswir1 | s->data_in_size = 0;
|
736 | 6e6b7363 | blueswir1 | s->data_in_index = 0;
|
737 | 6e6b7363 | blueswir1 | s->data_out_index = 0;
|
738 | 6e6b7363 | blueswir1 | s->autopoll = 0;
|
739 | 6e6b7363 | blueswir1 | |
740 | 6e6b7363 | blueswir1 | s->timers[0].latch = 0xffff; |
741 | 6e6b7363 | blueswir1 | set_counter(s, &s->timers[0], 0xffff); |
742 | 6e6b7363 | blueswir1 | |
743 | 6e6b7363 | blueswir1 | s->timers[1].latch = 0; |
744 | 6e6b7363 | blueswir1 | set_counter(s, &s->timers[1], 0xffff); |
745 | 6e6b7363 | blueswir1 | } |
746 | 6e6b7363 | blueswir1 | |
747 | 3cbee15b | j_mayer | void cuda_init (int *cuda_mem_index, qemu_irq irq) |
748 | 267002cd | bellard | { |
749 | 5703c174 | aurel32 | struct tm tm;
|
750 | 267002cd | bellard | CUDAState *s = &cuda_state; |
751 | 267002cd | bellard | |
752 | 819e712b | bellard | s->irq = irq; |
753 | 819e712b | bellard | |
754 | 61271e5c | bellard | s->timers[0].index = 0; |
755 | 267002cd | bellard | s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
|
756 | 61271e5c | bellard | |
757 | 61271e5c | bellard | s->timers[1].index = 1; |
758 | e2733d20 | bellard | |
759 | 9c554c1c | aurel32 | qemu_get_timedate(&tm, 0);
|
760 | 9c554c1c | aurel32 | s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; |
761 | 5703c174 | aurel32 | |
762 | e2733d20 | bellard | s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s); |
763 | 1eed09cb | Avi Kivity | *cuda_mem_index = cpu_register_io_memory(cuda_read, cuda_write, s); |
764 | 9b64997f | blueswir1 | register_savevm("cuda", -1, 1, cuda_save, cuda_load, s); |
765 | a08d4367 | Jan Kiszka | qemu_register_reset(cuda_reset, s); |
766 | 6e6b7363 | blueswir1 | cuda_reset(s); |
767 | 267002cd | bellard | } |