root / hw / slavio_timer.c @ a702b353
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1 | e80cfcfc | bellard | /*
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2 | e80cfcfc | bellard | * QEMU Sparc SLAVIO timer controller emulation
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3 | e80cfcfc | bellard | *
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4 | 66321a11 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | e80cfcfc | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | e80cfcfc | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | e80cfcfc | bellard | * in the Software without restriction, including without limitation the rights
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9 | e80cfcfc | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | e80cfcfc | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | e80cfcfc | bellard | * furnished to do so, subject to the following conditions:
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12 | e80cfcfc | bellard | *
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13 | e80cfcfc | bellard | * The above copyright notice and this permission notice shall be included in
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14 | e80cfcfc | bellard | * all copies or substantial portions of the Software.
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15 | e80cfcfc | bellard | *
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16 | e80cfcfc | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | e80cfcfc | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | e80cfcfc | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | e80cfcfc | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | e80cfcfc | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | e80cfcfc | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | e80cfcfc | bellard | * THE SOFTWARE.
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23 | e80cfcfc | bellard | */
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24 | e80cfcfc | bellard | #include "vl.h" |
25 | e80cfcfc | bellard | |
26 | e80cfcfc | bellard | //#define DEBUG_TIMER
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27 | e80cfcfc | bellard | |
28 | 66321a11 | bellard | #ifdef DEBUG_TIMER
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29 | 66321a11 | bellard | #define DPRINTF(fmt, args...) \
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30 | 66321a11 | bellard | do { printf("TIMER: " fmt , ##args); } while (0) |
31 | 66321a11 | bellard | #else
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32 | 66321a11 | bellard | #define DPRINTF(fmt, args...)
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33 | 66321a11 | bellard | #endif
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34 | 66321a11 | bellard | |
35 | e80cfcfc | bellard | /*
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36 | e80cfcfc | bellard | * Registers of hardware timer in sun4m.
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37 | e80cfcfc | bellard | *
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38 | e80cfcfc | bellard | * This is the timer/counter part of chip STP2001 (Slave I/O), also
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39 | e80cfcfc | bellard | * produced as NCR89C105. See
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40 | e80cfcfc | bellard | * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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41 | 5fafdf24 | ths | *
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42 | e80cfcfc | bellard | * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
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43 | e80cfcfc | bellard | * are zero. Bit 31 is 1 when count has been reached.
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44 | e80cfcfc | bellard | *
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45 | ba3c64fb | bellard | * Per-CPU timers interrupt local CPU, system timer uses normal
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46 | ba3c64fb | bellard | * interrupt routing.
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47 | ba3c64fb | bellard | *
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48 | e80cfcfc | bellard | */
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49 | e80cfcfc | bellard | |
50 | 81732d19 | blueswir1 | #define MAX_CPUS 16 |
51 | 81732d19 | blueswir1 | |
52 | e80cfcfc | bellard | typedef struct SLAVIO_TIMERState { |
53 | d7edfd27 | blueswir1 | qemu_irq irq; |
54 | 8d05ea8a | blueswir1 | ptimer_state *timer; |
55 | 8d05ea8a | blueswir1 | uint32_t count, counthigh, reached; |
56 | 8d05ea8a | blueswir1 | uint64_t limit; |
57 | 115646b6 | blueswir1 | // processor only
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58 | 115646b6 | blueswir1 | int running;
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59 | 115646b6 | blueswir1 | struct SLAVIO_TIMERState *master;
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60 | 115646b6 | blueswir1 | int slave_index;
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61 | 115646b6 | blueswir1 | // system only
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62 | 81732d19 | blueswir1 | struct SLAVIO_TIMERState *slave[MAX_CPUS];
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63 | 81732d19 | blueswir1 | uint32_t slave_mode; |
64 | e80cfcfc | bellard | } SLAVIO_TIMERState; |
65 | e80cfcfc | bellard | |
66 | e80cfcfc | bellard | #define TIMER_MAXADDR 0x1f |
67 | 115646b6 | blueswir1 | #define SYS_TIMER_SIZE 0x14 |
68 | 81732d19 | blueswir1 | #define CPU_TIMER_SIZE 0x10 |
69 | e80cfcfc | bellard | |
70 | 115646b6 | blueswir1 | static int slavio_timer_is_user(SLAVIO_TIMERState *s) |
71 | 115646b6 | blueswir1 | { |
72 | 115646b6 | blueswir1 | return s->master && (s->master->slave_mode & (1 << s->slave_index)); |
73 | 115646b6 | blueswir1 | } |
74 | 115646b6 | blueswir1 | |
75 | e80cfcfc | bellard | // Update count, set irq, update expire_time
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76 | 8d05ea8a | blueswir1 | // Convert from ptimer countdown units
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77 | e80cfcfc | bellard | static void slavio_timer_get_out(SLAVIO_TIMERState *s) |
78 | e80cfcfc | bellard | { |
79 | 8d05ea8a | blueswir1 | uint64_t count; |
80 | e80cfcfc | bellard | |
81 | 8d05ea8a | blueswir1 | count = s->limit - (ptimer_get_count(s->timer) << 9);
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82 | 8d05ea8a | blueswir1 | DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, s->counthigh, |
83 | 8d05ea8a | blueswir1 | s->count); |
84 | 8d05ea8a | blueswir1 | s->count = count & 0xfffffe00;
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85 | 8d05ea8a | blueswir1 | s->counthigh = count >> 32;
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86 | e80cfcfc | bellard | } |
87 | e80cfcfc | bellard | |
88 | e80cfcfc | bellard | // timer callback
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89 | e80cfcfc | bellard | static void slavio_timer_irq(void *opaque) |
90 | e80cfcfc | bellard | { |
91 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
92 | e80cfcfc | bellard | |
93 | e80cfcfc | bellard | slavio_timer_get_out(s); |
94 | 8d05ea8a | blueswir1 | DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
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95 | 115646b6 | blueswir1 | if (!slavio_timer_is_user(s)) {
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96 | 115646b6 | blueswir1 | s->reached = 0x80000000;
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97 | f930d07e | blueswir1 | qemu_irq_raise(s->irq); |
98 | 115646b6 | blueswir1 | } |
99 | e80cfcfc | bellard | } |
100 | e80cfcfc | bellard | |
101 | e80cfcfc | bellard | static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr) |
102 | e80cfcfc | bellard | { |
103 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
104 | 8d05ea8a | blueswir1 | uint32_t saddr, ret; |
105 | e80cfcfc | bellard | |
106 | e80cfcfc | bellard | saddr = (addr & TIMER_MAXADDR) >> 2;
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107 | e80cfcfc | bellard | switch (saddr) {
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108 | e80cfcfc | bellard | case 0: |
109 | f930d07e | blueswir1 | // read limit (system counter mode) or read most signifying
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110 | f930d07e | blueswir1 | // part of counter (user mode)
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111 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
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112 | 115646b6 | blueswir1 | // read user timer MSW
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113 | 115646b6 | blueswir1 | slavio_timer_get_out(s); |
114 | 115646b6 | blueswir1 | ret = s->counthigh; |
115 | 115646b6 | blueswir1 | } else {
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116 | 115646b6 | blueswir1 | // read limit
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117 | f930d07e | blueswir1 | // clear irq
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118 | d7edfd27 | blueswir1 | qemu_irq_lower(s->irq); |
119 | f930d07e | blueswir1 | s->reached = 0;
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120 | 8d05ea8a | blueswir1 | ret = s->limit & 0x7fffffff;
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121 | f930d07e | blueswir1 | } |
122 | 8d05ea8a | blueswir1 | break;
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123 | e80cfcfc | bellard | case 1: |
124 | f930d07e | blueswir1 | // read counter and reached bit (system mode) or read lsbits
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125 | f930d07e | blueswir1 | // of counter (user mode)
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126 | f930d07e | blueswir1 | slavio_timer_get_out(s); |
127 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) // read user timer LSW |
128 | a702b353 | bellard | ret = s->count & 0xfffffe00;
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129 | 115646b6 | blueswir1 | else // read limit |
130 | 115646b6 | blueswir1 | ret = (s->count & 0x7ffffe00) | s->reached;
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131 | 8d05ea8a | blueswir1 | break;
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132 | e80cfcfc | bellard | case 3: |
133 | 115646b6 | blueswir1 | // only available in processor counter/timer
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134 | f930d07e | blueswir1 | // read start/stop status
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135 | 115646b6 | blueswir1 | ret = s->running; |
136 | 8d05ea8a | blueswir1 | break;
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137 | e80cfcfc | bellard | case 4: |
138 | 115646b6 | blueswir1 | // only available in system counter
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139 | f930d07e | blueswir1 | // read user/system mode
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140 | 81732d19 | blueswir1 | ret = s->slave_mode; |
141 | 8d05ea8a | blueswir1 | break;
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142 | e80cfcfc | bellard | default:
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143 | 115646b6 | blueswir1 | DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr); |
144 | 8d05ea8a | blueswir1 | ret = 0;
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145 | 8d05ea8a | blueswir1 | break;
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146 | e80cfcfc | bellard | } |
147 | 8d05ea8a | blueswir1 | DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret); |
148 | 8d05ea8a | blueswir1 | |
149 | 8d05ea8a | blueswir1 | return ret;
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150 | e80cfcfc | bellard | } |
151 | e80cfcfc | bellard | |
152 | e80cfcfc | bellard | static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
153 | e80cfcfc | bellard | { |
154 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
155 | e80cfcfc | bellard | uint32_t saddr; |
156 | 8d05ea8a | blueswir1 | int reload = 0; |
157 | e80cfcfc | bellard | |
158 | 8d05ea8a | blueswir1 | DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val); |
159 | e80cfcfc | bellard | saddr = (addr & TIMER_MAXADDR) >> 2;
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160 | e80cfcfc | bellard | switch (saddr) {
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161 | e80cfcfc | bellard | case 0: |
162 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
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163 | 115646b6 | blueswir1 | // set user counter MSW, reset counter
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164 | 81732d19 | blueswir1 | qemu_irq_lower(s->irq); |
165 | 115646b6 | blueswir1 | s->limit = 0x7ffffffffffffe00ULL;
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166 | 115646b6 | blueswir1 | DPRINTF("processor %d user timer reset\n", s->slave_index);
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167 | 115646b6 | blueswir1 | ptimer_set_limit(s->timer, s->limit >> 9, 1); |
168 | 115646b6 | blueswir1 | } else {
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169 | 115646b6 | blueswir1 | // set limit, reset counter
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170 | 115646b6 | blueswir1 | qemu_irq_lower(s->irq); |
171 | 115646b6 | blueswir1 | s->limit = val & 0x7ffffe00ULL;
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172 | 81732d19 | blueswir1 | if (!s->limit)
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173 | 115646b6 | blueswir1 | s->limit = 0x7ffffe00ULL;
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174 | 81732d19 | blueswir1 | ptimer_set_limit(s->timer, s->limit >> 9, 1); |
175 | 81732d19 | blueswir1 | } |
176 | 115646b6 | blueswir1 | break;
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177 | 115646b6 | blueswir1 | case 1: |
178 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
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179 | 115646b6 | blueswir1 | // set user counter LSW, reset counter
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180 | 115646b6 | blueswir1 | qemu_irq_lower(s->irq); |
181 | 115646b6 | blueswir1 | s->limit = 0x7ffffffffffffe00ULL;
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182 | 115646b6 | blueswir1 | DPRINTF("processor %d user timer reset\n", s->slave_index);
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183 | 115646b6 | blueswir1 | ptimer_set_limit(s->timer, s->limit >> 9, 1); |
184 | 115646b6 | blueswir1 | } else
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185 | 115646b6 | blueswir1 | DPRINTF("not user timer\n");
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186 | 115646b6 | blueswir1 | break;
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187 | e80cfcfc | bellard | case 2: |
188 | f930d07e | blueswir1 | // set limit without resetting counter
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189 | 8d05ea8a | blueswir1 | s->limit = val & 0x7ffffe00ULL;
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190 | 8d05ea8a | blueswir1 | if (!s->limit)
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191 | 8d05ea8a | blueswir1 | s->limit = 0x7ffffe00ULL;
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192 | 8d05ea8a | blueswir1 | ptimer_set_limit(s->timer, s->limit >> 9, reload);
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193 | f930d07e | blueswir1 | break;
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194 | e80cfcfc | bellard | case 3: |
195 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s)) {
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196 | 115646b6 | blueswir1 | // start/stop user counter
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197 | 115646b6 | blueswir1 | if ((val & 1) && !s->running) { |
198 | 115646b6 | blueswir1 | DPRINTF("processor %d user timer started\n", s->slave_index);
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199 | 8d05ea8a | blueswir1 | ptimer_run(s->timer, 0);
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200 | 115646b6 | blueswir1 | s->running = 1;
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201 | 115646b6 | blueswir1 | } else if (!(val & 1) && s->running) { |
202 | 115646b6 | blueswir1 | DPRINTF("processor %d user timer stopped\n", s->slave_index);
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203 | 115646b6 | blueswir1 | ptimer_stop(s->timer); |
204 | 115646b6 | blueswir1 | s->running = 0;
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205 | f930d07e | blueswir1 | } |
206 | f930d07e | blueswir1 | } |
207 | f930d07e | blueswir1 | break;
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208 | e80cfcfc | bellard | case 4: |
209 | 115646b6 | blueswir1 | if (s->master == NULL) { |
210 | 81732d19 | blueswir1 | unsigned int i; |
211 | 81732d19 | blueswir1 | |
212 | 81732d19 | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
213 | 81732d19 | blueswir1 | if (val & (1 << i)) { |
214 | 81732d19 | blueswir1 | qemu_irq_lower(s->slave[i]->irq); |
215 | 81732d19 | blueswir1 | s->slave[i]->limit = -1ULL;
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216 | 81732d19 | blueswir1 | } |
217 | 115646b6 | blueswir1 | if ((val & (1 << i)) != (s->slave_mode & (1 << i))) { |
218 | 115646b6 | blueswir1 | ptimer_stop(s->slave[i]->timer); |
219 | 115646b6 | blueswir1 | ptimer_set_limit(s->slave[i]->timer, s->slave[i]->limit >> 9, 1); |
220 | 115646b6 | blueswir1 | DPRINTF("processor %d timer changed\n", s->slave[i]->slave_index);
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221 | 115646b6 | blueswir1 | ptimer_run(s->slave[i]->timer, 0);
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222 | 115646b6 | blueswir1 | } |
223 | 81732d19 | blueswir1 | } |
224 | 81732d19 | blueswir1 | s->slave_mode = val & ((1 << MAX_CPUS) - 1); |
225 | 115646b6 | blueswir1 | } else
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226 | 115646b6 | blueswir1 | DPRINTF("not system timer\n");
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227 | f930d07e | blueswir1 | break;
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228 | e80cfcfc | bellard | default:
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229 | 115646b6 | blueswir1 | DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr); |
230 | f930d07e | blueswir1 | break;
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231 | e80cfcfc | bellard | } |
232 | e80cfcfc | bellard | } |
233 | e80cfcfc | bellard | |
234 | e80cfcfc | bellard | static CPUReadMemoryFunc *slavio_timer_mem_read[3] = { |
235 | e80cfcfc | bellard | slavio_timer_mem_readl, |
236 | e80cfcfc | bellard | slavio_timer_mem_readl, |
237 | e80cfcfc | bellard | slavio_timer_mem_readl, |
238 | e80cfcfc | bellard | }; |
239 | e80cfcfc | bellard | |
240 | e80cfcfc | bellard | static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = { |
241 | e80cfcfc | bellard | slavio_timer_mem_writel, |
242 | e80cfcfc | bellard | slavio_timer_mem_writel, |
243 | e80cfcfc | bellard | slavio_timer_mem_writel, |
244 | e80cfcfc | bellard | }; |
245 | e80cfcfc | bellard | |
246 | e80cfcfc | bellard | static void slavio_timer_save(QEMUFile *f, void *opaque) |
247 | e80cfcfc | bellard | { |
248 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
249 | e80cfcfc | bellard | |
250 | 8d05ea8a | blueswir1 | qemu_put_be64s(f, &s->limit); |
251 | e80cfcfc | bellard | qemu_put_be32s(f, &s->count); |
252 | e80cfcfc | bellard | qemu_put_be32s(f, &s->counthigh); |
253 | d7edfd27 | blueswir1 | qemu_put_be32(f, 0); // Was irq |
254 | e80cfcfc | bellard | qemu_put_be32s(f, &s->reached); |
255 | 115646b6 | blueswir1 | qemu_put_be32s(f, &s->running); |
256 | 115646b6 | blueswir1 | qemu_put_be32s(f, 0); // Was mode |
257 | 8d05ea8a | blueswir1 | qemu_put_ptimer(f, s->timer); |
258 | e80cfcfc | bellard | } |
259 | e80cfcfc | bellard | |
260 | e80cfcfc | bellard | static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id) |
261 | e80cfcfc | bellard | { |
262 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
263 | d7edfd27 | blueswir1 | uint32_t tmp; |
264 | 3b46e624 | ths | |
265 | 8d05ea8a | blueswir1 | if (version_id != 2) |
266 | e80cfcfc | bellard | return -EINVAL;
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267 | e80cfcfc | bellard | |
268 | 8d05ea8a | blueswir1 | qemu_get_be64s(f, &s->limit); |
269 | e80cfcfc | bellard | qemu_get_be32s(f, &s->count); |
270 | e80cfcfc | bellard | qemu_get_be32s(f, &s->counthigh); |
271 | d7edfd27 | blueswir1 | qemu_get_be32s(f, &tmp); // Was irq
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272 | e80cfcfc | bellard | qemu_get_be32s(f, &s->reached); |
273 | 115646b6 | blueswir1 | qemu_get_be32s(f, &s->running); |
274 | 115646b6 | blueswir1 | qemu_get_be32s(f, &tmp); // Was mode
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275 | 8d05ea8a | blueswir1 | qemu_get_ptimer(f, s->timer); |
276 | 8d05ea8a | blueswir1 | |
277 | e80cfcfc | bellard | return 0; |
278 | e80cfcfc | bellard | } |
279 | e80cfcfc | bellard | |
280 | e80cfcfc | bellard | static void slavio_timer_reset(void *opaque) |
281 | e80cfcfc | bellard | { |
282 | e80cfcfc | bellard | SLAVIO_TIMERState *s = opaque; |
283 | e80cfcfc | bellard | |
284 | 115646b6 | blueswir1 | if (slavio_timer_is_user(s))
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285 | 115646b6 | blueswir1 | s->limit = 0x7ffffffffffffe00ULL;
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286 | 115646b6 | blueswir1 | else
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287 | 115646b6 | blueswir1 | s->limit = 0x7ffffe00ULL;
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288 | e80cfcfc | bellard | s->count = 0;
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289 | e80cfcfc | bellard | s->reached = 0;
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290 | 8d05ea8a | blueswir1 | ptimer_set_limit(s->timer, s->limit >> 9, 1); |
291 | 8d05ea8a | blueswir1 | ptimer_run(s->timer, 0);
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292 | 115646b6 | blueswir1 | s->running = 1;
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293 | d7edfd27 | blueswir1 | qemu_irq_lower(s->irq); |
294 | e80cfcfc | bellard | } |
295 | e80cfcfc | bellard | |
296 | 81732d19 | blueswir1 | static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
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297 | 115646b6 | blueswir1 | qemu_irq irq, |
298 | 115646b6 | blueswir1 | SLAVIO_TIMERState *master, |
299 | 115646b6 | blueswir1 | int slave_index)
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300 | e80cfcfc | bellard | { |
301 | e80cfcfc | bellard | int slavio_timer_io_memory;
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302 | e80cfcfc | bellard | SLAVIO_TIMERState *s; |
303 | 8d05ea8a | blueswir1 | QEMUBH *bh; |
304 | e80cfcfc | bellard | |
305 | e80cfcfc | bellard | s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
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306 | e80cfcfc | bellard | if (!s)
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307 | 81732d19 | blueswir1 | return s;
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308 | e80cfcfc | bellard | s->irq = irq; |
309 | 115646b6 | blueswir1 | s->master = master; |
310 | 115646b6 | blueswir1 | s->slave_index = slave_index; |
311 | 8d05ea8a | blueswir1 | bh = qemu_bh_new(slavio_timer_irq, s); |
312 | 8d05ea8a | blueswir1 | s->timer = ptimer_init(bh); |
313 | 8d05ea8a | blueswir1 | ptimer_set_period(s->timer, 500ULL);
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314 | e80cfcfc | bellard | |
315 | e80cfcfc | bellard | slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
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316 | f930d07e | blueswir1 | slavio_timer_mem_write, s); |
317 | 115646b6 | blueswir1 | if (master)
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318 | 81732d19 | blueswir1 | cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory); |
319 | 81732d19 | blueswir1 | else
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320 | 115646b6 | blueswir1 | cpu_register_physical_memory(addr, SYS_TIMER_SIZE, slavio_timer_io_memory); |
321 | 8d05ea8a | blueswir1 | register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s); |
322 | e80cfcfc | bellard | qemu_register_reset(slavio_timer_reset, s); |
323 | e80cfcfc | bellard | slavio_timer_reset(s); |
324 | 81732d19 | blueswir1 | |
325 | 81732d19 | blueswir1 | return s;
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326 | 81732d19 | blueswir1 | } |
327 | 81732d19 | blueswir1 | |
328 | 81732d19 | blueswir1 | void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
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329 | 81732d19 | blueswir1 | qemu_irq *cpu_irqs) |
330 | 81732d19 | blueswir1 | { |
331 | 81732d19 | blueswir1 | SLAVIO_TIMERState *master; |
332 | 81732d19 | blueswir1 | unsigned int i; |
333 | 81732d19 | blueswir1 | |
334 | 115646b6 | blueswir1 | master = slavio_timer_init(base + 0x10000ULL, master_irq, NULL, 0); |
335 | 81732d19 | blueswir1 | |
336 | 81732d19 | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
337 | 81732d19 | blueswir1 | master->slave[i] = slavio_timer_init(base + (target_phys_addr_t) |
338 | 81732d19 | blueswir1 | (i * TARGET_PAGE_SIZE), |
339 | 115646b6 | blueswir1 | cpu_irqs[i], master, i); |
340 | 81732d19 | blueswir1 | } |
341 | e80cfcfc | bellard | } |