root / hw / arm_gic.c @ a8170e5e
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1 | 5fafdf24 | ths | /*
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2 | 9ee6e8bb | pbrook | * ARM Generic/Distributed Interrupt Controller
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3 | e69954b9 | pbrook | *
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4 | 9ee6e8bb | pbrook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | e69954b9 | pbrook | * Written by Paul Brook
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6 | e69954b9 | pbrook | *
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7 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GPL.
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8 | e69954b9 | pbrook | */
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9 | e69954b9 | pbrook | |
10 | 9ee6e8bb | pbrook | /* This file contains implementation code for the RealView EB interrupt
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11 | 0d256bdc | Peter Maydell | * controller, MPCore distributed interrupt controller and ARMv7-M
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12 | 0d256bdc | Peter Maydell | * Nested Vectored Interrupt Controller.
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13 | 0d256bdc | Peter Maydell | * It is compiled in two ways:
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14 | 0d256bdc | Peter Maydell | * (1) as a standalone file to produce a sysbus device which is a GIC
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15 | 0d256bdc | Peter Maydell | * that can be used on the realview board and as one of the builtin
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16 | 0d256bdc | Peter Maydell | * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
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17 | 0d256bdc | Peter Maydell | * (2) by being directly #included into armv7m_nvic.c to produce the
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18 | 0d256bdc | Peter Maydell | * armv7m_nvic device.
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19 | 0d256bdc | Peter Maydell | */
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20 | e69954b9 | pbrook | |
21 | 496dbcd1 | Peter Maydell | #include "sysbus.h" |
22 | 1e8cae4d | Peter Maydell | #include "arm_gic_internal.h" |
23 | 386e2955 | Peter Maydell | |
24 | e69954b9 | pbrook | //#define DEBUG_GIC
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25 | e69954b9 | pbrook | |
26 | e69954b9 | pbrook | #ifdef DEBUG_GIC
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27 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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28 | 5eb98401 | Peter A. G. Crosthwaite | do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0) |
29 | e69954b9 | pbrook | #else
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30 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) do {} while(0) |
31 | e69954b9 | pbrook | #endif
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32 | e69954b9 | pbrook | |
33 | 2a29ddee | Peter Maydell | static const uint8_t gic_id[] = { |
34 | 2a29ddee | Peter Maydell | 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 |
35 | 2a29ddee | Peter Maydell | }; |
36 | 2a29ddee | Peter Maydell | |
37 | c988bfad | Paul Brook | #define NUM_CPU(s) ((s)->num_cpu)
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38 | 9ee6e8bb | pbrook | |
39 | fae15286 | Peter Maydell | static inline int gic_get_current_cpu(GICState *s) |
40 | 926c4aff | Peter Maydell | { |
41 | 926c4aff | Peter Maydell | if (s->num_cpu > 1) { |
42 | 926c4aff | Peter Maydell | return cpu_single_env->cpu_index;
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43 | 926c4aff | Peter Maydell | } |
44 | 926c4aff | Peter Maydell | return 0; |
45 | 926c4aff | Peter Maydell | } |
46 | 926c4aff | Peter Maydell | |
47 | e69954b9 | pbrook | /* TODO: Many places that call this routine could be optimized. */
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48 | e69954b9 | pbrook | /* Update interrupt status after enabled or pending bits have been changed. */
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49 | fae15286 | Peter Maydell | void gic_update(GICState *s)
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50 | e69954b9 | pbrook | { |
51 | e69954b9 | pbrook | int best_irq;
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52 | e69954b9 | pbrook | int best_prio;
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53 | e69954b9 | pbrook | int irq;
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54 | 9ee6e8bb | pbrook | int level;
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55 | 9ee6e8bb | pbrook | int cpu;
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56 | 9ee6e8bb | pbrook | int cm;
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57 | 9ee6e8bb | pbrook | |
58 | c988bfad | Paul Brook | for (cpu = 0; cpu < NUM_CPU(s); cpu++) { |
59 | 9ee6e8bb | pbrook | cm = 1 << cpu;
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60 | 9ee6e8bb | pbrook | s->current_pending[cpu] = 1023;
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61 | 9ee6e8bb | pbrook | if (!s->enabled || !s->cpu_enabled[cpu]) {
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62 | c79981ce | Peter Maydell | qemu_irq_lower(s->parent_irq[cpu]); |
63 | 9ee6e8bb | pbrook | return;
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64 | 9ee6e8bb | pbrook | } |
65 | 9ee6e8bb | pbrook | best_prio = 0x100;
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66 | 9ee6e8bb | pbrook | best_irq = 1023;
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67 | a32134aa | Mark Langsdorf | for (irq = 0; irq < s->num_irq; irq++) { |
68 | 41bf234d | Rabin Vincent | if (GIC_TEST_ENABLED(irq, cm) && GIC_TEST_PENDING(irq, cm)) {
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69 | 9ee6e8bb | pbrook | if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
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70 | 9ee6e8bb | pbrook | best_prio = GIC_GET_PRIORITY(irq, cpu); |
71 | 9ee6e8bb | pbrook | best_irq = irq; |
72 | 9ee6e8bb | pbrook | } |
73 | e69954b9 | pbrook | } |
74 | e69954b9 | pbrook | } |
75 | 9ee6e8bb | pbrook | level = 0;
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76 | 9ee6e8bb | pbrook | if (best_prio <= s->priority_mask[cpu]) {
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77 | 9ee6e8bb | pbrook | s->current_pending[cpu] = best_irq; |
78 | 9ee6e8bb | pbrook | if (best_prio < s->running_priority[cpu]) {
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79 | 9ee6e8bb | pbrook | DPRINTF("Raised pending IRQ %d\n", best_irq);
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80 | 9ee6e8bb | pbrook | level = 1;
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81 | 9ee6e8bb | pbrook | } |
82 | e69954b9 | pbrook | } |
83 | 9ee6e8bb | pbrook | qemu_set_irq(s->parent_irq[cpu], level); |
84 | e69954b9 | pbrook | } |
85 | e69954b9 | pbrook | } |
86 | e69954b9 | pbrook | |
87 | fae15286 | Peter Maydell | void gic_set_pending_private(GICState *s, int cpu, int irq) |
88 | 9ee6e8bb | pbrook | { |
89 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
90 | 9ee6e8bb | pbrook | |
91 | 9ee6e8bb | pbrook | if (GIC_TEST_PENDING(irq, cm))
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92 | 9ee6e8bb | pbrook | return;
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93 | 9ee6e8bb | pbrook | |
94 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending cpu %d\n", irq, cpu);
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95 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, cm); |
96 | 9ee6e8bb | pbrook | gic_update(s); |
97 | 9ee6e8bb | pbrook | } |
98 | 9ee6e8bb | pbrook | |
99 | 9ee6e8bb | pbrook | /* Process a change in an external IRQ input. */
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100 | e69954b9 | pbrook | static void gic_set_irq(void *opaque, int irq, int level) |
101 | e69954b9 | pbrook | { |
102 | 544d1afa | Peter Maydell | /* Meaning of the 'irq' parameter:
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103 | 544d1afa | Peter Maydell | * [0..N-1] : external interrupts
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104 | 544d1afa | Peter Maydell | * [N..N+31] : PPI (internal) interrupts for CPU 0
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105 | 544d1afa | Peter Maydell | * [N+32..N+63] : PPI (internal interrupts for CPU 1
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106 | 544d1afa | Peter Maydell | * ...
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107 | 544d1afa | Peter Maydell | */
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108 | fae15286 | Peter Maydell | GICState *s = (GICState *)opaque; |
109 | 544d1afa | Peter Maydell | int cm, target;
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110 | 544d1afa | Peter Maydell | if (irq < (s->num_irq - GIC_INTERNAL)) {
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111 | 544d1afa | Peter Maydell | /* The first external input line is internal interrupt 32. */
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112 | 544d1afa | Peter Maydell | cm = ALL_CPU_MASK; |
113 | 544d1afa | Peter Maydell | irq += GIC_INTERNAL; |
114 | 544d1afa | Peter Maydell | target = GIC_TARGET(irq); |
115 | 544d1afa | Peter Maydell | } else {
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116 | 544d1afa | Peter Maydell | int cpu;
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117 | 544d1afa | Peter Maydell | irq -= (s->num_irq - GIC_INTERNAL); |
118 | 544d1afa | Peter Maydell | cpu = irq / GIC_INTERNAL; |
119 | 544d1afa | Peter Maydell | irq %= GIC_INTERNAL; |
120 | 544d1afa | Peter Maydell | cm = 1 << cpu;
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121 | 544d1afa | Peter Maydell | target = cm; |
122 | 544d1afa | Peter Maydell | } |
123 | 544d1afa | Peter Maydell | |
124 | 544d1afa | Peter Maydell | if (level == GIC_TEST_LEVEL(irq, cm)) {
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125 | e69954b9 | pbrook | return;
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126 | 544d1afa | Peter Maydell | } |
127 | e69954b9 | pbrook | |
128 | e69954b9 | pbrook | if (level) {
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129 | 544d1afa | Peter Maydell | GIC_SET_LEVEL(irq, cm); |
130 | 544d1afa | Peter Maydell | if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) {
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131 | 544d1afa | Peter Maydell | DPRINTF("Set %d pending mask %x\n", irq, target);
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132 | 544d1afa | Peter Maydell | GIC_SET_PENDING(irq, target); |
133 | e69954b9 | pbrook | } |
134 | e69954b9 | pbrook | } else {
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135 | 544d1afa | Peter Maydell | GIC_CLEAR_LEVEL(irq, cm); |
136 | e69954b9 | pbrook | } |
137 | e69954b9 | pbrook | gic_update(s); |
138 | e69954b9 | pbrook | } |
139 | e69954b9 | pbrook | |
140 | fae15286 | Peter Maydell | static void gic_set_running_irq(GICState *s, int cpu, int irq) |
141 | e69954b9 | pbrook | { |
142 | 9ee6e8bb | pbrook | s->running_irq[cpu] = irq; |
143 | 9ee6e8bb | pbrook | if (irq == 1023) { |
144 | 9ee6e8bb | pbrook | s->running_priority[cpu] = 0x100;
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145 | 9ee6e8bb | pbrook | } else {
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146 | 9ee6e8bb | pbrook | s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu); |
147 | 9ee6e8bb | pbrook | } |
148 | e69954b9 | pbrook | gic_update(s); |
149 | e69954b9 | pbrook | } |
150 | e69954b9 | pbrook | |
151 | fae15286 | Peter Maydell | uint32_t gic_acknowledge_irq(GICState *s, int cpu)
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152 | e69954b9 | pbrook | { |
153 | e69954b9 | pbrook | int new_irq;
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154 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
155 | 9ee6e8bb | pbrook | new_irq = s->current_pending[cpu]; |
156 | 9ee6e8bb | pbrook | if (new_irq == 1023 |
157 | 9ee6e8bb | pbrook | || GIC_GET_PRIORITY(new_irq, cpu) >= s->running_priority[cpu]) { |
158 | e69954b9 | pbrook | DPRINTF("ACK no pending IRQ\n");
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159 | e69954b9 | pbrook | return 1023; |
160 | e69954b9 | pbrook | } |
161 | 9ee6e8bb | pbrook | s->last_active[new_irq][cpu] = s->running_irq[cpu]; |
162 | 9ee6e8bb | pbrook | /* Clear pending flags for both level and edge triggered interrupts.
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163 | 9ee6e8bb | pbrook | Level triggered IRQs will be reasserted once they become inactive. */
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164 | 9ee6e8bb | pbrook | GIC_CLEAR_PENDING(new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm); |
165 | 9ee6e8bb | pbrook | gic_set_running_irq(s, cpu, new_irq); |
166 | e69954b9 | pbrook | DPRINTF("ACK %d\n", new_irq);
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167 | e69954b9 | pbrook | return new_irq;
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168 | e69954b9 | pbrook | } |
169 | e69954b9 | pbrook | |
170 | fae15286 | Peter Maydell | void gic_complete_irq(GICState *s, int cpu, int irq) |
171 | e69954b9 | pbrook | { |
172 | e69954b9 | pbrook | int update = 0; |
173 | 9ee6e8bb | pbrook | int cm = 1 << cpu; |
174 | df628ff1 | pbrook | DPRINTF("EOI %d\n", irq);
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175 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq) {
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176 | 217bfb44 | Peter Maydell | /* This handles two cases:
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177 | 217bfb44 | Peter Maydell | * 1. If software writes the ID of a spurious interrupt [ie 1023]
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178 | 217bfb44 | Peter Maydell | * to the GICC_EOIR, the GIC ignores that write.
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179 | 217bfb44 | Peter Maydell | * 2. If software writes the number of a non-existent interrupt
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180 | 217bfb44 | Peter Maydell | * this must be a subcase of "value written does not match the last
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181 | 217bfb44 | Peter Maydell | * valid interrupt value read from the Interrupt Acknowledge
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182 | 217bfb44 | Peter Maydell | * register" and so this is UNPREDICTABLE. We choose to ignore it.
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183 | 217bfb44 | Peter Maydell | */
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184 | 217bfb44 | Peter Maydell | return;
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185 | 217bfb44 | Peter Maydell | } |
186 | 9ee6e8bb | pbrook | if (s->running_irq[cpu] == 1023) |
187 | e69954b9 | pbrook | return; /* No active IRQ. */ |
188 | 217bfb44 | Peter Maydell | /* Mark level triggered interrupts as pending if they are still
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189 | 217bfb44 | Peter Maydell | raised. */
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190 | 217bfb44 | Peter Maydell | if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
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191 | 217bfb44 | Peter Maydell | && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
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192 | 217bfb44 | Peter Maydell | DPRINTF("Set %d pending mask %x\n", irq, cm);
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193 | 217bfb44 | Peter Maydell | GIC_SET_PENDING(irq, cm); |
194 | 217bfb44 | Peter Maydell | update = 1;
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195 | e69954b9 | pbrook | } |
196 | 9ee6e8bb | pbrook | if (irq != s->running_irq[cpu]) {
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197 | e69954b9 | pbrook | /* Complete an IRQ that is not currently running. */
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198 | 9ee6e8bb | pbrook | int tmp = s->running_irq[cpu];
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199 | 9ee6e8bb | pbrook | while (s->last_active[tmp][cpu] != 1023) { |
200 | 9ee6e8bb | pbrook | if (s->last_active[tmp][cpu] == irq) {
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201 | 9ee6e8bb | pbrook | s->last_active[tmp][cpu] = s->last_active[irq][cpu]; |
202 | e69954b9 | pbrook | break;
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203 | e69954b9 | pbrook | } |
204 | 9ee6e8bb | pbrook | tmp = s->last_active[tmp][cpu]; |
205 | e69954b9 | pbrook | } |
206 | e69954b9 | pbrook | if (update) {
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207 | e69954b9 | pbrook | gic_update(s); |
208 | e69954b9 | pbrook | } |
209 | e69954b9 | pbrook | } else {
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210 | e69954b9 | pbrook | /* Complete the current running IRQ. */
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211 | 9ee6e8bb | pbrook | gic_set_running_irq(s, cpu, s->last_active[s->running_irq[cpu]][cpu]); |
212 | e69954b9 | pbrook | } |
213 | e69954b9 | pbrook | } |
214 | e69954b9 | pbrook | |
215 | a8170e5e | Avi Kivity | static uint32_t gic_dist_readb(void *opaque, hwaddr offset) |
216 | e69954b9 | pbrook | { |
217 | fae15286 | Peter Maydell | GICState *s = (GICState *)opaque; |
218 | e69954b9 | pbrook | uint32_t res; |
219 | e69954b9 | pbrook | int irq;
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220 | e69954b9 | pbrook | int i;
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221 | 9ee6e8bb | pbrook | int cpu;
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222 | 9ee6e8bb | pbrook | int cm;
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223 | 9ee6e8bb | pbrook | int mask;
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224 | e69954b9 | pbrook | |
225 | 926c4aff | Peter Maydell | cpu = gic_get_current_cpu(s); |
226 | 9ee6e8bb | pbrook | cm = 1 << cpu;
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227 | e69954b9 | pbrook | if (offset < 0x100) { |
228 | e69954b9 | pbrook | if (offset == 0) |
229 | e69954b9 | pbrook | return s->enabled;
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230 | e69954b9 | pbrook | if (offset == 4) |
231 | a32134aa | Mark Langsdorf | return ((s->num_irq / 32) - 1) | ((NUM_CPU(s) - 1) << 5); |
232 | e69954b9 | pbrook | if (offset < 0x08) |
233 | e69954b9 | pbrook | return 0; |
234 | b79f2265 | Rob Herring | if (offset >= 0x80) { |
235 | b79f2265 | Rob Herring | /* Interrupt Security , RAZ/WI */
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236 | b79f2265 | Rob Herring | return 0; |
237 | b79f2265 | Rob Herring | } |
238 | e69954b9 | pbrook | goto bad_reg;
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239 | e69954b9 | pbrook | } else if (offset < 0x200) { |
240 | e69954b9 | pbrook | /* Interrupt Set/Clear Enable. */
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241 | e69954b9 | pbrook | if (offset < 0x180) |
242 | e69954b9 | pbrook | irq = (offset - 0x100) * 8; |
243 | e69954b9 | pbrook | else
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244 | e69954b9 | pbrook | irq = (offset - 0x180) * 8; |
245 | 9ee6e8bb | pbrook | irq += GIC_BASE_IRQ; |
246 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
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247 | e69954b9 | pbrook | goto bad_reg;
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248 | e69954b9 | pbrook | res = 0;
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249 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
250 | 41bf234d | Rabin Vincent | if (GIC_TEST_ENABLED(irq + i, cm)) {
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251 | e69954b9 | pbrook | res |= (1 << i);
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252 | e69954b9 | pbrook | } |
253 | e69954b9 | pbrook | } |
254 | e69954b9 | pbrook | } else if (offset < 0x300) { |
255 | e69954b9 | pbrook | /* Interrupt Set/Clear Pending. */
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256 | e69954b9 | pbrook | if (offset < 0x280) |
257 | e69954b9 | pbrook | irq = (offset - 0x200) * 8; |
258 | e69954b9 | pbrook | else
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259 | e69954b9 | pbrook | irq = (offset - 0x280) * 8; |
260 | 9ee6e8bb | pbrook | irq += GIC_BASE_IRQ; |
261 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
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262 | e69954b9 | pbrook | goto bad_reg;
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263 | e69954b9 | pbrook | res = 0;
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264 | 69253800 | Rusty Russell | mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
265 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
266 | 9ee6e8bb | pbrook | if (GIC_TEST_PENDING(irq + i, mask)) {
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267 | e69954b9 | pbrook | res |= (1 << i);
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268 | e69954b9 | pbrook | } |
269 | e69954b9 | pbrook | } |
270 | e69954b9 | pbrook | } else if (offset < 0x400) { |
271 | e69954b9 | pbrook | /* Interrupt Active. */
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272 | 9ee6e8bb | pbrook | irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; |
273 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
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274 | e69954b9 | pbrook | goto bad_reg;
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275 | e69954b9 | pbrook | res = 0;
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276 | 69253800 | Rusty Russell | mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; |
277 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
278 | 9ee6e8bb | pbrook | if (GIC_TEST_ACTIVE(irq + i, mask)) {
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279 | e69954b9 | pbrook | res |= (1 << i);
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280 | e69954b9 | pbrook | } |
281 | e69954b9 | pbrook | } |
282 | e69954b9 | pbrook | } else if (offset < 0x800) { |
283 | e69954b9 | pbrook | /* Interrupt Priority. */
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284 | 9ee6e8bb | pbrook | irq = (offset - 0x400) + GIC_BASE_IRQ;
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285 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
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286 | e69954b9 | pbrook | goto bad_reg;
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287 | 9ee6e8bb | pbrook | res = GIC_GET_PRIORITY(irq, cpu); |
288 | e69954b9 | pbrook | } else if (offset < 0xc00) { |
289 | e69954b9 | pbrook | /* Interrupt CPU Target. */
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290 | 6b9680bb | Peter Maydell | if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { |
291 | 6b9680bb | Peter Maydell | /* For uniprocessor GICs these RAZ/WI */
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292 | 6b9680bb | Peter Maydell | res = 0;
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293 | 9ee6e8bb | pbrook | } else {
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294 | 6b9680bb | Peter Maydell | irq = (offset - 0x800) + GIC_BASE_IRQ;
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295 | 6b9680bb | Peter Maydell | if (irq >= s->num_irq) {
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296 | 6b9680bb | Peter Maydell | goto bad_reg;
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297 | 6b9680bb | Peter Maydell | } |
298 | 6b9680bb | Peter Maydell | if (irq >= 29 && irq <= 31) { |
299 | 6b9680bb | Peter Maydell | res = cm; |
300 | 6b9680bb | Peter Maydell | } else {
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301 | 6b9680bb | Peter Maydell | res = GIC_TARGET(irq); |
302 | 6b9680bb | Peter Maydell | } |
303 | 9ee6e8bb | pbrook | } |
304 | e69954b9 | pbrook | } else if (offset < 0xf00) { |
305 | e69954b9 | pbrook | /* Interrupt Configuration. */
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306 | 9ee6e8bb | pbrook | irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ; |
307 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
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308 | e69954b9 | pbrook | goto bad_reg;
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309 | e69954b9 | pbrook | res = 0;
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310 | e69954b9 | pbrook | for (i = 0; i < 4; i++) { |
311 | e69954b9 | pbrook | if (GIC_TEST_MODEL(irq + i))
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312 | e69954b9 | pbrook | res |= (1 << (i * 2)); |
313 | e69954b9 | pbrook | if (GIC_TEST_TRIGGER(irq + i))
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314 | e69954b9 | pbrook | res |= (2 << (i * 2)); |
315 | e69954b9 | pbrook | } |
316 | e69954b9 | pbrook | } else if (offset < 0xfe0) { |
317 | e69954b9 | pbrook | goto bad_reg;
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318 | e69954b9 | pbrook | } else /* offset >= 0xfe0 */ { |
319 | e69954b9 | pbrook | if (offset & 3) { |
320 | e69954b9 | pbrook | res = 0;
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321 | e69954b9 | pbrook | } else {
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322 | e69954b9 | pbrook | res = gic_id[(offset - 0xfe0) >> 2]; |
323 | e69954b9 | pbrook | } |
324 | e69954b9 | pbrook | } |
325 | e69954b9 | pbrook | return res;
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326 | e69954b9 | pbrook | bad_reg:
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327 | 2ac71179 | Paul Brook | hw_error("gic_dist_readb: Bad offset %x\n", (int)offset); |
328 | e69954b9 | pbrook | return 0; |
329 | e69954b9 | pbrook | } |
330 | e69954b9 | pbrook | |
331 | a8170e5e | Avi Kivity | static uint32_t gic_dist_readw(void *opaque, hwaddr offset) |
332 | e69954b9 | pbrook | { |
333 | e69954b9 | pbrook | uint32_t val; |
334 | e69954b9 | pbrook | val = gic_dist_readb(opaque, offset); |
335 | e69954b9 | pbrook | val |= gic_dist_readb(opaque, offset + 1) << 8; |
336 | e69954b9 | pbrook | return val;
|
337 | e69954b9 | pbrook | } |
338 | e69954b9 | pbrook | |
339 | a8170e5e | Avi Kivity | static uint32_t gic_dist_readl(void *opaque, hwaddr offset) |
340 | e69954b9 | pbrook | { |
341 | e69954b9 | pbrook | uint32_t val; |
342 | e69954b9 | pbrook | val = gic_dist_readw(opaque, offset); |
343 | e69954b9 | pbrook | val |= gic_dist_readw(opaque, offset + 2) << 16; |
344 | e69954b9 | pbrook | return val;
|
345 | e69954b9 | pbrook | } |
346 | e69954b9 | pbrook | |
347 | a8170e5e | Avi Kivity | static void gic_dist_writeb(void *opaque, hwaddr offset, |
348 | e69954b9 | pbrook | uint32_t value) |
349 | e69954b9 | pbrook | { |
350 | fae15286 | Peter Maydell | GICState *s = (GICState *)opaque; |
351 | e69954b9 | pbrook | int irq;
|
352 | e69954b9 | pbrook | int i;
|
353 | 9ee6e8bb | pbrook | int cpu;
|
354 | e69954b9 | pbrook | |
355 | 926c4aff | Peter Maydell | cpu = gic_get_current_cpu(s); |
356 | e69954b9 | pbrook | if (offset < 0x100) { |
357 | e69954b9 | pbrook | if (offset == 0) { |
358 | e69954b9 | pbrook | s->enabled = (value & 1);
|
359 | e69954b9 | pbrook | DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); |
360 | e69954b9 | pbrook | } else if (offset < 4) { |
361 | e69954b9 | pbrook | /* ignored. */
|
362 | b79f2265 | Rob Herring | } else if (offset >= 0x80) { |
363 | b79f2265 | Rob Herring | /* Interrupt Security Registers, RAZ/WI */
|
364 | e69954b9 | pbrook | } else {
|
365 | e69954b9 | pbrook | goto bad_reg;
|
366 | e69954b9 | pbrook | } |
367 | e69954b9 | pbrook | } else if (offset < 0x180) { |
368 | e69954b9 | pbrook | /* Interrupt Set Enable. */
|
369 | 9ee6e8bb | pbrook | irq = (offset - 0x100) * 8 + GIC_BASE_IRQ; |
370 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
371 | e69954b9 | pbrook | goto bad_reg;
|
372 | 9ee6e8bb | pbrook | if (irq < 16) |
373 | 9ee6e8bb | pbrook | value = 0xff;
|
374 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
375 | e69954b9 | pbrook | if (value & (1 << i)) { |
376 | 69253800 | Rusty Russell | int mask = (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq); |
377 | 69253800 | Rusty Russell | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
378 | 41bf234d | Rabin Vincent | |
379 | 41bf234d | Rabin Vincent | if (!GIC_TEST_ENABLED(irq + i, cm)) {
|
380 | e69954b9 | pbrook | DPRINTF("Enabled IRQ %d\n", irq + i);
|
381 | 41bf234d | Rabin Vincent | } |
382 | 41bf234d | Rabin Vincent | GIC_SET_ENABLED(irq + i, cm); |
383 | e69954b9 | pbrook | /* If a raised level triggered IRQ enabled then mark
|
384 | e69954b9 | pbrook | is as pending. */
|
385 | 9ee6e8bb | pbrook | if (GIC_TEST_LEVEL(irq + i, mask)
|
386 | 9ee6e8bb | pbrook | && !GIC_TEST_TRIGGER(irq + i)) { |
387 | 9ee6e8bb | pbrook | DPRINTF("Set %d pending mask %x\n", irq + i, mask);
|
388 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq + i, mask); |
389 | 9ee6e8bb | pbrook | } |
390 | e69954b9 | pbrook | } |
391 | e69954b9 | pbrook | } |
392 | e69954b9 | pbrook | } else if (offset < 0x200) { |
393 | e69954b9 | pbrook | /* Interrupt Clear Enable. */
|
394 | 9ee6e8bb | pbrook | irq = (offset - 0x180) * 8 + GIC_BASE_IRQ; |
395 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
396 | e69954b9 | pbrook | goto bad_reg;
|
397 | 9ee6e8bb | pbrook | if (irq < 16) |
398 | 9ee6e8bb | pbrook | value = 0;
|
399 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
400 | e69954b9 | pbrook | if (value & (1 << i)) { |
401 | 69253800 | Rusty Russell | int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; |
402 | 41bf234d | Rabin Vincent | |
403 | 41bf234d | Rabin Vincent | if (GIC_TEST_ENABLED(irq + i, cm)) {
|
404 | e69954b9 | pbrook | DPRINTF("Disabled IRQ %d\n", irq + i);
|
405 | 41bf234d | Rabin Vincent | } |
406 | 41bf234d | Rabin Vincent | GIC_CLEAR_ENABLED(irq + i, cm); |
407 | e69954b9 | pbrook | } |
408 | e69954b9 | pbrook | } |
409 | e69954b9 | pbrook | } else if (offset < 0x280) { |
410 | e69954b9 | pbrook | /* Interrupt Set Pending. */
|
411 | 9ee6e8bb | pbrook | irq = (offset - 0x200) * 8 + GIC_BASE_IRQ; |
412 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
413 | e69954b9 | pbrook | goto bad_reg;
|
414 | 9ee6e8bb | pbrook | if (irq < 16) |
415 | 9ee6e8bb | pbrook | irq = 0;
|
416 | 9ee6e8bb | pbrook | |
417 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
418 | e69954b9 | pbrook | if (value & (1 << i)) { |
419 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq + i, GIC_TARGET(irq)); |
420 | e69954b9 | pbrook | } |
421 | e69954b9 | pbrook | } |
422 | e69954b9 | pbrook | } else if (offset < 0x300) { |
423 | e69954b9 | pbrook | /* Interrupt Clear Pending. */
|
424 | 9ee6e8bb | pbrook | irq = (offset - 0x280) * 8 + GIC_BASE_IRQ; |
425 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
426 | e69954b9 | pbrook | goto bad_reg;
|
427 | e69954b9 | pbrook | for (i = 0; i < 8; i++) { |
428 | 9ee6e8bb | pbrook | /* ??? This currently clears the pending bit for all CPUs, even
|
429 | 9ee6e8bb | pbrook | for per-CPU interrupts. It's unclear whether this is the
|
430 | 9ee6e8bb | pbrook | corect behavior. */
|
431 | e69954b9 | pbrook | if (value & (1 << i)) { |
432 | 9ee6e8bb | pbrook | GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); |
433 | e69954b9 | pbrook | } |
434 | e69954b9 | pbrook | } |
435 | e69954b9 | pbrook | } else if (offset < 0x400) { |
436 | e69954b9 | pbrook | /* Interrupt Active. */
|
437 | e69954b9 | pbrook | goto bad_reg;
|
438 | e69954b9 | pbrook | } else if (offset < 0x800) { |
439 | e69954b9 | pbrook | /* Interrupt Priority. */
|
440 | 9ee6e8bb | pbrook | irq = (offset - 0x400) + GIC_BASE_IRQ;
|
441 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
442 | e69954b9 | pbrook | goto bad_reg;
|
443 | 69253800 | Rusty Russell | if (irq < GIC_INTERNAL) {
|
444 | 9ee6e8bb | pbrook | s->priority1[irq][cpu] = value; |
445 | 9ee6e8bb | pbrook | } else {
|
446 | 69253800 | Rusty Russell | s->priority2[irq - GIC_INTERNAL] = value; |
447 | 9ee6e8bb | pbrook | } |
448 | e69954b9 | pbrook | } else if (offset < 0xc00) { |
449 | 6b9680bb | Peter Maydell | /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
|
450 | 6b9680bb | Peter Maydell | * annoying exception of the 11MPCore's GIC.
|
451 | 6b9680bb | Peter Maydell | */
|
452 | 6b9680bb | Peter Maydell | if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { |
453 | 6b9680bb | Peter Maydell | irq = (offset - 0x800) + GIC_BASE_IRQ;
|
454 | 6b9680bb | Peter Maydell | if (irq >= s->num_irq) {
|
455 | 6b9680bb | Peter Maydell | goto bad_reg;
|
456 | 6b9680bb | Peter Maydell | } |
457 | 6b9680bb | Peter Maydell | if (irq < 29) { |
458 | 6b9680bb | Peter Maydell | value = 0;
|
459 | 6b9680bb | Peter Maydell | } else if (irq < GIC_INTERNAL) { |
460 | 6b9680bb | Peter Maydell | value = ALL_CPU_MASK; |
461 | 6b9680bb | Peter Maydell | } |
462 | 6b9680bb | Peter Maydell | s->irq_target[irq] = value & ALL_CPU_MASK; |
463 | 6b9680bb | Peter Maydell | } |
464 | e69954b9 | pbrook | } else if (offset < 0xf00) { |
465 | e69954b9 | pbrook | /* Interrupt Configuration. */
|
466 | 9ee6e8bb | pbrook | irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; |
467 | a32134aa | Mark Langsdorf | if (irq >= s->num_irq)
|
468 | e69954b9 | pbrook | goto bad_reg;
|
469 | 69253800 | Rusty Russell | if (irq < GIC_INTERNAL)
|
470 | 9ee6e8bb | pbrook | value |= 0xaa;
|
471 | e69954b9 | pbrook | for (i = 0; i < 4; i++) { |
472 | e69954b9 | pbrook | if (value & (1 << (i * 2))) { |
473 | e69954b9 | pbrook | GIC_SET_MODEL(irq + i); |
474 | e69954b9 | pbrook | } else {
|
475 | e69954b9 | pbrook | GIC_CLEAR_MODEL(irq + i); |
476 | e69954b9 | pbrook | } |
477 | e69954b9 | pbrook | if (value & (2 << (i * 2))) { |
478 | e69954b9 | pbrook | GIC_SET_TRIGGER(irq + i); |
479 | e69954b9 | pbrook | } else {
|
480 | e69954b9 | pbrook | GIC_CLEAR_TRIGGER(irq + i); |
481 | e69954b9 | pbrook | } |
482 | e69954b9 | pbrook | } |
483 | e69954b9 | pbrook | } else {
|
484 | 9ee6e8bb | pbrook | /* 0xf00 is only handled for 32-bit writes. */
|
485 | e69954b9 | pbrook | goto bad_reg;
|
486 | e69954b9 | pbrook | } |
487 | e69954b9 | pbrook | gic_update(s); |
488 | e69954b9 | pbrook | return;
|
489 | e69954b9 | pbrook | bad_reg:
|
490 | 2ac71179 | Paul Brook | hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset); |
491 | e69954b9 | pbrook | } |
492 | e69954b9 | pbrook | |
493 | a8170e5e | Avi Kivity | static void gic_dist_writew(void *opaque, hwaddr offset, |
494 | e69954b9 | pbrook | uint32_t value) |
495 | e69954b9 | pbrook | { |
496 | e69954b9 | pbrook | gic_dist_writeb(opaque, offset, value & 0xff);
|
497 | e69954b9 | pbrook | gic_dist_writeb(opaque, offset + 1, value >> 8); |
498 | e69954b9 | pbrook | } |
499 | e69954b9 | pbrook | |
500 | a8170e5e | Avi Kivity | static void gic_dist_writel(void *opaque, hwaddr offset, |
501 | e69954b9 | pbrook | uint32_t value) |
502 | e69954b9 | pbrook | { |
503 | fae15286 | Peter Maydell | GICState *s = (GICState *)opaque; |
504 | 8da3ff18 | pbrook | if (offset == 0xf00) { |
505 | 9ee6e8bb | pbrook | int cpu;
|
506 | 9ee6e8bb | pbrook | int irq;
|
507 | 9ee6e8bb | pbrook | int mask;
|
508 | 9ee6e8bb | pbrook | |
509 | 926c4aff | Peter Maydell | cpu = gic_get_current_cpu(s); |
510 | 9ee6e8bb | pbrook | irq = value & 0x3ff;
|
511 | 9ee6e8bb | pbrook | switch ((value >> 24) & 3) { |
512 | 9ee6e8bb | pbrook | case 0: |
513 | 9ee6e8bb | pbrook | mask = (value >> 16) & ALL_CPU_MASK;
|
514 | 9ee6e8bb | pbrook | break;
|
515 | 9ee6e8bb | pbrook | case 1: |
516 | fa250144 | Adam Lackorzynski | mask = ALL_CPU_MASK ^ (1 << cpu);
|
517 | 9ee6e8bb | pbrook | break;
|
518 | 9ee6e8bb | pbrook | case 2: |
519 | fa250144 | Adam Lackorzynski | mask = 1 << cpu;
|
520 | 9ee6e8bb | pbrook | break;
|
521 | 9ee6e8bb | pbrook | default:
|
522 | 9ee6e8bb | pbrook | DPRINTF("Bad Soft Int target filter\n");
|
523 | 9ee6e8bb | pbrook | mask = ALL_CPU_MASK; |
524 | 9ee6e8bb | pbrook | break;
|
525 | 9ee6e8bb | pbrook | } |
526 | 9ee6e8bb | pbrook | GIC_SET_PENDING(irq, mask); |
527 | 9ee6e8bb | pbrook | gic_update(s); |
528 | 9ee6e8bb | pbrook | return;
|
529 | 9ee6e8bb | pbrook | } |
530 | e69954b9 | pbrook | gic_dist_writew(opaque, offset, value & 0xffff);
|
531 | e69954b9 | pbrook | gic_dist_writew(opaque, offset + 2, value >> 16); |
532 | e69954b9 | pbrook | } |
533 | e69954b9 | pbrook | |
534 | 755c0802 | Avi Kivity | static const MemoryRegionOps gic_dist_ops = { |
535 | 755c0802 | Avi Kivity | .old_mmio = { |
536 | 755c0802 | Avi Kivity | .read = { gic_dist_readb, gic_dist_readw, gic_dist_readl, }, |
537 | 755c0802 | Avi Kivity | .write = { gic_dist_writeb, gic_dist_writew, gic_dist_writel, }, |
538 | 755c0802 | Avi Kivity | }, |
539 | 755c0802 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
540 | e69954b9 | pbrook | }; |
541 | e69954b9 | pbrook | |
542 | fae15286 | Peter Maydell | static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) |
543 | e69954b9 | pbrook | { |
544 | e69954b9 | pbrook | switch (offset) {
|
545 | e69954b9 | pbrook | case 0x00: /* Control */ |
546 | 9ee6e8bb | pbrook | return s->cpu_enabled[cpu];
|
547 | e69954b9 | pbrook | case 0x04: /* Priority mask */ |
548 | 9ee6e8bb | pbrook | return s->priority_mask[cpu];
|
549 | e69954b9 | pbrook | case 0x08: /* Binary Point */ |
550 | e69954b9 | pbrook | /* ??? Not implemented. */
|
551 | e69954b9 | pbrook | return 0; |
552 | e69954b9 | pbrook | case 0x0c: /* Acknowledge */ |
553 | 9ee6e8bb | pbrook | return gic_acknowledge_irq(s, cpu);
|
554 | 66a0a2cb | Dong Xu Wang | case 0x14: /* Running Priority */ |
555 | 9ee6e8bb | pbrook | return s->running_priority[cpu];
|
556 | e69954b9 | pbrook | case 0x18: /* Highest Pending Interrupt */ |
557 | 9ee6e8bb | pbrook | return s->current_pending[cpu];
|
558 | e69954b9 | pbrook | default:
|
559 | 2ac71179 | Paul Brook | hw_error("gic_cpu_read: Bad offset %x\n", (int)offset); |
560 | e69954b9 | pbrook | return 0; |
561 | e69954b9 | pbrook | } |
562 | e69954b9 | pbrook | } |
563 | e69954b9 | pbrook | |
564 | fae15286 | Peter Maydell | static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) |
565 | e69954b9 | pbrook | { |
566 | e69954b9 | pbrook | switch (offset) {
|
567 | e69954b9 | pbrook | case 0x00: /* Control */ |
568 | 9ee6e8bb | pbrook | s->cpu_enabled[cpu] = (value & 1);
|
569 | 9ab1b605 | Evgeny Voevodin | DPRINTF("CPU %d %sabled\n", cpu, s->cpu_enabled[cpu] ? "En" : "Dis"); |
570 | e69954b9 | pbrook | break;
|
571 | e69954b9 | pbrook | case 0x04: /* Priority mask */ |
572 | 9ee6e8bb | pbrook | s->priority_mask[cpu] = (value & 0xff);
|
573 | e69954b9 | pbrook | break;
|
574 | e69954b9 | pbrook | case 0x08: /* Binary Point */ |
575 | e69954b9 | pbrook | /* ??? Not implemented. */
|
576 | e69954b9 | pbrook | break;
|
577 | e69954b9 | pbrook | case 0x10: /* End Of Interrupt */ |
578 | 9ee6e8bb | pbrook | return gic_complete_irq(s, cpu, value & 0x3ff); |
579 | e69954b9 | pbrook | default:
|
580 | 2ac71179 | Paul Brook | hw_error("gic_cpu_write: Bad offset %x\n", (int)offset); |
581 | e69954b9 | pbrook | return;
|
582 | e69954b9 | pbrook | } |
583 | e69954b9 | pbrook | gic_update(s); |
584 | e69954b9 | pbrook | } |
585 | e2c56465 | Peter Maydell | |
586 | e2c56465 | Peter Maydell | /* Wrappers to read/write the GIC CPU interface for the current CPU */
|
587 | a8170e5e | Avi Kivity | static uint64_t gic_thiscpu_read(void *opaque, hwaddr addr, |
588 | e2c56465 | Peter Maydell | unsigned size)
|
589 | e2c56465 | Peter Maydell | { |
590 | fae15286 | Peter Maydell | GICState *s = (GICState *)opaque; |
591 | 926c4aff | Peter Maydell | return gic_cpu_read(s, gic_get_current_cpu(s), addr);
|
592 | e2c56465 | Peter Maydell | } |
593 | e2c56465 | Peter Maydell | |
594 | a8170e5e | Avi Kivity | static void gic_thiscpu_write(void *opaque, hwaddr addr, |
595 | e2c56465 | Peter Maydell | uint64_t value, unsigned size)
|
596 | e2c56465 | Peter Maydell | { |
597 | fae15286 | Peter Maydell | GICState *s = (GICState *)opaque; |
598 | 926c4aff | Peter Maydell | gic_cpu_write(s, gic_get_current_cpu(s), addr, value); |
599 | e2c56465 | Peter Maydell | } |
600 | e2c56465 | Peter Maydell | |
601 | e2c56465 | Peter Maydell | /* Wrappers to read/write the GIC CPU interface for a specific CPU.
|
602 | fae15286 | Peter Maydell | * These just decode the opaque pointer into GICState* + cpu id.
|
603 | e2c56465 | Peter Maydell | */
|
604 | a8170e5e | Avi Kivity | static uint64_t gic_do_cpu_read(void *opaque, hwaddr addr, |
605 | e2c56465 | Peter Maydell | unsigned size)
|
606 | e2c56465 | Peter Maydell | { |
607 | fae15286 | Peter Maydell | GICState **backref = (GICState **)opaque; |
608 | fae15286 | Peter Maydell | GICState *s = *backref; |
609 | e2c56465 | Peter Maydell | int id = (backref - s->backref);
|
610 | 0e4a398a | Peter Maydell | return gic_cpu_read(s, id, addr);
|
611 | e2c56465 | Peter Maydell | } |
612 | e2c56465 | Peter Maydell | |
613 | a8170e5e | Avi Kivity | static void gic_do_cpu_write(void *opaque, hwaddr addr, |
614 | e2c56465 | Peter Maydell | uint64_t value, unsigned size)
|
615 | e2c56465 | Peter Maydell | { |
616 | fae15286 | Peter Maydell | GICState **backref = (GICState **)opaque; |
617 | fae15286 | Peter Maydell | GICState *s = *backref; |
618 | e2c56465 | Peter Maydell | int id = (backref - s->backref);
|
619 | 0e4a398a | Peter Maydell | gic_cpu_write(s, id, addr, value); |
620 | e2c56465 | Peter Maydell | } |
621 | e2c56465 | Peter Maydell | |
622 | e2c56465 | Peter Maydell | static const MemoryRegionOps gic_thiscpu_ops = { |
623 | e2c56465 | Peter Maydell | .read = gic_thiscpu_read, |
624 | e2c56465 | Peter Maydell | .write = gic_thiscpu_write, |
625 | e2c56465 | Peter Maydell | .endianness = DEVICE_NATIVE_ENDIAN, |
626 | e2c56465 | Peter Maydell | }; |
627 | e2c56465 | Peter Maydell | |
628 | e2c56465 | Peter Maydell | static const MemoryRegionOps gic_cpu_ops = { |
629 | e2c56465 | Peter Maydell | .read = gic_do_cpu_read, |
630 | e2c56465 | Peter Maydell | .write = gic_do_cpu_write, |
631 | e2c56465 | Peter Maydell | .endianness = DEVICE_NATIVE_ENDIAN, |
632 | e2c56465 | Peter Maydell | }; |
633 | e69954b9 | pbrook | |
634 | fae15286 | Peter Maydell | void gic_init_irqs_and_distributor(GICState *s, int num_irq) |
635 | e69954b9 | pbrook | { |
636 | 23e39294 | pbrook | int i;
|
637 | 41c1e2f5 | Rusty Russell | |
638 | 544d1afa | Peter Maydell | i = s->num_irq - GIC_INTERNAL; |
639 | 544d1afa | Peter Maydell | /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
|
640 | 544d1afa | Peter Maydell | * GPIO array layout is thus:
|
641 | 544d1afa | Peter Maydell | * [0..N-1] SPIs
|
642 | 544d1afa | Peter Maydell | * [N..N+31] PPIs for CPU 0
|
643 | 544d1afa | Peter Maydell | * [N+32..N+63] PPIs for CPU 1
|
644 | 544d1afa | Peter Maydell | * ...
|
645 | 544d1afa | Peter Maydell | */
|
646 | 84e4fccb | Peter Maydell | if (s->revision != REV_NVIC) {
|
647 | 84e4fccb | Peter Maydell | i += (GIC_INTERNAL * s->num_cpu); |
648 | 84e4fccb | Peter Maydell | } |
649 | 544d1afa | Peter Maydell | qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i); |
650 | c988bfad | Paul Brook | for (i = 0; i < NUM_CPU(s); i++) { |
651 | fe7e8758 | Paul Brook | sysbus_init_irq(&s->busdev, &s->parent_irq[i]); |
652 | e69954b9 | pbrook | } |
653 | 755c0802 | Avi Kivity | memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000); |
654 | 2b518c56 | Peter Maydell | } |
655 | 2b518c56 | Peter Maydell | |
656 | 2b518c56 | Peter Maydell | static int arm_gic_init(SysBusDevice *dev) |
657 | 2b518c56 | Peter Maydell | { |
658 | 2b518c56 | Peter Maydell | /* Device instance init function for the GIC sysbus device */
|
659 | 2b518c56 | Peter Maydell | int i;
|
660 | fae15286 | Peter Maydell | GICState *s = FROM_SYSBUS(GICState, dev); |
661 | 1e8cae4d | Peter Maydell | ARMGICClass *agc = ARM_GIC_GET_CLASS(s); |
662 | 1e8cae4d | Peter Maydell | |
663 | 1e8cae4d | Peter Maydell | agc->parent_init(dev); |
664 | 1e8cae4d | Peter Maydell | |
665 | 2b518c56 | Peter Maydell | gic_init_irqs_and_distributor(s, s->num_irq); |
666 | 2b518c56 | Peter Maydell | |
667 | e2c56465 | Peter Maydell | /* Memory regions for the CPU interfaces (NVIC doesn't have these):
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668 | e2c56465 | Peter Maydell | * a region for "CPU interface for this core", then a region for
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669 | e2c56465 | Peter Maydell | * "CPU interface for core 0", "for core 1", ...
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670 | e2c56465 | Peter Maydell | * NB that the memory region size of 0x100 applies for the 11MPCore
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671 | e2c56465 | Peter Maydell | * and also cores following the GIC v1 spec (ie A9).
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672 | e2c56465 | Peter Maydell | * GIC v2 defines a larger memory region (0x1000) so this will need
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673 | e2c56465 | Peter Maydell | * to be extended when we implement A15.
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674 | e2c56465 | Peter Maydell | */
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675 | e2c56465 | Peter Maydell | memory_region_init_io(&s->cpuiomem[0], &gic_thiscpu_ops, s,
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676 | e2c56465 | Peter Maydell | "gic_cpu", 0x100); |
677 | e2c56465 | Peter Maydell | for (i = 0; i < NUM_CPU(s); i++) { |
678 | e2c56465 | Peter Maydell | s->backref[i] = s; |
679 | e2c56465 | Peter Maydell | memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i],
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680 | e2c56465 | Peter Maydell | "gic_cpu", 0x100); |
681 | e2c56465 | Peter Maydell | } |
682 | 496dbcd1 | Peter Maydell | /* Distributor */
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683 | 496dbcd1 | Peter Maydell | sysbus_init_mmio(dev, &s->iomem); |
684 | 496dbcd1 | Peter Maydell | /* cpu interfaces (one for "current cpu" plus one per cpu) */
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685 | 496dbcd1 | Peter Maydell | for (i = 0; i <= NUM_CPU(s); i++) { |
686 | 496dbcd1 | Peter Maydell | sysbus_init_mmio(dev, &s->cpuiomem[i]); |
687 | 496dbcd1 | Peter Maydell | } |
688 | 496dbcd1 | Peter Maydell | return 0; |
689 | 496dbcd1 | Peter Maydell | } |
690 | 496dbcd1 | Peter Maydell | |
691 | 496dbcd1 | Peter Maydell | static void arm_gic_class_init(ObjectClass *klass, void *data) |
692 | 496dbcd1 | Peter Maydell | { |
693 | 496dbcd1 | Peter Maydell | DeviceClass *dc = DEVICE_CLASS(klass); |
694 | 496dbcd1 | Peter Maydell | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
695 | 1e8cae4d | Peter Maydell | ARMGICClass *agc = ARM_GIC_CLASS(klass); |
696 | 1e8cae4d | Peter Maydell | agc->parent_init = sbc->init; |
697 | 496dbcd1 | Peter Maydell | sbc->init = arm_gic_init; |
698 | 496dbcd1 | Peter Maydell | dc->no_user = 1;
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699 | 496dbcd1 | Peter Maydell | } |
700 | 496dbcd1 | Peter Maydell | |
701 | 496dbcd1 | Peter Maydell | static TypeInfo arm_gic_info = {
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702 | 1e8cae4d | Peter Maydell | .name = TYPE_ARM_GIC, |
703 | 1e8cae4d | Peter Maydell | .parent = TYPE_ARM_GIC_COMMON, |
704 | fae15286 | Peter Maydell | .instance_size = sizeof(GICState),
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705 | 496dbcd1 | Peter Maydell | .class_init = arm_gic_class_init, |
706 | 998a74bc | Peter Maydell | .class_size = sizeof(ARMGICClass),
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707 | 496dbcd1 | Peter Maydell | }; |
708 | 496dbcd1 | Peter Maydell | |
709 | 496dbcd1 | Peter Maydell | static void arm_gic_register_types(void) |
710 | 496dbcd1 | Peter Maydell | { |
711 | 496dbcd1 | Peter Maydell | type_register_static(&arm_gic_info); |
712 | 496dbcd1 | Peter Maydell | } |
713 | 496dbcd1 | Peter Maydell | |
714 | 496dbcd1 | Peter Maydell | type_init(arm_gic_register_types) |