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1 | 6515b203 | bellard | /*
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2 | 6515b203 | bellard | * ACPI implementation
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3 | 5fafdf24 | ths | *
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4 | 6515b203 | bellard | * Copyright (c) 2006 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 6515b203 | bellard | * This library is free software; you can redistribute it and/or
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7 | 6515b203 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 6515b203 | bellard | * License version 2 as published by the Free Software Foundation.
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9 | 6515b203 | bellard | *
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10 | 6515b203 | bellard | * This library is distributed in the hope that it will be useful,
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11 | 6515b203 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 | 6515b203 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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13 | 6515b203 | bellard | * Lesser General Public License for more details.
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14 | 6515b203 | bellard | *
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15 | 6515b203 | bellard | * You should have received a copy of the GNU Lesser General Public
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16 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>
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17 | 6515b203 | bellard | */
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18 | 87ecb68b | pbrook | #include "hw.h" |
19 | 87ecb68b | pbrook | #include "pc.h" |
20 | 87ecb68b | pbrook | #include "pci.h" |
21 | 87ecb68b | pbrook | #include "qemu-timer.h" |
22 | 87ecb68b | pbrook | #include "sysemu.h" |
23 | 87ecb68b | pbrook | #include "i2c.h" |
24 | 87ecb68b | pbrook | #include "smbus.h" |
25 | 7ba1e619 | aliguori | #include "kvm.h" |
26 | 6515b203 | bellard | |
27 | 6515b203 | bellard | //#define DEBUG
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28 | 6515b203 | bellard | |
29 | 6515b203 | bellard | /* i82731AB (PIIX4) compatible power management function */
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30 | 6515b203 | bellard | #define PM_FREQ 3579545 |
31 | 6515b203 | bellard | |
32 | 6515b203 | bellard | #define ACPI_DBG_IO_ADDR 0xb044 |
33 | 6515b203 | bellard | |
34 | 6515b203 | bellard | typedef struct PIIX4PMState { |
35 | 6515b203 | bellard | PCIDevice dev; |
36 | 6515b203 | bellard | uint16_t pmsts; |
37 | 6515b203 | bellard | uint16_t pmen; |
38 | 6515b203 | bellard | uint16_t pmcntrl; |
39 | ab1e34ad | bellard | uint8_t apmc; |
40 | ab1e34ad | bellard | uint8_t apms; |
41 | 6515b203 | bellard | QEMUTimer *tmr_timer; |
42 | 6515b203 | bellard | int64_t tmr_overflow_time; |
43 | 0ff596d0 | pbrook | i2c_bus *smbus; |
44 | 3fffc223 | ths | uint8_t smb_stat; |
45 | 3fffc223 | ths | uint8_t smb_ctl; |
46 | 3fffc223 | ths | uint8_t smb_cmd; |
47 | 3fffc223 | ths | uint8_t smb_addr; |
48 | 3fffc223 | ths | uint8_t smb_data0; |
49 | 3fffc223 | ths | uint8_t smb_data1; |
50 | 3fffc223 | ths | uint8_t smb_data[32];
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51 | 3fffc223 | ths | uint8_t smb_index; |
52 | cf7a2fe2 | aurel32 | qemu_irq irq; |
53 | 6515b203 | bellard | } PIIX4PMState; |
54 | 6515b203 | bellard | |
55 | 0bacd130 | aliguori | #define RSM_STS (1 << 15) |
56 | 0bacd130 | aliguori | #define PWRBTN_STS (1 << 8) |
57 | 6515b203 | bellard | #define RTC_EN (1 << 10) |
58 | 6515b203 | bellard | #define PWRBTN_EN (1 << 8) |
59 | 6515b203 | bellard | #define GBL_EN (1 << 5) |
60 | 6515b203 | bellard | #define TMROF_EN (1 << 0) |
61 | 6515b203 | bellard | |
62 | 6515b203 | bellard | #define SCI_EN (1 << 0) |
63 | 6515b203 | bellard | |
64 | 6515b203 | bellard | #define SUS_EN (1 << 13) |
65 | 6515b203 | bellard | |
66 | 24bc1cbc | ths | #define ACPI_ENABLE 0xf1 |
67 | 24bc1cbc | ths | #define ACPI_DISABLE 0xf0 |
68 | 24bc1cbc | ths | |
69 | 3fffc223 | ths | #define SMBHSTSTS 0x00 |
70 | 3fffc223 | ths | #define SMBHSTCNT 0x02 |
71 | 3fffc223 | ths | #define SMBHSTCMD 0x03 |
72 | 3fffc223 | ths | #define SMBHSTADD 0x04 |
73 | 3fffc223 | ths | #define SMBHSTDAT0 0x05 |
74 | 3fffc223 | ths | #define SMBHSTDAT1 0x06 |
75 | 3fffc223 | ths | #define SMBBLKDAT 0x07 |
76 | 3fffc223 | ths | |
77 | 9669d3c5 | aurel32 | static PIIX4PMState *pm_state;
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78 | cf7a2fe2 | aurel32 | |
79 | 6515b203 | bellard | static uint32_t get_pmtmr(PIIX4PMState *s)
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80 | 6515b203 | bellard | { |
81 | 7546c016 | balrog | uint32_t d; |
82 | 7546c016 | balrog | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
83 | 7546c016 | balrog | return d & 0xffffff; |
84 | 6515b203 | bellard | } |
85 | 6515b203 | bellard | |
86 | 6515b203 | bellard | static int get_pmsts(PIIX4PMState *s) |
87 | 6515b203 | bellard | { |
88 | 7546c016 | balrog | int64_t d; |
89 | 7546c016 | balrog | int pmsts;
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90 | 7546c016 | balrog | pmsts = s->pmsts; |
91 | 7546c016 | balrog | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
92 | 7546c016 | balrog | if (d >= s->tmr_overflow_time)
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93 | 7546c016 | balrog | s->pmsts |= TMROF_EN; |
94 | 055479fe | aliguori | return s->pmsts;
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95 | 6515b203 | bellard | } |
96 | 6515b203 | bellard | |
97 | 6515b203 | bellard | static void pm_update_sci(PIIX4PMState *s) |
98 | 6515b203 | bellard | { |
99 | 7546c016 | balrog | int sci_level, pmsts;
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100 | 7546c016 | balrog | int64_t expire_time; |
101 | 7546c016 | balrog | |
102 | 7546c016 | balrog | pmsts = get_pmsts(s); |
103 | 7546c016 | balrog | sci_level = (((pmsts & s->pmen) & |
104 | 7546c016 | balrog | (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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105 | 7546c016 | balrog | qemu_set_irq(s->irq, sci_level); |
106 | 7546c016 | balrog | /* schedule a timer interruption if needed */
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107 | 7546c016 | balrog | if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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108 | 7546c016 | balrog | expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ); |
109 | 7546c016 | balrog | qemu_mod_timer(s->tmr_timer, expire_time); |
110 | 7546c016 | balrog | } else {
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111 | 7546c016 | balrog | qemu_del_timer(s->tmr_timer); |
112 | 7546c016 | balrog | } |
113 | 6515b203 | bellard | } |
114 | 6515b203 | bellard | |
115 | 6515b203 | bellard | static void pm_tmr_timer(void *opaque) |
116 | 6515b203 | bellard | { |
117 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
118 | 7546c016 | balrog | pm_update_sci(s); |
119 | 6515b203 | bellard | } |
120 | 6515b203 | bellard | |
121 | 6515b203 | bellard | static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
122 | 6515b203 | bellard | { |
123 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
124 | 6515b203 | bellard | addr &= 0x3f;
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125 | 6515b203 | bellard | switch(addr) {
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126 | 6515b203 | bellard | case 0x00: |
127 | 7546c016 | balrog | { |
128 | 7546c016 | balrog | int64_t d; |
129 | 7546c016 | balrog | int pmsts;
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130 | 7546c016 | balrog | pmsts = get_pmsts(s); |
131 | 7546c016 | balrog | if (pmsts & val & TMROF_EN) {
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132 | 7546c016 | balrog | /* if TMRSTS is reset, then compute the new overflow time */
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133 | 7546c016 | balrog | d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
134 | 7546c016 | balrog | s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; |
135 | 7546c016 | balrog | } |
136 | 7546c016 | balrog | s->pmsts &= ~val; |
137 | 7546c016 | balrog | pm_update_sci(s); |
138 | 7546c016 | balrog | } |
139 | 6515b203 | bellard | break;
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140 | 6515b203 | bellard | case 0x02: |
141 | 6515b203 | bellard | s->pmen = val; |
142 | 6515b203 | bellard | pm_update_sci(s); |
143 | 6515b203 | bellard | break;
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144 | 6515b203 | bellard | case 0x04: |
145 | 6515b203 | bellard | { |
146 | 6515b203 | bellard | int sus_typ;
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147 | 6515b203 | bellard | s->pmcntrl = val & ~(SUS_EN); |
148 | 6515b203 | bellard | if (val & SUS_EN) {
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149 | 6515b203 | bellard | /* change suspend type */
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150 | f99ed40a | aurel32 | sus_typ = (val >> 10) & 7; |
151 | 6515b203 | bellard | switch(sus_typ) {
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152 | 6515b203 | bellard | case 0: /* soft power off */ |
153 | 6515b203 | bellard | qemu_system_shutdown_request(); |
154 | 6515b203 | bellard | break;
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155 | 0bacd130 | aliguori | case 1: |
156 | 0bacd130 | aliguori | /* RSM_STS should be set on resume. Pretend that resume
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157 | 0bacd130 | aliguori | was caused by power button */
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158 | 0bacd130 | aliguori | s->pmsts |= (RSM_STS | PWRBTN_STS); |
159 | 0bacd130 | aliguori | qemu_system_reset_request(); |
160 | 0bacd130 | aliguori | #if defined(TARGET_I386)
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161 | 0bacd130 | aliguori | cmos_set_s3_resume(); |
162 | 0bacd130 | aliguori | #endif
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163 | 6515b203 | bellard | default:
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164 | 6515b203 | bellard | break;
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165 | 6515b203 | bellard | } |
166 | 6515b203 | bellard | } |
167 | 6515b203 | bellard | } |
168 | 6515b203 | bellard | break;
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169 | 6515b203 | bellard | default:
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170 | 6515b203 | bellard | break;
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171 | 6515b203 | bellard | } |
172 | 6515b203 | bellard | #ifdef DEBUG
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173 | 6515b203 | bellard | printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
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174 | 6515b203 | bellard | #endif
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175 | 6515b203 | bellard | } |
176 | 6515b203 | bellard | |
177 | 6515b203 | bellard | static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
178 | 6515b203 | bellard | { |
179 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
180 | 6515b203 | bellard | uint32_t val; |
181 | 6515b203 | bellard | |
182 | 6515b203 | bellard | addr &= 0x3f;
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183 | 6515b203 | bellard | switch(addr) {
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184 | 6515b203 | bellard | case 0x00: |
185 | 6515b203 | bellard | val = get_pmsts(s); |
186 | 6515b203 | bellard | break;
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187 | 6515b203 | bellard | case 0x02: |
188 | 6515b203 | bellard | val = s->pmen; |
189 | 6515b203 | bellard | break;
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190 | 6515b203 | bellard | case 0x04: |
191 | 6515b203 | bellard | val = s->pmcntrl; |
192 | 6515b203 | bellard | break;
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193 | 6515b203 | bellard | default:
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194 | 6515b203 | bellard | val = 0;
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195 | 6515b203 | bellard | break;
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196 | 6515b203 | bellard | } |
197 | 6515b203 | bellard | #ifdef DEBUG
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198 | 6515b203 | bellard | printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
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199 | 6515b203 | bellard | #endif
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200 | 6515b203 | bellard | return val;
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201 | 6515b203 | bellard | } |
202 | 6515b203 | bellard | |
203 | 6515b203 | bellard | static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
204 | 6515b203 | bellard | { |
205 | 6515b203 | bellard | // PIIX4PMState *s = opaque;
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206 | 6515b203 | bellard | addr &= 0x3f;
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207 | 6515b203 | bellard | #ifdef DEBUG
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208 | 6515b203 | bellard | printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
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209 | 6515b203 | bellard | #endif
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210 | 6515b203 | bellard | } |
211 | 6515b203 | bellard | |
212 | 6515b203 | bellard | static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
213 | 6515b203 | bellard | { |
214 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
215 | 6515b203 | bellard | uint32_t val; |
216 | 6515b203 | bellard | |
217 | 6515b203 | bellard | addr &= 0x3f;
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218 | 6515b203 | bellard | switch(addr) {
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219 | 6515b203 | bellard | case 0x08: |
220 | 6515b203 | bellard | val = get_pmtmr(s); |
221 | 6515b203 | bellard | break;
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222 | 6515b203 | bellard | default:
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223 | 6515b203 | bellard | val = 0;
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224 | 6515b203 | bellard | break;
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225 | 6515b203 | bellard | } |
226 | 6515b203 | bellard | #ifdef DEBUG
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227 | 6515b203 | bellard | printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
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228 | 6515b203 | bellard | #endif
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229 | 6515b203 | bellard | return val;
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230 | 6515b203 | bellard | } |
231 | 6515b203 | bellard | |
232 | ab1e34ad | bellard | static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val) |
233 | 6515b203 | bellard | { |
234 | 6515b203 | bellard | PIIX4PMState *s = opaque; |
235 | ab1e34ad | bellard | addr &= 1;
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236 | 6515b203 | bellard | #ifdef DEBUG
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237 | ab1e34ad | bellard | printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
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238 | 6515b203 | bellard | #endif
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239 | ab1e34ad | bellard | if (addr == 0) { |
240 | ab1e34ad | bellard | s->apmc = val; |
241 | 24bc1cbc | ths | |
242 | 24bc1cbc | ths | /* ACPI specs 3.0, 4.7.2.5 */
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243 | 24bc1cbc | ths | if (val == ACPI_ENABLE) {
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244 | 24bc1cbc | ths | s->pmcntrl |= SCI_EN; |
245 | 24bc1cbc | ths | } else if (val == ACPI_DISABLE) { |
246 | 24bc1cbc | ths | s->pmcntrl &= ~SCI_EN; |
247 | 24bc1cbc | ths | } |
248 | 24bc1cbc | ths | |
249 | 47d02f6d | bellard | if (s->dev.config[0x5b] & (1 << 1)) { |
250 | 47d02f6d | bellard | cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); |
251 | ab1e34ad | bellard | } |
252 | ab1e34ad | bellard | } else {
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253 | ab1e34ad | bellard | s->apms = val; |
254 | 6515b203 | bellard | } |
255 | 6515b203 | bellard | } |
256 | 6515b203 | bellard | |
257 | ab1e34ad | bellard | static uint32_t pm_smi_readb(void *opaque, uint32_t addr) |
258 | ab1e34ad | bellard | { |
259 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
260 | ab1e34ad | bellard | uint32_t val; |
261 | 3b46e624 | ths | |
262 | ab1e34ad | bellard | addr &= 1;
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263 | ab1e34ad | bellard | if (addr == 0) { |
264 | ab1e34ad | bellard | val = s->apmc; |
265 | ab1e34ad | bellard | } else {
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266 | ab1e34ad | bellard | val = s->apms; |
267 | ab1e34ad | bellard | } |
268 | ab1e34ad | bellard | #ifdef DEBUG
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269 | ab1e34ad | bellard | printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
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270 | ab1e34ad | bellard | #endif
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271 | ab1e34ad | bellard | return val;
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272 | ab1e34ad | bellard | } |
273 | ab1e34ad | bellard | |
274 | 6515b203 | bellard | static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
275 | 6515b203 | bellard | { |
276 | 6515b203 | bellard | #if defined(DEBUG)
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277 | 6515b203 | bellard | printf("ACPI: DBG: 0x%08x\n", val);
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278 | 6515b203 | bellard | #endif
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279 | 6515b203 | bellard | } |
280 | 6515b203 | bellard | |
281 | 3fffc223 | ths | static void smb_transaction(PIIX4PMState *s) |
282 | 3fffc223 | ths | { |
283 | 3fffc223 | ths | uint8_t prot = (s->smb_ctl >> 2) & 0x07; |
284 | 3fffc223 | ths | uint8_t read = s->smb_addr & 0x01;
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285 | 3fffc223 | ths | uint8_t cmd = s->smb_cmd; |
286 | 3fffc223 | ths | uint8_t addr = s->smb_addr >> 1;
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287 | 0ff596d0 | pbrook | i2c_bus *bus = s->smbus; |
288 | 3fffc223 | ths | |
289 | 3fffc223 | ths | #ifdef DEBUG
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290 | 3fffc223 | ths | printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
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291 | 3fffc223 | ths | #endif
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292 | 3fffc223 | ths | switch(prot) {
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293 | 3fffc223 | ths | case 0x0: |
294 | 0ff596d0 | pbrook | smbus_quick_command(bus, addr, read); |
295 | 3fffc223 | ths | break;
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296 | 3fffc223 | ths | case 0x1: |
297 | 3fffc223 | ths | if (read) {
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298 | 0ff596d0 | pbrook | s->smb_data0 = smbus_receive_byte(bus, addr); |
299 | 0ff596d0 | pbrook | } else {
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300 | 0ff596d0 | pbrook | smbus_send_byte(bus, addr, cmd); |
301 | 3fffc223 | ths | } |
302 | 3fffc223 | ths | break;
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303 | 3fffc223 | ths | case 0x2: |
304 | 3fffc223 | ths | if (read) {
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305 | 0ff596d0 | pbrook | s->smb_data0 = smbus_read_byte(bus, addr, cmd); |
306 | 0ff596d0 | pbrook | } else {
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307 | 0ff596d0 | pbrook | smbus_write_byte(bus, addr, cmd, s->smb_data0); |
308 | 3fffc223 | ths | } |
309 | 3fffc223 | ths | break;
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310 | 3fffc223 | ths | case 0x3: |
311 | 3fffc223 | ths | if (read) {
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312 | 3fffc223 | ths | uint16_t val; |
313 | 0ff596d0 | pbrook | val = smbus_read_word(bus, addr, cmd); |
314 | 3fffc223 | ths | s->smb_data0 = val; |
315 | 3fffc223 | ths | s->smb_data1 = val >> 8;
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316 | 0ff596d0 | pbrook | } else {
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317 | 0ff596d0 | pbrook | smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
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318 | 3fffc223 | ths | } |
319 | 3fffc223 | ths | break;
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320 | 3fffc223 | ths | case 0x5: |
321 | 3fffc223 | ths | if (read) {
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322 | 0ff596d0 | pbrook | s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data); |
323 | 0ff596d0 | pbrook | } else {
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324 | 0ff596d0 | pbrook | smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0); |
325 | 3fffc223 | ths | } |
326 | 3fffc223 | ths | break;
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327 | 3fffc223 | ths | default:
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328 | 3fffc223 | ths | goto error;
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329 | 3fffc223 | ths | } |
330 | 3fffc223 | ths | return;
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331 | 3fffc223 | ths | |
332 | 3fffc223 | ths | error:
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333 | 3fffc223 | ths | s->smb_stat |= 0x04;
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334 | 3fffc223 | ths | } |
335 | 3fffc223 | ths | |
336 | 3fffc223 | ths | static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
337 | 3fffc223 | ths | { |
338 | 3fffc223 | ths | PIIX4PMState *s = opaque; |
339 | 3fffc223 | ths | addr &= 0x3f;
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340 | 3fffc223 | ths | #ifdef DEBUG
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341 | 3fffc223 | ths | printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
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342 | 3fffc223 | ths | #endif
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343 | 3fffc223 | ths | switch(addr) {
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344 | 3fffc223 | ths | case SMBHSTSTS:
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345 | 3fffc223 | ths | s->smb_stat = 0;
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346 | 3fffc223 | ths | s->smb_index = 0;
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347 | 3fffc223 | ths | break;
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348 | 3fffc223 | ths | case SMBHSTCNT:
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349 | 3fffc223 | ths | s->smb_ctl = val; |
350 | 3fffc223 | ths | if (val & 0x40) |
351 | 3fffc223 | ths | smb_transaction(s); |
352 | 3fffc223 | ths | break;
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353 | 3fffc223 | ths | case SMBHSTCMD:
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354 | 3fffc223 | ths | s->smb_cmd = val; |
355 | 3fffc223 | ths | break;
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356 | 3fffc223 | ths | case SMBHSTADD:
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357 | 3fffc223 | ths | s->smb_addr = val; |
358 | 3fffc223 | ths | break;
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359 | 3fffc223 | ths | case SMBHSTDAT0:
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360 | 3fffc223 | ths | s->smb_data0 = val; |
361 | 3fffc223 | ths | break;
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362 | 3fffc223 | ths | case SMBHSTDAT1:
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363 | 3fffc223 | ths | s->smb_data1 = val; |
364 | 3fffc223 | ths | break;
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365 | 3fffc223 | ths | case SMBBLKDAT:
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366 | 3fffc223 | ths | s->smb_data[s->smb_index++] = val; |
367 | 3fffc223 | ths | if (s->smb_index > 31) |
368 | 3fffc223 | ths | s->smb_index = 0;
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369 | 3fffc223 | ths | break;
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370 | 3fffc223 | ths | default:
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371 | 3fffc223 | ths | break;
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372 | 3fffc223 | ths | } |
373 | 3fffc223 | ths | } |
374 | 3fffc223 | ths | |
375 | 3fffc223 | ths | static uint32_t smb_ioport_readb(void *opaque, uint32_t addr) |
376 | 3fffc223 | ths | { |
377 | 3fffc223 | ths | PIIX4PMState *s = opaque; |
378 | 3fffc223 | ths | uint32_t val; |
379 | 3fffc223 | ths | |
380 | 3fffc223 | ths | addr &= 0x3f;
|
381 | 3fffc223 | ths | switch(addr) {
|
382 | 3fffc223 | ths | case SMBHSTSTS:
|
383 | 3fffc223 | ths | val = s->smb_stat; |
384 | 3fffc223 | ths | break;
|
385 | 3fffc223 | ths | case SMBHSTCNT:
|
386 | 3fffc223 | ths | s->smb_index = 0;
|
387 | 3fffc223 | ths | val = s->smb_ctl & 0x1f;
|
388 | 3fffc223 | ths | break;
|
389 | 3fffc223 | ths | case SMBHSTCMD:
|
390 | 3fffc223 | ths | val = s->smb_cmd; |
391 | 3fffc223 | ths | break;
|
392 | 3fffc223 | ths | case SMBHSTADD:
|
393 | 3fffc223 | ths | val = s->smb_addr; |
394 | 3fffc223 | ths | break;
|
395 | 3fffc223 | ths | case SMBHSTDAT0:
|
396 | 3fffc223 | ths | val = s->smb_data0; |
397 | 3fffc223 | ths | break;
|
398 | 3fffc223 | ths | case SMBHSTDAT1:
|
399 | 3fffc223 | ths | val = s->smb_data1; |
400 | 3fffc223 | ths | break;
|
401 | 3fffc223 | ths | case SMBBLKDAT:
|
402 | 3fffc223 | ths | val = s->smb_data[s->smb_index++]; |
403 | 3fffc223 | ths | if (s->smb_index > 31) |
404 | 3fffc223 | ths | s->smb_index = 0;
|
405 | 3fffc223 | ths | break;
|
406 | 3fffc223 | ths | default:
|
407 | 3fffc223 | ths | val = 0;
|
408 | 3fffc223 | ths | break;
|
409 | 3fffc223 | ths | } |
410 | 3fffc223 | ths | #ifdef DEBUG
|
411 | 3fffc223 | ths | printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
|
412 | 3fffc223 | ths | #endif
|
413 | 3fffc223 | ths | return val;
|
414 | 3fffc223 | ths | } |
415 | 3fffc223 | ths | |
416 | ab1e34ad | bellard | static void pm_io_space_update(PIIX4PMState *s) |
417 | ab1e34ad | bellard | { |
418 | ab1e34ad | bellard | uint32_t pm_io_base; |
419 | ab1e34ad | bellard | |
420 | ab1e34ad | bellard | if (s->dev.config[0x80] & 1) { |
421 | ab1e34ad | bellard | pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
|
422 | bf367b54 | ths | pm_io_base &= 0xffc0;
|
423 | ab1e34ad | bellard | |
424 | ab1e34ad | bellard | /* XXX: need to improve memory and ioport allocation */
|
425 | ab1e34ad | bellard | #if defined(DEBUG)
|
426 | ab1e34ad | bellard | printf("PM: mapping to 0x%x\n", pm_io_base);
|
427 | ab1e34ad | bellard | #endif
|
428 | ab1e34ad | bellard | register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
429 | ab1e34ad | bellard | register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
430 | ab1e34ad | bellard | register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
431 | ab1e34ad | bellard | register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); |
432 | ab1e34ad | bellard | } |
433 | ab1e34ad | bellard | } |
434 | ab1e34ad | bellard | |
435 | 5fafdf24 | ths | static void pm_write_config(PCIDevice *d, |
436 | ab1e34ad | bellard | uint32_t address, uint32_t val, int len)
|
437 | ab1e34ad | bellard | { |
438 | ab1e34ad | bellard | pci_default_write_config(d, address, val, len); |
439 | ab1e34ad | bellard | if (address == 0x80) |
440 | ab1e34ad | bellard | pm_io_space_update((PIIX4PMState *)d); |
441 | ab1e34ad | bellard | } |
442 | ab1e34ad | bellard | |
443 | ab1e34ad | bellard | static void pm_save(QEMUFile* f,void *opaque) |
444 | ab1e34ad | bellard | { |
445 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
446 | ab1e34ad | bellard | |
447 | ab1e34ad | bellard | pci_device_save(&s->dev, f); |
448 | ab1e34ad | bellard | |
449 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmsts); |
450 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmen); |
451 | ab1e34ad | bellard | qemu_put_be16s(f, &s->pmcntrl); |
452 | ab1e34ad | bellard | qemu_put_8s(f, &s->apmc); |
453 | ab1e34ad | bellard | qemu_put_8s(f, &s->apms); |
454 | ab1e34ad | bellard | qemu_put_timer(f, s->tmr_timer); |
455 | bee8d684 | ths | qemu_put_be64(f, s->tmr_overflow_time); |
456 | ab1e34ad | bellard | } |
457 | ab1e34ad | bellard | |
458 | ab1e34ad | bellard | static int pm_load(QEMUFile* f,void* opaque,int version_id) |
459 | ab1e34ad | bellard | { |
460 | ab1e34ad | bellard | PIIX4PMState *s = opaque; |
461 | ab1e34ad | bellard | int ret;
|
462 | ab1e34ad | bellard | |
463 | ab1e34ad | bellard | if (version_id > 1) |
464 | ab1e34ad | bellard | return -EINVAL;
|
465 | ab1e34ad | bellard | |
466 | ab1e34ad | bellard | ret = pci_device_load(&s->dev, f); |
467 | ab1e34ad | bellard | if (ret < 0) |
468 | ab1e34ad | bellard | return ret;
|
469 | ab1e34ad | bellard | |
470 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmsts); |
471 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmen); |
472 | ab1e34ad | bellard | qemu_get_be16s(f, &s->pmcntrl); |
473 | ab1e34ad | bellard | qemu_get_8s(f, &s->apmc); |
474 | ab1e34ad | bellard | qemu_get_8s(f, &s->apms); |
475 | ab1e34ad | bellard | qemu_get_timer(f, s->tmr_timer); |
476 | bee8d684 | ths | s->tmr_overflow_time=qemu_get_be64(f); |
477 | ab1e34ad | bellard | |
478 | ab1e34ad | bellard | pm_io_space_update(s); |
479 | ab1e34ad | bellard | |
480 | ab1e34ad | bellard | return 0; |
481 | ab1e34ad | bellard | } |
482 | ab1e34ad | bellard | |
483 | 0bacd130 | aliguori | static void piix4_reset(void *opaque) |
484 | 0bacd130 | aliguori | { |
485 | 3c892168 | aliguori | PIIX4PMState *s = opaque; |
486 | 3c892168 | aliguori | uint8_t *pci_conf = s->dev.config; |
487 | 3c892168 | aliguori | |
488 | 3c892168 | aliguori | pci_conf[0x58] = 0; |
489 | 3c892168 | aliguori | pci_conf[0x59] = 0; |
490 | 3c892168 | aliguori | pci_conf[0x5a] = 0; |
491 | 3c892168 | aliguori | pci_conf[0x5b] = 0; |
492 | 0bacd130 | aliguori | |
493 | 3c892168 | aliguori | if (kvm_enabled()) {
|
494 | 3c892168 | aliguori | /* Mark SMM as already inited (until KVM supports SMM). */
|
495 | 3c892168 | aliguori | pci_conf[0x5B] = 0x02; |
496 | 3c892168 | aliguori | } |
497 | 0bacd130 | aliguori | } |
498 | 0bacd130 | aliguori | |
499 | d9c32310 | Blue Swirl | static void piix4_powerdown(void *opaque, int irq, int power_failing) |
500 | d9c32310 | Blue Swirl | { |
501 | d9c32310 | Blue Swirl | #if defined(TARGET_I386)
|
502 | d9c32310 | Blue Swirl | PIIX4PMState *s = opaque; |
503 | d9c32310 | Blue Swirl | |
504 | d9c32310 | Blue Swirl | if (!s) {
|
505 | d9c32310 | Blue Swirl | qemu_system_shutdown_request(); |
506 | d9c32310 | Blue Swirl | } else if (s->pmen & PWRBTN_EN) { |
507 | d9c32310 | Blue Swirl | s->pmsts |= PWRBTN_EN; |
508 | d9c32310 | Blue Swirl | pm_update_sci(s); |
509 | d9c32310 | Blue Swirl | } |
510 | d9c32310 | Blue Swirl | #endif
|
511 | d9c32310 | Blue Swirl | } |
512 | d9c32310 | Blue Swirl | |
513 | cf7a2fe2 | aurel32 | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
514 | cf7a2fe2 | aurel32 | qemu_irq sci_irq) |
515 | 6515b203 | bellard | { |
516 | 6515b203 | bellard | PIIX4PMState *s; |
517 | 6515b203 | bellard | uint8_t *pci_conf; |
518 | 6515b203 | bellard | |
519 | 6515b203 | bellard | s = (PIIX4PMState *)pci_register_device(bus, |
520 | 6515b203 | bellard | "PM", sizeof(PIIX4PMState), |
521 | ab1e34ad | bellard | devfn, NULL, pm_write_config);
|
522 | cf7a2fe2 | aurel32 | pm_state = s; |
523 | 6515b203 | bellard | pci_conf = s->dev.config; |
524 | deb54399 | aliguori | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
525 | deb54399 | aliguori | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3); |
526 | bf367b54 | ths | pci_conf[0x06] = 0x80; |
527 | bf367b54 | ths | pci_conf[0x07] = 0x02; |
528 | a78b03cb | balrog | pci_conf[0x08] = 0x03; // revision number |
529 | 6515b203 | bellard | pci_conf[0x09] = 0x00; |
530 | 173a543b | blueswir1 | pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); |
531 | 6407f373 | Isaku Yamahata | pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
532 | 6515b203 | bellard | pci_conf[0x3d] = 0x01; // interrupt pin 1 |
533 | 3b46e624 | ths | |
534 | ab1e34ad | bellard | pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
535 | 3b46e624 | ths | |
536 | ab1e34ad | bellard | register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s); |
537 | ab1e34ad | bellard | register_ioport_read(0xb2, 2, 1, pm_smi_readb, s); |
538 | ab1e34ad | bellard | |
539 | 6515b203 | bellard | register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); |
540 | 6515b203 | bellard | |
541 | 7ba1e619 | aliguori | if (kvm_enabled()) {
|
542 | 7ba1e619 | aliguori | /* Mark SMM as already inited to prevent SMM from running. KVM does not
|
543 | 7ba1e619 | aliguori | * support SMM mode. */
|
544 | 7ba1e619 | aliguori | pci_conf[0x5B] = 0x02; |
545 | 7ba1e619 | aliguori | } |
546 | 7ba1e619 | aliguori | |
547 | 1ce549ab | bellard | /* XXX: which specification is used ? The i82731AB has different
|
548 | 1ce549ab | bellard | mappings */
|
549 | 1ce549ab | bellard | pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10; |
550 | 1ce549ab | bellard | pci_conf[0x63] = 0x60; |
551 | 1ce549ab | bellard | pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) | |
552 | 1ce549ab | bellard | (serial_hds[1] != NULL ? 0x90 : 0); |
553 | 1ce549ab | bellard | |
554 | 3fffc223 | ths | pci_conf[0x90] = smb_io_base | 1; |
555 | 3fffc223 | ths | pci_conf[0x91] = smb_io_base >> 8; |
556 | 3fffc223 | ths | pci_conf[0xd2] = 0x09; |
557 | 3fffc223 | ths | register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s); |
558 | 3fffc223 | ths | register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s); |
559 | 3fffc223 | ths | |
560 | 6515b203 | bellard | s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); |
561 | 6515b203 | bellard | |
562 | d9c32310 | Blue Swirl | qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
|
563 | d9c32310 | Blue Swirl | |
564 | ab1e34ad | bellard | register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s); |
565 | 3fffc223 | ths | |
566 | 02e2da45 | Paul Brook | s->smbus = i2c_init_bus(NULL, "i2c"); |
567 | cf7a2fe2 | aurel32 | s->irq = sci_irq; |
568 | a08d4367 | Jan Kiszka | qemu_register_reset(piix4_reset, s); |
569 | 0bacd130 | aliguori | |
570 | 0ff596d0 | pbrook | return s->smbus;
|
571 | 6515b203 | bellard | } |
572 | cf7a2fe2 | aurel32 | |
573 | 5e3cb534 | aliguori | #define GPE_BASE 0xafe0 |
574 | ca2c72be | aliguori | #define PCI_BASE 0xae00 |
575 | ca2c72be | aliguori | #define PCI_EJ_BASE 0xae08 |
576 | 5e3cb534 | aliguori | |
577 | 5e3cb534 | aliguori | struct gpe_regs {
|
578 | 5e3cb534 | aliguori | uint16_t sts; /* status */
|
579 | 5e3cb534 | aliguori | uint16_t en; /* enabled */
|
580 | 5e3cb534 | aliguori | }; |
581 | 5e3cb534 | aliguori | |
582 | ca2c72be | aliguori | struct pci_status {
|
583 | ca2c72be | aliguori | uint32_t up; |
584 | ca2c72be | aliguori | uint32_t down; |
585 | ca2c72be | aliguori | }; |
586 | ca2c72be | aliguori | |
587 | 5e3cb534 | aliguori | static struct gpe_regs gpe; |
588 | ca2c72be | aliguori | static struct pci_status pci0_status; |
589 | 5e3cb534 | aliguori | |
590 | 6eb011b0 | aliguori | static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
|
591 | 6eb011b0 | aliguori | { |
592 | 6eb011b0 | aliguori | if (addr & 1) |
593 | 6eb011b0 | aliguori | return (val >> 8) & 0xff; |
594 | 6eb011b0 | aliguori | return val & 0xff; |
595 | 6eb011b0 | aliguori | } |
596 | 6eb011b0 | aliguori | |
597 | 5e3cb534 | aliguori | static uint32_t gpe_readb(void *opaque, uint32_t addr) |
598 | 5e3cb534 | aliguori | { |
599 | 5e3cb534 | aliguori | uint32_t val = 0;
|
600 | 5e3cb534 | aliguori | struct gpe_regs *g = opaque;
|
601 | 5e3cb534 | aliguori | switch (addr) {
|
602 | 5e3cb534 | aliguori | case GPE_BASE:
|
603 | 5e3cb534 | aliguori | case GPE_BASE + 1: |
604 | 6eb011b0 | aliguori | val = gpe_read_val(g->sts, addr); |
605 | 5e3cb534 | aliguori | break;
|
606 | 5e3cb534 | aliguori | case GPE_BASE + 2: |
607 | 5e3cb534 | aliguori | case GPE_BASE + 3: |
608 | 6eb011b0 | aliguori | val = gpe_read_val(g->en, addr); |
609 | 5e3cb534 | aliguori | break;
|
610 | 5e3cb534 | aliguori | default:
|
611 | 5e3cb534 | aliguori | break;
|
612 | 5e3cb534 | aliguori | } |
613 | 5e3cb534 | aliguori | |
614 | 5e3cb534 | aliguori | #if defined(DEBUG)
|
615 | f654d9e2 | Alex Williamson | printf("gpe read %x == %x\n", addr, val);
|
616 | 5e3cb534 | aliguori | #endif
|
617 | 5e3cb534 | aliguori | return val;
|
618 | 5e3cb534 | aliguori | } |
619 | 5e3cb534 | aliguori | |
620 | 6eb011b0 | aliguori | static void gpe_write_val(uint16_t *cur, int addr, uint32_t val) |
621 | 6eb011b0 | aliguori | { |
622 | 6eb011b0 | aliguori | if (addr & 1) |
623 | 6eb011b0 | aliguori | *cur = (*cur & 0xff) | (val << 8); |
624 | 6eb011b0 | aliguori | else
|
625 | 6eb011b0 | aliguori | *cur = (*cur & 0xff00) | (val & 0xff); |
626 | 6eb011b0 | aliguori | } |
627 | 6eb011b0 | aliguori | |
628 | 6eb011b0 | aliguori | static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val) |
629 | 6eb011b0 | aliguori | { |
630 | 6eb011b0 | aliguori | uint16_t x1, x0 = val & 0xff;
|
631 | 6eb011b0 | aliguori | int shift = (addr & 1) ? 8 : 0; |
632 | 6eb011b0 | aliguori | |
633 | 6eb011b0 | aliguori | x1 = (*cur >> shift) & 0xff;
|
634 | 6eb011b0 | aliguori | |
635 | 6eb011b0 | aliguori | x1 = x1 & ~x0; |
636 | 6eb011b0 | aliguori | |
637 | 6eb011b0 | aliguori | *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift); |
638 | 6eb011b0 | aliguori | } |
639 | 6eb011b0 | aliguori | |
640 | 5e3cb534 | aliguori | static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
641 | 5e3cb534 | aliguori | { |
642 | 5e3cb534 | aliguori | struct gpe_regs *g = opaque;
|
643 | 5e3cb534 | aliguori | switch (addr) {
|
644 | 5e3cb534 | aliguori | case GPE_BASE:
|
645 | 5e3cb534 | aliguori | case GPE_BASE + 1: |
646 | 6eb011b0 | aliguori | gpe_reset_val(&g->sts, addr, val); |
647 | 5e3cb534 | aliguori | break;
|
648 | 5e3cb534 | aliguori | case GPE_BASE + 2: |
649 | 5e3cb534 | aliguori | case GPE_BASE + 3: |
650 | 6eb011b0 | aliguori | gpe_write_val(&g->en, addr, val); |
651 | 5e3cb534 | aliguori | break;
|
652 | 5e3cb534 | aliguori | default:
|
653 | 5e3cb534 | aliguori | break;
|
654 | 5e3cb534 | aliguori | } |
655 | 5e3cb534 | aliguori | |
656 | 5e3cb534 | aliguori | #if defined(DEBUG)
|
657 | f654d9e2 | Alex Williamson | printf("gpe write %x <== %d\n", addr, val);
|
658 | 5e3cb534 | aliguori | #endif
|
659 | 5e3cb534 | aliguori | } |
660 | 5e3cb534 | aliguori | |
661 | ca2c72be | aliguori | static uint32_t pcihotplug_read(void *opaque, uint32_t addr) |
662 | ca2c72be | aliguori | { |
663 | ca2c72be | aliguori | uint32_t val = 0;
|
664 | ca2c72be | aliguori | struct pci_status *g = opaque;
|
665 | ca2c72be | aliguori | switch (addr) {
|
666 | ca2c72be | aliguori | case PCI_BASE:
|
667 | ca2c72be | aliguori | val = g->up; |
668 | ca2c72be | aliguori | break;
|
669 | ca2c72be | aliguori | case PCI_BASE + 4: |
670 | ca2c72be | aliguori | val = g->down; |
671 | ca2c72be | aliguori | break;
|
672 | ca2c72be | aliguori | default:
|
673 | ca2c72be | aliguori | break;
|
674 | ca2c72be | aliguori | } |
675 | ca2c72be | aliguori | |
676 | ca2c72be | aliguori | #if defined(DEBUG)
|
677 | f654d9e2 | Alex Williamson | printf("pcihotplug read %x == %x\n", addr, val);
|
678 | ca2c72be | aliguori | #endif
|
679 | ca2c72be | aliguori | return val;
|
680 | ca2c72be | aliguori | } |
681 | ca2c72be | aliguori | |
682 | ca2c72be | aliguori | static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val) |
683 | ca2c72be | aliguori | { |
684 | ca2c72be | aliguori | struct pci_status *g = opaque;
|
685 | ca2c72be | aliguori | switch (addr) {
|
686 | ca2c72be | aliguori | case PCI_BASE:
|
687 | ca2c72be | aliguori | g->up = val; |
688 | ca2c72be | aliguori | break;
|
689 | ca2c72be | aliguori | case PCI_BASE + 4: |
690 | ca2c72be | aliguori | g->down = val; |
691 | ca2c72be | aliguori | break;
|
692 | ca2c72be | aliguori | } |
693 | ca2c72be | aliguori | |
694 | ca2c72be | aliguori | #if defined(DEBUG)
|
695 | f654d9e2 | Alex Williamson | printf("pcihotplug write %x <== %d\n", addr, val);
|
696 | ca2c72be | aliguori | #endif
|
697 | ca2c72be | aliguori | } |
698 | ca2c72be | aliguori | |
699 | ca2c72be | aliguori | static uint32_t pciej_read(void *opaque, uint32_t addr) |
700 | ca2c72be | aliguori | { |
701 | ca2c72be | aliguori | #if defined(DEBUG)
|
702 | f654d9e2 | Alex Williamson | printf("pciej read %x\n", addr);
|
703 | ca2c72be | aliguori | #endif
|
704 | ca2c72be | aliguori | return 0; |
705 | ca2c72be | aliguori | } |
706 | ca2c72be | aliguori | |
707 | ca2c72be | aliguori | static void pciej_write(void *opaque, uint32_t addr, uint32_t val) |
708 | ca2c72be | aliguori | { |
709 | 6f338c34 | aliguori | #if defined (TARGET_I386)
|
710 | ca2c72be | aliguori | int slot = ffs(val) - 1; |
711 | ca2c72be | aliguori | |
712 | 6f338c34 | aliguori | pci_device_hot_remove_success(0, slot);
|
713 | 6f338c34 | aliguori | #endif
|
714 | 6f338c34 | aliguori | |
715 | ca2c72be | aliguori | #if defined(DEBUG)
|
716 | f654d9e2 | Alex Williamson | printf("pciej write %x <== %d\n", addr, val);
|
717 | ca2c72be | aliguori | #endif
|
718 | ca2c72be | aliguori | } |
719 | ca2c72be | aliguori | |
720 | 9d5e77a2 | Isaku Yamahata | static void piix4_device_hot_add(int bus, int slot, int state); |
721 | 9d5e77a2 | Isaku Yamahata | |
722 | 9d5e77a2 | Isaku Yamahata | void piix4_acpi_system_hot_add_init(void) |
723 | 5e3cb534 | aliguori | { |
724 | 5e3cb534 | aliguori | register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe); |
725 | 5e3cb534 | aliguori | register_ioport_read(GPE_BASE, 4, 1, gpe_readb, &gpe); |
726 | 5e3cb534 | aliguori | |
727 | ca2c72be | aliguori | register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status); |
728 | ca2c72be | aliguori | register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, &pci0_status); |
729 | ca2c72be | aliguori | |
730 | ca2c72be | aliguori | register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL); |
731 | ca2c72be | aliguori | register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, NULL); |
732 | 9d5e77a2 | Isaku Yamahata | |
733 | 9d5e77a2 | Isaku Yamahata | qemu_system_device_hot_add_register(piix4_device_hot_add); |
734 | ca2c72be | aliguori | } |
735 | ca2c72be | aliguori | |
736 | ca2c72be | aliguori | static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot) |
737 | ca2c72be | aliguori | { |
738 | ca2c72be | aliguori | g->sts |= 2;
|
739 | ca2c72be | aliguori | p->up |= (1 << slot);
|
740 | ca2c72be | aliguori | } |
741 | ca2c72be | aliguori | |
742 | ca2c72be | aliguori | static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot) |
743 | ca2c72be | aliguori | { |
744 | ca2c72be | aliguori | g->sts |= 2;
|
745 | ca2c72be | aliguori | p->down |= (1 << slot);
|
746 | ca2c72be | aliguori | } |
747 | ca2c72be | aliguori | |
748 | 9d5e77a2 | Isaku Yamahata | static void piix4_device_hot_add(int bus, int slot, int state) |
749 | ca2c72be | aliguori | { |
750 | ca2c72be | aliguori | pci0_status.up = 0;
|
751 | ca2c72be | aliguori | pci0_status.down = 0;
|
752 | ca2c72be | aliguori | if (state)
|
753 | ca2c72be | aliguori | enable_device(&pci0_status, &gpe, slot); |
754 | ca2c72be | aliguori | else
|
755 | ca2c72be | aliguori | disable_device(&pci0_status, &gpe, slot); |
756 | 1f0711e2 | aliguori | if (gpe.en & 2) { |
757 | 1f0711e2 | aliguori | qemu_set_irq(pm_state->irq, 1);
|
758 | 1f0711e2 | aliguori | qemu_set_irq(pm_state->irq, 0);
|
759 | 1f0711e2 | aliguori | } |
760 | 5e3cb534 | aliguori | } |
761 | 8a92ea2f | aliguori | |
762 | 9d5e77a2 | Isaku Yamahata | static qemu_system_device_hot_add_t device_hot_add_callback;
|
763 | 9d5e77a2 | Isaku Yamahata | void qemu_system_device_hot_add_register(qemu_system_device_hot_add_t callback)
|
764 | 9d5e77a2 | Isaku Yamahata | { |
765 | 9d5e77a2 | Isaku Yamahata | device_hot_add_callback = callback; |
766 | 9d5e77a2 | Isaku Yamahata | } |
767 | 9d5e77a2 | Isaku Yamahata | |
768 | 9d5e77a2 | Isaku Yamahata | void qemu_system_device_hot_add(int pcibus, int slot, int state) |
769 | 9d5e77a2 | Isaku Yamahata | { |
770 | 9d5e77a2 | Isaku Yamahata | if (device_hot_add_callback)
|
771 | 9d5e77a2 | Isaku Yamahata | device_hot_add_callback(pcibus, slot, state); |
772 | 9d5e77a2 | Isaku Yamahata | } |
773 | 9d5e77a2 | Isaku Yamahata | |
774 | 8a92ea2f | aliguori | struct acpi_table_header
|
775 | 8a92ea2f | aliguori | { |
776 | 8a92ea2f | aliguori | char signature [4]; /* ACPI signature (4 ASCII characters) */ |
777 | 8a92ea2f | aliguori | uint32_t length; /* Length of table, in bytes, including header */
|
778 | 8a92ea2f | aliguori | uint8_t revision; /* ACPI Specification minor version # */
|
779 | 8a92ea2f | aliguori | uint8_t checksum; /* To make sum of entire table == 0 */
|
780 | 8a92ea2f | aliguori | char oem_id [6]; /* OEM identification */ |
781 | 8a92ea2f | aliguori | char oem_table_id [8]; /* OEM table identification */ |
782 | 8a92ea2f | aliguori | uint32_t oem_revision; /* OEM revision number */
|
783 | 8a92ea2f | aliguori | char asl_compiler_id [4]; /* ASL compiler vendor ID */ |
784 | 8a92ea2f | aliguori | uint32_t asl_compiler_revision; /* ASL compiler revision number */
|
785 | 8a92ea2f | aliguori | } __attribute__((packed)); |
786 | 8a92ea2f | aliguori | |
787 | 8a92ea2f | aliguori | char *acpi_tables;
|
788 | 8a92ea2f | aliguori | size_t acpi_tables_len; |
789 | 8a92ea2f | aliguori | |
790 | 8a92ea2f | aliguori | static int acpi_checksum(const uint8_t *data, int len) |
791 | 8a92ea2f | aliguori | { |
792 | 8a92ea2f | aliguori | int sum, i;
|
793 | 8a92ea2f | aliguori | sum = 0;
|
794 | 8a92ea2f | aliguori | for(i = 0; i < len; i++) |
795 | 8a92ea2f | aliguori | sum += data[i]; |
796 | 8a92ea2f | aliguori | return (-sum) & 0xff; |
797 | 8a92ea2f | aliguori | } |
798 | 8a92ea2f | aliguori | |
799 | 8a92ea2f | aliguori | int acpi_table_add(const char *t) |
800 | 8a92ea2f | aliguori | { |
801 | 8a92ea2f | aliguori | static const char *dfl_id = "QEMUQEMU"; |
802 | 8a92ea2f | aliguori | char buf[1024], *p, *f; |
803 | 8a92ea2f | aliguori | struct acpi_table_header acpi_hdr;
|
804 | 8a92ea2f | aliguori | unsigned long val; |
805 | 8a92ea2f | aliguori | size_t off; |
806 | 8a92ea2f | aliguori | |
807 | 8a92ea2f | aliguori | memset(&acpi_hdr, 0, sizeof(acpi_hdr)); |
808 | 8a92ea2f | aliguori | |
809 | 8a92ea2f | aliguori | if (get_param_value(buf, sizeof(buf), "sig", t)) { |
810 | 8a92ea2f | aliguori | strncpy(acpi_hdr.signature, buf, 4);
|
811 | 8a92ea2f | aliguori | } else {
|
812 | 8a92ea2f | aliguori | strncpy(acpi_hdr.signature, dfl_id, 4);
|
813 | 8a92ea2f | aliguori | } |
814 | 8a92ea2f | aliguori | if (get_param_value(buf, sizeof(buf), "rev", t)) { |
815 | 8a92ea2f | aliguori | val = strtoul(buf, &p, 10);
|
816 | 8a92ea2f | aliguori | if (val > 255 || *p != '\0') |
817 | 8a92ea2f | aliguori | goto out;
|
818 | 8a92ea2f | aliguori | } else {
|
819 | 8a92ea2f | aliguori | val = 1;
|
820 | 8a92ea2f | aliguori | } |
821 | 8a92ea2f | aliguori | acpi_hdr.revision = (int8_t)val; |
822 | 8a92ea2f | aliguori | |
823 | 8a92ea2f | aliguori | if (get_param_value(buf, sizeof(buf), "oem_id", t)) { |
824 | 8a92ea2f | aliguori | strncpy(acpi_hdr.oem_id, buf, 6);
|
825 | 8a92ea2f | aliguori | } else {
|
826 | 8a92ea2f | aliguori | strncpy(acpi_hdr.oem_id, dfl_id, 6);
|
827 | 8a92ea2f | aliguori | } |
828 | 8a92ea2f | aliguori | |
829 | 8a92ea2f | aliguori | if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) { |
830 | 8a92ea2f | aliguori | strncpy(acpi_hdr.oem_table_id, buf, 8);
|
831 | 8a92ea2f | aliguori | } else {
|
832 | 8a92ea2f | aliguori | strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
|
833 | 8a92ea2f | aliguori | } |
834 | 8a92ea2f | aliguori | |
835 | 8a92ea2f | aliguori | if (get_param_value(buf, sizeof(buf), "oem_rev", t)) { |
836 | 8a92ea2f | aliguori | val = strtol(buf, &p, 10);
|
837 | 8a92ea2f | aliguori | if(*p != '\0') |
838 | 8a92ea2f | aliguori | goto out;
|
839 | 8a92ea2f | aliguori | } else {
|
840 | 8a92ea2f | aliguori | val = 1;
|
841 | 8a92ea2f | aliguori | } |
842 | 8a92ea2f | aliguori | acpi_hdr.oem_revision = cpu_to_le32(val); |
843 | 8a92ea2f | aliguori | |
844 | 8a92ea2f | aliguori | if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) { |
845 | 8a92ea2f | aliguori | strncpy(acpi_hdr.asl_compiler_id, buf, 4);
|
846 | 8a92ea2f | aliguori | } else {
|
847 | 8a92ea2f | aliguori | strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
|
848 | 8a92ea2f | aliguori | } |
849 | 8a92ea2f | aliguori | |
850 | 8a92ea2f | aliguori | if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) { |
851 | 8a92ea2f | aliguori | val = strtol(buf, &p, 10);
|
852 | 8a92ea2f | aliguori | if(*p != '\0') |
853 | 8a92ea2f | aliguori | goto out;
|
854 | 8a92ea2f | aliguori | } else {
|
855 | 8a92ea2f | aliguori | val = 1;
|
856 | 8a92ea2f | aliguori | } |
857 | 8a92ea2f | aliguori | acpi_hdr.asl_compiler_revision = cpu_to_le32(val); |
858 | 8a92ea2f | aliguori | |
859 | 8a92ea2f | aliguori | if (!get_param_value(buf, sizeof(buf), "data", t)) { |
860 | 8a92ea2f | aliguori | buf[0] = '\0'; |
861 | 8a92ea2f | aliguori | } |
862 | 8a92ea2f | aliguori | |
863 | 8a92ea2f | aliguori | acpi_hdr.length = sizeof(acpi_hdr);
|
864 | 8a92ea2f | aliguori | |
865 | 8a92ea2f | aliguori | f = buf; |
866 | 8a92ea2f | aliguori | while (buf[0]) { |
867 | 8a92ea2f | aliguori | struct stat s;
|
868 | 54042bcf | aliguori | char *n = strchr(f, ':'); |
869 | 8a92ea2f | aliguori | if (n)
|
870 | 8a92ea2f | aliguori | *n = '\0';
|
871 | 8a92ea2f | aliguori | if(stat(f, &s) < 0) { |
872 | 8a92ea2f | aliguori | fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
|
873 | 8a92ea2f | aliguori | goto out;
|
874 | 8a92ea2f | aliguori | } |
875 | 8a92ea2f | aliguori | acpi_hdr.length += s.st_size; |
876 | 8a92ea2f | aliguori | if (!n)
|
877 | 8a92ea2f | aliguori | break;
|
878 | 8a92ea2f | aliguori | *n = ':';
|
879 | 8a92ea2f | aliguori | f = n + 1;
|
880 | 8a92ea2f | aliguori | } |
881 | 8a92ea2f | aliguori | |
882 | 8a92ea2f | aliguori | if (!acpi_tables) {
|
883 | 8a92ea2f | aliguori | acpi_tables_len = sizeof(uint16_t);
|
884 | 8a92ea2f | aliguori | acpi_tables = qemu_mallocz(acpi_tables_len); |
885 | 8a92ea2f | aliguori | } |
886 | 8a92ea2f | aliguori | p = acpi_tables + acpi_tables_len; |
887 | 8a92ea2f | aliguori | acpi_tables_len += sizeof(uint16_t) + acpi_hdr.length;
|
888 | 8a92ea2f | aliguori | acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len); |
889 | 8a92ea2f | aliguori | |
890 | 8a92ea2f | aliguori | acpi_hdr.length = cpu_to_le32(acpi_hdr.length); |
891 | 8a92ea2f | aliguori | *(uint16_t*)p = acpi_hdr.length; |
892 | 8a92ea2f | aliguori | p += sizeof(uint16_t);
|
893 | 8a92ea2f | aliguori | memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
|
894 | 8a92ea2f | aliguori | off = sizeof(acpi_hdr);
|
895 | 8a92ea2f | aliguori | |
896 | 8a92ea2f | aliguori | f = buf; |
897 | 8a92ea2f | aliguori | while (buf[0]) { |
898 | 8a92ea2f | aliguori | struct stat s;
|
899 | 8a92ea2f | aliguori | int fd;
|
900 | 54042bcf | aliguori | char *n = strchr(f, ':'); |
901 | 8a92ea2f | aliguori | if (n)
|
902 | 8a92ea2f | aliguori | *n = '\0';
|
903 | 8a92ea2f | aliguori | fd = open(f, O_RDONLY); |
904 | 8a92ea2f | aliguori | |
905 | 8a92ea2f | aliguori | if(fd < 0) |
906 | 8a92ea2f | aliguori | goto out;
|
907 | 8a92ea2f | aliguori | if(fstat(fd, &s) < 0) { |
908 | 8a92ea2f | aliguori | close(fd); |
909 | 8a92ea2f | aliguori | goto out;
|
910 | 8a92ea2f | aliguori | } |
911 | 8a92ea2f | aliguori | |
912 | 8a92ea2f | aliguori | do {
|
913 | 8a92ea2f | aliguori | int r;
|
914 | 8a92ea2f | aliguori | r = read(fd, p + off, s.st_size); |
915 | 8a92ea2f | aliguori | if (r > 0) { |
916 | 8a92ea2f | aliguori | off += r; |
917 | 8a92ea2f | aliguori | s.st_size -= r; |
918 | 8a92ea2f | aliguori | } else if ((r < 0 && errno != EINTR) || r == 0) { |
919 | 8a92ea2f | aliguori | close(fd); |
920 | 8a92ea2f | aliguori | goto out;
|
921 | 8a92ea2f | aliguori | } |
922 | 8a92ea2f | aliguori | } while(s.st_size);
|
923 | 8a92ea2f | aliguori | |
924 | 8a92ea2f | aliguori | close(fd); |
925 | 8a92ea2f | aliguori | if (!n)
|
926 | 8a92ea2f | aliguori | break;
|
927 | 8a92ea2f | aliguori | f = n + 1;
|
928 | 8a92ea2f | aliguori | } |
929 | 8a92ea2f | aliguori | |
930 | 8a92ea2f | aliguori | ((struct acpi_table_header*)p)->checksum = acpi_checksum((uint8_t*)p, off);
|
931 | 8a92ea2f | aliguori | /* increase number of tables */
|
932 | 8a92ea2f | aliguori | (*(uint16_t*)acpi_tables) = |
933 | 8a92ea2f | aliguori | cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
|
934 | 8a92ea2f | aliguori | return 0; |
935 | 8a92ea2f | aliguori | out:
|
936 | 8a92ea2f | aliguori | if (acpi_tables) {
|
937 | 8a92ea2f | aliguori | free(acpi_tables); |
938 | 8a92ea2f | aliguori | acpi_tables = NULL;
|
939 | 8a92ea2f | aliguori | } |
940 | 8a92ea2f | aliguori | return -1; |
941 | 8a92ea2f | aliguori | } |