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/*
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* ACPI implementation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License version 2 as published by the Free Software Foundation.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "pci.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "i2c.h" |
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#include "smbus.h" |
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#include "kvm.h" |
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//#define DEBUG
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/* i82731AB (PIIX4) compatible power management function */
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#define PM_FREQ 3579545 |
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|
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#define ACPI_DBG_IO_ADDR 0xb044 |
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typedef struct PIIX4PMState { |
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PCIDevice dev; |
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uint16_t pmsts; |
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uint16_t pmen; |
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uint16_t pmcntrl; |
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uint8_t apmc; |
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uint8_t apms; |
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QEMUTimer *tmr_timer; |
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int64_t tmr_overflow_time; |
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i2c_bus *smbus; |
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uint8_t smb_stat; |
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uint8_t smb_ctl; |
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uint8_t smb_cmd; |
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uint8_t smb_addr; |
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uint8_t smb_data0; |
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uint8_t smb_data1; |
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uint8_t smb_data[32];
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uint8_t smb_index; |
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qemu_irq irq; |
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} PIIX4PMState; |
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#define RSM_STS (1 << 15) |
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#define PWRBTN_STS (1 << 8) |
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#define RTC_EN (1 << 10) |
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#define PWRBTN_EN (1 << 8) |
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#define GBL_EN (1 << 5) |
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#define TMROF_EN (1 << 0) |
61 |
|
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#define SCI_EN (1 << 0) |
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#define SUS_EN (1 << 13) |
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#define ACPI_ENABLE 0xf1 |
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#define ACPI_DISABLE 0xf0 |
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#define SMBHSTSTS 0x00 |
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#define SMBHSTCNT 0x02 |
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#define SMBHSTCMD 0x03 |
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#define SMBHSTADD 0x04 |
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#define SMBHSTDAT0 0x05 |
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#define SMBHSTDAT1 0x06 |
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#define SMBBLKDAT 0x07 |
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static PIIX4PMState *pm_state;
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|
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static uint32_t get_pmtmr(PIIX4PMState *s)
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{ |
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uint32_t d; |
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
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return d & 0xffffff; |
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} |
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static int get_pmsts(PIIX4PMState *s) |
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{ |
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int64_t d; |
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int pmsts;
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pmsts = s->pmsts; |
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
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if (d >= s->tmr_overflow_time)
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s->pmsts |= TMROF_EN; |
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return s->pmsts;
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} |
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static void pm_update_sci(PIIX4PMState *s) |
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{ |
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int sci_level, pmsts;
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int64_t expire_time; |
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pmsts = get_pmsts(s); |
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sci_level = (((pmsts & s->pmen) & |
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(RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
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qemu_set_irq(s->irq, sci_level); |
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/* schedule a timer interruption if needed */
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if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
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expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ); |
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qemu_mod_timer(s->tmr_timer, expire_time); |
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} else {
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qemu_del_timer(s->tmr_timer); |
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} |
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} |
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static void pm_tmr_timer(void *opaque) |
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{ |
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PIIX4PMState *s = opaque; |
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pm_update_sci(s); |
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} |
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|
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static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PIIX4PMState *s = opaque; |
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addr &= 0x3f;
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switch(addr) {
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case 0x00: |
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{ |
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int64_t d; |
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int pmsts;
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pmsts = get_pmsts(s); |
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if (pmsts & val & TMROF_EN) {
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/* if TMRSTS is reset, then compute the new overflow time */
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d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec); |
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s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL; |
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} |
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s->pmsts &= ~val; |
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pm_update_sci(s); |
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} |
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break;
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case 0x02: |
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s->pmen = val; |
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pm_update_sci(s); |
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break;
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case 0x04: |
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{ |
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int sus_typ;
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s->pmcntrl = val & ~(SUS_EN); |
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if (val & SUS_EN) {
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/* change suspend type */
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sus_typ = (val >> 10) & 7; |
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switch(sus_typ) {
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case 0: /* soft power off */ |
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qemu_system_shutdown_request(); |
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break;
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case 1: |
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/* RSM_STS should be set on resume. Pretend that resume
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was caused by power button */
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s->pmsts |= (RSM_STS | PWRBTN_STS); |
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qemu_system_reset_request(); |
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#if defined(TARGET_I386)
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cmos_set_s3_resume(); |
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#endif
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default:
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break;
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} |
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} |
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} |
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break;
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default:
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break;
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} |
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#ifdef DEBUG
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printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
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#endif
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} |
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static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) |
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{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
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addr &= 0x3f;
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switch(addr) {
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case 0x00: |
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val = get_pmsts(s); |
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break;
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case 0x02: |
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val = s->pmen; |
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break;
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case 0x04: |
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val = s->pmcntrl; |
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break;
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default:
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val = 0;
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break;
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} |
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#ifdef DEBUG
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printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
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#endif
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return val;
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} |
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static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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// PIIX4PMState *s = opaque;
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addr &= 0x3f;
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#ifdef DEBUG
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printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
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#endif
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} |
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static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) |
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{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
216 |
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addr &= 0x3f;
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switch(addr) {
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case 0x08: |
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val = get_pmtmr(s); |
221 |
break;
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default:
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val = 0;
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break;
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} |
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#ifdef DEBUG
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printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
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#endif
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return val;
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} |
231 |
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static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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PIIX4PMState *s = opaque; |
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addr &= 1;
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#ifdef DEBUG
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printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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if (addr == 0) { |
240 |
s->apmc = val; |
241 |
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/* ACPI specs 3.0, 4.7.2.5 */
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if (val == ACPI_ENABLE) {
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s->pmcntrl |= SCI_EN; |
245 |
} else if (val == ACPI_DISABLE) { |
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s->pmcntrl &= ~SCI_EN; |
247 |
} |
248 |
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if (s->dev.config[0x5b] & (1 << 1)) { |
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cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); |
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} |
252 |
} else {
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s->apms = val; |
254 |
} |
255 |
} |
256 |
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static uint32_t pm_smi_readb(void *opaque, uint32_t addr) |
258 |
{ |
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PIIX4PMState *s = opaque; |
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uint32_t val; |
261 |
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addr &= 1;
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if (addr == 0) { |
264 |
val = s->apmc; |
265 |
} else {
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val = s->apms; |
267 |
} |
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#ifdef DEBUG
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printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
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#endif
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return val;
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} |
273 |
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static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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#if defined(DEBUG)
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printf("ACPI: DBG: 0x%08x\n", val);
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#endif
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} |
280 |
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static void smb_transaction(PIIX4PMState *s) |
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{ |
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uint8_t prot = (s->smb_ctl >> 2) & 0x07; |
284 |
uint8_t read = s->smb_addr & 0x01;
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uint8_t cmd = s->smb_cmd; |
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uint8_t addr = s->smb_addr >> 1;
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i2c_bus *bus = s->smbus; |
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#ifdef DEBUG
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printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
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#endif
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switch(prot) {
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case 0x0: |
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smbus_quick_command(bus, addr, read); |
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break;
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case 0x1: |
297 |
if (read) {
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s->smb_data0 = smbus_receive_byte(bus, addr); |
299 |
} else {
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smbus_send_byte(bus, addr, cmd); |
301 |
} |
302 |
break;
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case 0x2: |
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if (read) {
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s->smb_data0 = smbus_read_byte(bus, addr, cmd); |
306 |
} else {
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smbus_write_byte(bus, addr, cmd, s->smb_data0); |
308 |
} |
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break;
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case 0x3: |
311 |
if (read) {
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uint16_t val; |
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val = smbus_read_word(bus, addr, cmd); |
314 |
s->smb_data0 = val; |
315 |
s->smb_data1 = val >> 8;
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} else {
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smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
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} |
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break;
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case 0x5: |
321 |
if (read) {
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s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data); |
323 |
} else {
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smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0); |
325 |
} |
326 |
break;
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327 |
default:
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328 |
goto error;
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329 |
} |
330 |
return;
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331 |
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332 |
error:
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s->smb_stat |= 0x04;
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} |
335 |
|
336 |
static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
337 |
{ |
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PIIX4PMState *s = opaque; |
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addr &= 0x3f;
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#ifdef DEBUG
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printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
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#endif
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switch(addr) {
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344 |
case SMBHSTSTS:
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s->smb_stat = 0;
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346 |
s->smb_index = 0;
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347 |
break;
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348 |
case SMBHSTCNT:
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349 |
s->smb_ctl = val; |
350 |
if (val & 0x40) |
351 |
smb_transaction(s); |
352 |
break;
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353 |
case SMBHSTCMD:
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354 |
s->smb_cmd = val; |
355 |
break;
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356 |
case SMBHSTADD:
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357 |
s->smb_addr = val; |
358 |
break;
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359 |
case SMBHSTDAT0:
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360 |
s->smb_data0 = val; |
361 |
break;
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362 |
case SMBHSTDAT1:
|
363 |
s->smb_data1 = val; |
364 |
break;
|
365 |
case SMBBLKDAT:
|
366 |
s->smb_data[s->smb_index++] = val; |
367 |
if (s->smb_index > 31) |
368 |
s->smb_index = 0;
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369 |
break;
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370 |
default:
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371 |
break;
|
372 |
} |
373 |
} |
374 |
|
375 |
static uint32_t smb_ioport_readb(void *opaque, uint32_t addr) |
376 |
{ |
377 |
PIIX4PMState *s = opaque; |
378 |
uint32_t val; |
379 |
|
380 |
addr &= 0x3f;
|
381 |
switch(addr) {
|
382 |
case SMBHSTSTS:
|
383 |
val = s->smb_stat; |
384 |
break;
|
385 |
case SMBHSTCNT:
|
386 |
s->smb_index = 0;
|
387 |
val = s->smb_ctl & 0x1f;
|
388 |
break;
|
389 |
case SMBHSTCMD:
|
390 |
val = s->smb_cmd; |
391 |
break;
|
392 |
case SMBHSTADD:
|
393 |
val = s->smb_addr; |
394 |
break;
|
395 |
case SMBHSTDAT0:
|
396 |
val = s->smb_data0; |
397 |
break;
|
398 |
case SMBHSTDAT1:
|
399 |
val = s->smb_data1; |
400 |
break;
|
401 |
case SMBBLKDAT:
|
402 |
val = s->smb_data[s->smb_index++]; |
403 |
if (s->smb_index > 31) |
404 |
s->smb_index = 0;
|
405 |
break;
|
406 |
default:
|
407 |
val = 0;
|
408 |
break;
|
409 |
} |
410 |
#ifdef DEBUG
|
411 |
printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
|
412 |
#endif
|
413 |
return val;
|
414 |
} |
415 |
|
416 |
static void pm_io_space_update(PIIX4PMState *s) |
417 |
{ |
418 |
uint32_t pm_io_base; |
419 |
|
420 |
if (s->dev.config[0x80] & 1) { |
421 |
pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
|
422 |
pm_io_base &= 0xffc0;
|
423 |
|
424 |
/* XXX: need to improve memory and ioport allocation */
|
425 |
#if defined(DEBUG)
|
426 |
printf("PM: mapping to 0x%x\n", pm_io_base);
|
427 |
#endif
|
428 |
register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); |
429 |
register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); |
430 |
register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); |
431 |
register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); |
432 |
} |
433 |
} |
434 |
|
435 |
static void pm_write_config(PCIDevice *d, |
436 |
uint32_t address, uint32_t val, int len)
|
437 |
{ |
438 |
pci_default_write_config(d, address, val, len); |
439 |
if (address == 0x80) |
440 |
pm_io_space_update((PIIX4PMState *)d); |
441 |
} |
442 |
|
443 |
static void pm_save(QEMUFile* f,void *opaque) |
444 |
{ |
445 |
PIIX4PMState *s = opaque; |
446 |
|
447 |
pci_device_save(&s->dev, f); |
448 |
|
449 |
qemu_put_be16s(f, &s->pmsts); |
450 |
qemu_put_be16s(f, &s->pmen); |
451 |
qemu_put_be16s(f, &s->pmcntrl); |
452 |
qemu_put_8s(f, &s->apmc); |
453 |
qemu_put_8s(f, &s->apms); |
454 |
qemu_put_timer(f, s->tmr_timer); |
455 |
qemu_put_be64(f, s->tmr_overflow_time); |
456 |
} |
457 |
|
458 |
static int pm_load(QEMUFile* f,void* opaque,int version_id) |
459 |
{ |
460 |
PIIX4PMState *s = opaque; |
461 |
int ret;
|
462 |
|
463 |
if (version_id > 1) |
464 |
return -EINVAL;
|
465 |
|
466 |
ret = pci_device_load(&s->dev, f); |
467 |
if (ret < 0) |
468 |
return ret;
|
469 |
|
470 |
qemu_get_be16s(f, &s->pmsts); |
471 |
qemu_get_be16s(f, &s->pmen); |
472 |
qemu_get_be16s(f, &s->pmcntrl); |
473 |
qemu_get_8s(f, &s->apmc); |
474 |
qemu_get_8s(f, &s->apms); |
475 |
qemu_get_timer(f, s->tmr_timer); |
476 |
s->tmr_overflow_time=qemu_get_be64(f); |
477 |
|
478 |
pm_io_space_update(s); |
479 |
|
480 |
return 0; |
481 |
} |
482 |
|
483 |
static void piix4_reset(void *opaque) |
484 |
{ |
485 |
PIIX4PMState *s = opaque; |
486 |
uint8_t *pci_conf = s->dev.config; |
487 |
|
488 |
pci_conf[0x58] = 0; |
489 |
pci_conf[0x59] = 0; |
490 |
pci_conf[0x5a] = 0; |
491 |
pci_conf[0x5b] = 0; |
492 |
|
493 |
if (kvm_enabled()) {
|
494 |
/* Mark SMM as already inited (until KVM supports SMM). */
|
495 |
pci_conf[0x5B] = 0x02; |
496 |
} |
497 |
} |
498 |
|
499 |
static void piix4_powerdown(void *opaque, int irq, int power_failing) |
500 |
{ |
501 |
#if defined(TARGET_I386)
|
502 |
PIIX4PMState *s = opaque; |
503 |
|
504 |
if (!s) {
|
505 |
qemu_system_shutdown_request(); |
506 |
} else if (s->pmen & PWRBTN_EN) { |
507 |
s->pmsts |= PWRBTN_EN; |
508 |
pm_update_sci(s); |
509 |
} |
510 |
#endif
|
511 |
} |
512 |
|
513 |
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
514 |
qemu_irq sci_irq) |
515 |
{ |
516 |
PIIX4PMState *s; |
517 |
uint8_t *pci_conf; |
518 |
|
519 |
s = (PIIX4PMState *)pci_register_device(bus, |
520 |
"PM", sizeof(PIIX4PMState), |
521 |
devfn, NULL, pm_write_config);
|
522 |
pm_state = s; |
523 |
pci_conf = s->dev.config; |
524 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
525 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3); |
526 |
pci_conf[0x06] = 0x80; |
527 |
pci_conf[0x07] = 0x02; |
528 |
pci_conf[0x08] = 0x03; // revision number |
529 |
pci_conf[0x09] = 0x00; |
530 |
pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); |
531 |
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
532 |
pci_conf[0x3d] = 0x01; // interrupt pin 1 |
533 |
|
534 |
pci_conf[0x40] = 0x01; /* PM io base read only bit */ |
535 |
|
536 |
register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s); |
537 |
register_ioport_read(0xb2, 2, 1, pm_smi_readb, s); |
538 |
|
539 |
register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); |
540 |
|
541 |
if (kvm_enabled()) {
|
542 |
/* Mark SMM as already inited to prevent SMM from running. KVM does not
|
543 |
* support SMM mode. */
|
544 |
pci_conf[0x5B] = 0x02; |
545 |
} |
546 |
|
547 |
/* XXX: which specification is used ? The i82731AB has different
|
548 |
mappings */
|
549 |
pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10; |
550 |
pci_conf[0x63] = 0x60; |
551 |
pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) | |
552 |
(serial_hds[1] != NULL ? 0x90 : 0); |
553 |
|
554 |
pci_conf[0x90] = smb_io_base | 1; |
555 |
pci_conf[0x91] = smb_io_base >> 8; |
556 |
pci_conf[0xd2] = 0x09; |
557 |
register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s); |
558 |
register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s); |
559 |
|
560 |
s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); |
561 |
|
562 |
qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
|
563 |
|
564 |
register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s); |
565 |
|
566 |
s->smbus = i2c_init_bus(NULL, "i2c"); |
567 |
s->irq = sci_irq; |
568 |
qemu_register_reset(piix4_reset, s); |
569 |
|
570 |
return s->smbus;
|
571 |
} |
572 |
|
573 |
#define GPE_BASE 0xafe0 |
574 |
#define PCI_BASE 0xae00 |
575 |
#define PCI_EJ_BASE 0xae08 |
576 |
|
577 |
struct gpe_regs {
|
578 |
uint16_t sts; /* status */
|
579 |
uint16_t en; /* enabled */
|
580 |
}; |
581 |
|
582 |
struct pci_status {
|
583 |
uint32_t up; |
584 |
uint32_t down; |
585 |
}; |
586 |
|
587 |
static struct gpe_regs gpe; |
588 |
static struct pci_status pci0_status; |
589 |
|
590 |
static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
|
591 |
{ |
592 |
if (addr & 1) |
593 |
return (val >> 8) & 0xff; |
594 |
return val & 0xff; |
595 |
} |
596 |
|
597 |
static uint32_t gpe_readb(void *opaque, uint32_t addr) |
598 |
{ |
599 |
uint32_t val = 0;
|
600 |
struct gpe_regs *g = opaque;
|
601 |
switch (addr) {
|
602 |
case GPE_BASE:
|
603 |
case GPE_BASE + 1: |
604 |
val = gpe_read_val(g->sts, addr); |
605 |
break;
|
606 |
case GPE_BASE + 2: |
607 |
case GPE_BASE + 3: |
608 |
val = gpe_read_val(g->en, addr); |
609 |
break;
|
610 |
default:
|
611 |
break;
|
612 |
} |
613 |
|
614 |
#if defined(DEBUG)
|
615 |
printf("gpe read %x == %x\n", addr, val);
|
616 |
#endif
|
617 |
return val;
|
618 |
} |
619 |
|
620 |
static void gpe_write_val(uint16_t *cur, int addr, uint32_t val) |
621 |
{ |
622 |
if (addr & 1) |
623 |
*cur = (*cur & 0xff) | (val << 8); |
624 |
else
|
625 |
*cur = (*cur & 0xff00) | (val & 0xff); |
626 |
} |
627 |
|
628 |
static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val) |
629 |
{ |
630 |
uint16_t x1, x0 = val & 0xff;
|
631 |
int shift = (addr & 1) ? 8 : 0; |
632 |
|
633 |
x1 = (*cur >> shift) & 0xff;
|
634 |
|
635 |
x1 = x1 & ~x0; |
636 |
|
637 |
*cur = (*cur & (0xff << (8 - shift))) | (x1 << shift); |
638 |
} |
639 |
|
640 |
static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val) |
641 |
{ |
642 |
struct gpe_regs *g = opaque;
|
643 |
switch (addr) {
|
644 |
case GPE_BASE:
|
645 |
case GPE_BASE + 1: |
646 |
gpe_reset_val(&g->sts, addr, val); |
647 |
break;
|
648 |
case GPE_BASE + 2: |
649 |
case GPE_BASE + 3: |
650 |
gpe_write_val(&g->en, addr, val); |
651 |
break;
|
652 |
default:
|
653 |
break;
|
654 |
} |
655 |
|
656 |
#if defined(DEBUG)
|
657 |
printf("gpe write %x <== %d\n", addr, val);
|
658 |
#endif
|
659 |
} |
660 |
|
661 |
static uint32_t pcihotplug_read(void *opaque, uint32_t addr) |
662 |
{ |
663 |
uint32_t val = 0;
|
664 |
struct pci_status *g = opaque;
|
665 |
switch (addr) {
|
666 |
case PCI_BASE:
|
667 |
val = g->up; |
668 |
break;
|
669 |
case PCI_BASE + 4: |
670 |
val = g->down; |
671 |
break;
|
672 |
default:
|
673 |
break;
|
674 |
} |
675 |
|
676 |
#if defined(DEBUG)
|
677 |
printf("pcihotplug read %x == %x\n", addr, val);
|
678 |
#endif
|
679 |
return val;
|
680 |
} |
681 |
|
682 |
static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val) |
683 |
{ |
684 |
struct pci_status *g = opaque;
|
685 |
switch (addr) {
|
686 |
case PCI_BASE:
|
687 |
g->up = val; |
688 |
break;
|
689 |
case PCI_BASE + 4: |
690 |
g->down = val; |
691 |
break;
|
692 |
} |
693 |
|
694 |
#if defined(DEBUG)
|
695 |
printf("pcihotplug write %x <== %d\n", addr, val);
|
696 |
#endif
|
697 |
} |
698 |
|
699 |
static uint32_t pciej_read(void *opaque, uint32_t addr) |
700 |
{ |
701 |
#if defined(DEBUG)
|
702 |
printf("pciej read %x\n", addr);
|
703 |
#endif
|
704 |
return 0; |
705 |
} |
706 |
|
707 |
static void pciej_write(void *opaque, uint32_t addr, uint32_t val) |
708 |
{ |
709 |
#if defined (TARGET_I386)
|
710 |
int slot = ffs(val) - 1; |
711 |
|
712 |
pci_device_hot_remove_success(0, slot);
|
713 |
#endif
|
714 |
|
715 |
#if defined(DEBUG)
|
716 |
printf("pciej write %x <== %d\n", addr, val);
|
717 |
#endif
|
718 |
} |
719 |
|
720 |
static void piix4_device_hot_add(int bus, int slot, int state); |
721 |
|
722 |
void piix4_acpi_system_hot_add_init(void) |
723 |
{ |
724 |
register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe); |
725 |
register_ioport_read(GPE_BASE, 4, 1, gpe_readb, &gpe); |
726 |
|
727 |
register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status); |
728 |
register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, &pci0_status); |
729 |
|
730 |
register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL); |
731 |
register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, NULL); |
732 |
|
733 |
qemu_system_device_hot_add_register(piix4_device_hot_add); |
734 |
} |
735 |
|
736 |
static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot) |
737 |
{ |
738 |
g->sts |= 2;
|
739 |
p->up |= (1 << slot);
|
740 |
} |
741 |
|
742 |
static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot) |
743 |
{ |
744 |
g->sts |= 2;
|
745 |
p->down |= (1 << slot);
|
746 |
} |
747 |
|
748 |
static void piix4_device_hot_add(int bus, int slot, int state) |
749 |
{ |
750 |
pci0_status.up = 0;
|
751 |
pci0_status.down = 0;
|
752 |
if (state)
|
753 |
enable_device(&pci0_status, &gpe, slot); |
754 |
else
|
755 |
disable_device(&pci0_status, &gpe, slot); |
756 |
if (gpe.en & 2) { |
757 |
qemu_set_irq(pm_state->irq, 1);
|
758 |
qemu_set_irq(pm_state->irq, 0);
|
759 |
} |
760 |
} |
761 |
|
762 |
static qemu_system_device_hot_add_t device_hot_add_callback;
|
763 |
void qemu_system_device_hot_add_register(qemu_system_device_hot_add_t callback)
|
764 |
{ |
765 |
device_hot_add_callback = callback; |
766 |
} |
767 |
|
768 |
void qemu_system_device_hot_add(int pcibus, int slot, int state) |
769 |
{ |
770 |
if (device_hot_add_callback)
|
771 |
device_hot_add_callback(pcibus, slot, state); |
772 |
} |
773 |
|
774 |
struct acpi_table_header
|
775 |
{ |
776 |
char signature [4]; /* ACPI signature (4 ASCII characters) */ |
777 |
uint32_t length; /* Length of table, in bytes, including header */
|
778 |
uint8_t revision; /* ACPI Specification minor version # */
|
779 |
uint8_t checksum; /* To make sum of entire table == 0 */
|
780 |
char oem_id [6]; /* OEM identification */ |
781 |
char oem_table_id [8]; /* OEM table identification */ |
782 |
uint32_t oem_revision; /* OEM revision number */
|
783 |
char asl_compiler_id [4]; /* ASL compiler vendor ID */ |
784 |
uint32_t asl_compiler_revision; /* ASL compiler revision number */
|
785 |
} __attribute__((packed)); |
786 |
|
787 |
char *acpi_tables;
|
788 |
size_t acpi_tables_len; |
789 |
|
790 |
static int acpi_checksum(const uint8_t *data, int len) |
791 |
{ |
792 |
int sum, i;
|
793 |
sum = 0;
|
794 |
for(i = 0; i < len; i++) |
795 |
sum += data[i]; |
796 |
return (-sum) & 0xff; |
797 |
} |
798 |
|
799 |
int acpi_table_add(const char *t) |
800 |
{ |
801 |
static const char *dfl_id = "QEMUQEMU"; |
802 |
char buf[1024], *p, *f; |
803 |
struct acpi_table_header acpi_hdr;
|
804 |
unsigned long val; |
805 |
size_t off; |
806 |
|
807 |
memset(&acpi_hdr, 0, sizeof(acpi_hdr)); |
808 |
|
809 |
if (get_param_value(buf, sizeof(buf), "sig", t)) { |
810 |
strncpy(acpi_hdr.signature, buf, 4);
|
811 |
} else {
|
812 |
strncpy(acpi_hdr.signature, dfl_id, 4);
|
813 |
} |
814 |
if (get_param_value(buf, sizeof(buf), "rev", t)) { |
815 |
val = strtoul(buf, &p, 10);
|
816 |
if (val > 255 || *p != '\0') |
817 |
goto out;
|
818 |
} else {
|
819 |
val = 1;
|
820 |
} |
821 |
acpi_hdr.revision = (int8_t)val; |
822 |
|
823 |
if (get_param_value(buf, sizeof(buf), "oem_id", t)) { |
824 |
strncpy(acpi_hdr.oem_id, buf, 6);
|
825 |
} else {
|
826 |
strncpy(acpi_hdr.oem_id, dfl_id, 6);
|
827 |
} |
828 |
|
829 |
if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) { |
830 |
strncpy(acpi_hdr.oem_table_id, buf, 8);
|
831 |
} else {
|
832 |
strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
|
833 |
} |
834 |
|
835 |
if (get_param_value(buf, sizeof(buf), "oem_rev", t)) { |
836 |
val = strtol(buf, &p, 10);
|
837 |
if(*p != '\0') |
838 |
goto out;
|
839 |
} else {
|
840 |
val = 1;
|
841 |
} |
842 |
acpi_hdr.oem_revision = cpu_to_le32(val); |
843 |
|
844 |
if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) { |
845 |
strncpy(acpi_hdr.asl_compiler_id, buf, 4);
|
846 |
} else {
|
847 |
strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
|
848 |
} |
849 |
|
850 |
if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) { |
851 |
val = strtol(buf, &p, 10);
|
852 |
if(*p != '\0') |
853 |
goto out;
|
854 |
} else {
|
855 |
val = 1;
|
856 |
} |
857 |
acpi_hdr.asl_compiler_revision = cpu_to_le32(val); |
858 |
|
859 |
if (!get_param_value(buf, sizeof(buf), "data", t)) { |
860 |
buf[0] = '\0'; |
861 |
} |
862 |
|
863 |
acpi_hdr.length = sizeof(acpi_hdr);
|
864 |
|
865 |
f = buf; |
866 |
while (buf[0]) { |
867 |
struct stat s;
|
868 |
char *n = strchr(f, ':'); |
869 |
if (n)
|
870 |
*n = '\0';
|
871 |
if(stat(f, &s) < 0) { |
872 |
fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
|
873 |
goto out;
|
874 |
} |
875 |
acpi_hdr.length += s.st_size; |
876 |
if (!n)
|
877 |
break;
|
878 |
*n = ':';
|
879 |
f = n + 1;
|
880 |
} |
881 |
|
882 |
if (!acpi_tables) {
|
883 |
acpi_tables_len = sizeof(uint16_t);
|
884 |
acpi_tables = qemu_mallocz(acpi_tables_len); |
885 |
} |
886 |
p = acpi_tables + acpi_tables_len; |
887 |
acpi_tables_len += sizeof(uint16_t) + acpi_hdr.length;
|
888 |
acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len); |
889 |
|
890 |
acpi_hdr.length = cpu_to_le32(acpi_hdr.length); |
891 |
*(uint16_t*)p = acpi_hdr.length; |
892 |
p += sizeof(uint16_t);
|
893 |
memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
|
894 |
off = sizeof(acpi_hdr);
|
895 |
|
896 |
f = buf; |
897 |
while (buf[0]) { |
898 |
struct stat s;
|
899 |
int fd;
|
900 |
char *n = strchr(f, ':'); |
901 |
if (n)
|
902 |
*n = '\0';
|
903 |
fd = open(f, O_RDONLY); |
904 |
|
905 |
if(fd < 0) |
906 |
goto out;
|
907 |
if(fstat(fd, &s) < 0) { |
908 |
close(fd); |
909 |
goto out;
|
910 |
} |
911 |
|
912 |
do {
|
913 |
int r;
|
914 |
r = read(fd, p + off, s.st_size); |
915 |
if (r > 0) { |
916 |
off += r; |
917 |
s.st_size -= r; |
918 |
} else if ((r < 0 && errno != EINTR) || r == 0) { |
919 |
close(fd); |
920 |
goto out;
|
921 |
} |
922 |
} while(s.st_size);
|
923 |
|
924 |
close(fd); |
925 |
if (!n)
|
926 |
break;
|
927 |
f = n + 1;
|
928 |
} |
929 |
|
930 |
((struct acpi_table_header*)p)->checksum = acpi_checksum((uint8_t*)p, off);
|
931 |
/* increase number of tables */
|
932 |
(*(uint16_t*)acpi_tables) = |
933 |
cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
|
934 |
return 0; |
935 |
out:
|
936 |
if (acpi_tables) {
|
937 |
free(acpi_tables); |
938 |
acpi_tables = NULL;
|
939 |
} |
940 |
return -1; |
941 |
} |