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1 | a541f297 | bellard | /*
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2 | e9df014c | j_mayer | * QEMU generic PowerPC hardware System Emulator
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "ppc.h" |
26 | 87ecb68b | pbrook | #include "qemu-timer.h" |
27 | 87ecb68b | pbrook | #include "sysemu.h" |
28 | 87ecb68b | pbrook | #include "nvram.h" |
29 | 3b3fb322 | blueswir1 | #include "qemu-log.h" |
30 | a541f297 | bellard | |
31 | e9df014c | j_mayer | //#define PPC_DEBUG_IRQ
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32 | 4b6d0a4c | j_mayer | //#define PPC_DEBUG_TB
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33 | e9df014c | j_mayer | |
34 | d12d51d5 | aliguori | #ifdef PPC_DEBUG_IRQ
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35 | 93fcfe39 | aliguori | # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) |
36 | d12d51d5 | aliguori | #else
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37 | d12d51d5 | aliguori | # define LOG_IRQ(...) do { } while (0) |
38 | d12d51d5 | aliguori | #endif
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39 | d12d51d5 | aliguori | |
40 | d12d51d5 | aliguori | |
41 | d12d51d5 | aliguori | #ifdef PPC_DEBUG_TB
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42 | 93fcfe39 | aliguori | # define LOG_TB(...) qemu_log(__VA_ARGS__)
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43 | d12d51d5 | aliguori | #else
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44 | d12d51d5 | aliguori | # define LOG_TB(...) do { } while (0) |
45 | d12d51d5 | aliguori | #endif
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46 | d12d51d5 | aliguori | |
47 | dbdd2506 | j_mayer | static void cpu_ppc_tb_stop (CPUState *env); |
48 | dbdd2506 | j_mayer | static void cpu_ppc_tb_start (CPUState *env); |
49 | dbdd2506 | j_mayer | |
50 | 00af685f | j_mayer | static void ppc_set_irq (CPUState *env, int n_IRQ, int level) |
51 | 47103572 | j_mayer | { |
52 | 47103572 | j_mayer | if (level) {
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53 | 47103572 | j_mayer | env->pending_interrupts |= 1 << n_IRQ;
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54 | 47103572 | j_mayer | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
55 | 47103572 | j_mayer | } else {
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56 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << n_IRQ);
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57 | 47103572 | j_mayer | if (env->pending_interrupts == 0) |
58 | 47103572 | j_mayer | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
59 | 47103572 | j_mayer | } |
60 | d12d51d5 | aliguori | LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
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61 | aae9366a | j_mayer | "req %08x\n", __func__, env, n_IRQ, level,
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62 | a496775f | j_mayer | env->pending_interrupts, env->interrupt_request); |
63 | 47103572 | j_mayer | } |
64 | 47103572 | j_mayer | |
65 | e9df014c | j_mayer | /* PowerPC 6xx / 7xx internal IRQ controller */
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66 | e9df014c | j_mayer | static void ppc6xx_set_irq (void *opaque, int pin, int level) |
67 | d537cf6c | pbrook | { |
68 | e9df014c | j_mayer | CPUState *env = opaque; |
69 | e9df014c | j_mayer | int cur_level;
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70 | d537cf6c | pbrook | |
71 | d12d51d5 | aliguori | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
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72 | a496775f | j_mayer | env, pin, level); |
73 | e9df014c | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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74 | e9df014c | j_mayer | /* Don't generate spurious events */
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75 | 24be5ae3 | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
76 | e9df014c | j_mayer | switch (pin) {
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77 | dbdd2506 | j_mayer | case PPC6xx_INPUT_TBEN:
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78 | dbdd2506 | j_mayer | /* Level sensitive - active high */
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79 | d12d51d5 | aliguori | LOG_IRQ("%s: %s the time base\n",
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80 | dbdd2506 | j_mayer | __func__, level ? "start" : "stop"); |
81 | dbdd2506 | j_mayer | if (level) {
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82 | dbdd2506 | j_mayer | cpu_ppc_tb_start(env); |
83 | dbdd2506 | j_mayer | } else {
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84 | dbdd2506 | j_mayer | cpu_ppc_tb_stop(env); |
85 | dbdd2506 | j_mayer | } |
86 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_INT:
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87 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
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88 | d12d51d5 | aliguori | LOG_IRQ("%s: set the external IRQ state to %d\n",
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89 | a496775f | j_mayer | __func__, level); |
90 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
91 | e9df014c | j_mayer | break;
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92 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_SMI:
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93 | e9df014c | j_mayer | /* Level sensitive - active high */
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94 | d12d51d5 | aliguori | LOG_IRQ("%s: set the SMI IRQ state to %d\n",
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95 | a496775f | j_mayer | __func__, level); |
96 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_SMI, level); |
97 | e9df014c | j_mayer | break;
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98 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_MCP:
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99 | e9df014c | j_mayer | /* Negative edge sensitive */
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100 | e9df014c | j_mayer | /* XXX: TODO: actual reaction may depends on HID0 status
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101 | e9df014c | j_mayer | * 603/604/740/750: check HID0[EMCP]
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102 | e9df014c | j_mayer | */
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103 | e9df014c | j_mayer | if (cur_level == 1 && level == 0) { |
104 | d12d51d5 | aliguori | LOG_IRQ("%s: raise machine check state\n",
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105 | a496775f | j_mayer | __func__); |
106 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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107 | e9df014c | j_mayer | } |
108 | e9df014c | j_mayer | break;
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109 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_CKSTP_IN:
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110 | e9df014c | j_mayer | /* Level sensitive - active low */
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111 | e9df014c | j_mayer | /* XXX: TODO: relay the signal to CKSTP_OUT pin */
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112 | e63ecc6f | j_mayer | /* XXX: Note that the only way to restart the CPU is to reset it */
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113 | e9df014c | j_mayer | if (level) {
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114 | d12d51d5 | aliguori | LOG_IRQ("%s: stop the CPU\n", __func__);
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115 | e9df014c | j_mayer | env->halted = 1;
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116 | e9df014c | j_mayer | } |
117 | e9df014c | j_mayer | break;
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118 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_HRESET:
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119 | e9df014c | j_mayer | /* Level sensitive - active low */
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120 | e9df014c | j_mayer | if (level) {
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121 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the CPU\n", __func__);
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122 | ef397e88 | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
123 | ef397e88 | j_mayer | /* XXX: TOFIX */
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124 | ef397e88 | j_mayer | #if 0
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125 | ef397e88 | j_mayer | cpu_ppc_reset(env);
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126 | ef397e88 | j_mayer | #else
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127 | ef397e88 | j_mayer | qemu_system_reset_request(); |
128 | e9df014c | j_mayer | #endif
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129 | e9df014c | j_mayer | } |
130 | e9df014c | j_mayer | break;
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131 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_SRESET:
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132 | d12d51d5 | aliguori | LOG_IRQ("%s: set the RESET IRQ state to %d\n",
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133 | a496775f | j_mayer | __func__, level); |
134 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
135 | e9df014c | j_mayer | break;
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136 | e9df014c | j_mayer | default:
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137 | e9df014c | j_mayer | /* Unknown pin - do nothing */
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138 | d12d51d5 | aliguori | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
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139 | e9df014c | j_mayer | return;
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140 | e9df014c | j_mayer | } |
141 | e9df014c | j_mayer | if (level)
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142 | e9df014c | j_mayer | env->irq_input_state |= 1 << pin;
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143 | e9df014c | j_mayer | else
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144 | e9df014c | j_mayer | env->irq_input_state &= ~(1 << pin);
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145 | d537cf6c | pbrook | } |
146 | d537cf6c | pbrook | } |
147 | d537cf6c | pbrook | |
148 | e9df014c | j_mayer | void ppc6xx_irq_init (CPUState *env)
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149 | 47103572 | j_mayer | { |
150 | 7b62a955 | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env,
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151 | 7b62a955 | j_mayer | PPC6xx_INPUT_NB); |
152 | 47103572 | j_mayer | } |
153 | 47103572 | j_mayer | |
154 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
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155 | d0dfae6e | j_mayer | /* PowerPC 970 internal IRQ controller */
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156 | d0dfae6e | j_mayer | static void ppc970_set_irq (void *opaque, int pin, int level) |
157 | d0dfae6e | j_mayer | { |
158 | d0dfae6e | j_mayer | CPUState *env = opaque; |
159 | d0dfae6e | j_mayer | int cur_level;
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160 | d0dfae6e | j_mayer | |
161 | d12d51d5 | aliguori | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
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162 | d0dfae6e | j_mayer | env, pin, level); |
163 | d0dfae6e | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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164 | d0dfae6e | j_mayer | /* Don't generate spurious events */
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165 | d0dfae6e | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
166 | d0dfae6e | j_mayer | switch (pin) {
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167 | d0dfae6e | j_mayer | case PPC970_INPUT_INT:
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168 | d0dfae6e | j_mayer | /* Level sensitive - active high */
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169 | d12d51d5 | aliguori | LOG_IRQ("%s: set the external IRQ state to %d\n",
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170 | d0dfae6e | j_mayer | __func__, level); |
171 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
172 | d0dfae6e | j_mayer | break;
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173 | d0dfae6e | j_mayer | case PPC970_INPUT_THINT:
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174 | d0dfae6e | j_mayer | /* Level sensitive - active high */
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175 | d12d51d5 | aliguori | LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
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176 | d0dfae6e | j_mayer | level); |
177 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_THERM, level); |
178 | d0dfae6e | j_mayer | break;
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179 | d0dfae6e | j_mayer | case PPC970_INPUT_MCP:
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180 | d0dfae6e | j_mayer | /* Negative edge sensitive */
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181 | d0dfae6e | j_mayer | /* XXX: TODO: actual reaction may depends on HID0 status
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182 | d0dfae6e | j_mayer | * 603/604/740/750: check HID0[EMCP]
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183 | d0dfae6e | j_mayer | */
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184 | d0dfae6e | j_mayer | if (cur_level == 1 && level == 0) { |
185 | d12d51d5 | aliguori | LOG_IRQ("%s: raise machine check state\n",
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186 | d0dfae6e | j_mayer | __func__); |
187 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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188 | d0dfae6e | j_mayer | } |
189 | d0dfae6e | j_mayer | break;
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190 | d0dfae6e | j_mayer | case PPC970_INPUT_CKSTP:
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191 | d0dfae6e | j_mayer | /* Level sensitive - active low */
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192 | d0dfae6e | j_mayer | /* XXX: TODO: relay the signal to CKSTP_OUT pin */
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193 | d0dfae6e | j_mayer | if (level) {
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194 | d12d51d5 | aliguori | LOG_IRQ("%s: stop the CPU\n", __func__);
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195 | d0dfae6e | j_mayer | env->halted = 1;
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196 | d0dfae6e | j_mayer | } else {
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197 | d12d51d5 | aliguori | LOG_IRQ("%s: restart the CPU\n", __func__);
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198 | d0dfae6e | j_mayer | env->halted = 0;
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199 | d0dfae6e | j_mayer | } |
200 | d0dfae6e | j_mayer | break;
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201 | d0dfae6e | j_mayer | case PPC970_INPUT_HRESET:
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202 | d0dfae6e | j_mayer | /* Level sensitive - active low */
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203 | d0dfae6e | j_mayer | if (level) {
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204 | d0dfae6e | j_mayer | #if 0 // XXX: TOFIX
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205 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the CPU\n", __func__);
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206 | d0dfae6e | j_mayer | cpu_reset(env);
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207 | d0dfae6e | j_mayer | #endif
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208 | d0dfae6e | j_mayer | } |
209 | d0dfae6e | j_mayer | break;
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210 | d0dfae6e | j_mayer | case PPC970_INPUT_SRESET:
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211 | d12d51d5 | aliguori | LOG_IRQ("%s: set the RESET IRQ state to %d\n",
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212 | d0dfae6e | j_mayer | __func__, level); |
213 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
214 | d0dfae6e | j_mayer | break;
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215 | d0dfae6e | j_mayer | case PPC970_INPUT_TBEN:
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216 | d12d51d5 | aliguori | LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
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217 | d0dfae6e | j_mayer | level); |
218 | d0dfae6e | j_mayer | /* XXX: TODO */
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219 | d0dfae6e | j_mayer | break;
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220 | d0dfae6e | j_mayer | default:
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221 | d0dfae6e | j_mayer | /* Unknown pin - do nothing */
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222 | d12d51d5 | aliguori | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
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223 | d0dfae6e | j_mayer | return;
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224 | d0dfae6e | j_mayer | } |
225 | d0dfae6e | j_mayer | if (level)
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226 | d0dfae6e | j_mayer | env->irq_input_state |= 1 << pin;
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227 | d0dfae6e | j_mayer | else
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228 | d0dfae6e | j_mayer | env->irq_input_state &= ~(1 << pin);
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229 | d0dfae6e | j_mayer | } |
230 | d0dfae6e | j_mayer | } |
231 | d0dfae6e | j_mayer | |
232 | d0dfae6e | j_mayer | void ppc970_irq_init (CPUState *env)
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233 | d0dfae6e | j_mayer | { |
234 | 7b62a955 | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env,
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235 | 7b62a955 | j_mayer | PPC970_INPUT_NB); |
236 | d0dfae6e | j_mayer | } |
237 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
238 | d0dfae6e | j_mayer | |
239 | 4e290a0b | j_mayer | /* PowerPC 40x internal IRQ controller */
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240 | 4e290a0b | j_mayer | static void ppc40x_set_irq (void *opaque, int pin, int level) |
241 | 24be5ae3 | j_mayer | { |
242 | 24be5ae3 | j_mayer | CPUState *env = opaque; |
243 | 24be5ae3 | j_mayer | int cur_level;
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244 | 24be5ae3 | j_mayer | |
245 | d12d51d5 | aliguori | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
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246 | 8ecc7913 | j_mayer | env, pin, level); |
247 | 24be5ae3 | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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248 | 24be5ae3 | j_mayer | /* Don't generate spurious events */
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249 | 24be5ae3 | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
250 | 24be5ae3 | j_mayer | switch (pin) {
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251 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_SYS:
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252 | 8ecc7913 | j_mayer | if (level) {
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253 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the PowerPC system\n",
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254 | 8ecc7913 | j_mayer | __func__); |
255 | 8ecc7913 | j_mayer | ppc40x_system_reset(env); |
256 | 8ecc7913 | j_mayer | } |
257 | 8ecc7913 | j_mayer | break;
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258 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_CHIP:
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259 | 8ecc7913 | j_mayer | if (level) {
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260 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
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261 | 8ecc7913 | j_mayer | ppc40x_chip_reset(env); |
262 | 8ecc7913 | j_mayer | } |
263 | 8ecc7913 | j_mayer | break;
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264 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_CORE:
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265 | 24be5ae3 | j_mayer | /* XXX: TODO: update DBSR[MRR] */
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266 | 24be5ae3 | j_mayer | if (level) {
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267 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the PowerPC core\n", __func__);
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268 | 8ecc7913 | j_mayer | ppc40x_core_reset(env); |
269 | 24be5ae3 | j_mayer | } |
270 | 24be5ae3 | j_mayer | break;
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271 | 4e290a0b | j_mayer | case PPC40x_INPUT_CINT:
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272 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
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273 | d12d51d5 | aliguori | LOG_IRQ("%s: set the critical IRQ state to %d\n",
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274 | 8ecc7913 | j_mayer | __func__, level); |
275 | 4e290a0b | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); |
276 | 24be5ae3 | j_mayer | break;
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277 | 4e290a0b | j_mayer | case PPC40x_INPUT_INT:
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278 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
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279 | d12d51d5 | aliguori | LOG_IRQ("%s: set the external IRQ state to %d\n",
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280 | a496775f | j_mayer | __func__, level); |
281 | 24be5ae3 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
282 | 24be5ae3 | j_mayer | break;
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283 | 4e290a0b | j_mayer | case PPC40x_INPUT_HALT:
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284 | 24be5ae3 | j_mayer | /* Level sensitive - active low */
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285 | 24be5ae3 | j_mayer | if (level) {
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286 | d12d51d5 | aliguori | LOG_IRQ("%s: stop the CPU\n", __func__);
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287 | 24be5ae3 | j_mayer | env->halted = 1;
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288 | 24be5ae3 | j_mayer | } else {
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289 | d12d51d5 | aliguori | LOG_IRQ("%s: restart the CPU\n", __func__);
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290 | 24be5ae3 | j_mayer | env->halted = 0;
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291 | 24be5ae3 | j_mayer | } |
292 | 24be5ae3 | j_mayer | break;
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293 | 4e290a0b | j_mayer | case PPC40x_INPUT_DEBUG:
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294 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
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295 | d12d51d5 | aliguori | LOG_IRQ("%s: set the debug pin state to %d\n",
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296 | a496775f | j_mayer | __func__, level); |
297 | a750fc0b | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); |
298 | 24be5ae3 | j_mayer | break;
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299 | 24be5ae3 | j_mayer | default:
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300 | 24be5ae3 | j_mayer | /* Unknown pin - do nothing */
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301 | d12d51d5 | aliguori | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
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302 | 24be5ae3 | j_mayer | return;
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303 | 24be5ae3 | j_mayer | } |
304 | 24be5ae3 | j_mayer | if (level)
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305 | 24be5ae3 | j_mayer | env->irq_input_state |= 1 << pin;
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306 | 24be5ae3 | j_mayer | else
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307 | 24be5ae3 | j_mayer | env->irq_input_state &= ~(1 << pin);
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308 | 24be5ae3 | j_mayer | } |
309 | 24be5ae3 | j_mayer | } |
310 | 24be5ae3 | j_mayer | |
311 | 4e290a0b | j_mayer | void ppc40x_irq_init (CPUState *env)
|
312 | 24be5ae3 | j_mayer | { |
313 | 4e290a0b | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
|
314 | 4e290a0b | j_mayer | env, PPC40x_INPUT_NB); |
315 | 24be5ae3 | j_mayer | } |
316 | 24be5ae3 | j_mayer | |
317 | 9fdc60bf | aurel32 | /* PowerPC E500 internal IRQ controller */
|
318 | 9fdc60bf | aurel32 | static void ppce500_set_irq (void *opaque, int pin, int level) |
319 | 9fdc60bf | aurel32 | { |
320 | 9fdc60bf | aurel32 | CPUState *env = opaque; |
321 | 9fdc60bf | aurel32 | int cur_level;
|
322 | 9fdc60bf | aurel32 | |
323 | 9fdc60bf | aurel32 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
|
324 | 9fdc60bf | aurel32 | env, pin, level); |
325 | 9fdc60bf | aurel32 | cur_level = (env->irq_input_state >> pin) & 1;
|
326 | 9fdc60bf | aurel32 | /* Don't generate spurious events */
|
327 | 9fdc60bf | aurel32 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
328 | 9fdc60bf | aurel32 | switch (pin) {
|
329 | 9fdc60bf | aurel32 | case PPCE500_INPUT_MCK:
|
330 | 9fdc60bf | aurel32 | if (level) {
|
331 | 9fdc60bf | aurel32 | LOG_IRQ("%s: reset the PowerPC system\n",
|
332 | 9fdc60bf | aurel32 | __func__); |
333 | 9fdc60bf | aurel32 | qemu_system_reset_request(); |
334 | 9fdc60bf | aurel32 | } |
335 | 9fdc60bf | aurel32 | break;
|
336 | 9fdc60bf | aurel32 | case PPCE500_INPUT_RESET_CORE:
|
337 | 9fdc60bf | aurel32 | if (level) {
|
338 | 9fdc60bf | aurel32 | LOG_IRQ("%s: reset the PowerPC core\n", __func__);
|
339 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_MCK, level); |
340 | 9fdc60bf | aurel32 | } |
341 | 9fdc60bf | aurel32 | break;
|
342 | 9fdc60bf | aurel32 | case PPCE500_INPUT_CINT:
|
343 | 9fdc60bf | aurel32 | /* Level sensitive - active high */
|
344 | 9fdc60bf | aurel32 | LOG_IRQ("%s: set the critical IRQ state to %d\n",
|
345 | 9fdc60bf | aurel32 | __func__, level); |
346 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); |
347 | 9fdc60bf | aurel32 | break;
|
348 | 9fdc60bf | aurel32 | case PPCE500_INPUT_INT:
|
349 | 9fdc60bf | aurel32 | /* Level sensitive - active high */
|
350 | 9fdc60bf | aurel32 | LOG_IRQ("%s: set the core IRQ state to %d\n",
|
351 | 9fdc60bf | aurel32 | __func__, level); |
352 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
353 | 9fdc60bf | aurel32 | break;
|
354 | 9fdc60bf | aurel32 | case PPCE500_INPUT_DEBUG:
|
355 | 9fdc60bf | aurel32 | /* Level sensitive - active high */
|
356 | 9fdc60bf | aurel32 | LOG_IRQ("%s: set the debug pin state to %d\n",
|
357 | 9fdc60bf | aurel32 | __func__, level); |
358 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); |
359 | 9fdc60bf | aurel32 | break;
|
360 | 9fdc60bf | aurel32 | default:
|
361 | 9fdc60bf | aurel32 | /* Unknown pin - do nothing */
|
362 | 9fdc60bf | aurel32 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
|
363 | 9fdc60bf | aurel32 | return;
|
364 | 9fdc60bf | aurel32 | } |
365 | 9fdc60bf | aurel32 | if (level)
|
366 | 9fdc60bf | aurel32 | env->irq_input_state |= 1 << pin;
|
367 | 9fdc60bf | aurel32 | else
|
368 | 9fdc60bf | aurel32 | env->irq_input_state &= ~(1 << pin);
|
369 | 9fdc60bf | aurel32 | } |
370 | 9fdc60bf | aurel32 | } |
371 | 9fdc60bf | aurel32 | |
372 | 9fdc60bf | aurel32 | void ppce500_irq_init (CPUState *env)
|
373 | 9fdc60bf | aurel32 | { |
374 | 9fdc60bf | aurel32 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
|
375 | 9fdc60bf | aurel32 | env, PPCE500_INPUT_NB); |
376 | 9fdc60bf | aurel32 | } |
377 | 9fddaa0c | bellard | /*****************************************************************************/
|
378 | e9df014c | j_mayer | /* PowerPC time base and decrementer emulation */
|
379 | 9fddaa0c | bellard | struct ppc_tb_t {
|
380 | 9fddaa0c | bellard | /* Time base management */
|
381 | dbdd2506 | j_mayer | int64_t tb_offset; /* Compensation */
|
382 | dbdd2506 | j_mayer | int64_t atb_offset; /* Compensation */
|
383 | dbdd2506 | j_mayer | uint32_t tb_freq; /* TB frequency */
|
384 | 9fddaa0c | bellard | /* Decrementer management */
|
385 | dbdd2506 | j_mayer | uint64_t decr_next; /* Tick for next decr interrupt */
|
386 | dbdd2506 | j_mayer | uint32_t decr_freq; /* decrementer frequency */
|
387 | 9fddaa0c | bellard | struct QEMUTimer *decr_timer;
|
388 | 58a7d328 | j_mayer | /* Hypervisor decrementer management */
|
389 | 58a7d328 | j_mayer | uint64_t hdecr_next; /* Tick for next hdecr interrupt */
|
390 | 58a7d328 | j_mayer | struct QEMUTimer *hdecr_timer;
|
391 | 58a7d328 | j_mayer | uint64_t purr_load; |
392 | 58a7d328 | j_mayer | uint64_t purr_start; |
393 | 47103572 | j_mayer | void *opaque;
|
394 | 9fddaa0c | bellard | }; |
395 | 9fddaa0c | bellard | |
396 | 636aa200 | Blue Swirl | static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, |
397 | 636aa200 | Blue Swirl | int64_t tb_offset) |
398 | 9fddaa0c | bellard | { |
399 | 9fddaa0c | bellard | /* TB time in tb periods */
|
400 | dbdd2506 | j_mayer | return muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec) + tb_offset;
|
401 | 9fddaa0c | bellard | } |
402 | 9fddaa0c | bellard | |
403 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbl (CPUState *env) |
404 | 9fddaa0c | bellard | { |
405 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
406 | 9fddaa0c | bellard | uint64_t tb; |
407 | 9fddaa0c | bellard | |
408 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
409 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
410 | 9fddaa0c | bellard | |
411 | 9fddaa0c | bellard | return tb & 0xFFFFFFFF; |
412 | 9fddaa0c | bellard | } |
413 | 9fddaa0c | bellard | |
414 | 636aa200 | Blue Swirl | static inline uint32_t _cpu_ppc_load_tbu(CPUState *env) |
415 | 9fddaa0c | bellard | { |
416 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
417 | 9fddaa0c | bellard | uint64_t tb; |
418 | 9fddaa0c | bellard | |
419 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
420 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
421 | 76a66253 | j_mayer | |
422 | 9fddaa0c | bellard | return tb >> 32; |
423 | 9fddaa0c | bellard | } |
424 | 9fddaa0c | bellard | |
425 | 8a84de23 | j_mayer | uint32_t cpu_ppc_load_tbu (CPUState *env) |
426 | 8a84de23 | j_mayer | { |
427 | 8a84de23 | j_mayer | return _cpu_ppc_load_tbu(env);
|
428 | 8a84de23 | j_mayer | } |
429 | 8a84de23 | j_mayer | |
430 | 636aa200 | Blue Swirl | static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, |
431 | 636aa200 | Blue Swirl | int64_t *tb_offsetp, uint64_t value) |
432 | 9fddaa0c | bellard | { |
433 | dbdd2506 | j_mayer | *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec); |
434 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", |
435 | aae9366a | j_mayer | __func__, value, *tb_offsetp); |
436 | 9fddaa0c | bellard | } |
437 | 9fddaa0c | bellard | |
438 | a062e36c | j_mayer | void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
|
439 | a062e36c | j_mayer | { |
440 | a062e36c | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
441 | a062e36c | j_mayer | uint64_t tb; |
442 | a062e36c | j_mayer | |
443 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
444 | a062e36c | j_mayer | tb &= 0xFFFFFFFF00000000ULL;
|
445 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
446 | dbdd2506 | j_mayer | &tb_env->tb_offset, tb | (uint64_t)value); |
447 | a062e36c | j_mayer | } |
448 | a062e36c | j_mayer | |
449 | 636aa200 | Blue Swirl | static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value) |
450 | 9fddaa0c | bellard | { |
451 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
452 | a062e36c | j_mayer | uint64_t tb; |
453 | 9fddaa0c | bellard | |
454 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); |
455 | a062e36c | j_mayer | tb &= 0x00000000FFFFFFFFULL;
|
456 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
457 | dbdd2506 | j_mayer | &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
|
458 | 9fddaa0c | bellard | } |
459 | 9fddaa0c | bellard | |
460 | 8a84de23 | j_mayer | void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
|
461 | 8a84de23 | j_mayer | { |
462 | 8a84de23 | j_mayer | _cpu_ppc_store_tbu(env, value); |
463 | 8a84de23 | j_mayer | } |
464 | 8a84de23 | j_mayer | |
465 | a062e36c | j_mayer | uint32_t cpu_ppc_load_atbl (CPUState *env) |
466 | a062e36c | j_mayer | { |
467 | a062e36c | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
468 | a062e36c | j_mayer | uint64_t tb; |
469 | a062e36c | j_mayer | |
470 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
471 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
472 | a062e36c | j_mayer | |
473 | a062e36c | j_mayer | return tb & 0xFFFFFFFF; |
474 | a062e36c | j_mayer | } |
475 | a062e36c | j_mayer | |
476 | a062e36c | j_mayer | uint32_t cpu_ppc_load_atbu (CPUState *env) |
477 | a062e36c | j_mayer | { |
478 | a062e36c | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
479 | a062e36c | j_mayer | uint64_t tb; |
480 | a062e36c | j_mayer | |
481 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
482 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
483 | a062e36c | j_mayer | |
484 | a062e36c | j_mayer | return tb >> 32; |
485 | a062e36c | j_mayer | } |
486 | a062e36c | j_mayer | |
487 | a062e36c | j_mayer | void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
|
488 | a062e36c | j_mayer | { |
489 | a062e36c | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
490 | a062e36c | j_mayer | uint64_t tb; |
491 | a062e36c | j_mayer | |
492 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
493 | a062e36c | j_mayer | tb &= 0xFFFFFFFF00000000ULL;
|
494 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
495 | dbdd2506 | j_mayer | &tb_env->atb_offset, tb | (uint64_t)value); |
496 | a062e36c | j_mayer | } |
497 | a062e36c | j_mayer | |
498 | a062e36c | j_mayer | void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
|
499 | 9fddaa0c | bellard | { |
500 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
501 | a062e36c | j_mayer | uint64_t tb; |
502 | 9fddaa0c | bellard | |
503 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset); |
504 | a062e36c | j_mayer | tb &= 0x00000000FFFFFFFFULL;
|
505 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock), |
506 | dbdd2506 | j_mayer | &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
|
507 | dbdd2506 | j_mayer | } |
508 | dbdd2506 | j_mayer | |
509 | dbdd2506 | j_mayer | static void cpu_ppc_tb_stop (CPUState *env) |
510 | dbdd2506 | j_mayer | { |
511 | dbdd2506 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
512 | dbdd2506 | j_mayer | uint64_t tb, atb, vmclk; |
513 | dbdd2506 | j_mayer | |
514 | dbdd2506 | j_mayer | /* If the time base is already frozen, do nothing */
|
515 | dbdd2506 | j_mayer | if (tb_env->tb_freq != 0) { |
516 | dbdd2506 | j_mayer | vmclk = qemu_get_clock(vm_clock); |
517 | dbdd2506 | j_mayer | /* Get the time base */
|
518 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); |
519 | dbdd2506 | j_mayer | /* Get the alternate time base */
|
520 | dbdd2506 | j_mayer | atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); |
521 | dbdd2506 | j_mayer | /* Store the time base value (ie compute the current offset) */
|
522 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
523 | dbdd2506 | j_mayer | /* Store the alternate time base value (compute the current offset) */
|
524 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
525 | dbdd2506 | j_mayer | /* Set the time base frequency to zero */
|
526 | dbdd2506 | j_mayer | tb_env->tb_freq = 0;
|
527 | dbdd2506 | j_mayer | /* Now, the time bases are frozen to tb_offset / atb_offset value */
|
528 | dbdd2506 | j_mayer | } |
529 | dbdd2506 | j_mayer | } |
530 | dbdd2506 | j_mayer | |
531 | dbdd2506 | j_mayer | static void cpu_ppc_tb_start (CPUState *env) |
532 | dbdd2506 | j_mayer | { |
533 | dbdd2506 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
534 | dbdd2506 | j_mayer | uint64_t tb, atb, vmclk; |
535 | aae9366a | j_mayer | |
536 | dbdd2506 | j_mayer | /* If the time base is not frozen, do nothing */
|
537 | dbdd2506 | j_mayer | if (tb_env->tb_freq == 0) { |
538 | dbdd2506 | j_mayer | vmclk = qemu_get_clock(vm_clock); |
539 | dbdd2506 | j_mayer | /* Get the time base from tb_offset */
|
540 | dbdd2506 | j_mayer | tb = tb_env->tb_offset; |
541 | dbdd2506 | j_mayer | /* Get the alternate time base from atb_offset */
|
542 | dbdd2506 | j_mayer | atb = tb_env->atb_offset; |
543 | dbdd2506 | j_mayer | /* Restore the tb frequency from the decrementer frequency */
|
544 | dbdd2506 | j_mayer | tb_env->tb_freq = tb_env->decr_freq; |
545 | dbdd2506 | j_mayer | /* Store the time base value */
|
546 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
547 | dbdd2506 | j_mayer | /* Store the alternate time base value */
|
548 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
549 | dbdd2506 | j_mayer | } |
550 | 9fddaa0c | bellard | } |
551 | 9fddaa0c | bellard | |
552 | 636aa200 | Blue Swirl | static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) |
553 | 9fddaa0c | bellard | { |
554 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
555 | 9fddaa0c | bellard | uint32_t decr; |
556 | 4e588a4d | bellard | int64_t diff; |
557 | 9fddaa0c | bellard | |
558 | f55e9d9a | Tristan Gingold | diff = next - qemu_get_clock(vm_clock); |
559 | 4e588a4d | bellard | if (diff >= 0) |
560 | dbdd2506 | j_mayer | decr = muldiv64(diff, tb_env->decr_freq, ticks_per_sec); |
561 | 4e588a4d | bellard | else
|
562 | dbdd2506 | j_mayer | decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec); |
563 | d12d51d5 | aliguori | LOG_TB("%s: %08" PRIx32 "\n", __func__, decr); |
564 | 76a66253 | j_mayer | |
565 | 9fddaa0c | bellard | return decr;
|
566 | 9fddaa0c | bellard | } |
567 | 9fddaa0c | bellard | |
568 | 58a7d328 | j_mayer | uint32_t cpu_ppc_load_decr (CPUState *env) |
569 | 58a7d328 | j_mayer | { |
570 | 58a7d328 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
571 | 58a7d328 | j_mayer | |
572 | f55e9d9a | Tristan Gingold | return _cpu_ppc_load_decr(env, tb_env->decr_next);
|
573 | 58a7d328 | j_mayer | } |
574 | 58a7d328 | j_mayer | |
575 | 58a7d328 | j_mayer | uint32_t cpu_ppc_load_hdecr (CPUState *env) |
576 | 58a7d328 | j_mayer | { |
577 | 58a7d328 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
578 | 58a7d328 | j_mayer | |
579 | f55e9d9a | Tristan Gingold | return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
|
580 | 58a7d328 | j_mayer | } |
581 | 58a7d328 | j_mayer | |
582 | 58a7d328 | j_mayer | uint64_t cpu_ppc_load_purr (CPUState *env) |
583 | 58a7d328 | j_mayer | { |
584 | 58a7d328 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
585 | 58a7d328 | j_mayer | uint64_t diff; |
586 | 58a7d328 | j_mayer | |
587 | 58a7d328 | j_mayer | diff = qemu_get_clock(vm_clock) - tb_env->purr_start; |
588 | b33c17e1 | j_mayer | |
589 | 58a7d328 | j_mayer | return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec);
|
590 | 58a7d328 | j_mayer | } |
591 | 58a7d328 | j_mayer | |
592 | 9fddaa0c | bellard | /* When decrementer expires,
|
593 | 9fddaa0c | bellard | * all we need to do is generate or queue a CPU exception
|
594 | 9fddaa0c | bellard | */
|
595 | 636aa200 | Blue Swirl | static inline void cpu_ppc_decr_excp(CPUState *env) |
596 | 9fddaa0c | bellard | { |
597 | 9fddaa0c | bellard | /* Raise it */
|
598 | d12d51d5 | aliguori | LOG_TB("raise decrementer exception\n");
|
599 | 47103572 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
|
600 | 9fddaa0c | bellard | } |
601 | 9fddaa0c | bellard | |
602 | 636aa200 | Blue Swirl | static inline void cpu_ppc_hdecr_excp(CPUState *env) |
603 | 58a7d328 | j_mayer | { |
604 | 58a7d328 | j_mayer | /* Raise it */
|
605 | d12d51d5 | aliguori | LOG_TB("raise decrementer exception\n");
|
606 | 58a7d328 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
|
607 | 58a7d328 | j_mayer | } |
608 | 58a7d328 | j_mayer | |
609 | 58a7d328 | j_mayer | static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, |
610 | b33c17e1 | j_mayer | struct QEMUTimer *timer,
|
611 | b33c17e1 | j_mayer | void (*raise_excp)(CPUState *),
|
612 | b33c17e1 | j_mayer | uint32_t decr, uint32_t value, |
613 | b33c17e1 | j_mayer | int is_excp)
|
614 | 9fddaa0c | bellard | { |
615 | 9fddaa0c | bellard | ppc_tb_t *tb_env = env->tb_env; |
616 | 9fddaa0c | bellard | uint64_t now, next; |
617 | 9fddaa0c | bellard | |
618 | d12d51d5 | aliguori | LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, |
619 | aae9366a | j_mayer | decr, value); |
620 | 9fddaa0c | bellard | now = qemu_get_clock(vm_clock); |
621 | dbdd2506 | j_mayer | next = now + muldiv64(value, ticks_per_sec, tb_env->decr_freq); |
622 | 9fddaa0c | bellard | if (is_excp)
|
623 | 58a7d328 | j_mayer | next += *nextp - now; |
624 | 9fddaa0c | bellard | if (next == now)
|
625 | 76a66253 | j_mayer | next++; |
626 | 58a7d328 | j_mayer | *nextp = next; |
627 | 9fddaa0c | bellard | /* Adjust timer */
|
628 | 58a7d328 | j_mayer | qemu_mod_timer(timer, next); |
629 | 9fddaa0c | bellard | /* If we set a negative value and the decrementer was positive,
|
630 | 9fddaa0c | bellard | * raise an exception.
|
631 | 9fddaa0c | bellard | */
|
632 | 9fddaa0c | bellard | if ((value & 0x80000000) && !(decr & 0x80000000)) |
633 | 58a7d328 | j_mayer | (*raise_excp)(env); |
634 | 58a7d328 | j_mayer | } |
635 | 58a7d328 | j_mayer | |
636 | 636aa200 | Blue Swirl | static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr, |
637 | 636aa200 | Blue Swirl | uint32_t value, int is_excp)
|
638 | 58a7d328 | j_mayer | { |
639 | 58a7d328 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
640 | 58a7d328 | j_mayer | |
641 | 58a7d328 | j_mayer | __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer, |
642 | 58a7d328 | j_mayer | &cpu_ppc_decr_excp, decr, value, is_excp); |
643 | 9fddaa0c | bellard | } |
644 | 9fddaa0c | bellard | |
645 | 9fddaa0c | bellard | void cpu_ppc_store_decr (CPUState *env, uint32_t value)
|
646 | 9fddaa0c | bellard | { |
647 | 9fddaa0c | bellard | _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
|
648 | 9fddaa0c | bellard | } |
649 | 9fddaa0c | bellard | |
650 | 9fddaa0c | bellard | static void cpu_ppc_decr_cb (void *opaque) |
651 | 9fddaa0c | bellard | { |
652 | 9fddaa0c | bellard | _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
653 | 9fddaa0c | bellard | } |
654 | 9fddaa0c | bellard | |
655 | 636aa200 | Blue Swirl | static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr, |
656 | 636aa200 | Blue Swirl | uint32_t value, int is_excp)
|
657 | 58a7d328 | j_mayer | { |
658 | 58a7d328 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
659 | 58a7d328 | j_mayer | |
660 | b172c56a | j_mayer | if (tb_env->hdecr_timer != NULL) { |
661 | b172c56a | j_mayer | __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer, |
662 | b172c56a | j_mayer | &cpu_ppc_hdecr_excp, hdecr, value, is_excp); |
663 | b172c56a | j_mayer | } |
664 | 58a7d328 | j_mayer | } |
665 | 58a7d328 | j_mayer | |
666 | 58a7d328 | j_mayer | void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
|
667 | 58a7d328 | j_mayer | { |
668 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
|
669 | 58a7d328 | j_mayer | } |
670 | 58a7d328 | j_mayer | |
671 | 58a7d328 | j_mayer | static void cpu_ppc_hdecr_cb (void *opaque) |
672 | 58a7d328 | j_mayer | { |
673 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
674 | 58a7d328 | j_mayer | } |
675 | 58a7d328 | j_mayer | |
676 | 58a7d328 | j_mayer | void cpu_ppc_store_purr (CPUState *env, uint64_t value)
|
677 | 58a7d328 | j_mayer | { |
678 | 58a7d328 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
679 | 58a7d328 | j_mayer | |
680 | 58a7d328 | j_mayer | tb_env->purr_load = value; |
681 | 58a7d328 | j_mayer | tb_env->purr_start = qemu_get_clock(vm_clock); |
682 | 58a7d328 | j_mayer | } |
683 | 58a7d328 | j_mayer | |
684 | 8ecc7913 | j_mayer | static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) |
685 | 8ecc7913 | j_mayer | { |
686 | 8ecc7913 | j_mayer | CPUState *env = opaque; |
687 | 8ecc7913 | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
688 | 8ecc7913 | j_mayer | |
689 | 8ecc7913 | j_mayer | tb_env->tb_freq = freq; |
690 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
691 | 8ecc7913 | j_mayer | /* There is a bug in Linux 2.4 kernels:
|
692 | 8ecc7913 | j_mayer | * if a decrementer exception is pending when it enables msr_ee at startup,
|
693 | 8ecc7913 | j_mayer | * it's not ready to handle it...
|
694 | 8ecc7913 | j_mayer | */
|
695 | 8ecc7913 | j_mayer | _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
696 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
697 | 58a7d328 | j_mayer | cpu_ppc_store_purr(env, 0x0000000000000000ULL);
|
698 | 8ecc7913 | j_mayer | } |
699 | 8ecc7913 | j_mayer | |
700 | 9fddaa0c | bellard | /* Set up (once) timebase frequency (in Hz) */
|
701 | 8ecc7913 | j_mayer | clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) |
702 | 9fddaa0c | bellard | { |
703 | 9fddaa0c | bellard | ppc_tb_t *tb_env; |
704 | 9fddaa0c | bellard | |
705 | 9fddaa0c | bellard | tb_env = qemu_mallocz(sizeof(ppc_tb_t));
|
706 | 9fddaa0c | bellard | env->tb_env = tb_env; |
707 | 8ecc7913 | j_mayer | /* Create new timer */
|
708 | 8ecc7913 | j_mayer | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env); |
709 | b172c56a | j_mayer | if (0) { |
710 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor decrementer
|
711 | b172c56a | j_mayer | */
|
712 | b172c56a | j_mayer | tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env); |
713 | b172c56a | j_mayer | } else {
|
714 | b172c56a | j_mayer | tb_env->hdecr_timer = NULL;
|
715 | b172c56a | j_mayer | } |
716 | 8ecc7913 | j_mayer | cpu_ppc_set_tb_clk(env, freq); |
717 | 9fddaa0c | bellard | |
718 | 8ecc7913 | j_mayer | return &cpu_ppc_set_tb_clk;
|
719 | 9fddaa0c | bellard | } |
720 | 9fddaa0c | bellard | |
721 | 76a66253 | j_mayer | /* Specific helpers for POWER & PowerPC 601 RTC */
|
722 | b1d8e52e | blueswir1 | #if 0
|
723 | b1d8e52e | blueswir1 | static clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)
|
724 | 76a66253 | j_mayer | {
|
725 | 76a66253 | j_mayer | return cpu_ppc_tb_init(env, 7812500);
|
726 | 76a66253 | j_mayer | }
|
727 | b1d8e52e | blueswir1 | #endif
|
728 | 76a66253 | j_mayer | |
729 | 76a66253 | j_mayer | void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
|
730 | 8a84de23 | j_mayer | { |
731 | 8a84de23 | j_mayer | _cpu_ppc_store_tbu(env, value); |
732 | 8a84de23 | j_mayer | } |
733 | 76a66253 | j_mayer | |
734 | 76a66253 | j_mayer | uint32_t cpu_ppc601_load_rtcu (CPUState *env) |
735 | 8a84de23 | j_mayer | { |
736 | 8a84de23 | j_mayer | return _cpu_ppc_load_tbu(env);
|
737 | 8a84de23 | j_mayer | } |
738 | 76a66253 | j_mayer | |
739 | 76a66253 | j_mayer | void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
|
740 | 76a66253 | j_mayer | { |
741 | 76a66253 | j_mayer | cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
|
742 | 76a66253 | j_mayer | } |
743 | 76a66253 | j_mayer | |
744 | 76a66253 | j_mayer | uint32_t cpu_ppc601_load_rtcl (CPUState *env) |
745 | 76a66253 | j_mayer | { |
746 | 76a66253 | j_mayer | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
747 | 76a66253 | j_mayer | } |
748 | 76a66253 | j_mayer | |
749 | 636aaad7 | j_mayer | /*****************************************************************************/
|
750 | 76a66253 | j_mayer | /* Embedded PowerPC timers */
|
751 | 636aaad7 | j_mayer | |
752 | 636aaad7 | j_mayer | /* PIT, FIT & WDT */
|
753 | 636aaad7 | j_mayer | typedef struct ppcemb_timer_t ppcemb_timer_t; |
754 | 636aaad7 | j_mayer | struct ppcemb_timer_t {
|
755 | 636aaad7 | j_mayer | uint64_t pit_reload; /* PIT auto-reload value */
|
756 | 636aaad7 | j_mayer | uint64_t fit_next; /* Tick for next FIT interrupt */
|
757 | 636aaad7 | j_mayer | struct QEMUTimer *fit_timer;
|
758 | 636aaad7 | j_mayer | uint64_t wdt_next; /* Tick for next WDT interrupt */
|
759 | 636aaad7 | j_mayer | struct QEMUTimer *wdt_timer;
|
760 | 636aaad7 | j_mayer | }; |
761 | 3b46e624 | ths | |
762 | 636aaad7 | j_mayer | /* Fixed interval timer */
|
763 | 636aaad7 | j_mayer | static void cpu_4xx_fit_cb (void *opaque) |
764 | 636aaad7 | j_mayer | { |
765 | 636aaad7 | j_mayer | CPUState *env; |
766 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
767 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
768 | 636aaad7 | j_mayer | uint64_t now, next; |
769 | 636aaad7 | j_mayer | |
770 | 636aaad7 | j_mayer | env = opaque; |
771 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
772 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
773 | 636aaad7 | j_mayer | now = qemu_get_clock(vm_clock); |
774 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { |
775 | 636aaad7 | j_mayer | case 0: |
776 | 636aaad7 | j_mayer | next = 1 << 9; |
777 | 636aaad7 | j_mayer | break;
|
778 | 636aaad7 | j_mayer | case 1: |
779 | 636aaad7 | j_mayer | next = 1 << 13; |
780 | 636aaad7 | j_mayer | break;
|
781 | 636aaad7 | j_mayer | case 2: |
782 | 636aaad7 | j_mayer | next = 1 << 17; |
783 | 636aaad7 | j_mayer | break;
|
784 | 636aaad7 | j_mayer | case 3: |
785 | 636aaad7 | j_mayer | next = 1 << 21; |
786 | 636aaad7 | j_mayer | break;
|
787 | 636aaad7 | j_mayer | default:
|
788 | 636aaad7 | j_mayer | /* Cannot occur, but makes gcc happy */
|
789 | 636aaad7 | j_mayer | return;
|
790 | 636aaad7 | j_mayer | } |
791 | 636aaad7 | j_mayer | next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq); |
792 | 636aaad7 | j_mayer | if (next == now)
|
793 | 636aaad7 | j_mayer | next++; |
794 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->fit_timer, next); |
795 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 26; |
796 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) |
797 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
|
798 | 90e189ec | Blue Swirl | LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, |
799 | 90e189ec | Blue Swirl | (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), |
800 | 90e189ec | Blue Swirl | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
801 | 636aaad7 | j_mayer | } |
802 | 636aaad7 | j_mayer | |
803 | 636aaad7 | j_mayer | /* Programmable interval timer */
|
804 | 4b6d0a4c | j_mayer | static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) |
805 | 76a66253 | j_mayer | { |
806 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
807 | 636aaad7 | j_mayer | uint64_t now, next; |
808 | 636aaad7 | j_mayer | |
809 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
810 | 4b6d0a4c | j_mayer | if (ppcemb_timer->pit_reload <= 1 || |
811 | 4b6d0a4c | j_mayer | !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || |
812 | 4b6d0a4c | j_mayer | (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { |
813 | 4b6d0a4c | j_mayer | /* Stop PIT */
|
814 | d12d51d5 | aliguori | LOG_TB("%s: stop PIT\n", __func__);
|
815 | 4b6d0a4c | j_mayer | qemu_del_timer(tb_env->decr_timer); |
816 | 4b6d0a4c | j_mayer | } else {
|
817 | d12d51d5 | aliguori | LOG_TB("%s: start PIT %016" PRIx64 "\n", |
818 | 4b6d0a4c | j_mayer | __func__, ppcemb_timer->pit_reload); |
819 | 4b6d0a4c | j_mayer | now = qemu_get_clock(vm_clock); |
820 | 636aaad7 | j_mayer | next = now + muldiv64(ppcemb_timer->pit_reload, |
821 | dbdd2506 | j_mayer | ticks_per_sec, tb_env->decr_freq); |
822 | 4b6d0a4c | j_mayer | if (is_excp)
|
823 | 4b6d0a4c | j_mayer | next += tb_env->decr_next - now; |
824 | 636aaad7 | j_mayer | if (next == now)
|
825 | 636aaad7 | j_mayer | next++; |
826 | 636aaad7 | j_mayer | qemu_mod_timer(tb_env->decr_timer, next); |
827 | 636aaad7 | j_mayer | tb_env->decr_next = next; |
828 | 636aaad7 | j_mayer | } |
829 | 4b6d0a4c | j_mayer | } |
830 | 4b6d0a4c | j_mayer | |
831 | 4b6d0a4c | j_mayer | static void cpu_4xx_pit_cb (void *opaque) |
832 | 4b6d0a4c | j_mayer | { |
833 | 4b6d0a4c | j_mayer | CPUState *env; |
834 | 4b6d0a4c | j_mayer | ppc_tb_t *tb_env; |
835 | 4b6d0a4c | j_mayer | ppcemb_timer_t *ppcemb_timer; |
836 | 4b6d0a4c | j_mayer | |
837 | 4b6d0a4c | j_mayer | env = opaque; |
838 | 4b6d0a4c | j_mayer | tb_env = env->tb_env; |
839 | 4b6d0a4c | j_mayer | ppcemb_timer = tb_env->opaque; |
840 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 27; |
841 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) |
842 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
|
843 | 4b6d0a4c | j_mayer | start_stop_pit(env, tb_env, 1);
|
844 | 90e189ec | Blue Swirl | LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " " |
845 | 90e189ec | Blue Swirl | "%016" PRIx64 "\n", __func__, |
846 | 90e189ec | Blue Swirl | (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), |
847 | 90e189ec | Blue Swirl | (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), |
848 | 90e189ec | Blue Swirl | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
849 | 90e189ec | Blue Swirl | ppcemb_timer->pit_reload); |
850 | 636aaad7 | j_mayer | } |
851 | 636aaad7 | j_mayer | |
852 | 636aaad7 | j_mayer | /* Watchdog timer */
|
853 | 636aaad7 | j_mayer | static void cpu_4xx_wdt_cb (void *opaque) |
854 | 636aaad7 | j_mayer | { |
855 | 636aaad7 | j_mayer | CPUState *env; |
856 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
857 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
858 | 636aaad7 | j_mayer | uint64_t now, next; |
859 | 636aaad7 | j_mayer | |
860 | 636aaad7 | j_mayer | env = opaque; |
861 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
862 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
863 | 636aaad7 | j_mayer | now = qemu_get_clock(vm_clock); |
864 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { |
865 | 636aaad7 | j_mayer | case 0: |
866 | 636aaad7 | j_mayer | next = 1 << 17; |
867 | 636aaad7 | j_mayer | break;
|
868 | 636aaad7 | j_mayer | case 1: |
869 | 636aaad7 | j_mayer | next = 1 << 21; |
870 | 636aaad7 | j_mayer | break;
|
871 | 636aaad7 | j_mayer | case 2: |
872 | 636aaad7 | j_mayer | next = 1 << 25; |
873 | 636aaad7 | j_mayer | break;
|
874 | 636aaad7 | j_mayer | case 3: |
875 | 636aaad7 | j_mayer | next = 1 << 29; |
876 | 636aaad7 | j_mayer | break;
|
877 | 636aaad7 | j_mayer | default:
|
878 | 636aaad7 | j_mayer | /* Cannot occur, but makes gcc happy */
|
879 | 636aaad7 | j_mayer | return;
|
880 | 636aaad7 | j_mayer | } |
881 | dbdd2506 | j_mayer | next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq); |
882 | 636aaad7 | j_mayer | if (next == now)
|
883 | 636aaad7 | j_mayer | next++; |
884 | 90e189ec | Blue Swirl | LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, |
885 | 90e189ec | Blue Swirl | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
886 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
887 | 636aaad7 | j_mayer | case 0x0: |
888 | 636aaad7 | j_mayer | case 0x1: |
889 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
890 | 636aaad7 | j_mayer | ppcemb_timer->wdt_next = next; |
891 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 31; |
892 | 636aaad7 | j_mayer | break;
|
893 | 636aaad7 | j_mayer | case 0x2: |
894 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
895 | 636aaad7 | j_mayer | ppcemb_timer->wdt_next = next; |
896 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 30; |
897 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) |
898 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
|
899 | 636aaad7 | j_mayer | break;
|
900 | 636aaad7 | j_mayer | case 0x3: |
901 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] &= ~0x30000000;
|
902 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
|
903 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { |
904 | 636aaad7 | j_mayer | case 0x0: |
905 | 636aaad7 | j_mayer | /* No reset */
|
906 | 636aaad7 | j_mayer | break;
|
907 | 636aaad7 | j_mayer | case 0x1: /* Core reset */ |
908 | 8ecc7913 | j_mayer | ppc40x_core_reset(env); |
909 | 8ecc7913 | j_mayer | break;
|
910 | 636aaad7 | j_mayer | case 0x2: /* Chip reset */ |
911 | 8ecc7913 | j_mayer | ppc40x_chip_reset(env); |
912 | 8ecc7913 | j_mayer | break;
|
913 | 636aaad7 | j_mayer | case 0x3: /* System reset */ |
914 | 8ecc7913 | j_mayer | ppc40x_system_reset(env); |
915 | 8ecc7913 | j_mayer | break;
|
916 | 636aaad7 | j_mayer | } |
917 | 636aaad7 | j_mayer | } |
918 | 76a66253 | j_mayer | } |
919 | 76a66253 | j_mayer | |
920 | 76a66253 | j_mayer | void store_40x_pit (CPUState *env, target_ulong val)
|
921 | 76a66253 | j_mayer | { |
922 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
923 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
924 | 636aaad7 | j_mayer | |
925 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
926 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
927 | 90e189ec | Blue Swirl | LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val); |
928 | 636aaad7 | j_mayer | ppcemb_timer->pit_reload = val; |
929 | 4b6d0a4c | j_mayer | start_stop_pit(env, tb_env, 0);
|
930 | 76a66253 | j_mayer | } |
931 | 76a66253 | j_mayer | |
932 | 636aaad7 | j_mayer | target_ulong load_40x_pit (CPUState *env) |
933 | 76a66253 | j_mayer | { |
934 | 636aaad7 | j_mayer | return cpu_ppc_load_decr(env);
|
935 | 76a66253 | j_mayer | } |
936 | 76a66253 | j_mayer | |
937 | 76a66253 | j_mayer | void store_booke_tsr (CPUState *env, target_ulong val)
|
938 | 76a66253 | j_mayer | { |
939 | 90e189ec | Blue Swirl | LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val); |
940 | 4b6d0a4c | j_mayer | env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
|
941 | 4b6d0a4c | j_mayer | if (val & 0x80000000) |
942 | 4b6d0a4c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);
|
943 | 636aaad7 | j_mayer | } |
944 | 636aaad7 | j_mayer | |
945 | 636aaad7 | j_mayer | void store_booke_tcr (CPUState *env, target_ulong val)
|
946 | 636aaad7 | j_mayer | { |
947 | 4b6d0a4c | j_mayer | ppc_tb_t *tb_env; |
948 | 4b6d0a4c | j_mayer | |
949 | 4b6d0a4c | j_mayer | tb_env = env->tb_env; |
950 | 90e189ec | Blue Swirl | LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val); |
951 | 4b6d0a4c | j_mayer | env->spr[SPR_40x_TCR] = val & 0xFFC00000;
|
952 | 4b6d0a4c | j_mayer | start_stop_pit(env, tb_env, 1);
|
953 | 8ecc7913 | j_mayer | cpu_4xx_wdt_cb(env); |
954 | 636aaad7 | j_mayer | } |
955 | 636aaad7 | j_mayer | |
956 | 4b6d0a4c | j_mayer | static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq) |
957 | 4b6d0a4c | j_mayer | { |
958 | 4b6d0a4c | j_mayer | CPUState *env = opaque; |
959 | 4b6d0a4c | j_mayer | ppc_tb_t *tb_env = env->tb_env; |
960 | 4b6d0a4c | j_mayer | |
961 | d12d51d5 | aliguori | LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, |
962 | aae9366a | j_mayer | freq); |
963 | 4b6d0a4c | j_mayer | tb_env->tb_freq = freq; |
964 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
965 | 4b6d0a4c | j_mayer | /* XXX: we should also update all timers */
|
966 | 4b6d0a4c | j_mayer | } |
967 | 4b6d0a4c | j_mayer | |
968 | 8ecc7913 | j_mayer | clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq) |
969 | 636aaad7 | j_mayer | { |
970 | 636aaad7 | j_mayer | ppc_tb_t *tb_env; |
971 | 636aaad7 | j_mayer | ppcemb_timer_t *ppcemb_timer; |
972 | 636aaad7 | j_mayer | |
973 | 8ecc7913 | j_mayer | tb_env = qemu_mallocz(sizeof(ppc_tb_t));
|
974 | 8ecc7913 | j_mayer | env->tb_env = tb_env; |
975 | 636aaad7 | j_mayer | ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
|
976 | 8ecc7913 | j_mayer | tb_env->tb_freq = freq; |
977 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
978 | 636aaad7 | j_mayer | tb_env->opaque = ppcemb_timer; |
979 | d12d51d5 | aliguori | LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); |
980 | 636aaad7 | j_mayer | if (ppcemb_timer != NULL) { |
981 | 636aaad7 | j_mayer | /* We use decr timer for PIT */
|
982 | 636aaad7 | j_mayer | tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env); |
983 | 636aaad7 | j_mayer | ppcemb_timer->fit_timer = |
984 | 636aaad7 | j_mayer | qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env); |
985 | 636aaad7 | j_mayer | ppcemb_timer->wdt_timer = |
986 | 636aaad7 | j_mayer | qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env); |
987 | 636aaad7 | j_mayer | } |
988 | 8ecc7913 | j_mayer | |
989 | 4b6d0a4c | j_mayer | return &ppc_emb_set_tb_clk;
|
990 | 76a66253 | j_mayer | } |
991 | 76a66253 | j_mayer | |
992 | 2e719ba3 | j_mayer | /*****************************************************************************/
|
993 | 2e719ba3 | j_mayer | /* Embedded PowerPC Device Control Registers */
|
994 | 2e719ba3 | j_mayer | typedef struct ppc_dcrn_t ppc_dcrn_t; |
995 | 2e719ba3 | j_mayer | struct ppc_dcrn_t {
|
996 | 2e719ba3 | j_mayer | dcr_read_cb dcr_read; |
997 | 2e719ba3 | j_mayer | dcr_write_cb dcr_write; |
998 | 2e719ba3 | j_mayer | void *opaque;
|
999 | 2e719ba3 | j_mayer | }; |
1000 | 2e719ba3 | j_mayer | |
1001 | a750fc0b | j_mayer | /* XXX: on 460, DCR addresses are 32 bits wide,
|
1002 | a750fc0b | j_mayer | * using DCRIPR to get the 22 upper bits of the DCR address
|
1003 | a750fc0b | j_mayer | */
|
1004 | 2e719ba3 | j_mayer | #define DCRN_NB 1024 |
1005 | 2e719ba3 | j_mayer | struct ppc_dcr_t {
|
1006 | 2e719ba3 | j_mayer | ppc_dcrn_t dcrn[DCRN_NB]; |
1007 | 2e719ba3 | j_mayer | int (*read_error)(int dcrn); |
1008 | 2e719ba3 | j_mayer | int (*write_error)(int dcrn); |
1009 | 2e719ba3 | j_mayer | }; |
1010 | 2e719ba3 | j_mayer | |
1011 | 2e719ba3 | j_mayer | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp) |
1012 | 2e719ba3 | j_mayer | { |
1013 | 2e719ba3 | j_mayer | ppc_dcrn_t *dcr; |
1014 | 2e719ba3 | j_mayer | |
1015 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1016 | 2e719ba3 | j_mayer | goto error;
|
1017 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1018 | 2e719ba3 | j_mayer | if (dcr->dcr_read == NULL) |
1019 | 2e719ba3 | j_mayer | goto error;
|
1020 | 2e719ba3 | j_mayer | *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); |
1021 | 2e719ba3 | j_mayer | |
1022 | 2e719ba3 | j_mayer | return 0; |
1023 | 2e719ba3 | j_mayer | |
1024 | 2e719ba3 | j_mayer | error:
|
1025 | 2e719ba3 | j_mayer | if (dcr_env->read_error != NULL) |
1026 | 2e719ba3 | j_mayer | return (*dcr_env->read_error)(dcrn);
|
1027 | 2e719ba3 | j_mayer | |
1028 | 2e719ba3 | j_mayer | return -1; |
1029 | 2e719ba3 | j_mayer | } |
1030 | 2e719ba3 | j_mayer | |
1031 | 2e719ba3 | j_mayer | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val) |
1032 | 2e719ba3 | j_mayer | { |
1033 | 2e719ba3 | j_mayer | ppc_dcrn_t *dcr; |
1034 | 2e719ba3 | j_mayer | |
1035 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1036 | 2e719ba3 | j_mayer | goto error;
|
1037 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1038 | 2e719ba3 | j_mayer | if (dcr->dcr_write == NULL) |
1039 | 2e719ba3 | j_mayer | goto error;
|
1040 | 2e719ba3 | j_mayer | (*dcr->dcr_write)(dcr->opaque, dcrn, val); |
1041 | 2e719ba3 | j_mayer | |
1042 | 2e719ba3 | j_mayer | return 0; |
1043 | 2e719ba3 | j_mayer | |
1044 | 2e719ba3 | j_mayer | error:
|
1045 | 2e719ba3 | j_mayer | if (dcr_env->write_error != NULL) |
1046 | 2e719ba3 | j_mayer | return (*dcr_env->write_error)(dcrn);
|
1047 | 2e719ba3 | j_mayer | |
1048 | 2e719ba3 | j_mayer | return -1; |
1049 | 2e719ba3 | j_mayer | } |
1050 | 2e719ba3 | j_mayer | |
1051 | 2e719ba3 | j_mayer | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
1052 | 2e719ba3 | j_mayer | dcr_read_cb dcr_read, dcr_write_cb dcr_write) |
1053 | 2e719ba3 | j_mayer | { |
1054 | 2e719ba3 | j_mayer | ppc_dcr_t *dcr_env; |
1055 | 2e719ba3 | j_mayer | ppc_dcrn_t *dcr; |
1056 | 2e719ba3 | j_mayer | |
1057 | 2e719ba3 | j_mayer | dcr_env = env->dcr_env; |
1058 | 2e719ba3 | j_mayer | if (dcr_env == NULL) |
1059 | 2e719ba3 | j_mayer | return -1; |
1060 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1061 | 2e719ba3 | j_mayer | return -1; |
1062 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1063 | 2e719ba3 | j_mayer | if (dcr->opaque != NULL || |
1064 | 2e719ba3 | j_mayer | dcr->dcr_read != NULL ||
|
1065 | 2e719ba3 | j_mayer | dcr->dcr_write != NULL)
|
1066 | 2e719ba3 | j_mayer | return -1; |
1067 | 2e719ba3 | j_mayer | dcr->opaque = opaque; |
1068 | 2e719ba3 | j_mayer | dcr->dcr_read = dcr_read; |
1069 | 2e719ba3 | j_mayer | dcr->dcr_write = dcr_write; |
1070 | 2e719ba3 | j_mayer | |
1071 | 2e719ba3 | j_mayer | return 0; |
1072 | 2e719ba3 | j_mayer | } |
1073 | 2e719ba3 | j_mayer | |
1074 | 2e719ba3 | j_mayer | int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), |
1075 | 2e719ba3 | j_mayer | int (*write_error)(int dcrn)) |
1076 | 2e719ba3 | j_mayer | { |
1077 | 2e719ba3 | j_mayer | ppc_dcr_t *dcr_env; |
1078 | 2e719ba3 | j_mayer | |
1079 | 2e719ba3 | j_mayer | dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
|
1080 | 2e719ba3 | j_mayer | dcr_env->read_error = read_error; |
1081 | 2e719ba3 | j_mayer | dcr_env->write_error = write_error; |
1082 | 2e719ba3 | j_mayer | env->dcr_env = dcr_env; |
1083 | 2e719ba3 | j_mayer | |
1084 | 2e719ba3 | j_mayer | return 0; |
1085 | 2e719ba3 | j_mayer | } |
1086 | 2e719ba3 | j_mayer | |
1087 | 9fddaa0c | bellard | #if 0
|
1088 | 9fddaa0c | bellard | /*****************************************************************************/
|
1089 | 9fddaa0c | bellard | /* Handle system reset (for now, just stop emulation) */
|
1090 | 9fddaa0c | bellard | void cpu_ppc_reset (CPUState *env)
|
1091 | 9fddaa0c | bellard | {
|
1092 | 9fddaa0c | bellard | printf("Reset asked... Stop emulation\n");
|
1093 | 9fddaa0c | bellard | abort();
|
1094 | 9fddaa0c | bellard | }
|
1095 | 9fddaa0c | bellard | #endif
|
1096 | 9fddaa0c | bellard | |
1097 | 64201201 | bellard | /*****************************************************************************/
|
1098 | 64201201 | bellard | /* Debug port */
|
1099 | fd0bbb12 | bellard | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
1100 | 64201201 | bellard | { |
1101 | 64201201 | bellard | addr &= 0xF;
|
1102 | 64201201 | bellard | switch (addr) {
|
1103 | 64201201 | bellard | case 0: |
1104 | 64201201 | bellard | printf("%c", val);
|
1105 | 64201201 | bellard | break;
|
1106 | 64201201 | bellard | case 1: |
1107 | 64201201 | bellard | printf("\n");
|
1108 | 64201201 | bellard | fflush(stdout); |
1109 | 64201201 | bellard | break;
|
1110 | 64201201 | bellard | case 2: |
1111 | aae9366a | j_mayer | printf("Set loglevel to %04" PRIx32 "\n", val); |
1112 | fd0bbb12 | bellard | cpu_set_log(val | 0x100);
|
1113 | 64201201 | bellard | break;
|
1114 | 64201201 | bellard | } |
1115 | 64201201 | bellard | } |
1116 | 64201201 | bellard | |
1117 | 64201201 | bellard | /*****************************************************************************/
|
1118 | 64201201 | bellard | /* NVRAM helpers */
|
1119 | 3cbee15b | j_mayer | static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr) |
1120 | 64201201 | bellard | { |
1121 | 3cbee15b | j_mayer | return (*nvram->read_fn)(nvram->opaque, addr);;
|
1122 | 64201201 | bellard | } |
1123 | 64201201 | bellard | |
1124 | 3cbee15b | j_mayer | static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val) |
1125 | 64201201 | bellard | { |
1126 | 3cbee15b | j_mayer | (*nvram->write_fn)(nvram->opaque, addr, val); |
1127 | 64201201 | bellard | } |
1128 | 64201201 | bellard | |
1129 | 3cbee15b | j_mayer | void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value)
|
1130 | 64201201 | bellard | { |
1131 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value); |
1132 | 64201201 | bellard | } |
1133 | 64201201 | bellard | |
1134 | 3cbee15b | j_mayer | uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr) |
1135 | 3cbee15b | j_mayer | { |
1136 | 3cbee15b | j_mayer | return nvram_read(nvram, addr);
|
1137 | 3cbee15b | j_mayer | } |
1138 | 3cbee15b | j_mayer | |
1139 | 3cbee15b | j_mayer | void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value)
|
1140 | 3cbee15b | j_mayer | { |
1141 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value >> 8);
|
1142 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 1, value & 0xFF); |
1143 | 3cbee15b | j_mayer | } |
1144 | 3cbee15b | j_mayer | |
1145 | 3cbee15b | j_mayer | uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr) |
1146 | 64201201 | bellard | { |
1147 | 64201201 | bellard | uint16_t tmp; |
1148 | 64201201 | bellard | |
1149 | 3cbee15b | j_mayer | tmp = nvram_read(nvram, addr) << 8;
|
1150 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 1);
|
1151 | 3cbee15b | j_mayer | |
1152 | 64201201 | bellard | return tmp;
|
1153 | 64201201 | bellard | } |
1154 | 64201201 | bellard | |
1155 | 3cbee15b | j_mayer | void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value)
|
1156 | 64201201 | bellard | { |
1157 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value >> 24);
|
1158 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); |
1159 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); |
1160 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 3, value & 0xFF); |
1161 | 64201201 | bellard | } |
1162 | 64201201 | bellard | |
1163 | 3cbee15b | j_mayer | uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) |
1164 | 64201201 | bellard | { |
1165 | 64201201 | bellard | uint32_t tmp; |
1166 | 64201201 | bellard | |
1167 | 3cbee15b | j_mayer | tmp = nvram_read(nvram, addr) << 24;
|
1168 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 1) << 16; |
1169 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 2) << 8; |
1170 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 3);
|
1171 | 76a66253 | j_mayer | |
1172 | 64201201 | bellard | return tmp;
|
1173 | 64201201 | bellard | } |
1174 | 64201201 | bellard | |
1175 | 3cbee15b | j_mayer | void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
|
1176 | b55266b5 | blueswir1 | const char *str, uint32_t max) |
1177 | 64201201 | bellard | { |
1178 | 64201201 | bellard | int i;
|
1179 | 64201201 | bellard | |
1180 | 64201201 | bellard | for (i = 0; i < max && str[i] != '\0'; i++) { |
1181 | 3cbee15b | j_mayer | nvram_write(nvram, addr + i, str[i]); |
1182 | 64201201 | bellard | } |
1183 | 3cbee15b | j_mayer | nvram_write(nvram, addr + i, str[i]); |
1184 | 3cbee15b | j_mayer | nvram_write(nvram, addr + max - 1, '\0'); |
1185 | 64201201 | bellard | } |
1186 | 64201201 | bellard | |
1187 | 3cbee15b | j_mayer | int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max) |
1188 | 64201201 | bellard | { |
1189 | 64201201 | bellard | int i;
|
1190 | 64201201 | bellard | |
1191 | 64201201 | bellard | memset(dst, 0, max);
|
1192 | 64201201 | bellard | for (i = 0; i < max; i++) { |
1193 | 64201201 | bellard | dst[i] = NVRAM_get_byte(nvram, addr + i); |
1194 | 64201201 | bellard | if (dst[i] == '\0') |
1195 | 64201201 | bellard | break;
|
1196 | 64201201 | bellard | } |
1197 | 64201201 | bellard | |
1198 | 64201201 | bellard | return i;
|
1199 | 64201201 | bellard | } |
1200 | 64201201 | bellard | |
1201 | 64201201 | bellard | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
|
1202 | 64201201 | bellard | { |
1203 | 64201201 | bellard | uint16_t tmp; |
1204 | 64201201 | bellard | uint16_t pd, pd1, pd2; |
1205 | 64201201 | bellard | |
1206 | 64201201 | bellard | tmp = prev >> 8;
|
1207 | 64201201 | bellard | pd = prev ^ value; |
1208 | 64201201 | bellard | pd1 = pd & 0x000F;
|
1209 | 64201201 | bellard | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
1210 | 64201201 | bellard | tmp ^= (pd1 << 3) | (pd1 << 8); |
1211 | 64201201 | bellard | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
1212 | 64201201 | bellard | |
1213 | 64201201 | bellard | return tmp;
|
1214 | 64201201 | bellard | } |
1215 | 64201201 | bellard | |
1216 | b1d8e52e | blueswir1 | static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count)
|
1217 | 64201201 | bellard | { |
1218 | 64201201 | bellard | uint32_t i; |
1219 | 64201201 | bellard | uint16_t crc = 0xFFFF;
|
1220 | 64201201 | bellard | int odd;
|
1221 | 64201201 | bellard | |
1222 | 64201201 | bellard | odd = count & 1;
|
1223 | 64201201 | bellard | count &= ~1;
|
1224 | 64201201 | bellard | for (i = 0; i != count; i++) { |
1225 | 76a66253 | j_mayer | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
1226 | 64201201 | bellard | } |
1227 | 64201201 | bellard | if (odd) {
|
1228 | 76a66253 | j_mayer | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
|
1229 | 64201201 | bellard | } |
1230 | 64201201 | bellard | |
1231 | 64201201 | bellard | return crc;
|
1232 | 64201201 | bellard | } |
1233 | 64201201 | bellard | |
1234 | fd0bbb12 | bellard | #define CMDLINE_ADDR 0x017ff000 |
1235 | fd0bbb12 | bellard | |
1236 | 3cbee15b | j_mayer | int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
|
1237 | b55266b5 | blueswir1 | const char *arch, |
1238 | 64201201 | bellard | uint32_t RAM_size, int boot_device,
|
1239 | 64201201 | bellard | uint32_t kernel_image, uint32_t kernel_size, |
1240 | fd0bbb12 | bellard | const char *cmdline, |
1241 | 64201201 | bellard | uint32_t initrd_image, uint32_t initrd_size, |
1242 | fd0bbb12 | bellard | uint32_t NVRAM_image, |
1243 | fd0bbb12 | bellard | int width, int height, int depth) |
1244 | 64201201 | bellard | { |
1245 | 64201201 | bellard | uint16_t crc; |
1246 | 64201201 | bellard | |
1247 | 64201201 | bellard | /* Set parameters for Open Hack'Ware BIOS */
|
1248 | 64201201 | bellard | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
1249 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
1250 | 64201201 | bellard | NVRAM_set_word(nvram, 0x14, NVRAM_size);
|
1251 | 64201201 | bellard | NVRAM_set_string(nvram, 0x20, arch, 16); |
1252 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x30, RAM_size);
|
1253 | 64201201 | bellard | NVRAM_set_byte(nvram, 0x34, boot_device);
|
1254 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x38, kernel_image);
|
1255 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x3C, kernel_size);
|
1256 | fd0bbb12 | bellard | if (cmdline) {
|
1257 | fd0bbb12 | bellard | /* XXX: put the cmdline in NVRAM too ? */
|
1258 | 5c130f65 | pbrook | pstrcpy_targphys(CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline); |
1259 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
1260 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
|
1261 | fd0bbb12 | bellard | } else {
|
1262 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, 0); |
1263 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, 0); |
1264 | fd0bbb12 | bellard | } |
1265 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x48, initrd_image);
|
1266 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x4C, initrd_size);
|
1267 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x50, NVRAM_image);
|
1268 | fd0bbb12 | bellard | |
1269 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x54, width);
|
1270 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x56, height);
|
1271 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x58, depth);
|
1272 | fd0bbb12 | bellard | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
1273 | 3cbee15b | j_mayer | NVRAM_set_word(nvram, 0xFC, crc);
|
1274 | 64201201 | bellard | |
1275 | 64201201 | bellard | return 0; |
1276 | a541f297 | bellard | } |