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target-mips: Use mul[us]2 in [D]MULT[U] insns
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-mips: implement DSP (d)append sub-class with TCG
DSP instruction from the (d)append sub-class can be implemented withTCG. Use a different function for these instructions are they are quitedifferent from compare-pick sub-class.
Fix BALIGN instruction for negative value, where the value should be...
exec: move include files to include/exec/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target-mips: implement unaligned loads using TCG
Load/store from helpers should be avoided as they are quiteinefficient. Rewrite unaligned loads instructions using TCG andaligned loads. The number of actual loads operations to implementan unaligned load instruction is reduced from up to 8 to 1....
target-mips: use the softfloat floatXX_muladd functions
Use the new softfloat floatXX_muladd() functions to implement the madd,msub, nmadd and nmsub instructions. At the same time replace the name ofthe helpers by the name of the instruction, as the only reason for the...
target-mips: Add ASE DSP accumulator instructions
Add MIPS ASE DSP Accumulator and DSPControl Access instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Add ASE DSP compare-pick instructions
Add MIPS ASE DSP Compare-Pick instructions.
target-mips: Add ASE DSP multiply instructions
Add MIPS ASE DSP Multiply instructions.
target-mips: Add ASE DSP bit/manipulation instructions
Add MIPS ASE DSP Bit/Manipulation instructions.
target-mips: Add ASE DSP GPR-based shift instructions
Add MIPS ASE DSP GPR-Based Shift instructions.
target-mips: Add ASE DSP arithmetic instructions
Add MIPS ASE DSP Arithmetic instructions.
target-mips: rename helper flags
Rename helper flags to the new ones. This is purely a mechanical change,it's possible to use better flags by looking at the helpers.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Implement Loongson Multimedia Instructions
Implements all of the COP2 instructions except for the S<cond>family of comparisons. The documentation is unclear for those.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: switch to AREG0 free mode
Add an explicit CPUState parameter instead of relying on AREG0and switch to AREG0 free mode.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: Add compiler attribute to some functions which don't return
helper_raise_exception_err does not return, nor do helper_raise_exceptionand do_unaligned_access.
Cc: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Stefan Weil <sw@weilnetz.de>...
mips: Hook in more reg accesses via mttr/mftr
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
target-mips: fix translation of MT instructions
The translation of dmt/emt/dvpe/evpe was doing the moral equivalent of:
int x; ... /* no initialization of x */ x = f (x);
which confused later bits of TCG rather badly, leading to crashes.
Fix the helpers to only return results (those instructions have no...
mips: more fixes to the MIPS interrupt glue logic
Commit 36388314febad3d7675ab919287f03733a560ff6 moved most of theinterrupt logic to cpu-exec.c. Remove the remaining useless codeand fix software interrupts.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-mips: microMIPS ASE support
Add instruction decoding for the microMIPS ASE. All we do is decode andthen forward to the existing gen_* routines.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: use physical address in lladdr
Currently the ll/sc instructions use the virtual address in bothuser and system mode. Use the physical address insteead in systemmode.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-mips: make CP0_LLAddr register CPU dependent
Depending on the CPU, CP0_LLAddr is either read-only or read-write,and the returned value can be shifted by a variable amount of bits.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
target-mips: use the TCG_CALL_PURE and TCG_CALL_CONST for some helpers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7009 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: rename helpers from do_ to helper_
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6773 c046a42c-6fe2-441c-8c8c-71466251a162
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: convert bit shuffle ops to TCG
Bit shuffle operations can be written with very few TCG instructions(between 5 and 8), so it is worth converting them to TCG.
This code also move all bit shuffle generation code to a separatefunction in order to have a cleaner exception code path, that is it...
target-mips: convert bitfield ops to TCG
Bitfield operations can be written with very few TCG instructions(between 2 and 5), so it is worth converting them to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5678 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips: fix mft* helpers/call
This patch attempts to fix mft* helpers and the associated TCG calls.mft* helpers do not take a register in argument, however:- some helpers are called with an argument while they do not take one.- some helpers are declared with an argument they don't use....
Less hardcoding of TARGET_USER_ONLY.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4928 c046a42c-6fe2-441c-8c8c-71466251a162
Use temporary registers for the MIPS FPU emulation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4861 c046a42c-6fe2-441c-8c8c-71466251a162
Remove unnecessary helper arguments, and fix some typos.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4802 c046a42c-6fe2-441c-8c8c-71466251a162
Avoid unused input arguments which triggered tcg errors. Spotted byStefan Weil.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4795 c046a42c-6fe2-441c-8c8c-71466251a162
Remove remaining uses of T0 in the MIPS target.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4788 c046a42c-6fe2-441c-8c8c-71466251a162
Use temporaries instead of fixed registers for some instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4784 c046a42c-6fe2-441c-8c8c-71466251a162
Pass T0/T1 explicitly to helper functions, and clean up a few dyngenleftovers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4780 c046a42c-6fe2-441c-8c8c-71466251a162
Convert unaligned load/store to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4759 c046a42c-6fe2-441c-8c8c-71466251a162
Convert vr54xx multiply instructions to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4756 c046a42c-6fe2-441c-8c8c-71466251a162
Convert remaining MIPS FP instructions to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4753 c046a42c-6fe2-441c-8c8c-71466251a162
Switch the standard multiplication instructions to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4740 c046a42c-6fe2-441c-8c8c-71466251a162
Switch bitfield instructions and assorted special ops to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4739 c046a42c-6fe2-441c-8c8c-71466251a162
TCGify a few more instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4736 c046a42c-6fe2-441c-8c8c-71466251a162
Call most FP helpers without deroute through op.c
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4734 c046a42c-6fe2-441c-8c8c-71466251a162
Switch remaining CP0 instructions to TCG or helper functions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4708 c046a42c-6fe2-441c-8c8c-71466251a162
Register helper functions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4700 c046a42c-6fe2-441c-8c8c-71466251a162
Switch MIPS clo/clz and the condition tests to TCG.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4507 c046a42c-6fe2-441c-8c8c-71466251a162
Add file left out from previous commit.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4497 c046a42c-6fe2-441c-8c8c-71466251a162