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gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-sparc: Use official add2/sub2 interfaces for addx/subx
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: Use mul*2 for multiply
SPARC LEON power-down support added
Signed-off-by: Ronald Hecht <address@hidden>Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
exec: move include files to include/exec/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
build: kill libdis, move disassemblers to disas/
TCG: Use gen_opc_instr_start from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_pc from context instead of global variable.
TCG: Use gen_opc_icount from context instead of global variable.
TCG: Use gen_opc_buf from context instead of global variable.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
TCG: Use gen_opc_ptr from context instead of global variable.
disas: avoid using cpu_single_env
Pass around CPUArchState instead of using global cpu_single_env.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Acked-by: Richard Henderson <rth@twiddle.net>Acked-by: Aurelien Jarno <aurelien@aurel32.net>Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
target-sparc: Revert setting cpu_dst to gen_dest_gpr
There is some read-after-write error within the OP=2 insns whichprevents setting cpu_dst to the real output register. Until thisis found and fixed, always write to a temporary first.
Cc: Blue Swirl <blauwirbel@gmail.com>...
target-sparc: fix FMOVr instruction
Like the MOVr instruction, the FMOVr instruction has the conditionencoded between bits 10 and 12.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: Tidy ldfsr, stfsr
Remove the last uses of cpu_tmp32. Unify the code between sparc64and sparc32 by using the proper "tl" functions.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: Remove usage of cpu_tmp64 from most helper functions
Use a locally allocated temporary instead.
target-sparc: Don't use a temporary for gen_dest_fpr_D
In all cases we don't have write-before-read problems.
target-sparc: Remove cpu_tmp64 use from softint insns
The use of "tl" functions and a tmp64 is logically incompatible.Use cpu_tmp0 instead.
target-sparc: Remove last uses of cpu_tmp64
target-sparc: Only use cpu_dst for eventual writes to a gpr
Use cpu_tmp0 for other stuff, like Write Priv Register.
target-sparc: Make cpu_dst local to OP=2 insns
And initialize it such that it (may) write directly to rd.
target-sparc: Remove cpu_tmp0 as a global
Subroutines do their own local temporary management.Within disas_sparc_insn we limit the existance of the variableto OP=2 insns, and delay initialization as late as is reasonablefor the specific XOP.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
target-sparc: Conversion to gen_*_gpr, part 1
Only handle the easy cases directly within disas_sparc_insn.
target-sparc: Use gen_load_gpr in get_src12
This means we can avoid the incoming temporary, though the cleanupof the existing temporaries is not performed in this patch.
target-sparc: Convert asi helpers to gen_*_gpr
Push the DisasContext down so that we can use gen_load/store_gprin sode gen_ldda_asi, gen_stda_ast, gen_cas_asi, gen_casx_asi.
target-sparc: Convert swap to gen_load/store_gpr
target-sparc: Finish conversion to gen_load_gpr
All users of gen_movl_{reg_TN,TN_reg} are removed. At the same time,make cpu_val a local variable for load/store disassembly.
target-sparc: Cleanup cpu_src12 allocation
Now that get_temp_tl is used for get_src12, we don't need topre-allocate these temporaries.
Fallout from this is moving some assignments around cas/casx toavoid uninitialized variable warnings.
target-sparc: Make the cpu_addr variable local to load/store handling
target-sparc: Split out get_temp_i32
target-sparc: Use get_temp_i32 in gen_dest_fpr_F
target-sparc: Avoid cpu_tmp32 in Read Priv Register
We don't need another temporary here. Load directly into theregister we want to set.
target-sparc: Avoid cpu_tmp32 in Write Priv Register
No need to copy to a temporary to store 32 bits.
target-sparc: Add gen_load/store/dest_gpr
Infrastructure to be used to clean up handling of temporaries.
target-sparc: Fix optimized %icc comparisons
Signed-off-by: Richard Henderson <rth@twiddle.net>Tested-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: Optimize CC_OP_LOGIC conditions
target-sparc: Avoid unnecessary local temporaries
Now that save_state never ends a BB, we don't need to copyvalues into local temps around it.
target-sparc: Don't compute full flags value so often
Avoid speculatively computing flags before every potentially trappingoperation and instead do the flags computation when a trap actuallyoccurs. This gives approximately 30% speedup in emulation.
target-sparc: Use movcond for FMOV*R
target-sparc: Cleanup "global" temporary allocation
There are 6 temporaries that disas_sparc_insn relies on having beenallocated. Now that they are no longer referenced across branches,they need not be allocated as local temps.
Move the allocation/free of these temporaries to make it clear that...
target-sparc: Fall through from not-taken trap
Now that we've cleaned up global temporary allocation, we cancontinue translating the fallthru path of a conditional trap.
target-sparc: Optimize conditionals using SUBCC
Aka "normal" comparisons. We now have the infrastructure topass back non-boolean results from gen_compare. This willautomatically get used by both branches and conditional moves.
target-sparc: Move sdivx and udivx out of line
The branches around the exception are maintaining an otherwiseunnecessary use of local temps for the cpu destination.
target-sparc: Tidy Tcc
Share more code between unconditional and conditional paths.
Move the computation of the trap number into the conditional BB;avoid using temporaries that have gone out of scope (cpu_tmp32)or rely on local temps (cpu_dst).
Fully fold the exception number when the trap number is %g0+imm....
target-sparc: Move taddcctv and tsubcctv out of line
Note that gen_op_t{add,sub}_cc were identical to gen_op_{add,sub}_cc.
target-sparc: Use movcond in mulscc
target-sparc: Use DisasCompare and movcond in FMOVR, FMOVCC
target-sparc: Use DisasCompare and movcond in MOVCC
target-sparc: Use DisasCompare and movcond in MOVR
target-sparc: Use movcond in gen_generic_branch
target-sparc: Tidy save_npc interface
Use the cpu_cond global register directly instead of passing it down.
target-sparc: Tidy gen_generic_branch interface
The arguments passed are always the same.Pass down just DisasContext instead.
target-sparc: Introduce DisasCompare and functions to generate it
For the moment gen_cond et al retain their existing interface,using setcond to turn a (potential) comparison back into a boolean.
target-sparc: Use DisasCompare in Tcc
target-sparc: Tidy flush_cond interface
We always pass cpu_cond to the cond parameter. Use that globalregister directly instead of passing it down.
target-sparc: Tidy gen_trap_ifnofpu interface
target-sparc: Tidy save_state interface
target-sparc: Tidy gen_mov_pc_npc interface
target-sparc: Tidy do_branch interfaces
We always pass cpu_cond to the r_cond parameter. Use that globalregister directly instead of passing it down.
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
For all targets that currently call tcg_gen_debug_insn_start,add CPU_LOG_TB_OP_OPT to the condition that gates it.
This is useful for comparing optimization dumps, when thepre-optimization dump is merely noise....
Implement address masking for SPARC v9 CPUs
According to UltraSPARC - IIi User's manual:
14.1.11 Address Masking (Impdep #125)When PSTATE.AM=1, the CALL, JMPL, and RDPC instructions and all trapstransmit zero in the high-order 32-bits of the PC to their specified...
Sparc: avoid AREG0 wrappers for memory access helpers
Adjust generation of load and store templates so that the functionstake a parameter for CPUState instead of relying on global env.
Remove wrappers. Move remaining memory helpers to ldst_helper.c.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Sparc: avoid AREG0 for memory access helpers
Make memory access helpers take a parameter for CPUState insteadof relying on global env. Introduce wrappers for load and store ops.
target-sparc: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUSPARCState/g" target-sparc/*.[hc] sed -i "s/#define CPUSPARCState/#define CPUState/" target-sparc/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>Acked-by: Anthony Liguori <aliguori@us.ibm.com>
Improve "ta 0" shutdown
This patch replace the previous implementation with this simplified andmore complete version (no shutdown when psret == 1).
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-sparc: Implement EDGE* instructions.
Signed-off-by: Richard Henderson <rth@twiddle.net>
target-sparc: Implement ALIGNADDR* inline.
While ALIGNADDR was implemented out-of-line, ALIGNADDRL was notimplemeneted at all. However, this is a very simple operationso we're better off doing this inline.
target-sparc: Implement BMASK/BSHUFFLE.
target-sparc: Implement FALIGNDATA inline.
This is a relatively simple sequence of shifts.
target-sparc: Implement fpack{16,32,fix}.
target-sparc: Implement PDIST.
target-sparc: Do exceptions management fully inside the helpers.
This reduces the size of the individual translation blocks, sincewe only emit a single call for each FOP rather than three. Inaddition, clear_float_exceptions expands inline to a single byte store....
target-sparc: Extract float128 move to a function.
target-sparc: Undo cpu_fpr rename.
target-sparc: Change fpr representation to doubles.
This allows a more efficient representation for 64-bit hosts.It should be about the same for 32-bit hosts, as we can stillaccess the individual pieces of the double.
target-sparc: Extract common code for floating-point operations.
target-sparc: Mark fprs dirty in store accessor.
target-sparc: Add accessors for double-precision fpr access.
Begin using i64 quantities to manipulate double-precision values.On a 64-bit host this will, for the moment, generate less efficientcode; on a 32-bit host code quality should be largely unchanged....
target-sparc: Pass float64 parameters instead of dt0/1 temporaries.
target-sparc: Make FPU/VIS helpers const when possible.
This also removes the unused ENV parameter from these helpers.
target-sparc: Add accessors for single-precision fpr access.
Load, store, and "create destination". This version attempts tochange the behaviour of the translator as little as possible. Wepreviously used cpu_tmp32 as the temporary destination, and we...
Sparc: avoid AREG0 for division op helpers
Make [su]div{,cc} helpers take a parameter for CPUState insteadof relying on global env. Move the functions to helper.c.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Sparc: avoid AREG0 for softint op helpers and Leon cache control
Make softint op helpers and Leon cache irq manager take a parameterfor CPUState instead of relying on global env. Move the functionsto int{32,64}_helper.c.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
Sparc: avoid AREG0 for CWP and PSTATE helpers
Make CWP and PSTATE helpers take a parameter for CPUState insteadof relying on global env. Remove wrapper functions.
target-sparc: Fix order of function parameters
The MinGW-w64 gcc complains about wrong parameters forgen_helper_fpadd16_s and three other functions.
gen_helper_fpadd16_s is declared like this (hidden in lots of macros):
static inline void gen_helper_fpadd16s(TCGv_i32 retval, TCGv_ptr arg1,...
Sparc: avoid AREG0 for lazy condition code helpers
Make lazy condition code helpers take a parameter for CPUState insteadof relying on global env.
Sparc: avoid AREG0 for float and VIS ops
Make floating point and VIS ops take a parameter for CPUState insteadof relying on global env.
Sparc: avoid AREG0 for raise_exception and helper_debug
Make raise_exception() and helper_debug() take a parameter forCPUState instead of relying on global env. Move the functionsto helper.c.
Fix handling of conditional branches in delay slot of a conditional branch
Check whether dc->npc is dynamic before using its value for branch.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
SPARC64: fix fnor* and fnand*
Fix the problem that result values are not assigned to the destinationregisters.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
SPARC64: implement %fprs dirty bits
Implement %fprs.DU/DL bits.The FPU sets %fprs.DL and %fprs.DU when values are assigned to %f0-31and %f32-63 respectively.
SPARC64: add missing break on fmovdcc
"break" is missing on V9 fmovdcc (%icc).
SPARC64: fix VIS1 SIMD signed compare instructions
The destination registers of SIMD signed compare instructions(fcmp*<16|32>) are not FP registers but general purpose r registers.Comparisons should be freg_rs1 CMP freg_rs2, that were reversed.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>...
Sparc: fix FPU and AM enable checks for translation
Translation used incorrectly CPUState fields directly to checkfor FPU enable state and 32 bit address masking on Sparc64.
Fix by using TB flags instead.
SPARC64: fp_disabled checks on stfa/stdfa/stqfa
stfa/stdfa/stqfa instructions should raise fp_disabled exceptionsif %pstate.PEF==0 or %fprs.FEF==0.
SPARC64: Implement stfa/stdfa/stqfa instrcutions properly
This patch implements sparcv9 stfa/stdfa/stqfa instructionswith non block-store ASIs.
SPARC64: fp_disabled checks on ldfa/lddfa/ldqfa
ldfa/lddfa/ldqfa instructions should raise fp_disabled exceptionsif %pstate.PEF==0 or %fprs.FEF==0.
fix cpu_cc_src and cpu_cc_src2 corruption in udivx and sdivx
udivx and sdvix don't modify condition flags, so they shall notoverwrite cpu_cc_*
Remove exec-all.h include directives
Most exec-all.h include directives are now useless, remove them.
Delete unused tb_invalidate_page_range
tb_invalidate_page_range() was intended to be used to invalidate anarea of a TB which the guest explicitly flushes from i-cache. However,QEMU detects writes to code areas where TBs have been generated, sohis has never been useful....