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tcg/mips: Implement muls2_i32
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
exec: move include files to include/exec/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
tcg/mips: use MUL instead of MULT on MIPS32 and above
MIPS32 and later instruction sets have a multiplication instructiondirectly operating on GPRs. It only produces a 32-bit result butit is exactly what is needed by QEMU.
Reviewed-by: Richard Henderson <rth@twiddle.net>...
tcg: remove obsolete jmp op
The TCG jmp operation doesn't really make sense in the QEMU context, itis unused, it is not implemented by some targets, and it is wronglyimplemented by some others.
This patch simply removes it.
tcg/mips: fix MIPS32 detection
Fix the MIPS32 cpu detection so that it also works with-march=octeon. Thanks to Andrew Pinski for the hint.
Cc: Andrew Pinski <apinski@cavium.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Revert "tcg/mips"
This reverts commit ad49d1f75115663731bfe06dec61eed6775526ad.
This commit was not supposed to be pushed.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/mips
tcg: Remove tcg_target_get_call_iarg_regs_count
The TCG targets no longer need individual implementations.
Since commit 6a18ae2d2947532d5c26439548afa0481c4529f9,'flags' is no longer used in tcg_target_get_call_iarg_regs_count.
The remaining tcg_target_get_call_iarg_regs_count is trivial and only...
tcg/mips: optimize brcond arg, 0
MIPS has some conditional branch instructions when comparing with zero.Use them.
tcg/mips: optimize bswap{16,16s,32} on MIPS32R2
bswap operations can be optimized on MIPS32 Release 2 using the ROTR,WSBH and SEH instructions. We can't use the non-R2 code to implement theops due to registers constraints, so don't define the corresponding...
tcg/mips: implement rotl/rotr ops on MIPS32R2
rotr operations can be optimized on MIPS32 Release 2 using the ROTR andROTRV instructions. Also implemented rotl operations by subtracting theshift from 32.
tcg/mips: implement deposit op on MIPS32R2
deposit operations can be optimized on MIPS32 Release 2 using the INSinstruction.
tcg/mips: implement movcond op on MIPS32R2
movcond operation can be implemented on MIPS32 Release 2 using the MOVN,MOVZ, SLT and SLTU instructions.
tcg-mips: fix wrong usage of 'Z' constraint
The 'Z' constraint has been introduced to map the zero register. Howeverwhen the op also accept a constant, there is no point to accept the zeroregister in addition.
tcg/mips: kill warnings in user mode
Recent versions of GCC emit warnings when compiling user mode targets.Kill them by reordering a bit the #ifdef.
tcg/mips: use TCGArg or TCGReg instead of int
Instead of int, use the correct TCGArg and TCGReg type: TCGReg whenrepresenting a TCG target register, TCGArg when representing the latteror a constant.
tcg/mips: don't use global pointer
Don't use the global pointer in TCG, in case helpers try access globalvariables.
tcg/mips: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCGtemps.
Remove unused CONFIG_TCG_PASS_AREG0 and dead code
Now that CONFIG_TCG_PASS_AREG0 is enabled for all targets,remove dead code and support for !CONFIG_TCG_PASS_AREG0 case.
Remove dyngen-exec.h and all references to it. Although included byhw/spapr_hcall.c, it does not seem to use it....
tcg/mips: fix broken CONFIG_TCG_PASS_AREG0 code
The CONFIG_TCG_PASS_AREG0 code for calling ld/st helpers wasbroken in that it did not respect the ABI requirement that 64bit values were passed in even-odd register pairs. The simplestway to fix this is to implement some new utility functions...
softmmu templates: optionally pass CPUState to memory access functions
Optionally, make memory access helpers take a parameter for CPUStateinstead of relying on global env.
On most targets, perform simple moves to reorder registers. On i386,switch from regparm(3) calling convention to standard stack-based...
Rename CPUState -> CPUArchState
Scripted conversion: for file in .[hc] hw/.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do sed -i "s/CPUState/CPUArchState/g" $file done...
tcg: Use TCGReg for standard tcg-target entry points.
Including tcg_out_ld, tcg_out_st, tcg_out_mov, tcg_out_movi.
Signed-off-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Andreas Färber <afaerber@suse.de>Reviewed-by: Stefan Weil <sw@weilnetz.de>...
tcg/mips: Fix regression caused by typo (copy + paste bug)
cppcheck reports an error:qemu/tcg/mips/tcg-target.c:1487: error: Invalid number of character (()
The unpatched code won't compile on mips hosts starting with commitcea5f9a28faa528b6b1b117c9ab2d8828f473fef....
Delegate setup of TCG temporaries to targets
Delegate TCG temp_buf setup to targets, so that they can use a stackframe later instead.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
cpu-exec.c: avoid AREG0 use
Make functions take a parameter for CPUState instead of relyingon global env. Pass CPUState pointer to TCG prologue, which movesit to AREG0.
Thanks to Peter Maydell and Laurent Desnogues for the ARM prologuechange.
Revert the hacks to avoid AREG0 use on Sparc hosts....
tcg arm/mips/ia64: add a comment about retranslation and caches
Add a comment about cache coherency and retranslation, so that peopledevelopping new targets based on existing ones are warned of the issue.
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>...
tcg/mips: fix branch target change during code retranslation
TCG on MIPS was trying to avoid changing the branch offset, but didn'tdue to a stupid typo. Fix it.
tcg: Make some tcg-target.c routines static.
Both tcg_target_init and tcg_target_qemu_prologueare unused outside of tcg.c.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Add TYPE parameter to tcg_out_mov.
Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64to perform the move at the proper width, which may elide a REX prefix.
Introduce a TCG_TYPE_REG enumerator to represent the "native width" of the host register, and to distinguish the usage from "pointer data"...
tcp/mips: Change TCG_AREG0 (fp -> s0)
Register fp (frame pointer) is a bad choice for compilationswithout optimisation, because the compiler makes heavy useof this register (so the resulting code crashes).
Register s0 had been used for TCG_AREG1 in earlier releases,...
tcg/mips: fix 64-bit linux-user on big endian MIPS
tcg/mips: use seb/seh instructions on MIPS32R2
Split TLB addend and target_phys_addr_t
Historically the qemu tlb "addend" field was used for both RAM and IO accesses,so needed to be able to hold both host addresses (unsigned long) and guestphysical addresses (target_phys_addr_t). However since the introduction of...
tcg/mips: fix branch offset during retranslation
Branch offsets should only be overwritten during relocation, to supportpartial retranslation.
tcg-mips: add guest base support
tcg/mips: implement the not_i32 op the same way as gcc
tcg-mips: implement nor
tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operandssign-extended in 64-bit registers (regardless of the "real" signof the operand). For that, we need to be able to distinguishbetween a 32-bit load with a 32-bit result and a 32-bit load with...
tcg: Use TCGCond where appropriate.
Use the TCGCond enumeration type in the brcond and setcondrelated prototypes in tcg-op.h and each code generator.
tcg: Name the opcode enumeration.
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.Use that enumeration type instead of "int" whereever appropriate.
tcg/mips: fix crash in tcg_out_qemu_ld()
The address register is overriden when it corresponds to v0 and the fastpath is taken, which leads to a crash. Fix that by using the a0 registerinstead.
tcg/mips: implement setcond2
tcg/mips: implement setcond
tcg: initial mips support
Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>