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root / target-arm @ acdf01ef

Name Size
cpu.h 16.9 kB
exec.h 1.6 kB
helper.c 75.8 kB
helpers.h 16.5 kB
iwmmxt_helper.c 24.7 kB
machine.c 6.6 kB
neon_helper.c 38.8 kB
op_addsub.h 1.8 kB
op_helper.c 9.5 kB
translate.c 319.5 kB

Latest revisions

# Date Author Comment
acdf01ef 02/09/2011 08:47 pm Christophe Lyon

target-arm: fix VSHLL Neon instruction.

Fix bit mask used when widening the result of shift on narrow input.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
cc2212c2 02/09/2011 08:37 pm Peter Maydell

target-arm: Fix 32 bit signed saturating narrow

The returned value when doing saturating signed 64->32 bit
conversion of a negative number was incorrect due to a missing cast.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
af1bbf30 02/09/2011 08:37 pm Juha Riihimäki

target-arm: Fix VQMOVUN Neon instruction.

VQMOVUN does a signed-to-unsigned saturating conversion. This is
different from both the signed-to-signed and unsigned-to-unsigned
conversions already implemented, so we need a new set of helper
functions (neon_unarrow_sat*)....
607b4b08 02/04/2011 10:30 pm Peter Maydell

target-arm: Clean up handling of MPIDR

The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architecture
as the MPIDR. Clean up its implementation to remove A9 specific handling.

This commit includes fixing an error in the value returned for the
MPIDR on A9, where we were erroneously claiming a cluster ID of 9....
3d185e5d 02/04/2011 10:30 pm Peter Maydell

target-arm: Fix decoding of preload and memory hint space

Correct the decoding of the ARM preload and memory hint space,
by adding decoding of PLI, PLDW and the v7MP unallocated hint
space. This commit also corrects a slightly overexuberant
decoding of PLD which was not checking that bit 4...
a2fdc890 02/04/2011 10:30 pm Peter Maydell

target-arm: Fix decoding of Thumb preload and hint space

Refine the decoding of the Thumb preload and hint space, so we
UNDEF on the patterns that are supposed to UNDEF rather than NOP.
We also move the tests for this space earlier, so we don't emit
harmless but unnecessary address generation code for preload...
e1bbf446 02/04/2011 10:30 pm Peter Maydell

target-arm: Add CPU feature flag for v7MP

Add a CPU feature flag for v7MP (the multiprocessing extensions); some
instructions exist only for v7MP and not for the base v7 architecture.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
72902672 02/04/2011 09:57 pm Christophe Lyon

Set the right overflow bit for neon 32 and 64 bit saturating add/sub.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
5371cb81 02/04/2011 09:48 pm Christophe Lyon

target-arm: Fix Neon vsra instructions.

This patch fixes the errors reported by my tests in VSRA.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>
46eece9d 01/29/2011 04:16 pm Juha Riihimäki

target-arm: Fix Neon VQDMULH.S16 instructions

Correct an error in the implementation of the 16 bit
forms of VQDMULH, bringing them into line with the
32 bit implementation.

Signed-off-by: Juha Riihimäki <>
Reviewed-by: Peter Maydell <>...

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