root / hw / sun4m.c @ afc7df11
History | View | Annotate | Download (6.6 kB)
1 | 420557e8 | bellard | /*
|
---|---|---|---|
2 | 420557e8 | bellard | * QEMU Sun4m System Emulator
|
3 | 420557e8 | bellard | *
|
4 | 420557e8 | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
|
5 | 420557e8 | bellard | *
|
6 | 420557e8 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 420557e8 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | 420557e8 | bellard | * in the Software without restriction, including without limitation the rights
|
9 | 420557e8 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 420557e8 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | 420557e8 | bellard | * furnished to do so, subject to the following conditions:
|
12 | 420557e8 | bellard | *
|
13 | 420557e8 | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | 420557e8 | bellard | * all copies or substantial portions of the Software.
|
15 | 420557e8 | bellard | *
|
16 | 420557e8 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 420557e8 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 420557e8 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 420557e8 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 420557e8 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 420557e8 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 420557e8 | bellard | * THE SOFTWARE.
|
23 | 420557e8 | bellard | */
|
24 | 420557e8 | bellard | #include "vl.h" |
25 | 420557e8 | bellard | #include "m48t08.h" |
26 | 420557e8 | bellard | |
27 | 420557e8 | bellard | #define KERNEL_LOAD_ADDR 0x00004000 |
28 | 713c45fa | bellard | #define INITRD_LOAD_ADDR 0x00800000 |
29 | e80cfcfc | bellard | #define PROM_ADDR 0xffd00000 |
30 | 8d5f07fa | bellard | #define PROM_FILENAMEB "proll.bin" |
31 | 8d5f07fa | bellard | #define PROM_FILENAMEE "proll.elf" |
32 | e80cfcfc | bellard | #define PHYS_JJ_EEPROM 0x71200000 /* m48t08 */ |
33 | 420557e8 | bellard | #define PHYS_JJ_IDPROM_OFF 0x1FD8 |
34 | 420557e8 | bellard | #define PHYS_JJ_EEPROM_SIZE 0x2000 |
35 | e80cfcfc | bellard | // IRQs are not PIL ones, but master interrupt controller register
|
36 | e80cfcfc | bellard | // bits
|
37 | e80cfcfc | bellard | #define PHYS_JJ_IOMMU 0x10000000 /* I/O MMU */ |
38 | 8d5f07fa | bellard | #define PHYS_JJ_TCX_FB 0x50800000 /* Start address, frame buffer body */ |
39 | e80cfcfc | bellard | #define PHYS_JJ_LEDMA 0x78400010 /* Lance DMA controller */ |
40 | e80cfcfc | bellard | #define PHYS_JJ_LE 0x78C00000 /* Lance ethernet */ |
41 | e80cfcfc | bellard | #define PHYS_JJ_LE_IRQ 16 |
42 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK 0x71D00000 /* Per-CPU timer/counter, L14 */ |
43 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK_IRQ 7 |
44 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK1 0x71D10000 /* System timer/counter, L10 */ |
45 | e80cfcfc | bellard | #define PHYS_JJ_CLOCK1_IRQ 19 |
46 | e80cfcfc | bellard | #define PHYS_JJ_INTR0 0x71E00000 /* Per-CPU interrupt control registers */ |
47 | 8d5f07fa | bellard | #define PHYS_JJ_INTR_G 0x71E10000 /* Master interrupt control registers */ |
48 | e80cfcfc | bellard | #define PHYS_JJ_MS_KBD 0x71000000 /* Mouse and keyboard */ |
49 | e80cfcfc | bellard | #define PHYS_JJ_MS_KBD_IRQ 14 |
50 | e80cfcfc | bellard | #define PHYS_JJ_SER 0x71100000 /* Serial */ |
51 | e80cfcfc | bellard | #define PHYS_JJ_SER_IRQ 15 |
52 | e80cfcfc | bellard | #define PHYS_JJ_SCSI_IRQ 18 |
53 | e80cfcfc | bellard | #define PHYS_JJ_FDC 0x71400000 /* Floppy */ |
54 | e80cfcfc | bellard | #define PHYS_JJ_FLOPPY_IRQ 22 |
55 | 420557e8 | bellard | |
56 | 420557e8 | bellard | /* TSC handling */
|
57 | 420557e8 | bellard | |
58 | 420557e8 | bellard | uint64_t cpu_get_tsc() |
59 | 420557e8 | bellard | { |
60 | 420557e8 | bellard | return qemu_get_clock(vm_clock);
|
61 | 420557e8 | bellard | } |
62 | 420557e8 | bellard | |
63 | 420557e8 | bellard | void DMA_run() {}
|
64 | 420557e8 | bellard | |
65 | 420557e8 | bellard | static m48t08_t *nvram;
|
66 | 420557e8 | bellard | |
67 | e80cfcfc | bellard | static void nvram_init(m48t08_t *nvram, uint8_t *macaddr) |
68 | e80cfcfc | bellard | { |
69 | e80cfcfc | bellard | unsigned char tmp = 0; |
70 | e80cfcfc | bellard | int i, j;
|
71 | e80cfcfc | bellard | |
72 | e80cfcfc | bellard | i = 0x1fd8;
|
73 | e80cfcfc | bellard | m48t08_write(nvram, i++, 0x01);
|
74 | e80cfcfc | bellard | m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */ |
75 | e80cfcfc | bellard | j = 0;
|
76 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
77 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
78 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
79 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
80 | e80cfcfc | bellard | m48t08_write(nvram, i++, macaddr[j++]); |
81 | e80cfcfc | bellard | m48t08_write(nvram, i, macaddr[j]); |
82 | e80cfcfc | bellard | |
83 | e80cfcfc | bellard | /* Calculate checksum */
|
84 | e80cfcfc | bellard | for (i = 0x1fd8; i < 0x1fe7; i++) { |
85 | e80cfcfc | bellard | tmp ^= m48t08_read(nvram, i); |
86 | e80cfcfc | bellard | } |
87 | e80cfcfc | bellard | m48t08_write(nvram, 0x1fe7, tmp);
|
88 | e80cfcfc | bellard | } |
89 | e80cfcfc | bellard | |
90 | e80cfcfc | bellard | static void *slavio_intctl; |
91 | e80cfcfc | bellard | |
92 | e80cfcfc | bellard | void pic_info()
|
93 | e80cfcfc | bellard | { |
94 | e80cfcfc | bellard | slavio_pic_info(slavio_intctl); |
95 | e80cfcfc | bellard | } |
96 | e80cfcfc | bellard | |
97 | e80cfcfc | bellard | void irq_info()
|
98 | e80cfcfc | bellard | { |
99 | e80cfcfc | bellard | slavio_irq_info(slavio_intctl); |
100 | e80cfcfc | bellard | } |
101 | e80cfcfc | bellard | |
102 | e80cfcfc | bellard | void pic_set_irq(int irq, int level) |
103 | e80cfcfc | bellard | { |
104 | e80cfcfc | bellard | slavio_pic_set_irq(slavio_intctl, irq, level); |
105 | e80cfcfc | bellard | } |
106 | e80cfcfc | bellard | |
107 | e80cfcfc | bellard | static void *tcx; |
108 | e80cfcfc | bellard | |
109 | e80cfcfc | bellard | void vga_update_display()
|
110 | e80cfcfc | bellard | { |
111 | e80cfcfc | bellard | tcx_update_display(tcx); |
112 | e80cfcfc | bellard | } |
113 | e80cfcfc | bellard | |
114 | e80cfcfc | bellard | void vga_invalidate_display()
|
115 | e80cfcfc | bellard | { |
116 | e80cfcfc | bellard | tcx_invalidate_display(tcx); |
117 | e80cfcfc | bellard | } |
118 | e80cfcfc | bellard | |
119 | e80cfcfc | bellard | void vga_screen_dump(const char *filename) |
120 | e80cfcfc | bellard | { |
121 | e80cfcfc | bellard | tcx_screen_dump(tcx, filename); |
122 | e80cfcfc | bellard | } |
123 | e80cfcfc | bellard | |
124 | e80cfcfc | bellard | static void *iommu; |
125 | e80cfcfc | bellard | |
126 | e80cfcfc | bellard | uint32_t iommu_translate(uint32_t addr) |
127 | e80cfcfc | bellard | { |
128 | e80cfcfc | bellard | return iommu_translate_local(iommu, addr);
|
129 | e80cfcfc | bellard | } |
130 | e80cfcfc | bellard | |
131 | 420557e8 | bellard | /* Sun4m hardware initialisation */
|
132 | 420557e8 | bellard | void sun4m_init(int ram_size, int vga_ram_size, int boot_device, |
133 | 420557e8 | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
134 | 420557e8 | bellard | const char *kernel_filename, const char *kernel_cmdline, |
135 | 420557e8 | bellard | const char *initrd_filename) |
136 | 420557e8 | bellard | { |
137 | 420557e8 | bellard | char buf[1024]; |
138 | 8d5f07fa | bellard | int ret, linux_boot;
|
139 | 713c45fa | bellard | unsigned int i; |
140 | 713c45fa | bellard | unsigned long vram_size = 0x100000, prom_offset, initrd_size; |
141 | 420557e8 | bellard | |
142 | 420557e8 | bellard | linux_boot = (kernel_filename != NULL);
|
143 | 420557e8 | bellard | |
144 | 420557e8 | bellard | /* allocate RAM */
|
145 | 420557e8 | bellard | cpu_register_physical_memory(0, ram_size, 0); |
146 | 420557e8 | bellard | |
147 | e80cfcfc | bellard | iommu = iommu_init(PHYS_JJ_IOMMU); |
148 | e80cfcfc | bellard | slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G); |
149 | e80cfcfc | bellard | tcx = tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size); |
150 | 8d5f07fa | bellard | lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
|
151 | e80cfcfc | bellard | nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE); |
152 | e80cfcfc | bellard | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr);
|
153 | e80cfcfc | bellard | slavio_timer_init(PHYS_JJ_CLOCK, PHYS_JJ_CLOCK_IRQ, PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ); |
154 | e80cfcfc | bellard | slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ); |
155 | e80cfcfc | bellard | slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[0], serial_hds[1]); |
156 | e80cfcfc | bellard | fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table); |
157 | 420557e8 | bellard | |
158 | e80cfcfc | bellard | prom_offset = ram_size + vram_size; |
159 | e80cfcfc | bellard | |
160 | e80cfcfc | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE); |
161 | e80cfcfc | bellard | ret = load_elf(buf, phys_ram_base + prom_offset); |
162 | e80cfcfc | bellard | if (ret < 0) { |
163 | 8d5f07fa | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB); |
164 | e80cfcfc | bellard | ret = load_image(buf, phys_ram_base + prom_offset); |
165 | e80cfcfc | bellard | } |
166 | e80cfcfc | bellard | if (ret < 0) { |
167 | e80cfcfc | bellard | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
168 | e80cfcfc | bellard | buf); |
169 | e80cfcfc | bellard | exit(1);
|
170 | e80cfcfc | bellard | } |
171 | e80cfcfc | bellard | cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, |
172 | e80cfcfc | bellard | prom_offset | IO_MEM_ROM); |
173 | e80cfcfc | bellard | |
174 | e80cfcfc | bellard | if (linux_boot) {
|
175 | e80cfcfc | bellard | ret = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
176 | e80cfcfc | bellard | if (ret < 0) |
177 | e80cfcfc | bellard | ret = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
178 | e80cfcfc | bellard | if (ret < 0) |
179 | e80cfcfc | bellard | ret = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
180 | 420557e8 | bellard | if (ret < 0) { |
181 | 420557e8 | bellard | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
182 | e80cfcfc | bellard | kernel_filename); |
183 | e80cfcfc | bellard | exit(1);
|
184 | 420557e8 | bellard | } |
185 | 713c45fa | bellard | |
186 | 713c45fa | bellard | /* load initrd */
|
187 | 713c45fa | bellard | initrd_size = 0;
|
188 | 713c45fa | bellard | if (initrd_filename) {
|
189 | 713c45fa | bellard | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); |
190 | 713c45fa | bellard | if (initrd_size < 0) { |
191 | 713c45fa | bellard | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
192 | 713c45fa | bellard | initrd_filename); |
193 | 713c45fa | bellard | exit(1);
|
194 | 713c45fa | bellard | } |
195 | 713c45fa | bellard | } |
196 | 713c45fa | bellard | if (initrd_size > 0) { |
197 | 713c45fa | bellard | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
198 | 713c45fa | bellard | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
|
199 | 713c45fa | bellard | == 0x48647253) { // HdrS |
200 | 713c45fa | bellard | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
201 | 713c45fa | bellard | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
202 | 713c45fa | bellard | break;
|
203 | 713c45fa | bellard | } |
204 | 713c45fa | bellard | } |
205 | 713c45fa | bellard | } |
206 | 420557e8 | bellard | } |
207 | 420557e8 | bellard | } |