root / hw / ppce500_pci.c @ b13ce26d
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1 | 74c62ba8 | aurel32 | /*
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2 | 74c62ba8 | aurel32 | * QEMU PowerPC E500 embedded processors pci controller emulation
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3 | 74c62ba8 | aurel32 | *
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4 | 74c62ba8 | aurel32 | * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
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5 | 74c62ba8 | aurel32 | *
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6 | 74c62ba8 | aurel32 | * Author: Yu Liu, <yu.liu@freescale.com>
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7 | 74c62ba8 | aurel32 | *
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8 | 74c62ba8 | aurel32 | * This file is derived from hw/ppc4xx_pci.c,
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9 | 74c62ba8 | aurel32 | * the copyright for that material belongs to the original owners.
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10 | 74c62ba8 | aurel32 | *
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11 | 74c62ba8 | aurel32 | * This is free software; you can redistribute it and/or modify
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12 | 74c62ba8 | aurel32 | * it under the terms of the GNU General Public License as published by
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13 | 74c62ba8 | aurel32 | * the Free Software Foundation; either version 2 of the License, or
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14 | 74c62ba8 | aurel32 | * (at your option) any later version.
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15 | 74c62ba8 | aurel32 | */
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16 | 74c62ba8 | aurel32 | |
17 | 74c62ba8 | aurel32 | #include "hw.h" |
18 | 74c62ba8 | aurel32 | #include "pci.h" |
19 | 74c62ba8 | aurel32 | #include "pci_host.h" |
20 | 74c62ba8 | aurel32 | #include "bswap.h" |
21 | 74c62ba8 | aurel32 | |
22 | 74c62ba8 | aurel32 | #ifdef DEBUG_PCI
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23 | 001faf32 | Blue Swirl | #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) |
24 | 74c62ba8 | aurel32 | #else
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25 | 001faf32 | Blue Swirl | #define pci_debug(fmt, ...)
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26 | 74c62ba8 | aurel32 | #endif
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27 | 74c62ba8 | aurel32 | |
28 | 74c62ba8 | aurel32 | #define PCIE500_CFGADDR 0x0 |
29 | 74c62ba8 | aurel32 | #define PCIE500_CFGDATA 0x4 |
30 | 74c62ba8 | aurel32 | #define PCIE500_REG_BASE 0xC00 |
31 | be13cc7a | Alexander Graf | #define PCIE500_ALL_SIZE 0x1000 |
32 | be13cc7a | Alexander Graf | #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
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33 | 74c62ba8 | aurel32 | |
34 | a1bc20df | Alexander Graf | #define PCIE500_PCI_IOLEN 0x10000ULL |
35 | a1bc20df | Alexander Graf | |
36 | 74c62ba8 | aurel32 | #define PPCE500_PCI_CONFIG_ADDR 0x0 |
37 | 74c62ba8 | aurel32 | #define PPCE500_PCI_CONFIG_DATA 0x4 |
38 | 74c62ba8 | aurel32 | #define PPCE500_PCI_INTACK 0x8 |
39 | 74c62ba8 | aurel32 | |
40 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE) |
41 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE) |
42 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE) |
43 | 74c62ba8 | aurel32 | #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE) |
44 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE) |
45 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE) |
46 | 74c62ba8 | aurel32 | #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE) |
47 | 74c62ba8 | aurel32 | |
48 | 74c62ba8 | aurel32 | #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE) |
49 | 74c62ba8 | aurel32 | |
50 | 74c62ba8 | aurel32 | #define PCI_POTAR 0x0 |
51 | 74c62ba8 | aurel32 | #define PCI_POTEAR 0x4 |
52 | 74c62ba8 | aurel32 | #define PCI_POWBAR 0x8 |
53 | 74c62ba8 | aurel32 | #define PCI_POWAR 0x10 |
54 | 74c62ba8 | aurel32 | |
55 | 74c62ba8 | aurel32 | #define PCI_PITAR 0x0 |
56 | 74c62ba8 | aurel32 | #define PCI_PIWBAR 0x8 |
57 | 74c62ba8 | aurel32 | #define PCI_PIWBEAR 0xC |
58 | 74c62ba8 | aurel32 | #define PCI_PIWAR 0x10 |
59 | 74c62ba8 | aurel32 | |
60 | 74c62ba8 | aurel32 | #define PPCE500_PCI_NR_POBS 5 |
61 | 74c62ba8 | aurel32 | #define PPCE500_PCI_NR_PIBS 3 |
62 | 74c62ba8 | aurel32 | |
63 | 74c62ba8 | aurel32 | struct pci_outbound {
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64 | 74c62ba8 | aurel32 | uint32_t potar; |
65 | 74c62ba8 | aurel32 | uint32_t potear; |
66 | 74c62ba8 | aurel32 | uint32_t powbar; |
67 | 74c62ba8 | aurel32 | uint32_t powar; |
68 | 74c62ba8 | aurel32 | }; |
69 | 74c62ba8 | aurel32 | |
70 | 74c62ba8 | aurel32 | struct pci_inbound {
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71 | 74c62ba8 | aurel32 | uint32_t pitar; |
72 | 74c62ba8 | aurel32 | uint32_t piwbar; |
73 | 74c62ba8 | aurel32 | uint32_t piwbear; |
74 | 74c62ba8 | aurel32 | uint32_t piwar; |
75 | 74c62ba8 | aurel32 | }; |
76 | 74c62ba8 | aurel32 | |
77 | 9c1a61f0 | Andreas Färber | #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost" |
78 | 9c1a61f0 | Andreas Färber | |
79 | 9c1a61f0 | Andreas Färber | #define PPC_E500_PCI_HOST_BRIDGE(obj) \
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80 | 9c1a61f0 | Andreas Färber | OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE) |
81 | 9c1a61f0 | Andreas Färber | |
82 | 74c62ba8 | aurel32 | struct PPCE500PCIState {
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83 | 67c332fd | Andreas Färber | PCIHostState parent_obj; |
84 | 9c1a61f0 | Andreas Färber | |
85 | 74c62ba8 | aurel32 | struct pci_outbound pob[PPCE500_PCI_NR_POBS];
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86 | 74c62ba8 | aurel32 | struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
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87 | 74c62ba8 | aurel32 | uint32_t gasket_time; |
88 | be13cc7a | Alexander Graf | qemu_irq irq[4];
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89 | be13cc7a | Alexander Graf | /* mmio maps */
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90 | cb4e15c7 | Benoît Canet | MemoryRegion container; |
91 | cd5cba79 | Avi Kivity | MemoryRegion iomem; |
92 | a1bc20df | Alexander Graf | MemoryRegion pio; |
93 | 74c62ba8 | aurel32 | }; |
94 | 74c62ba8 | aurel32 | |
95 | 74c62ba8 | aurel32 | typedef struct PPCE500PCIState PPCE500PCIState; |
96 | 74c62ba8 | aurel32 | |
97 | a8170e5e | Avi Kivity | static uint64_t pci_reg_read4(void *opaque, hwaddr addr, |
98 | cd5cba79 | Avi Kivity | unsigned size)
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99 | 74c62ba8 | aurel32 | { |
100 | 74c62ba8 | aurel32 | PPCE500PCIState *pci = opaque; |
101 | 74c62ba8 | aurel32 | unsigned long win; |
102 | 74c62ba8 | aurel32 | uint32_t value = 0;
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103 | eeae2e7b | Liu Yu-B13201 | int idx;
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104 | 74c62ba8 | aurel32 | |
105 | 74c62ba8 | aurel32 | win = addr & 0xfe0;
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106 | 74c62ba8 | aurel32 | |
107 | 74c62ba8 | aurel32 | switch (win) {
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108 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW1:
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109 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW2:
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110 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW3:
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111 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW4:
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112 | eeae2e7b | Liu Yu-B13201 | idx = (addr >> 5) & 0x7; |
113 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
114 | 6875dc8e | Liu Yu-B13201 | case PCI_POTAR:
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115 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].potar; |
116 | 6875dc8e | Liu Yu-B13201 | break;
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117 | 6875dc8e | Liu Yu-B13201 | case PCI_POTEAR:
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118 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].potear; |
119 | 6875dc8e | Liu Yu-B13201 | break;
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120 | 6875dc8e | Liu Yu-B13201 | case PCI_POWBAR:
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121 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].powbar; |
122 | 6875dc8e | Liu Yu-B13201 | break;
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123 | 6875dc8e | Liu Yu-B13201 | case PCI_POWAR:
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124 | eeae2e7b | Liu Yu-B13201 | value = pci->pob[idx].powar; |
125 | 6875dc8e | Liu Yu-B13201 | break;
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126 | 6875dc8e | Liu Yu-B13201 | default:
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127 | 6875dc8e | Liu Yu-B13201 | break;
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128 | 74c62ba8 | aurel32 | } |
129 | 74c62ba8 | aurel32 | break;
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130 | 74c62ba8 | aurel32 | |
131 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW3:
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132 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW2:
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133 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW1:
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134 | eeae2e7b | Liu Yu-B13201 | idx = ((addr >> 5) & 0x3) - 1; |
135 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
136 | 6875dc8e | Liu Yu-B13201 | case PCI_PITAR:
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137 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].pitar; |
138 | 6875dc8e | Liu Yu-B13201 | break;
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139 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBAR:
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140 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].piwbar; |
141 | 6875dc8e | Liu Yu-B13201 | break;
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142 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBEAR:
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143 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].piwbear; |
144 | 6875dc8e | Liu Yu-B13201 | break;
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145 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWAR:
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146 | eeae2e7b | Liu Yu-B13201 | value = pci->pib[idx].piwar; |
147 | 6875dc8e | Liu Yu-B13201 | break;
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148 | 6875dc8e | Liu Yu-B13201 | default:
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149 | 6875dc8e | Liu Yu-B13201 | break;
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150 | 74c62ba8 | aurel32 | }; |
151 | 74c62ba8 | aurel32 | break;
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152 | 74c62ba8 | aurel32 | |
153 | 74c62ba8 | aurel32 | case PPCE500_PCI_GASKET_TIMR:
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154 | 74c62ba8 | aurel32 | value = pci->gasket_time; |
155 | 74c62ba8 | aurel32 | break;
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156 | 74c62ba8 | aurel32 | |
157 | 74c62ba8 | aurel32 | default:
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158 | 74c62ba8 | aurel32 | break;
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159 | 74c62ba8 | aurel32 | } |
160 | 74c62ba8 | aurel32 | |
161 | c0a2a096 | Blue Swirl | pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, |
162 | c0a2a096 | Blue Swirl | win, addr, value); |
163 | 74c62ba8 | aurel32 | return value;
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164 | 74c62ba8 | aurel32 | } |
165 | 74c62ba8 | aurel32 | |
166 | a8170e5e | Avi Kivity | static void pci_reg_write4(void *opaque, hwaddr addr, |
167 | cd5cba79 | Avi Kivity | uint64_t value, unsigned size)
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168 | 74c62ba8 | aurel32 | { |
169 | 74c62ba8 | aurel32 | PPCE500PCIState *pci = opaque; |
170 | 74c62ba8 | aurel32 | unsigned long win; |
171 | eeae2e7b | Liu Yu-B13201 | int idx;
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172 | 74c62ba8 | aurel32 | |
173 | 74c62ba8 | aurel32 | win = addr & 0xfe0;
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174 | 74c62ba8 | aurel32 | |
175 | c0a2a096 | Blue Swirl | pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n", |
176 | cd5cba79 | Avi Kivity | __func__, (unsigned)value, win, addr);
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177 | 74c62ba8 | aurel32 | |
178 | 74c62ba8 | aurel32 | switch (win) {
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179 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW1:
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180 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW2:
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181 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW3:
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182 | 74c62ba8 | aurel32 | case PPCE500_PCI_OW4:
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183 | eeae2e7b | Liu Yu-B13201 | idx = (addr >> 5) & 0x7; |
184 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
185 | 6875dc8e | Liu Yu-B13201 | case PCI_POTAR:
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186 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].potar = value; |
187 | 6875dc8e | Liu Yu-B13201 | break;
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188 | 6875dc8e | Liu Yu-B13201 | case PCI_POTEAR:
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189 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].potear = value; |
190 | 6875dc8e | Liu Yu-B13201 | break;
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191 | 6875dc8e | Liu Yu-B13201 | case PCI_POWBAR:
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192 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].powbar = value; |
193 | 6875dc8e | Liu Yu-B13201 | break;
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194 | 6875dc8e | Liu Yu-B13201 | case PCI_POWAR:
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195 | eeae2e7b | Liu Yu-B13201 | pci->pob[idx].powar = value; |
196 | 6875dc8e | Liu Yu-B13201 | break;
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197 | 6875dc8e | Liu Yu-B13201 | default:
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198 | 6875dc8e | Liu Yu-B13201 | break;
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199 | 74c62ba8 | aurel32 | }; |
200 | 74c62ba8 | aurel32 | break;
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201 | 74c62ba8 | aurel32 | |
202 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW3:
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203 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW2:
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204 | 74c62ba8 | aurel32 | case PPCE500_PCI_IW1:
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205 | eeae2e7b | Liu Yu-B13201 | idx = ((addr >> 5) & 0x3) - 1; |
206 | 74c62ba8 | aurel32 | switch (addr & 0xC) { |
207 | 6875dc8e | Liu Yu-B13201 | case PCI_PITAR:
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208 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].pitar = value; |
209 | 6875dc8e | Liu Yu-B13201 | break;
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210 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBAR:
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211 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].piwbar = value; |
212 | 6875dc8e | Liu Yu-B13201 | break;
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213 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWBEAR:
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214 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].piwbear = value; |
215 | 6875dc8e | Liu Yu-B13201 | break;
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216 | 6875dc8e | Liu Yu-B13201 | case PCI_PIWAR:
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217 | eeae2e7b | Liu Yu-B13201 | pci->pib[idx].piwar = value; |
218 | 6875dc8e | Liu Yu-B13201 | break;
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219 | 6875dc8e | Liu Yu-B13201 | default:
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220 | 6875dc8e | Liu Yu-B13201 | break;
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221 | 74c62ba8 | aurel32 | }; |
222 | 74c62ba8 | aurel32 | break;
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223 | 74c62ba8 | aurel32 | |
224 | 74c62ba8 | aurel32 | case PPCE500_PCI_GASKET_TIMR:
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225 | 74c62ba8 | aurel32 | pci->gasket_time = value; |
226 | 74c62ba8 | aurel32 | break;
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227 | 74c62ba8 | aurel32 | |
228 | 74c62ba8 | aurel32 | default:
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229 | 74c62ba8 | aurel32 | break;
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230 | 74c62ba8 | aurel32 | }; |
231 | 74c62ba8 | aurel32 | } |
232 | 74c62ba8 | aurel32 | |
233 | cd5cba79 | Avi Kivity | static const MemoryRegionOps e500_pci_reg_ops = { |
234 | cd5cba79 | Avi Kivity | .read = pci_reg_read4, |
235 | cd5cba79 | Avi Kivity | .write = pci_reg_write4, |
236 | cd5cba79 | Avi Kivity | .endianness = DEVICE_BIG_ENDIAN, |
237 | 74c62ba8 | aurel32 | }; |
238 | 74c62ba8 | aurel32 | |
239 | 74c62ba8 | aurel32 | static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) |
240 | 74c62ba8 | aurel32 | { |
241 | 74c62ba8 | aurel32 | int devno = pci_dev->devfn >> 3, ret = 0; |
242 | 74c62ba8 | aurel32 | |
243 | 74c62ba8 | aurel32 | switch (devno) {
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244 | 74c62ba8 | aurel32 | /* Two PCI slot */
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245 | 74c62ba8 | aurel32 | case 0x11: |
246 | 74c62ba8 | aurel32 | case 0x12: |
247 | 74c62ba8 | aurel32 | ret = (irq_num + devno - 0x10) % 4; |
248 | 74c62ba8 | aurel32 | break;
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249 | 74c62ba8 | aurel32 | default:
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250 | 72b310e9 | Scott Wood | printf("Error:%s:unknown dev number\n", __func__);
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251 | 74c62ba8 | aurel32 | } |
252 | 74c62ba8 | aurel32 | |
253 | 74c62ba8 | aurel32 | pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
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254 | 74c62ba8 | aurel32 | pci_dev->devfn, irq_num, ret, devno); |
255 | 74c62ba8 | aurel32 | |
256 | 74c62ba8 | aurel32 | return ret;
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257 | 74c62ba8 | aurel32 | } |
258 | 74c62ba8 | aurel32 | |
259 | 5d4e84c8 | Juan Quintela | static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level) |
260 | 74c62ba8 | aurel32 | { |
261 | 5d4e84c8 | Juan Quintela | qemu_irq *pic = opaque; |
262 | 5d4e84c8 | Juan Quintela | |
263 | 74c62ba8 | aurel32 | pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
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264 | 74c62ba8 | aurel32 | |
265 | 74c62ba8 | aurel32 | qemu_set_irq(pic[irq_num], level); |
266 | 74c62ba8 | aurel32 | } |
267 | 74c62ba8 | aurel32 | |
268 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_pci_outbound = { |
269 | e0433ecc | Juan Quintela | .name = "pci_outbound",
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270 | e0433ecc | Juan Quintela | .version_id = 0,
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271 | e0433ecc | Juan Quintela | .minimum_version_id = 0,
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272 | e0433ecc | Juan Quintela | .minimum_version_id_old = 0,
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273 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
274 | e0433ecc | Juan Quintela | VMSTATE_UINT32(potar, struct pci_outbound),
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275 | e0433ecc | Juan Quintela | VMSTATE_UINT32(potear, struct pci_outbound),
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276 | e0433ecc | Juan Quintela | VMSTATE_UINT32(powbar, struct pci_outbound),
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277 | e0433ecc | Juan Quintela | VMSTATE_UINT32(powar, struct pci_outbound),
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278 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
279 | 74c62ba8 | aurel32 | } |
280 | e0433ecc | Juan Quintela | }; |
281 | 74c62ba8 | aurel32 | |
282 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_pci_inbound = { |
283 | e0433ecc | Juan Quintela | .name = "pci_inbound",
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284 | e0433ecc | Juan Quintela | .version_id = 0,
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285 | e0433ecc | Juan Quintela | .minimum_version_id = 0,
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286 | e0433ecc | Juan Quintela | .minimum_version_id_old = 0,
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287 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
288 | e0433ecc | Juan Quintela | VMSTATE_UINT32(pitar, struct pci_inbound),
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289 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwbar, struct pci_inbound),
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290 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwbear, struct pci_inbound),
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291 | e0433ecc | Juan Quintela | VMSTATE_UINT32(piwar, struct pci_inbound),
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292 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
293 | 74c62ba8 | aurel32 | } |
294 | e0433ecc | Juan Quintela | }; |
295 | 74c62ba8 | aurel32 | |
296 | e0433ecc | Juan Quintela | static const VMStateDescription vmstate_ppce500_pci = { |
297 | e0433ecc | Juan Quintela | .name = "ppce500_pci",
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298 | e0433ecc | Juan Quintela | .version_id = 1,
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299 | e0433ecc | Juan Quintela | .minimum_version_id = 1,
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300 | e0433ecc | Juan Quintela | .minimum_version_id_old = 1,
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301 | e0433ecc | Juan Quintela | .fields = (VMStateField[]) { |
302 | e0433ecc | Juan Quintela | VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
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303 | e0433ecc | Juan Quintela | vmstate_pci_outbound, struct pci_outbound),
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304 | e0433ecc | Juan Quintela | VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
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305 | e0433ecc | Juan Quintela | vmstate_pci_outbound, struct pci_inbound),
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306 | e0433ecc | Juan Quintela | VMSTATE_UINT32(gasket_time, PPCE500PCIState), |
307 | e0433ecc | Juan Quintela | VMSTATE_END_OF_LIST() |
308 | 74c62ba8 | aurel32 | } |
309 | e0433ecc | Juan Quintela | }; |
310 | 74c62ba8 | aurel32 | |
311 | 1e39101c | Avi Kivity | #include "exec-memory.h" |
312 | 1e39101c | Avi Kivity | |
313 | be13cc7a | Alexander Graf | static int e500_pcihost_initfn(SysBusDevice *dev) |
314 | be13cc7a | Alexander Graf | { |
315 | be13cc7a | Alexander Graf | PCIHostState *h; |
316 | be13cc7a | Alexander Graf | PPCE500PCIState *s; |
317 | be13cc7a | Alexander Graf | PCIBus *b; |
318 | be13cc7a | Alexander Graf | int i;
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319 | aee97b84 | Avi Kivity | MemoryRegion *address_space_mem = get_system_memory(); |
320 | be13cc7a | Alexander Graf | |
321 | 8558d942 | Andreas Färber | h = PCI_HOST_BRIDGE(dev); |
322 | 9c1a61f0 | Andreas Färber | s = PPC_E500_PCI_HOST_BRIDGE(dev); |
323 | be13cc7a | Alexander Graf | |
324 | be13cc7a | Alexander Graf | for (i = 0; i < ARRAY_SIZE(s->irq); i++) { |
325 | be13cc7a | Alexander Graf | sysbus_init_irq(dev, &s->irq[i]); |
326 | be13cc7a | Alexander Graf | } |
327 | be13cc7a | Alexander Graf | |
328 | a1bc20df | Alexander Graf | memory_region_init(&s->pio, "pci-pio", PCIE500_PCI_IOLEN);
|
329 | a1bc20df | Alexander Graf | |
330 | 9c1a61f0 | Andreas Färber | b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
|
331 | aee97b84 | Avi Kivity | mpc85xx_pci_map_irq, s->irq, address_space_mem, |
332 | a1bc20df | Alexander Graf | &s->pio, PCI_DEVFN(0x11, 0), 4); |
333 | 9c1a61f0 | Andreas Färber | h->bus = b; |
334 | be13cc7a | Alexander Graf | |
335 | be13cc7a | Alexander Graf | pci_create_simple(b, 0, "e500-host-bridge"); |
336 | be13cc7a | Alexander Graf | |
337 | cb4e15c7 | Benoît Canet | memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE);
|
338 | d0ed8076 | Avi Kivity | memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h, |
339 | d0ed8076 | Avi Kivity | "pci-conf-idx", 4); |
340 | d0ed8076 | Avi Kivity | memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h, |
341 | d0ed8076 | Avi Kivity | "pci-conf-data", 4); |
342 | cd5cba79 | Avi Kivity | memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s, |
343 | cd5cba79 | Avi Kivity | "pci.reg", PCIE500_REG_SIZE);
|
344 | cb4e15c7 | Benoît Canet | memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem); |
345 | cb4e15c7 | Benoît Canet | memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem); |
346 | cb4e15c7 | Benoît Canet | memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); |
347 | cb4e15c7 | Benoît Canet | sysbus_init_mmio(dev, &s->container); |
348 | a1bc20df | Alexander Graf | sysbus_init_mmio(dev, &s->pio); |
349 | be13cc7a | Alexander Graf | |
350 | be13cc7a | Alexander Graf | return 0; |
351 | be13cc7a | Alexander Graf | } |
352 | be13cc7a | Alexander Graf | |
353 | 40021f08 | Anthony Liguori | static void e500_host_bridge_class_init(ObjectClass *klass, void *data) |
354 | 40021f08 | Anthony Liguori | { |
355 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
356 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
357 | 40021f08 | Anthony Liguori | |
358 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_FREESCALE; |
359 | 40021f08 | Anthony Liguori | k->device_id = PCI_DEVICE_ID_MPC8533E; |
360 | 40021f08 | Anthony Liguori | k->class_id = PCI_CLASS_PROCESSOR_POWERPC; |
361 | 39bffca2 | Anthony Liguori | dc->desc = "Host bridge";
|
362 | 40021f08 | Anthony Liguori | } |
363 | 40021f08 | Anthony Liguori | |
364 | 4240abff | Andreas Färber | static const TypeInfo e500_host_bridge_info = { |
365 | 39bffca2 | Anthony Liguori | .name = "e500-host-bridge",
|
366 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
367 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PCIDevice),
|
368 | 39bffca2 | Anthony Liguori | .class_init = e500_host_bridge_class_init, |
369 | be13cc7a | Alexander Graf | }; |
370 | be13cc7a | Alexander Graf | |
371 | 999e12bb | Anthony Liguori | static void e500_pcihost_class_init(ObjectClass *klass, void *data) |
372 | 999e12bb | Anthony Liguori | { |
373 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
374 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
375 | 999e12bb | Anthony Liguori | |
376 | 999e12bb | Anthony Liguori | k->init = e500_pcihost_initfn; |
377 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_ppce500_pci; |
378 | 999e12bb | Anthony Liguori | } |
379 | 999e12bb | Anthony Liguori | |
380 | 4240abff | Andreas Färber | static const TypeInfo e500_pcihost_info = { |
381 | 9c1a61f0 | Andreas Färber | .name = TYPE_PPC_E500_PCI_HOST_BRIDGE, |
382 | 8558d942 | Andreas Färber | .parent = TYPE_PCI_HOST_BRIDGE, |
383 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PPCE500PCIState),
|
384 | 39bffca2 | Anthony Liguori | .class_init = e500_pcihost_class_init, |
385 | be13cc7a | Alexander Graf | }; |
386 | be13cc7a | Alexander Graf | |
387 | 83f7d43a | Andreas Färber | static void e500_pci_register_types(void) |
388 | 74c62ba8 | aurel32 | { |
389 | 39bffca2 | Anthony Liguori | type_register_static(&e500_pcihost_info); |
390 | 39bffca2 | Anthony Liguori | type_register_static(&e500_host_bridge_info); |
391 | 74c62ba8 | aurel32 | } |
392 | 83f7d43a | Andreas Färber | |
393 | 83f7d43a | Andreas Färber | type_init(e500_pci_register_types) |