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root / target-arm @ b305dba6

Name Size
Makefile.objs 465 Bytes
arm-semi.c 17.2 kB
cpu-qom.h 5.9 kB
cpu.c 32.5 kB
cpu.h 38.6 kB
cpu64.c 3.5 kB
crypto_helper.c 13 kB
gdbstub.c 2.8 kB
gdbstub64.c 1.9 kB
helper-a64.c 4.3 kB
helper-a64.h 1.4 kB
helper.c 143.4 kB
helper.h 18.8 kB
iwmmxt_helper.c 24.8 kB
kvm-consts.h 3.8 kB
kvm-stub.c 437 Bytes
kvm.c 9.4 kB
kvm32.c 15.7 kB
kvm64.c 5.2 kB
kvm_arm.h 3.8 kB
machine.c 7.9 kB
neon_helper.c 52.4 kB
op_addsub.h 1.8 kB
op_helper.c 8.9 kB
translate-a64.c 187.4 kB
translate.c 375.8 kB
translate.h 1.9 kB

Latest revisions

# Date Author Comment
a08582f4 01/31/2014 04:47 pm Peter Maydell

target-arm: A64: Add SIMD three-different multiply accumulate insns

Add support for the multiply-accumulate instructions from the
SIMD three-different instructions group (C3.6.15): * skeleton decode of unallocated encodings and split of
the group into its three sub-parts...
0ae39320 01/31/2014 04:47 pm Peter Maydell

target-arm: A64: Add SIMD three-different ABDL instructions

Implement the absolute-difference instructions in the SIMD
three-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL,
SABDL2, UABDL, UABDL2.

Signed-off-by: Peter Maydell <>...
b305dba6 01/31/2014 04:47 pm Peter Maydell

target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops

Implement the add, sub and compare ops from the SIMD "scalar three same"
group.

Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>
43630e58 01/31/2014 04:47 pm Will Newton

target-arm: Add set_neon_rmode helper

This helper sets the rounding mode in the standard_fp_status word to
allow NEON instructions to modify the rounding mode whilst using the
standard FPSCR values for everything else.

Signed-off-by: Will Newton <>...
34f7b0a2 01/31/2014 04:47 pm Will Newton

target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ

Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP
VRINTM and VRINTZ instructions.

Signed-off-by: Will Newton <>
Signed-off-by: Peter Maydell <>
c9975a83 01/31/2014 04:47 pm Will Newton

target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM

Add support for the AArch32 floating-point VCVTA, VCVTN, VCVTP
and VCVTM instructions.

Signed-off-by: Will Newton <>
Signed-off-by: Peter Maydell <>
901ad525 01/31/2014 04:47 pm Will Newton

target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM

Add support for the AArch32 Advanced SIMD VCVTA, VCVTN, VCVTP
and VCVTM instructions.

Signed-off-by: Will Newton <>
Signed-off-by: Peter Maydell <>
a290c62a 01/31/2014 04:47 pm Will Newton

target-arm: Add support for AArch32 FP VRINTZ

Add support for the AArch32 floating-point VRINTZ instruction.

Signed-off-by: Will Newton <>
Signed-off-by: Peter Maydell <>
4e82bc01 01/31/2014 04:47 pm Will Newton

target-arm: Add support for AArch32 FP VRINTX

Add support for the AArch32 floating-point VRINTX instruction.

Signed-off-by: Will Newton <>
Signed-off-by: Peter Maydell <>
2ce70625 01/31/2014 04:47 pm Will Newton

target-arm: Add support for AArch32 SIMD VRINTX

Add support for the AArch32 Advanced SIMD VRINTX instruction.

Signed-off-by: Will Newton <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Peter Maydell <>

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