root / hw / grackle_pci.c @ b31442c3
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1 | 502a5395 | pbrook | /*
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2 | 3cbee15b | j_mayer | * QEMU Grackle PCI host (heathrow OldWorld PowerMac)
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3 | 502a5395 | pbrook | *
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4 | 3cbee15b | j_mayer | * Copyright (c) 2006-2007 Fabrice Bellard
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5 | 3cbee15b | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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6 | 5fafdf24 | ths | *
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7 | 502a5395 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 502a5395 | pbrook | * of this software and associated documentation files (the "Software"), to deal
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9 | 502a5395 | pbrook | * in the Software without restriction, including without limitation the rights
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10 | 502a5395 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 502a5395 | pbrook | * copies of the Software, and to permit persons to whom the Software is
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12 | 502a5395 | pbrook | * furnished to do so, subject to the following conditions:
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13 | 502a5395 | pbrook | *
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14 | 502a5395 | pbrook | * The above copyright notice and this permission notice shall be included in
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15 | 502a5395 | pbrook | * all copies or substantial portions of the Software.
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16 | 502a5395 | pbrook | *
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17 | 502a5395 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 502a5395 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 502a5395 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 502a5395 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 502a5395 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 502a5395 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 502a5395 | pbrook | * THE SOFTWARE.
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24 | 502a5395 | pbrook | */
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25 | 502a5395 | pbrook | |
26 | 426f17bb | Blue Swirl | #include "sysbus.h" |
27 | 3cbee15b | j_mayer | #include "ppc_mac.h" |
28 | 87ecb68b | pbrook | #include "pci.h" |
29 | 87ecb68b | pbrook | |
30 | ea026b2f | blueswir1 | /* debug Grackle */
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31 | ea026b2f | blueswir1 | //#define DEBUG_GRACKLE
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32 | ea026b2f | blueswir1 | |
33 | ea026b2f | blueswir1 | #ifdef DEBUG_GRACKLE
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34 | 001faf32 | Blue Swirl | #define GRACKLE_DPRINTF(fmt, ...) \
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35 | 001faf32 | Blue Swirl | do { printf("GRACKLE: " fmt , ## __VA_ARGS__); } while (0) |
36 | ea026b2f | blueswir1 | #else
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37 | 001faf32 | Blue Swirl | #define GRACKLE_DPRINTF(fmt, ...)
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38 | ea026b2f | blueswir1 | #endif
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39 | ea026b2f | blueswir1 | |
40 | 502a5395 | pbrook | typedef target_phys_addr_t pci_addr_t;
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41 | 502a5395 | pbrook | #include "pci_host.h" |
42 | 502a5395 | pbrook | |
43 | 426f17bb | Blue Swirl | typedef struct GrackleState { |
44 | 426f17bb | Blue Swirl | SysBusDevice busdev; |
45 | 426f17bb | Blue Swirl | PCIHostState host_state; |
46 | 426f17bb | Blue Swirl | } GrackleState; |
47 | 502a5395 | pbrook | |
48 | 502a5395 | pbrook | static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr, |
49 | 502a5395 | pbrook | uint32_t val) |
50 | 502a5395 | pbrook | { |
51 | 502a5395 | pbrook | GrackleState *s = opaque; |
52 | ea026b2f | blueswir1 | |
53 | ea026b2f | blueswir1 | GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr, |
54 | ea026b2f | blueswir1 | val); |
55 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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56 | 502a5395 | pbrook | val = bswap32(val); |
57 | 502a5395 | pbrook | #endif
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58 | 426f17bb | Blue Swirl | s->host_state.config_reg = val; |
59 | 502a5395 | pbrook | } |
60 | 502a5395 | pbrook | |
61 | 502a5395 | pbrook | static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr) |
62 | 502a5395 | pbrook | { |
63 | 502a5395 | pbrook | GrackleState *s = opaque; |
64 | 502a5395 | pbrook | uint32_t val; |
65 | 502a5395 | pbrook | |
66 | 426f17bb | Blue Swirl | val = s->host_state.config_reg; |
67 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
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68 | 502a5395 | pbrook | val = bswap32(val); |
69 | 502a5395 | pbrook | #endif
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70 | ea026b2f | blueswir1 | GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr, |
71 | ea026b2f | blueswir1 | val); |
72 | 502a5395 | pbrook | return val;
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73 | 502a5395 | pbrook | } |
74 | 502a5395 | pbrook | |
75 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pci_grackle_config_write[] = { |
76 | 502a5395 | pbrook | &pci_grackle_config_writel, |
77 | 502a5395 | pbrook | &pci_grackle_config_writel, |
78 | 502a5395 | pbrook | &pci_grackle_config_writel, |
79 | 502a5395 | pbrook | }; |
80 | 502a5395 | pbrook | |
81 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pci_grackle_config_read[] = { |
82 | 502a5395 | pbrook | &pci_grackle_config_readl, |
83 | 502a5395 | pbrook | &pci_grackle_config_readl, |
84 | 502a5395 | pbrook | &pci_grackle_config_readl, |
85 | 502a5395 | pbrook | }; |
86 | 502a5395 | pbrook | |
87 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const pci_grackle_write[] = { |
88 | 502a5395 | pbrook | &pci_host_data_writeb, |
89 | 502a5395 | pbrook | &pci_host_data_writew, |
90 | 502a5395 | pbrook | &pci_host_data_writel, |
91 | 502a5395 | pbrook | }; |
92 | 502a5395 | pbrook | |
93 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const pci_grackle_read[] = { |
94 | 502a5395 | pbrook | &pci_host_data_readb, |
95 | 502a5395 | pbrook | &pci_host_data_readw, |
96 | 502a5395 | pbrook | &pci_host_data_readl, |
97 | 502a5395 | pbrook | }; |
98 | 502a5395 | pbrook | |
99 | d2b59317 | pbrook | /* Don't know if this matches real hardware, but it agrees with OHW. */
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100 | d2b59317 | pbrook | static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num) |
101 | 502a5395 | pbrook | { |
102 | d2b59317 | pbrook | return (irq_num + (pci_dev->devfn >> 3)) & 3; |
103 | d2b59317 | pbrook | } |
104 | d2b59317 | pbrook | |
105 | d537cf6c | pbrook | static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level) |
106 | d2b59317 | pbrook | { |
107 | ea026b2f | blueswir1 | GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
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108 | 3cbee15b | j_mayer | qemu_set_irq(pic[irq_num + 0x15], level);
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109 | 502a5395 | pbrook | } |
110 | 502a5395 | pbrook | |
111 | 9b64997f | blueswir1 | static void pci_grackle_save(QEMUFile* f, void *opaque) |
112 | 9b64997f | blueswir1 | { |
113 | 9b64997f | blueswir1 | PCIDevice *d = opaque; |
114 | 9b64997f | blueswir1 | |
115 | 9b64997f | blueswir1 | pci_device_save(d, f); |
116 | 9b64997f | blueswir1 | } |
117 | 9b64997f | blueswir1 | |
118 | 9b64997f | blueswir1 | static int pci_grackle_load(QEMUFile* f, void *opaque, int version_id) |
119 | 9b64997f | blueswir1 | { |
120 | 9b64997f | blueswir1 | PCIDevice *d = opaque; |
121 | 9b64997f | blueswir1 | |
122 | 9b64997f | blueswir1 | if (version_id != 1) |
123 | 9b64997f | blueswir1 | return -EINVAL;
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124 | 9b64997f | blueswir1 | |
125 | 9b64997f | blueswir1 | return pci_device_load(d, f);
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126 | 9b64997f | blueswir1 | } |
127 | 9b64997f | blueswir1 | |
128 | 6e6b7363 | blueswir1 | static void pci_grackle_reset(void *opaque) |
129 | 6e6b7363 | blueswir1 | { |
130 | 6e6b7363 | blueswir1 | } |
131 | 6e6b7363 | blueswir1 | |
132 | d537cf6c | pbrook | PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic) |
133 | 502a5395 | pbrook | { |
134 | 426f17bb | Blue Swirl | DeviceState *dev; |
135 | 426f17bb | Blue Swirl | SysBusDevice *s; |
136 | 426f17bb | Blue Swirl | GrackleState *d; |
137 | 426f17bb | Blue Swirl | |
138 | 426f17bb | Blue Swirl | dev = qdev_create(NULL, "grackle"); |
139 | 426f17bb | Blue Swirl | qdev_init(dev); |
140 | 426f17bb | Blue Swirl | s = sysbus_from_qdev(dev); |
141 | 426f17bb | Blue Swirl | d = FROM_SYSBUS(GrackleState, s); |
142 | 426f17bb | Blue Swirl | d->host_state.bus = pci_register_bus(NULL, "pci", |
143 | 426f17bb | Blue Swirl | pci_grackle_set_irq, |
144 | 426f17bb | Blue Swirl | pci_grackle_map_irq, |
145 | 426f17bb | Blue Swirl | pic, 0, 4); |
146 | 426f17bb | Blue Swirl | |
147 | 426f17bb | Blue Swirl | pci_create_simple(d->host_state.bus, 0, "grackle"); |
148 | 426f17bb | Blue Swirl | |
149 | 426f17bb | Blue Swirl | sysbus_mmio_map(s, 0, base);
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150 | 426f17bb | Blue Swirl | sysbus_mmio_map(s, 1, base + 0x00200000); |
151 | 426f17bb | Blue Swirl | |
152 | 426f17bb | Blue Swirl | return d->host_state.bus;
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153 | 426f17bb | Blue Swirl | } |
154 | 426f17bb | Blue Swirl | |
155 | 426f17bb | Blue Swirl | static void pci_grackle_init_device(SysBusDevice *dev) |
156 | 426f17bb | Blue Swirl | { |
157 | 426f17bb | Blue Swirl | GrackleState *s; |
158 | 426f17bb | Blue Swirl | int pci_mem_config, pci_mem_data;
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159 | 426f17bb | Blue Swirl | |
160 | 426f17bb | Blue Swirl | s = FROM_SYSBUS(GrackleState, dev); |
161 | 426f17bb | Blue Swirl | |
162 | 426f17bb | Blue Swirl | pci_mem_config = cpu_register_io_memory(pci_grackle_config_read, |
163 | 426f17bb | Blue Swirl | pci_grackle_config_write, s); |
164 | 426f17bb | Blue Swirl | pci_mem_data = cpu_register_io_memory(pci_grackle_read, |
165 | 426f17bb | Blue Swirl | pci_grackle_write, |
166 | 426f17bb | Blue Swirl | &s->host_state); |
167 | 426f17bb | Blue Swirl | sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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168 | 426f17bb | Blue Swirl | sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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169 | 426f17bb | Blue Swirl | |
170 | 426f17bb | Blue Swirl | register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load, |
171 | 426f17bb | Blue Swirl | &s->host_state); |
172 | 426f17bb | Blue Swirl | qemu_register_reset(pci_grackle_reset, &s->host_state); |
173 | 426f17bb | Blue Swirl | pci_grackle_reset(&s->host_state); |
174 | 426f17bb | Blue Swirl | } |
175 | 426f17bb | Blue Swirl | |
176 | 426f17bb | Blue Swirl | static void pci_dec_21154_init_device(SysBusDevice *dev) |
177 | 426f17bb | Blue Swirl | { |
178 | 502a5395 | pbrook | GrackleState *s; |
179 | 502a5395 | pbrook | int pci_mem_config, pci_mem_data;
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180 | 502a5395 | pbrook | |
181 | 426f17bb | Blue Swirl | s = FROM_SYSBUS(GrackleState, dev); |
182 | 502a5395 | pbrook | |
183 | 1eed09cb | Avi Kivity | pci_mem_config = cpu_register_io_memory(pci_grackle_config_read, |
184 | 502a5395 | pbrook | pci_grackle_config_write, s); |
185 | 1eed09cb | Avi Kivity | pci_mem_data = cpu_register_io_memory(pci_grackle_read, |
186 | 426f17bb | Blue Swirl | pci_grackle_write, |
187 | 426f17bb | Blue Swirl | &s->host_state); |
188 | 426f17bb | Blue Swirl | sysbus_init_mmio(dev, 0x1000, pci_mem_config);
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189 | 426f17bb | Blue Swirl | sysbus_init_mmio(dev, 0x1000, pci_mem_data);
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190 | 426f17bb | Blue Swirl | } |
191 | 426f17bb | Blue Swirl | |
192 | 426f17bb | Blue Swirl | static void grackle_pci_host_init(PCIDevice *d) |
193 | 426f17bb | Blue Swirl | { |
194 | deb54399 | aliguori | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA); |
195 | deb54399 | aliguori | pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106); |
196 | 502a5395 | pbrook | d->config[0x08] = 0x00; // revision |
197 | 502a5395 | pbrook | d->config[0x09] = 0x01; |
198 | 173a543b | blueswir1 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); |
199 | 6407f373 | Isaku Yamahata | d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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200 | 426f17bb | Blue Swirl | } |
201 | 502a5395 | pbrook | |
202 | 426f17bb | Blue Swirl | static void dec_21154_pci_host_init(PCIDevice *d) |
203 | 426f17bb | Blue Swirl | { |
204 | 502a5395 | pbrook | /* PCI2PCI bridge same values as PearPC - check this */
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205 | 4ebcf884 | blueswir1 | pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC); |
206 | 4ebcf884 | blueswir1 | pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154); |
207 | 502a5395 | pbrook | d->config[0x08] = 0x02; // revision |
208 | 173a543b | blueswir1 | pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); |
209 | 6407f373 | Isaku Yamahata | d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
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210 | 502a5395 | pbrook | |
211 | 502a5395 | pbrook | d->config[0x18] = 0x0; // primary_bus |
212 | 502a5395 | pbrook | d->config[0x19] = 0x1; // secondary_bus |
213 | 502a5395 | pbrook | d->config[0x1a] = 0x1; // subordinate_bus |
214 | 502a5395 | pbrook | d->config[0x1c] = 0x10; // io_base |
215 | 502a5395 | pbrook | d->config[0x1d] = 0x20; // io_limit |
216 | 3b46e624 | ths | |
217 | 502a5395 | pbrook | d->config[0x20] = 0x80; // memory_base |
218 | 502a5395 | pbrook | d->config[0x21] = 0x80; |
219 | 502a5395 | pbrook | d->config[0x22] = 0x90; // memory_limit |
220 | 502a5395 | pbrook | d->config[0x23] = 0x80; |
221 | 3b46e624 | ths | |
222 | 502a5395 | pbrook | d->config[0x24] = 0x00; // prefetchable_memory_base |
223 | 502a5395 | pbrook | d->config[0x25] = 0x84; |
224 | 502a5395 | pbrook | d->config[0x26] = 0x00; // prefetchable_memory_limit |
225 | 502a5395 | pbrook | d->config[0x27] = 0x85; |
226 | 426f17bb | Blue Swirl | } |
227 | 426f17bb | Blue Swirl | |
228 | 426f17bb | Blue Swirl | static PCIDeviceInfo grackle_pci_host_info = {
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229 | 426f17bb | Blue Swirl | .qdev.name = "grackle",
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230 | 426f17bb | Blue Swirl | .qdev.size = sizeof(PCIDevice),
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231 | 426f17bb | Blue Swirl | .init = grackle_pci_host_init, |
232 | 426f17bb | Blue Swirl | }; |
233 | 6e6b7363 | blueswir1 | |
234 | 426f17bb | Blue Swirl | static PCIDeviceInfo dec_21154_pci_host_info = {
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235 | 426f17bb | Blue Swirl | .qdev.name = "DEC 21154",
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236 | 426f17bb | Blue Swirl | .qdev.size = sizeof(PCIDevice),
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237 | 426f17bb | Blue Swirl | .init = dec_21154_pci_host_init, |
238 | 426f17bb | Blue Swirl | }; |
239 | 426f17bb | Blue Swirl | |
240 | 426f17bb | Blue Swirl | static void grackle_register_devices(void) |
241 | 426f17bb | Blue Swirl | { |
242 | 426f17bb | Blue Swirl | sysbus_register_dev("grackle", sizeof(GrackleState), |
243 | 426f17bb | Blue Swirl | pci_grackle_init_device); |
244 | 426f17bb | Blue Swirl | pci_qdev_register(&grackle_pci_host_info); |
245 | 426f17bb | Blue Swirl | sysbus_register_dev("DEC 21154", sizeof(GrackleState), |
246 | 426f17bb | Blue Swirl | pci_dec_21154_init_device); |
247 | 426f17bb | Blue Swirl | pci_qdev_register(&dec_21154_pci_host_info); |
248 | 502a5395 | pbrook | } |
249 | 426f17bb | Blue Swirl | |
250 | 426f17bb | Blue Swirl | device_init(grackle_register_devices) |