root / target-ppc / cpu.h @ b33c17e1
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/*
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* PowerPC emulation cpu definitions for qemu.
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*
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* Copyright (c) 2003-2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#if !defined (__CPU_PPC_H__)
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#define __CPU_PPC_H__
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#include "config.h" |
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#include <inttypes.h> |
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#if defined (TARGET_PPC64)
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typedef uint64_t ppc_gpr_t;
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#define TARGET_GPR_BITS 64 |
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#define TARGET_LONG_BITS 64 |
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#define REGX "%016" PRIx64 |
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#define TARGET_PAGE_BITS 12 |
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#elif defined(TARGET_PPCEMB)
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/* BookE have 36 bits physical address space */
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#define TARGET_PHYS_ADDR_BITS 64 |
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/* GPR are 64 bits: used by vector extension */
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typedef uint64_t ppc_gpr_t;
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#define TARGET_GPR_BITS 64 |
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#define TARGET_LONG_BITS 32 |
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#define REGX "%016" PRIx64 |
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#if defined(CONFIG_USER_ONLY)
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/* It looks like a lot of Linux programs assume page size
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* is 4kB long. This is evil, but we have to deal with it...
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*/
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#define TARGET_PAGE_BITS 12 |
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#else
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/* Pages can be 1 kB small */
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#define TARGET_PAGE_BITS 10 |
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#endif
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#else
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#if (HOST_LONG_BITS >= 64) |
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/* When using 64 bits temporary registers,
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* we can use 64 bits GPR with no extra cost
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* It's even an optimization as it will prevent
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* the compiler to do unuseful masking in the micro-ops.
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*/
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typedef uint64_t ppc_gpr_t;
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#define TARGET_GPR_BITS 64 |
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#define REGX "%08" PRIx64 |
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#else
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typedef uint32_t ppc_gpr_t;
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#define TARGET_GPR_BITS 32 |
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#define REGX "%08" PRIx32 |
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#endif
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#define TARGET_LONG_BITS 32 |
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#define TARGET_PAGE_BITS 12 |
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#endif
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#include "cpu-defs.h" |
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#define ADDRX TARGET_FMT_lx
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#define PADDRX TARGET_FMT_plx
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#include <setjmp.h> |
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#include "softfloat.h" |
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#define TARGET_HAS_ICE 1 |
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#if defined (TARGET_PPC64)
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#define ELF_MACHINE EM_PPC64
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#else
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#define ELF_MACHINE EM_PPC
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#endif
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/*****************************************************************************/
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/* MMU model */
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enum {
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POWERPC_MMU_UNKNOWN = 0,
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/* Standard 32 bits PowerPC MMU */
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POWERPC_MMU_32B, |
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/* PowerPC 601 MMU */
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POWERPC_MMU_601, |
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/* PowerPC 6xx MMU with software TLB */
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POWERPC_MMU_SOFT_6xx, |
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/* PowerPC 74xx MMU with software TLB */
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POWERPC_MMU_SOFT_74xx, |
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/* PowerPC 4xx MMU with software TLB */
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POWERPC_MMU_SOFT_4xx, |
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/* PowerPC 4xx MMU with software TLB and zones protections */
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POWERPC_MMU_SOFT_4xx_Z, |
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/* PowerPC 4xx MMU in real mode only */
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POWERPC_MMU_REAL_4xx, |
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/* BookE MMU model */
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POWERPC_MMU_BOOKE, |
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/* BookE FSL MMU model */
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POWERPC_MMU_BOOKE_FSL, |
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#if defined(TARGET_PPC64)
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/* 64 bits PowerPC MMU */
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POWERPC_MMU_64B, |
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#endif /* defined(TARGET_PPC64) */ |
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}; |
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/*****************************************************************************/
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/* Exception model */
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enum {
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POWERPC_EXCP_UNKNOWN = 0,
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/* Standard PowerPC exception model */
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POWERPC_EXCP_STD, |
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/* PowerPC 40x exception model */
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POWERPC_EXCP_40x, |
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/* PowerPC 601 exception model */
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POWERPC_EXCP_601, |
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/* PowerPC 602 exception model */
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POWERPC_EXCP_602, |
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/* PowerPC 603 exception model */
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POWERPC_EXCP_603, |
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/* PowerPC 603e exception model */
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POWERPC_EXCP_603E, |
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/* PowerPC G2 exception model */
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POWERPC_EXCP_G2, |
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/* PowerPC 604 exception model */
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POWERPC_EXCP_604, |
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/* PowerPC 7x0 exception model */
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POWERPC_EXCP_7x0, |
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/* PowerPC 7x5 exception model */
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POWERPC_EXCP_7x5, |
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/* PowerPC 74xx exception model */
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POWERPC_EXCP_74xx, |
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/* BookE exception model */
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POWERPC_EXCP_BOOKE, |
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#if defined(TARGET_PPC64)
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/* PowerPC 970 exception model */
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POWERPC_EXCP_970, |
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#endif /* defined(TARGET_PPC64) */ |
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}; |
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/*****************************************************************************/
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/* Exception vectors definitions */
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enum {
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POWERPC_EXCP_NONE = -1,
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/* The 64 first entries are used by the PowerPC embedded specification */
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POWERPC_EXCP_CRITICAL = 0, /* Critical input */ |
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POWERPC_EXCP_MCHECK = 1, /* Machine check exception */ |
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POWERPC_EXCP_DSI = 2, /* Data storage exception */ |
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POWERPC_EXCP_ISI = 3, /* Instruction storage exception */ |
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POWERPC_EXCP_EXTERNAL = 4, /* External input */ |
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POWERPC_EXCP_ALIGN = 5, /* Alignment exception */ |
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POWERPC_EXCP_PROGRAM = 6, /* Program exception */ |
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POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */ |
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POWERPC_EXCP_SYSCALL = 8, /* System call exception */ |
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POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */ |
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POWERPC_EXCP_DECR = 10, /* Decrementer exception */ |
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POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */ |
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POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */ |
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POWERPC_EXCP_DTLB = 13, /* Data TLB error */ |
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POWERPC_EXCP_ITLB = 14, /* Instruction TLB error */ |
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POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */ |
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/* Vectors 16 to 31 are reserved */
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#if defined(TARGET_PPCEMB)
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POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */ |
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POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */ |
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POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */ |
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POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */ |
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POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */ |
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POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */ |
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#endif /* defined(TARGET_PPCEMB) */ |
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/* Vectors 38 to 63 are reserved */
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/* Exceptions defined in the PowerPC server specification */
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POWERPC_EXCP_RESET = 64, /* System reset exception */ |
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#if defined(TARGET_PPC64) /* PowerPC 64 */ |
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POWERPC_EXCP_DSEG = 65, /* Data segment exception */ |
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POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */ |
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#endif /* defined(TARGET_PPC64) */ |
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#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */ |
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POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */ |
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#endif /* defined(TARGET_PPC64H) */ |
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POWERPC_EXCP_TRACE = 68, /* Trace exception */ |
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#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */ |
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POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */ |
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POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */ |
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POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */ |
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POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */ |
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#endif /* defined(TARGET_PPC64H) */ |
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POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */ |
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/* 40x specific exceptions */
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POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */ |
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/* 601 specific exceptions */
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POWERPC_EXCP_IO = 75, /* IO error exception */ |
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POWERPC_EXCP_RUNM = 76, /* Run mode exception */ |
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/* 602 specific exceptions */
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POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */ |
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/* 602/603 specific exceptions */
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POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB error */ |
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POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */ |
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POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */ |
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/* Exceptions available on most PowerPC */
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POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */ |
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POWERPC_EXCP_IABR = 82, /* Instruction address breakpoint */ |
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POWERPC_EXCP_SMI = 83, /* System management interrupt */ |
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POWERPC_EXCP_PERFM = 84, /* Embedded performance monitor interrupt */ |
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/* 7xx/74xx specific exceptions */
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POWERPC_EXCP_THERM = 85, /* Thermal interrupt */ |
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/* 74xx specific exceptions */
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POWERPC_EXCP_VPUA = 86, /* Vector assist exception */ |
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/* 970FX specific exceptions */
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POWERPC_EXCP_SOFTP = 87, /* Soft patch exception */ |
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POWERPC_EXCP_MAINT = 88, /* Maintenance exception */ |
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/* EOL */
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POWERPC_EXCP_NB = 96,
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/* Qemu exceptions: used internally during code translation */
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POWERPC_EXCP_STOP = 0x200, /* stop translation */ |
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POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ |
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/* Qemu exceptions: special cases we want to stop translation */
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POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ |
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POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ |
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}; |
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/* Exceptions error codes */
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enum {
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/* Exception subtypes for POWERPC_EXCP_ALIGN */
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POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
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POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
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POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
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POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
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POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
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POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
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/* Exception subtypes for POWERPC_EXCP_PROGRAM */
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/* FP exceptions */
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POWERPC_EXCP_FP = 0x10,
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POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */ |
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POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */ |
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POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
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POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */ |
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POWERPC_EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ |
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POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ |
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POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
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POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
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POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
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POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
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POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
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POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
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POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
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/* Invalid instruction */
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POWERPC_EXCP_INVAL = 0x20,
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POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
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POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
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POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
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POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
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/* Privileged instruction */
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POWERPC_EXCP_PRIV = 0x30,
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POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ |
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POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */ |
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/* Trap */
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POWERPC_EXCP_TRAP = 0x40,
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}; |
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/*****************************************************************************/
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/* Input pins model */
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enum {
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PPC_FLAGS_INPUT_UNKNOWN = 0,
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/* PowerPC 6xx bus */
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PPC_FLAGS_INPUT_6xx, |
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/* BookE bus */
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PPC_FLAGS_INPUT_BookE, |
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/* PowerPC 405 bus */
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PPC_FLAGS_INPUT_405, |
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/* PowerPC 970 bus */
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PPC_FLAGS_INPUT_970, |
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/* PowerPC 401 bus */
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PPC_FLAGS_INPUT_401, |
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}; |
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#define PPC_INPUT(env) (env->bus_model)
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/*****************************************************************************/
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typedef struct ppc_def_t ppc_def_t; |
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typedef struct opc_handler_t opc_handler_t; |
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/*****************************************************************************/
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/* Types used to describe some PowerPC registers */
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typedef struct CPUPPCState CPUPPCState; |
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typedef struct ppc_tb_t ppc_tb_t; |
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typedef struct ppc_spr_t ppc_spr_t; |
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typedef struct ppc_dcr_t ppc_dcr_t; |
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typedef struct ppc_avr_t ppc_avr_t; |
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typedef union ppc_tlb_t ppc_tlb_t; |
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/* SPR access micro-ops generations callbacks */
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struct ppc_spr_t {
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void (*uea_read)(void *opaque, int spr_num); |
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void (*uea_write)(void *opaque, int spr_num); |
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#if !defined(CONFIG_USER_ONLY)
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void (*oea_read)(void *opaque, int spr_num); |
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void (*oea_write)(void *opaque, int spr_num); |
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#if defined(TARGET_PPC64H)
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void (*hea_read)(void *opaque, int spr_num); |
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void (*hea_write)(void *opaque, int spr_num); |
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#endif
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#endif
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const unsigned char *name; |
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}; |
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/* Altivec registers (128 bits) */
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struct ppc_avr_t {
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uint32_t u[4];
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}; |
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/* Software TLB cache */
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typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; |
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struct ppc6xx_tlb_t {
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target_ulong pte0; |
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target_ulong pte1; |
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target_ulong EPN; |
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}; |
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typedef struct ppcemb_tlb_t ppcemb_tlb_t; |
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struct ppcemb_tlb_t {
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target_phys_addr_t RPN; |
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target_ulong EPN; |
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target_ulong PID; |
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target_ulong size; |
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uint32_t prot; |
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uint32_t attr; /* Storage attributes */
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}; |
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union ppc_tlb_t {
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ppc6xx_tlb_t tlb6; |
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ppcemb_tlb_t tlbe; |
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}; |
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/*****************************************************************************/
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/* Machine state register bits definition */
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#define MSR_SF 63 /* Sixty-four-bit mode hflags */ |
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#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
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#define MSR_HV 60 /* hypervisor state hflags */ |
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#define MSR_CM 31 /* Computation mode for BookE hflags */ |
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#define MSR_ICM 30 /* Interrupt computation mode for BookE */ |
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#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ |
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#define MSR_VR 25 /* altivec available x hflags */ |
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#define MSR_SPE 25 /* SPE enable for BookE x hflags */ |
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#define MSR_AP 23 /* Access privilege state on 602 hflags */ |
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#define MSR_SA 22 /* Supervisor access mode on 602 hflags */ |
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#define MSR_KEY 19 /* key bit on 603e */ |
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#define MSR_POW 18 /* Power management x */ |
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#define MSR_WE 18 /* Wait state enable on embedded PowerPC x */ |
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#define MSR_TGPR 17 /* TGPR usage on 602/603 x */ |
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#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */ |
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#define MSR_ILE 16 /* Interrupt little-endian mode */ |
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#define MSR_EE 15 /* External interrupt enable */ |
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#define MSR_PR 14 /* Problem state hflags */ |
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#define MSR_FP 13 /* Floating point available hflags */ |
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#define MSR_ME 12 /* Machine check interrupt enable */ |
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#define MSR_FE0 11 /* Floating point exception mode 0 hflags */ |
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#define MSR_SE 10 /* Single-step trace enable x hflags */ |
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#define MSR_DWE 10 /* Debug wait enable on 405 x */ |
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#define MSR_UBLE 10 /* User BTB lock enable on e500 x */ |
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#define MSR_BE 9 /* Branch trace enable x hflags */ |
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#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ |
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#define MSR_FE1 8 /* Floating point exception mode 1 hflags */ |
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#define MSR_AL 7 /* AL bit on POWER */ |
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#define MSR_IP 6 /* Interrupt prefix */ |
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#define MSR_IR 5 /* Instruction relocate */ |
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#define MSR_DR 4 /* Data relocate */ |
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#define MSR_PE 3 /* Protection enable on 403 x */ |
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#define MSR_EP 3 /* Exception prefix on 601 x */ |
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#define MSR_PX 2 /* Protection exclusive on 403 x */ |
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#define MSR_PMM 2 /* Performance monitor mark on POWER x */ |
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#define MSR_RI 1 /* Recoverable interrupt 1 */ |
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#define MSR_LE 0 /* Little-endian mode 1 hflags */ |
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#define msr_sf env->msr[MSR_SF]
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#define msr_isf env->msr[MSR_ISF]
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#define msr_hv env->msr[MSR_HV]
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#define msr_cm env->msr[MSR_CM]
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#define msr_icm env->msr[MSR_ICM]
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#define msr_ucle env->msr[MSR_UCLE]
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#define msr_vr env->msr[MSR_VR]
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#define msr_spe env->msr[MSR_SPE]
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#define msr_ap env->msr[MSR_AP]
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#define msr_sa env->msr[MSR_SA]
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#define msr_key env->msr[MSR_KEY]
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#define msr_pow env->msr[MSR_POW]
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#define msr_we env->msr[MSR_WE]
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#define msr_tgpr env->msr[MSR_TGPR]
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#define msr_ce env->msr[MSR_CE]
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#define msr_ile env->msr[MSR_ILE]
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#define msr_ee env->msr[MSR_EE]
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#define msr_pr env->msr[MSR_PR]
|
| 398 |
#define msr_fp env->msr[MSR_FP]
|
| 399 |
#define msr_me env->msr[MSR_ME]
|
| 400 |
#define msr_fe0 env->msr[MSR_FE0]
|
| 401 |
#define msr_se env->msr[MSR_SE]
|
| 402 |
#define msr_dwe env->msr[MSR_DWE]
|
| 403 |
#define msr_uble env->msr[MSR_UBLE]
|
| 404 |
#define msr_be env->msr[MSR_BE]
|
| 405 |
#define msr_de env->msr[MSR_DE]
|
| 406 |
#define msr_fe1 env->msr[MSR_FE1]
|
| 407 |
#define msr_al env->msr[MSR_AL]
|
| 408 |
#define msr_ip env->msr[MSR_IP]
|
| 409 |
#define msr_ir env->msr[MSR_IR]
|
| 410 |
#define msr_dr env->msr[MSR_DR]
|
| 411 |
#define msr_pe env->msr[MSR_PE]
|
| 412 |
#define msr_ep env->msr[MSR_EP]
|
| 413 |
#define msr_px env->msr[MSR_PX]
|
| 414 |
#define msr_pmm env->msr[MSR_PMM]
|
| 415 |
#define msr_ri env->msr[MSR_RI]
|
| 416 |
#define msr_le env->msr[MSR_LE]
|
| 417 |
|
| 418 |
enum {
|
| 419 |
/* Beware that MSR bits are given using IBM standard (ie MSB is 0 !) */
|
| 420 |
POWERPC_FLAG_NONE = 0x00000000,
|
| 421 |
/* Flag for MSR bit 25 signification (VRE/SPE) */
|
| 422 |
POWERPC_FLAG_SPE = 0x00000001,
|
| 423 |
POWERPC_FLAG_VRE = 0x00000002,
|
| 424 |
/* Flag for MSR bit 18 may not be needed... */
|
| 425 |
POWERPC_FLAG_POW = 0x00000004,
|
| 426 |
POWERPC_FLAG_WE = 0x00000008,
|
| 427 |
/* Flag for MSR bit 17 signification (TGPR/CE) */
|
| 428 |
POWERPC_FLAG_TGPR = 0x00000010,
|
| 429 |
POWERPC_FLAG_CE = 0x00000020,
|
| 430 |
/* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
|
| 431 |
POWERPC_FLAG_SE = 0x00000040,
|
| 432 |
POWERPC_FLAG_DWE = 0x00000080,
|
| 433 |
POWERPC_FLAG_UBLE = 0x00000100,
|
| 434 |
/* Flag for MSR bit 9 signification (BE/DE) */
|
| 435 |
POWERPC_FLAG_BE = 0x00000200,
|
| 436 |
POWERPC_FLAG_DE = 0x00000400,
|
| 437 |
/* Flag for MSR bit 3 signification (PE/EP) */
|
| 438 |
POWERPC_FLAG_PE = 0x00000800,
|
| 439 |
POWERPC_FLAG_EP = 0x00001000,
|
| 440 |
/* Flag for MSR but 2 signification (PX/PMM) */
|
| 441 |
POWERPC_FLAG_PX = 0x00002000,
|
| 442 |
POWERPC_FLAG_PMM = 0x00004000,
|
| 443 |
}; |
| 444 |
|
| 445 |
/*****************************************************************************/
|
| 446 |
/* The whole PowerPC CPU context */
|
| 447 |
struct CPUPPCState {
|
| 448 |
/* First are the most commonly used resources
|
| 449 |
* during translated code execution
|
| 450 |
*/
|
| 451 |
#if TARGET_GPR_BITS > HOST_LONG_BITS
|
| 452 |
/* temporary fixed-point registers
|
| 453 |
* used to emulate 64 bits target on 32 bits hosts
|
| 454 |
*/
|
| 455 |
ppc_gpr_t t0, t1, t2; |
| 456 |
#endif
|
| 457 |
ppc_avr_t t0_avr, t1_avr, t2_avr; |
| 458 |
|
| 459 |
/* general purpose registers */
|
| 460 |
ppc_gpr_t gpr[32];
|
| 461 |
/* LR */
|
| 462 |
target_ulong lr; |
| 463 |
/* CTR */
|
| 464 |
target_ulong ctr; |
| 465 |
/* condition register */
|
| 466 |
uint8_t crf[8];
|
| 467 |
/* XER */
|
| 468 |
/* XXX: We use only 5 fields, but we want to keep the structure aligned */
|
| 469 |
uint8_t xer[8];
|
| 470 |
/* Reservation address */
|
| 471 |
target_ulong reserve; |
| 472 |
|
| 473 |
/* Those ones are used in supervisor mode only */
|
| 474 |
/* machine state register */
|
| 475 |
uint8_t msr[64];
|
| 476 |
/* temporary general purpose registers */
|
| 477 |
ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */ |
| 478 |
|
| 479 |
/* Floating point execution context */
|
| 480 |
/* temporary float registers */
|
| 481 |
float64 ft0; |
| 482 |
float64 ft1; |
| 483 |
float64 ft2; |
| 484 |
float_status fp_status; |
| 485 |
/* floating point registers */
|
| 486 |
float64 fpr[32];
|
| 487 |
/* floating point status and control register */
|
| 488 |
uint8_t fpscr[8];
|
| 489 |
|
| 490 |
CPU_COMMON |
| 491 |
|
| 492 |
int halted; /* TRUE if the CPU is in suspend state */ |
| 493 |
|
| 494 |
int access_type; /* when a memory exception occurs, the access |
| 495 |
type is stored here */
|
| 496 |
|
| 497 |
/* MMU context - only relevant for full system emulation */
|
| 498 |
#if !defined(CONFIG_USER_ONLY)
|
| 499 |
#if defined(TARGET_PPC64)
|
| 500 |
/* Address space register */
|
| 501 |
target_ulong asr; |
| 502 |
/* PowerPC 64 SLB area */
|
| 503 |
int slb_nr;
|
| 504 |
#endif
|
| 505 |
/* segment registers */
|
| 506 |
target_ulong sdr1; |
| 507 |
target_ulong sr[16];
|
| 508 |
/* BATs */
|
| 509 |
int nb_BATs;
|
| 510 |
target_ulong DBAT[2][8]; |
| 511 |
target_ulong IBAT[2][8]; |
| 512 |
/* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
|
| 513 |
int nb_tlb; /* Total number of TLB */ |
| 514 |
int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ |
| 515 |
int nb_ways; /* Number of ways in the TLB set */ |
| 516 |
int last_way; /* Last used way used to allocate TLB in a LRU way */ |
| 517 |
int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ |
| 518 |
int nb_pids; /* Number of available PID registers */ |
| 519 |
ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
|
| 520 |
/* 403 dedicated access protection registers */
|
| 521 |
target_ulong pb[4];
|
| 522 |
#endif
|
| 523 |
|
| 524 |
/* Other registers */
|
| 525 |
/* Special purpose registers */
|
| 526 |
target_ulong spr[1024];
|
| 527 |
ppc_spr_t spr_cb[1024];
|
| 528 |
/* Altivec registers */
|
| 529 |
ppc_avr_t avr[32];
|
| 530 |
uint32_t vscr; |
| 531 |
#if defined(TARGET_PPCEMB)
|
| 532 |
/* SPE registers */
|
| 533 |
ppc_gpr_t spe_acc; |
| 534 |
float_status spe_status; |
| 535 |
uint32_t spe_fscr; |
| 536 |
#endif
|
| 537 |
|
| 538 |
/* Internal devices resources */
|
| 539 |
/* Time base and decrementer */
|
| 540 |
ppc_tb_t *tb_env; |
| 541 |
/* Device control registers */
|
| 542 |
ppc_dcr_t *dcr_env; |
| 543 |
|
| 544 |
int dcache_line_size;
|
| 545 |
int icache_line_size;
|
| 546 |
|
| 547 |
/* Those resources are used during exception processing */
|
| 548 |
/* CPU model definition */
|
| 549 |
target_ulong msr_mask; |
| 550 |
uint8_t mmu_model; |
| 551 |
uint8_t excp_model; |
| 552 |
uint8_t bus_model; |
| 553 |
uint8_t pad; |
| 554 |
int bfd_mach;
|
| 555 |
uint32_t flags; |
| 556 |
|
| 557 |
int exception_index;
|
| 558 |
int error_code;
|
| 559 |
int interrupt_request;
|
| 560 |
uint32_t pending_interrupts; |
| 561 |
#if !defined(CONFIG_USER_ONLY)
|
| 562 |
/* This is the IRQ controller, which is implementation dependant
|
| 563 |
* and only relevant when emulating a complete machine.
|
| 564 |
*/
|
| 565 |
uint32_t irq_input_state; |
| 566 |
void **irq_inputs;
|
| 567 |
/* Exception vectors */
|
| 568 |
target_ulong excp_vectors[POWERPC_EXCP_NB]; |
| 569 |
target_ulong excp_prefix; |
| 570 |
target_ulong ivor_mask; |
| 571 |
target_ulong ivpr_mask; |
| 572 |
target_ulong hreset_vector; |
| 573 |
#endif
|
| 574 |
|
| 575 |
/* Those resources are used only during code translation */
|
| 576 |
/* Next instruction pointer */
|
| 577 |
target_ulong nip; |
| 578 |
|
| 579 |
/* opcode handlers */
|
| 580 |
opc_handler_t *opcodes[0x40];
|
| 581 |
|
| 582 |
/* Those resources are used only in Qemu core */
|
| 583 |
jmp_buf jmp_env; |
| 584 |
int user_mode_only; /* user mode only simulation */ |
| 585 |
target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
|
| 586 |
|
| 587 |
/* Power management */
|
| 588 |
int power_mode;
|
| 589 |
|
| 590 |
/* temporary hack to handle OSI calls (only used if non NULL) */
|
| 591 |
int (*osi_call)(struct CPUPPCState *env); |
| 592 |
}; |
| 593 |
|
| 594 |
/* Context used internally during MMU translations */
|
| 595 |
typedef struct mmu_ctx_t mmu_ctx_t; |
| 596 |
struct mmu_ctx_t {
|
| 597 |
target_phys_addr_t raddr; /* Real address */
|
| 598 |
int prot; /* Protection bits */ |
| 599 |
target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */ |
| 600 |
target_ulong ptem; /* Virtual segment ID | API */
|
| 601 |
int key; /* Access key */ |
| 602 |
}; |
| 603 |
|
| 604 |
/*****************************************************************************/
|
| 605 |
CPUPPCState *cpu_ppc_init (void);
|
| 606 |
int cpu_ppc_exec (CPUPPCState *s);
|
| 607 |
void cpu_ppc_close (CPUPPCState *s);
|
| 608 |
/* you can call this signal handler from your SIGBUS and SIGSEGV
|
| 609 |
signal handlers to inform the virtual CPU of exceptions. non zero
|
| 610 |
is returned if the signal was handled by the virtual CPU. */
|
| 611 |
int cpu_ppc_signal_handler (int host_signum, void *pinfo, |
| 612 |
void *puc);
|
| 613 |
|
| 614 |
void do_interrupt (CPUPPCState *env);
|
| 615 |
void ppc_hw_interrupt (CPUPPCState *env);
|
| 616 |
void cpu_loop_exit (void); |
| 617 |
|
| 618 |
void dump_stack (CPUPPCState *env);
|
| 619 |
|
| 620 |
#if !defined(CONFIG_USER_ONLY)
|
| 621 |
target_ulong do_load_ibatu (CPUPPCState *env, int nr);
|
| 622 |
target_ulong do_load_ibatl (CPUPPCState *env, int nr);
|
| 623 |
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value); |
| 624 |
void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value); |
| 625 |
target_ulong do_load_dbatu (CPUPPCState *env, int nr);
|
| 626 |
target_ulong do_load_dbatl (CPUPPCState *env, int nr);
|
| 627 |
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value); |
| 628 |
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value); |
| 629 |
target_ulong do_load_sdr1 (CPUPPCState *env); |
| 630 |
void do_store_sdr1 (CPUPPCState *env, target_ulong value);
|
| 631 |
#if defined(TARGET_PPC64)
|
| 632 |
target_ulong ppc_load_asr (CPUPPCState *env); |
| 633 |
void ppc_store_asr (CPUPPCState *env, target_ulong value);
|
| 634 |
target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr);
|
| 635 |
void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs); |
| 636 |
#endif /* defined(TARGET_PPC64) */ |
| 637 |
#if 0 // Unused
|
| 638 |
target_ulong do_load_sr (CPUPPCState *env, int srnum);
|
| 639 |
#endif
|
| 640 |
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value); |
| 641 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
| 642 |
target_ulong ppc_load_xer (CPUPPCState *env); |
| 643 |
void ppc_store_xer (CPUPPCState *env, target_ulong value);
|
| 644 |
target_ulong do_load_msr (CPUPPCState *env); |
| 645 |
int do_store_msr (CPUPPCState *env, target_ulong value);
|
| 646 |
#if defined(TARGET_PPC64)
|
| 647 |
int ppc_store_msr_32 (CPUPPCState *env, uint32_t value);
|
| 648 |
#endif
|
| 649 |
|
| 650 |
void do_compute_hflags (CPUPPCState *env);
|
| 651 |
void cpu_ppc_reset (void *opaque); |
| 652 |
CPUPPCState *cpu_ppc_init (void);
|
| 653 |
void cpu_ppc_close(CPUPPCState *env);
|
| 654 |
|
| 655 |
int ppc_find_by_name (const unsigned char *name, ppc_def_t **def); |
| 656 |
int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
|
| 657 |
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
| 658 |
int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
|
| 659 |
|
| 660 |
/* Time-base and decrementer management */
|
| 661 |
#ifndef NO_CPU_IO_DEFS
|
| 662 |
uint32_t cpu_ppc_load_tbl (CPUPPCState *env); |
| 663 |
uint32_t cpu_ppc_load_tbu (CPUPPCState *env); |
| 664 |
void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
|
| 665 |
void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
|
| 666 |
uint32_t cpu_ppc_load_atbl (CPUPPCState *env); |
| 667 |
uint32_t cpu_ppc_load_atbu (CPUPPCState *env); |
| 668 |
void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
|
| 669 |
void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
|
| 670 |
uint32_t cpu_ppc_load_decr (CPUPPCState *env); |
| 671 |
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
|
| 672 |
#if defined(TARGET_PPC64H)
|
| 673 |
uint32_t cpu_ppc_load_hdecr (CPUPPCState *env); |
| 674 |
void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
|
| 675 |
uint64_t cpu_ppc_load_purr (CPUPPCState *env); |
| 676 |
void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value);
|
| 677 |
#endif
|
| 678 |
uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env); |
| 679 |
uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env); |
| 680 |
#if !defined(CONFIG_USER_ONLY)
|
| 681 |
void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
|
| 682 |
void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
|
| 683 |
target_ulong load_40x_pit (CPUPPCState *env); |
| 684 |
void store_40x_pit (CPUPPCState *env, target_ulong val);
|
| 685 |
void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
|
| 686 |
void store_40x_sler (CPUPPCState *env, uint32_t val);
|
| 687 |
void store_booke_tcr (CPUPPCState *env, target_ulong val);
|
| 688 |
void store_booke_tsr (CPUPPCState *env, target_ulong val);
|
| 689 |
void ppc_tlb_invalidate_all (CPUPPCState *env);
|
| 690 |
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
|
| 691 |
#if defined(TARGET_PPC64)
|
| 692 |
void ppc_slb_invalidate_all (CPUPPCState *env);
|
| 693 |
void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0);
|
| 694 |
#endif
|
| 695 |
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid);
|
| 696 |
#endif
|
| 697 |
#endif
|
| 698 |
|
| 699 |
/* Device control registers */
|
| 700 |
int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp); |
| 701 |
int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val); |
| 702 |
|
| 703 |
#define CPUState CPUPPCState
|
| 704 |
#define cpu_init cpu_ppc_init
|
| 705 |
#define cpu_exec cpu_ppc_exec
|
| 706 |
#define cpu_gen_code cpu_ppc_gen_code
|
| 707 |
#define cpu_signal_handler cpu_ppc_signal_handler
|
| 708 |
|
| 709 |
#include "cpu-all.h" |
| 710 |
|
| 711 |
/*****************************************************************************/
|
| 712 |
/* Registers definitions */
|
| 713 |
#define XER_SO 31 |
| 714 |
#define XER_OV 30 |
| 715 |
#define XER_CA 29 |
| 716 |
#define XER_CMP 8 |
| 717 |
#define XER_BC 0 |
| 718 |
#define xer_so env->xer[4] |
| 719 |
#define xer_ov env->xer[6] |
| 720 |
#define xer_ca env->xer[2] |
| 721 |
#define xer_cmp env->xer[1] |
| 722 |
#define xer_bc env->xer[0] |
| 723 |
|
| 724 |
/* SPR definitions */
|
| 725 |
#define SPR_MQ (0x000) |
| 726 |
#define SPR_XER (0x001) |
| 727 |
#define SPR_601_VRTCU (0x004) |
| 728 |
#define SPR_601_VRTCL (0x005) |
| 729 |
#define SPR_601_UDECR (0x006) |
| 730 |
#define SPR_LR (0x008) |
| 731 |
#define SPR_CTR (0x009) |
| 732 |
#define SPR_DSISR (0x012) |
| 733 |
#define SPR_DAR (0x013) /* DAE for PowerPC 601 */ |
| 734 |
#define SPR_601_RTCU (0x014) |
| 735 |
#define SPR_601_RTCL (0x015) |
| 736 |
#define SPR_DECR (0x016) |
| 737 |
#define SPR_SDR1 (0x019) |
| 738 |
#define SPR_SRR0 (0x01A) |
| 739 |
#define SPR_SRR1 (0x01B) |
| 740 |
#define SPR_AMR (0x01D) |
| 741 |
#define SPR_BOOKE_PID (0x030) |
| 742 |
#define SPR_BOOKE_DECAR (0x036) |
| 743 |
#define SPR_BOOKE_CSRR0 (0x03A) |
| 744 |
#define SPR_BOOKE_CSRR1 (0x03B) |
| 745 |
#define SPR_BOOKE_DEAR (0x03D) |
| 746 |
#define SPR_BOOKE_ESR (0x03E) |
| 747 |
#define SPR_BOOKE_IVPR (0x03F) |
| 748 |
#define SPR_8xx_EIE (0x050) |
| 749 |
#define SPR_8xx_EID (0x051) |
| 750 |
#define SPR_8xx_NRE (0x052) |
| 751 |
#define SPR_CTRL (0x088) |
| 752 |
#define SPR_58x_CMPA (0x090) |
| 753 |
#define SPR_58x_CMPB (0x091) |
| 754 |
#define SPR_58x_CMPC (0x092) |
| 755 |
#define SPR_58x_CMPD (0x093) |
| 756 |
#define SPR_58x_ICR (0x094) |
| 757 |
#define SPR_58x_DER (0x094) |
| 758 |
#define SPR_58x_COUNTA (0x096) |
| 759 |
#define SPR_58x_COUNTB (0x097) |
| 760 |
#define SPR_UCTRL (0x098) |
| 761 |
#define SPR_58x_CMPE (0x098) |
| 762 |
#define SPR_58x_CMPF (0x099) |
| 763 |
#define SPR_58x_CMPG (0x09A) |
| 764 |
#define SPR_58x_CMPH (0x09B) |
| 765 |
#define SPR_58x_LCTRL1 (0x09C) |
| 766 |
#define SPR_58x_LCTRL2 (0x09D) |
| 767 |
#define SPR_58x_ICTRL (0x09E) |
| 768 |
#define SPR_58x_BAR (0x09F) |
| 769 |
#define SPR_VRSAVE (0x100) |
| 770 |
#define SPR_USPRG0 (0x100) |
| 771 |
#define SPR_USPRG1 (0x101) |
| 772 |
#define SPR_USPRG2 (0x102) |
| 773 |
#define SPR_USPRG3 (0x103) |
| 774 |
#define SPR_USPRG4 (0x104) |
| 775 |
#define SPR_USPRG5 (0x105) |
| 776 |
#define SPR_USPRG6 (0x106) |
| 777 |
#define SPR_USPRG7 (0x107) |
| 778 |
#define SPR_VTBL (0x10C) |
| 779 |
#define SPR_VTBU (0x10D) |
| 780 |
#define SPR_SPRG0 (0x110) |
| 781 |
#define SPR_SPRG1 (0x111) |
| 782 |
#define SPR_SPRG2 (0x112) |
| 783 |
#define SPR_SPRG3 (0x113) |
| 784 |
#define SPR_SPRG4 (0x114) |
| 785 |
#define SPR_SCOMC (0x114) |
| 786 |
#define SPR_SPRG5 (0x115) |
| 787 |
#define SPR_SCOMD (0x115) |
| 788 |
#define SPR_SPRG6 (0x116) |
| 789 |
#define SPR_SPRG7 (0x117) |
| 790 |
#define SPR_ASR (0x118) |
| 791 |
#define SPR_EAR (0x11A) |
| 792 |
#define SPR_TBL (0x11C) |
| 793 |
#define SPR_TBU (0x11D) |
| 794 |
#define SPR_TBU40 (0x11E) |
| 795 |
#define SPR_SVR (0x11E) |
| 796 |
#define SPR_BOOKE_PIR (0x11E) |
| 797 |
#define SPR_PVR (0x11F) |
| 798 |
#define SPR_HSPRG0 (0x130) |
| 799 |
#define SPR_BOOKE_DBSR (0x130) |
| 800 |
#define SPR_HSPRG1 (0x131) |
| 801 |
#define SPR_HDSISR (0x132) |
| 802 |
#define SPR_HDAR (0x133) |
| 803 |
#define SPR_BOOKE_DBCR0 (0x134) |
| 804 |
#define SPR_IBCR (0x135) |
| 805 |
#define SPR_PURR (0x135) |
| 806 |
#define SPR_BOOKE_DBCR1 (0x135) |
| 807 |
#define SPR_DBCR (0x136) |
| 808 |
#define SPR_HDEC (0x136) |
| 809 |
#define SPR_BOOKE_DBCR2 (0x136) |
| 810 |
#define SPR_HIOR (0x137) |
| 811 |
#define SPR_MBAR (0x137) |
| 812 |
#define SPR_RMOR (0x138) |
| 813 |
#define SPR_BOOKE_IAC1 (0x138) |
| 814 |
#define SPR_HRMOR (0x139) |
| 815 |
#define SPR_BOOKE_IAC2 (0x139) |
| 816 |
#define SPR_HSRR0 (0x13A) |
| 817 |
#define SPR_BOOKE_IAC3 (0x13A) |
| 818 |
#define SPR_HSRR1 (0x13B) |
| 819 |
#define SPR_BOOKE_IAC4 (0x13B) |
| 820 |
#define SPR_LPCR (0x13C) |
| 821 |
#define SPR_BOOKE_DAC1 (0x13C) |
| 822 |
#define SPR_LPIDR (0x13D) |
| 823 |
#define SPR_DABR2 (0x13D) |
| 824 |
#define SPR_BOOKE_DAC2 (0x13D) |
| 825 |
#define SPR_BOOKE_DVC1 (0x13E) |
| 826 |
#define SPR_BOOKE_DVC2 (0x13F) |
| 827 |
#define SPR_BOOKE_TSR (0x150) |
| 828 |
#define SPR_BOOKE_TCR (0x154) |
| 829 |
#define SPR_BOOKE_IVOR0 (0x190) |
| 830 |
#define SPR_BOOKE_IVOR1 (0x191) |
| 831 |
#define SPR_BOOKE_IVOR2 (0x192) |
| 832 |
#define SPR_BOOKE_IVOR3 (0x193) |
| 833 |
#define SPR_BOOKE_IVOR4 (0x194) |
| 834 |
#define SPR_BOOKE_IVOR5 (0x195) |
| 835 |
#define SPR_BOOKE_IVOR6 (0x196) |
| 836 |
#define SPR_BOOKE_IVOR7 (0x197) |
| 837 |
#define SPR_BOOKE_IVOR8 (0x198) |
| 838 |
#define SPR_BOOKE_IVOR9 (0x199) |
| 839 |
#define SPR_BOOKE_IVOR10 (0x19A) |
| 840 |
#define SPR_BOOKE_IVOR11 (0x19B) |
| 841 |
#define SPR_BOOKE_IVOR12 (0x19C) |
| 842 |
#define SPR_BOOKE_IVOR13 (0x19D) |
| 843 |
#define SPR_BOOKE_IVOR14 (0x19E) |
| 844 |
#define SPR_BOOKE_IVOR15 (0x19F) |
| 845 |
#define SPR_BOOKE_SPEFSCR (0x200) |
| 846 |
#define SPR_E500_BBEAR (0x201) |
| 847 |
#define SPR_E500_BBTAR (0x202) |
| 848 |
#define SPR_ATBL (0x20E) |
| 849 |
#define SPR_ATBU (0x20F) |
| 850 |
#define SPR_IBAT0U (0x210) |
| 851 |
#define SPR_BOOKE_IVOR32 (0x210) |
| 852 |
#define SPR_IBAT0L (0x211) |
| 853 |
#define SPR_BOOKE_IVOR33 (0x211) |
| 854 |
#define SPR_IBAT1U (0x212) |
| 855 |
#define SPR_BOOKE_IVOR34 (0x212) |
| 856 |
#define SPR_IBAT1L (0x213) |
| 857 |
#define SPR_BOOKE_IVOR35 (0x213) |
| 858 |
#define SPR_IBAT2U (0x214) |
| 859 |
#define SPR_BOOKE_IVOR36 (0x214) |
| 860 |
#define SPR_IBAT2L (0x215) |
| 861 |
#define SPR_E500_L1CFG0 (0x215) |
| 862 |
#define SPR_BOOKE_IVOR37 (0x215) |
| 863 |
#define SPR_IBAT3U (0x216) |
| 864 |
#define SPR_E500_L1CFG1 (0x216) |
| 865 |
#define SPR_IBAT3L (0x217) |
| 866 |
#define SPR_DBAT0U (0x218) |
| 867 |
#define SPR_DBAT0L (0x219) |
| 868 |
#define SPR_DBAT1U (0x21A) |
| 869 |
#define SPR_DBAT1L (0x21B) |
| 870 |
#define SPR_DBAT2U (0x21C) |
| 871 |
#define SPR_DBAT2L (0x21D) |
| 872 |
#define SPR_DBAT3U (0x21E) |
| 873 |
#define SPR_DBAT3L (0x21F) |
| 874 |
#define SPR_IBAT4U (0x230) |
| 875 |
#define SPR_IBAT4L (0x231) |
| 876 |
#define SPR_IBAT5U (0x232) |
| 877 |
#define SPR_IBAT5L (0x233) |
| 878 |
#define SPR_IBAT6U (0x234) |
| 879 |
#define SPR_IBAT6L (0x235) |
| 880 |
#define SPR_IBAT7U (0x236) |
| 881 |
#define SPR_IBAT7L (0x237) |
| 882 |
#define SPR_DBAT4U (0x238) |
| 883 |
#define SPR_DBAT4L (0x239) |
| 884 |
#define SPR_DBAT5U (0x23A) |
| 885 |
#define SPR_BOOKE_MCSRR0 (0x23A) |
| 886 |
#define SPR_DBAT5L (0x23B) |
| 887 |
#define SPR_BOOKE_MCSRR1 (0x23B) |
| 888 |
#define SPR_DBAT6U (0x23C) |
| 889 |
#define SPR_BOOKE_MCSR (0x23C) |
| 890 |
#define SPR_DBAT6L (0x23D) |
| 891 |
#define SPR_E500_MCAR (0x23D) |
| 892 |
#define SPR_DBAT7U (0x23E) |
| 893 |
#define SPR_BOOKE_DSRR0 (0x23E) |
| 894 |
#define SPR_DBAT7L (0x23F) |
| 895 |
#define SPR_BOOKE_DSRR1 (0x23F) |
| 896 |
#define SPR_BOOKE_SPRG8 (0x25C) |
| 897 |
#define SPR_BOOKE_SPRG9 (0x25D) |
| 898 |
#define SPR_BOOKE_MAS0 (0x270) |
| 899 |
#define SPR_BOOKE_MAS1 (0x271) |
| 900 |
#define SPR_BOOKE_MAS2 (0x272) |
| 901 |
#define SPR_BOOKE_MAS3 (0x273) |
| 902 |
#define SPR_BOOKE_MAS4 (0x274) |
| 903 |
#define SPR_BOOKE_MAS6 (0x276) |
| 904 |
#define SPR_BOOKE_PID1 (0x279) |
| 905 |
#define SPR_BOOKE_PID2 (0x27A) |
| 906 |
#define SPR_BOOKE_TLB0CFG (0x2B0) |
| 907 |
#define SPR_BOOKE_TLB1CFG (0x2B1) |
| 908 |
#define SPR_BOOKE_TLB2CFG (0x2B2) |
| 909 |
#define SPR_BOOKE_TLB3CFG (0x2B3) |
| 910 |
#define SPR_BOOKE_EPR (0x2BE) |
| 911 |
#define SPR_PERF0 (0x300) |
| 912 |
#define SPR_PERF1 (0x301) |
| 913 |
#define SPR_PERF2 (0x302) |
| 914 |
#define SPR_PERF3 (0x303) |
| 915 |
#define SPR_PERF4 (0x304) |
| 916 |
#define SPR_PERF5 (0x305) |
| 917 |
#define SPR_PERF6 (0x306) |
| 918 |
#define SPR_PERF7 (0x307) |
| 919 |
#define SPR_PERF8 (0x308) |
| 920 |
#define SPR_PERF9 (0x309) |
| 921 |
#define SPR_PERFA (0x30A) |
| 922 |
#define SPR_PERFB (0x30B) |
| 923 |
#define SPR_PERFC (0x30C) |
| 924 |
#define SPR_PERFD (0x30D) |
| 925 |
#define SPR_PERFE (0x30E) |
| 926 |
#define SPR_PERFF (0x30F) |
| 927 |
#define SPR_UPERF0 (0x310) |
| 928 |
#define SPR_UPERF1 (0x311) |
| 929 |
#define SPR_UPERF2 (0x312) |
| 930 |
#define SPR_UPERF3 (0x313) |
| 931 |
#define SPR_UPERF4 (0x314) |
| 932 |
#define SPR_UPERF5 (0x315) |
| 933 |
#define SPR_UPERF6 (0x316) |
| 934 |
#define SPR_UPERF7 (0x317) |
| 935 |
#define SPR_UPERF8 (0x318) |
| 936 |
#define SPR_UPERF9 (0x319) |
| 937 |
#define SPR_UPERFA (0x31A) |
| 938 |
#define SPR_UPERFB (0x31B) |
| 939 |
#define SPR_UPERFC (0x31C) |
| 940 |
#define SPR_UPERFD (0x31D) |
| 941 |
#define SPR_UPERFE (0x31E) |
| 942 |
#define SPR_UPERFF (0x31F) |
| 943 |
#define SPR_440_INV0 (0x370) |
| 944 |
#define SPR_440_INV1 (0x371) |
| 945 |
#define SPR_440_INV2 (0x372) |
| 946 |
#define SPR_440_INV3 (0x373) |
| 947 |
#define SPR_440_ITV0 (0x374) |
| 948 |
#define SPR_440_ITV1 (0x375) |
| 949 |
#define SPR_440_ITV2 (0x376) |
| 950 |
#define SPR_440_ITV3 (0x377) |
| 951 |
#define SPR_440_CCR1 (0x378) |
| 952 |
#define SPR_DCRIPR (0x37B) |
| 953 |
#define SPR_PPR (0x380) |
| 954 |
#define SPR_440_DNV0 (0x390) |
| 955 |
#define SPR_440_DNV1 (0x391) |
| 956 |
#define SPR_440_DNV2 (0x392) |
| 957 |
#define SPR_440_DNV3 (0x393) |
| 958 |
#define SPR_440_DTV0 (0x394) |
| 959 |
#define SPR_440_DTV1 (0x395) |
| 960 |
#define SPR_440_DTV2 (0x396) |
| 961 |
#define SPR_440_DTV3 (0x397) |
| 962 |
#define SPR_440_DVLIM (0x398) |
| 963 |
#define SPR_440_IVLIM (0x399) |
| 964 |
#define SPR_440_RSTCFG (0x39B) |
| 965 |
#define SPR_BOOKE_DCDBTRL (0x39C) |
| 966 |
#define SPR_BOOKE_DCDBTRH (0x39D) |
| 967 |
#define SPR_BOOKE_ICDBTRL (0x39E) |
| 968 |
#define SPR_BOOKE_ICDBTRH (0x39F) |
| 969 |
#define SPR_UMMCR2 (0x3A0) |
| 970 |
#define SPR_UPMC5 (0x3A1) |
| 971 |
#define SPR_UPMC6 (0x3A2) |
| 972 |
#define SPR_UBAMR (0x3A7) |
| 973 |
#define SPR_UMMCR0 (0x3A8) |
| 974 |
#define SPR_UPMC1 (0x3A9) |
| 975 |
#define SPR_UPMC2 (0x3AA) |
| 976 |
#define SPR_USIAR (0x3AB) |
| 977 |
#define SPR_UMMCR1 (0x3AC) |
| 978 |
#define SPR_UPMC3 (0x3AD) |
| 979 |
#define SPR_UPMC4 (0x3AE) |
| 980 |
#define SPR_USDA (0x3AF) |
| 981 |
#define SPR_40x_ZPR (0x3B0) |
| 982 |
#define SPR_BOOKE_MAS7 (0x3B0) |
| 983 |
#define SPR_620_PMR0 (0x3B0) |
| 984 |
#define SPR_MMCR2 (0x3B0) |
| 985 |
#define SPR_PMC5 (0x3B1) |
| 986 |
#define SPR_40x_PID (0x3B1) |
| 987 |
#define SPR_620_PMR1 (0x3B1) |
| 988 |
#define SPR_PMC6 (0x3B2) |
| 989 |
#define SPR_440_MMUCR (0x3B2) |
| 990 |
#define SPR_620_PMR2 (0x3B2) |
| 991 |
#define SPR_4xx_CCR0 (0x3B3) |
| 992 |
#define SPR_BOOKE_EPLC (0x3B3) |
| 993 |
#define SPR_620_PMR3 (0x3B3) |
| 994 |
#define SPR_405_IAC3 (0x3B4) |
| 995 |
#define SPR_BOOKE_EPSC (0x3B4) |
| 996 |
#define SPR_620_PMR4 (0x3B4) |
| 997 |
#define SPR_405_IAC4 (0x3B5) |
| 998 |
#define SPR_620_PMR5 (0x3B5) |
| 999 |
#define SPR_405_DVC1 (0x3B6) |
| 1000 |
#define SPR_620_PMR6 (0x3B6) |
| 1001 |
#define SPR_405_DVC2 (0x3B7) |
| 1002 |
#define SPR_620_PMR7 (0x3B7) |
| 1003 |
#define SPR_BAMR (0x3B7) |
| 1004 |
#define SPR_MMCR0 (0x3B8) |
| 1005 |
#define SPR_620_PMR8 (0x3B8) |
| 1006 |
#define SPR_PMC1 (0x3B9) |
| 1007 |
#define SPR_40x_SGR (0x3B9) |
| 1008 |
#define SPR_620_PMR9 (0x3B9) |
| 1009 |
#define SPR_PMC2 (0x3BA) |
| 1010 |
#define SPR_40x_DCWR (0x3BA) |
| 1011 |
#define SPR_620_PMRA (0x3BA) |
| 1012 |
#define SPR_SIAR (0x3BB) |
| 1013 |
#define SPR_405_SLER (0x3BB) |
| 1014 |
#define SPR_620_PMRB (0x3BB) |
| 1015 |
#define SPR_MMCR1 (0x3BC) |
| 1016 |
#define SPR_405_SU0R (0x3BC) |
| 1017 |
#define SPR_620_PMRC (0x3BC) |
| 1018 |
#define SPR_401_SKR (0x3BC) |
| 1019 |
#define SPR_PMC3 (0x3BD) |
| 1020 |
#define SPR_405_DBCR1 (0x3BD) |
| 1021 |
#define SPR_620_PMRD (0x3BD) |
| 1022 |
#define SPR_PMC4 (0x3BE) |
| 1023 |
#define SPR_620_PMRE (0x3BE) |
| 1024 |
#define SPR_SDA (0x3BF) |
| 1025 |
#define SPR_620_PMRF (0x3BF) |
| 1026 |
#define SPR_403_VTBL (0x3CC) |
| 1027 |
#define SPR_403_VTBU (0x3CD) |
| 1028 |
#define SPR_DMISS (0x3D0) |
| 1029 |
#define SPR_DCMP (0x3D1) |
| 1030 |
#define SPR_HASH1 (0x3D2) |
| 1031 |
#define SPR_HASH2 (0x3D3) |
| 1032 |
#define SPR_BOOKE_ICDBDR (0x3D3) |
| 1033 |
#define SPR_TLBMISS (0x3D4) |
| 1034 |
#define SPR_IMISS (0x3D4) |
| 1035 |
#define SPR_40x_ESR (0x3D4) |
| 1036 |
#define SPR_PTEHI (0x3D5) |
| 1037 |
#define SPR_ICMP (0x3D5) |
| 1038 |
#define SPR_40x_DEAR (0x3D5) |
| 1039 |
#define SPR_PTELO (0x3D6) |
| 1040 |
#define SPR_RPA (0x3D6) |
| 1041 |
#define SPR_40x_EVPR (0x3D6) |
| 1042 |
#define SPR_L3PM (0x3D7) |
| 1043 |
#define SPR_403_CDBCR (0x3D7) |
| 1044 |
#define SPR_L3OHCR (0x3D8) |
| 1045 |
#define SPR_TCR (0x3D8) |
| 1046 |
#define SPR_40x_TSR (0x3D8) |
| 1047 |
#define SPR_IBR (0x3DA) |
| 1048 |
#define SPR_40x_TCR (0x3DA) |
| 1049 |
#define SPR_ESASRR (0x3DB) |
| 1050 |
#define SPR_40x_PIT (0x3DB) |
| 1051 |
#define SPR_403_TBL (0x3DC) |
| 1052 |
#define SPR_403_TBU (0x3DD) |
| 1053 |
#define SPR_SEBR (0x3DE) |
| 1054 |
#define SPR_40x_SRR2 (0x3DE) |
| 1055 |
#define SPR_SER (0x3DF) |
| 1056 |
#define SPR_40x_SRR3 (0x3DF) |
| 1057 |
#define SPR_L3ITCR0 (0x3E8) |
| 1058 |
#define SPR_L3ITCR1 (0x3E9) |
| 1059 |
#define SPR_L3ITCR2 (0x3EA) |
| 1060 |
#define SPR_L3ITCR3 (0x3EB) |
| 1061 |
#define SPR_HID0 (0x3F0) |
| 1062 |
#define SPR_40x_DBSR (0x3F0) |
| 1063 |
#define SPR_HID1 (0x3F1) |
| 1064 |
#define SPR_IABR (0x3F2) |
| 1065 |
#define SPR_40x_DBCR0 (0x3F2) |
| 1066 |
#define SPR_601_HID2 (0x3F2) |
| 1067 |
#define SPR_E500_L1CSR0 (0x3F2) |
| 1068 |
#define SPR_ICTRL (0x3F3) |
| 1069 |
#define SPR_HID2 (0x3F3) |
| 1070 |
#define SPR_E500_L1CSR1 (0x3F3) |
| 1071 |
#define SPR_440_DBDR (0x3F3) |
| 1072 |
#define SPR_LDSTDB (0x3F4) |
| 1073 |
#define SPR_40x_IAC1 (0x3F4) |
| 1074 |
#define SPR_MMUCSR0 (0x3F4) |
| 1075 |
#define SPR_DABR (0x3F5) |
| 1076 |
#define DABR_MASK (~(target_ulong)0x7) |
| 1077 |
#define SPR_E500_BUCSR (0x3F5) |
| 1078 |
#define SPR_40x_IAC2 (0x3F5) |
| 1079 |
#define SPR_601_HID5 (0x3F5) |
| 1080 |
#define SPR_40x_DAC1 (0x3F6) |
| 1081 |
#define SPR_MSSCR0 (0x3F6) |
| 1082 |
#define SPR_970_HID5 (0x3F6) |
| 1083 |
#define SPR_MSSSR0 (0x3F7) |
| 1084 |
#define SPR_DABRX (0x3F7) |
| 1085 |
#define SPR_40x_DAC2 (0x3F7) |
| 1086 |
#define SPR_MMUCFG (0x3F7) |
| 1087 |
#define SPR_LDSTCR (0x3F8) |
| 1088 |
#define SPR_L2PMCR (0x3F8) |
| 1089 |
#define SPR_750_HID2 (0x3F8) |
| 1090 |
#define SPR_620_HID8 (0x3F8) |
| 1091 |
#define SPR_L2CR (0x3F9) |
| 1092 |
#define SPR_620_HID9 (0x3F9) |
| 1093 |
#define SPR_L3CR (0x3FA) |
| 1094 |
#define SPR_IABR2 (0x3FA) |
| 1095 |
#define SPR_40x_DCCR (0x3FA) |
| 1096 |
#define SPR_ICTC (0x3FB) |
| 1097 |
#define SPR_40x_ICCR (0x3FB) |
| 1098 |
#define SPR_THRM1 (0x3FC) |
| 1099 |
#define SPR_403_PBL1 (0x3FC) |
| 1100 |
#define SPR_SP (0x3FD) |
| 1101 |
#define SPR_THRM2 (0x3FD) |
| 1102 |
#define SPR_403_PBU1 (0x3FD) |
| 1103 |
#define SPR_604_HID13 (0x3FD) |
| 1104 |
#define SPR_LT (0x3FE) |
| 1105 |
#define SPR_THRM3 (0x3FE) |
| 1106 |
#define SPR_FPECR (0x3FE) |
| 1107 |
#define SPR_403_PBL2 (0x3FE) |
| 1108 |
#define SPR_PIR (0x3FF) |
| 1109 |
#define SPR_403_PBU2 (0x3FF) |
| 1110 |
#define SPR_601_HID15 (0x3FF) |
| 1111 |
#define SPR_604_HID15 (0x3FF) |
| 1112 |
#define SPR_E500_SVR (0x3FF) |
| 1113 |
|
| 1114 |
/*****************************************************************************/
|
| 1115 |
/* Memory access type :
|
| 1116 |
* may be needed for precise access rights control and precise exceptions.
|
| 1117 |
*/
|
| 1118 |
enum {
|
| 1119 |
/* 1 bit to define user level / supervisor access */
|
| 1120 |
ACCESS_USER = 0x00,
|
| 1121 |
ACCESS_SUPER = 0x01,
|
| 1122 |
/* Type of instruction that generated the access */
|
| 1123 |
ACCESS_CODE = 0x10, /* Code fetch access */ |
| 1124 |
ACCESS_INT = 0x20, /* Integer load/store access */ |
| 1125 |
ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
| 1126 |
ACCESS_RES = 0x40, /* load/store with reservation */ |
| 1127 |
ACCESS_EXT = 0x50, /* external access */ |
| 1128 |
ACCESS_CACHE = 0x60, /* Cache manipulation */ |
| 1129 |
}; |
| 1130 |
|
| 1131 |
/* Hardware interruption sources:
|
| 1132 |
* all those exception can be raised simulteaneously
|
| 1133 |
*/
|
| 1134 |
/* Input pins definitions */
|
| 1135 |
enum {
|
| 1136 |
/* 6xx bus input pins */
|
| 1137 |
PPC6xx_INPUT_HRESET = 0,
|
| 1138 |
PPC6xx_INPUT_SRESET = 1,
|
| 1139 |
PPC6xx_INPUT_CKSTP_IN = 2,
|
| 1140 |
PPC6xx_INPUT_MCP = 3,
|
| 1141 |
PPC6xx_INPUT_SMI = 4,
|
| 1142 |
PPC6xx_INPUT_INT = 5,
|
| 1143 |
}; |
| 1144 |
|
| 1145 |
enum {
|
| 1146 |
/* Embedded PowerPC input pins */
|
| 1147 |
PPCBookE_INPUT_HRESET = 0,
|
| 1148 |
PPCBookE_INPUT_SRESET = 1,
|
| 1149 |
PPCBookE_INPUT_CKSTP_IN = 2,
|
| 1150 |
PPCBookE_INPUT_MCP = 3,
|
| 1151 |
PPCBookE_INPUT_SMI = 4,
|
| 1152 |
PPCBookE_INPUT_INT = 5,
|
| 1153 |
PPCBookE_INPUT_CINT = 6,
|
| 1154 |
}; |
| 1155 |
|
| 1156 |
enum {
|
| 1157 |
/* PowerPC 40x input pins */
|
| 1158 |
PPC40x_INPUT_RESET_CORE = 0,
|
| 1159 |
PPC40x_INPUT_RESET_CHIP = 1,
|
| 1160 |
PPC40x_INPUT_RESET_SYS = 2,
|
| 1161 |
PPC40x_INPUT_CINT = 3,
|
| 1162 |
PPC40x_INPUT_INT = 4,
|
| 1163 |
PPC40x_INPUT_HALT = 5,
|
| 1164 |
PPC40x_INPUT_DEBUG = 6,
|
| 1165 |
PPC40x_INPUT_NB, |
| 1166 |
}; |
| 1167 |
|
| 1168 |
#if defined(TARGET_PPC64)
|
| 1169 |
enum {
|
| 1170 |
/* PowerPC 620 (and probably others) input pins */
|
| 1171 |
PPC620_INPUT_HRESET = 0,
|
| 1172 |
PPC620_INPUT_SRESET = 1,
|
| 1173 |
PPC620_INPUT_CKSTP = 2,
|
| 1174 |
PPC620_INPUT_TBEN = 3,
|
| 1175 |
PPC620_INPUT_WAKEUP = 4,
|
| 1176 |
PPC620_INPUT_MCP = 5,
|
| 1177 |
PPC620_INPUT_SMI = 6,
|
| 1178 |
PPC620_INPUT_INT = 7,
|
| 1179 |
}; |
| 1180 |
|
| 1181 |
enum {
|
| 1182 |
/* PowerPC 970 input pins */
|
| 1183 |
PPC970_INPUT_HRESET = 0,
|
| 1184 |
PPC970_INPUT_SRESET = 1,
|
| 1185 |
PPC970_INPUT_CKSTP = 2,
|
| 1186 |
PPC970_INPUT_TBEN = 3,
|
| 1187 |
PPC970_INPUT_MCP = 4,
|
| 1188 |
PPC970_INPUT_INT = 5,
|
| 1189 |
PPC970_INPUT_THINT = 6,
|
| 1190 |
}; |
| 1191 |
#endif
|
| 1192 |
|
| 1193 |
/* Hardware exceptions definitions */
|
| 1194 |
enum {
|
| 1195 |
/* External hardware exception sources */
|
| 1196 |
PPC_INTERRUPT_RESET = 0, /* Reset exception */ |
| 1197 |
PPC_INTERRUPT_MCK = 1, /* Machine check exception */ |
| 1198 |
PPC_INTERRUPT_EXT = 2, /* External interrupt */ |
| 1199 |
PPC_INTERRUPT_SMI = 3, /* System management interrupt */ |
| 1200 |
PPC_INTERRUPT_CEXT = 4, /* Critical external interrupt */ |
| 1201 |
PPC_INTERRUPT_DEBUG = 5, /* External debug exception */ |
| 1202 |
PPC_INTERRUPT_THERM = 6, /* Thermal exception */ |
| 1203 |
/* Internal hardware exception sources */
|
| 1204 |
PPC_INTERRUPT_DECR = 7, /* Decrementer exception */ |
| 1205 |
PPC_INTERRUPT_HDECR = 8, /* Hypervisor decrementer exception */ |
| 1206 |
PPC_INTERRUPT_PIT = 9, /* Programmable inteval timer interrupt */ |
| 1207 |
PPC_INTERRUPT_FIT = 10, /* Fixed interval timer interrupt */ |
| 1208 |
PPC_INTERRUPT_WDT = 11, /* Watchdog timer interrupt */ |
| 1209 |
PPC_INTERRUPT_CDOORBELL = 12, /* Critical doorbell interrupt */ |
| 1210 |
PPC_INTERRUPT_DOORBELL = 13, /* Doorbell interrupt */ |
| 1211 |
PPC_INTERRUPT_PERFM = 14, /* Performance monitor interrupt */ |
| 1212 |
}; |
| 1213 |
|
| 1214 |
/*****************************************************************************/
|
| 1215 |
|
| 1216 |
#endif /* !defined (__CPU_PPC_H__) */ |