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# Date Author Comment
b36f100e 03/05/2014 04:06 am Alexey Kardashevskiy

PPC: KVM: suppress warnings about not supported SPRs

PR KVM lacks support of many SPRs in set/get one register API but it does
really break PR KVM. So convert them to switchable traces for now.

Signed-off-by: Alexey Kardashevskiy <>
Signed-off-by: Alexander Graf <>
66c3e328 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA2.06 lfiwzx Instruction

This patch adds the Load Floating Point as Integer Word and
Zero Indexed (lfiwzx) instruction which was introduced in
Power ISA 2.06.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
69b31b90 03/05/2014 04:06 am Alexey Kardashevskiy

PPC: KVM: store SLB slot number

When ppc_store_slb() is called from kvm_arch_get_registers(), it stores
a SLB in CPUPPCState::slb[slot]. However it drops the slot number from
ESID so when kvm_arch_put_registers() puts SLBs back to KVM, they do not
have correct "index" field anymore. This broke migration with LPCR_AIR...
da29cb7b 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA 2.06 ftdiv Instruction

This patch adds the Floating Point Test for Divide instruction which
was introduced in Power ISA 2.06B.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Signed-off-by: Alexander Graf <>
6d41d146 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA 2.06 ftsqrt

This patch adds the Floating Point Test for Square Root instruction
which was introduced in Power ISA 2.06.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Signed-off-by: Alexander Graf <>
ce8ca30b 03/05/2014 04:06 am Tom Musta

target-ppc: Enable frsqrtes on Power7 and Power8

The frsqrtes instruction was introduced prior to ISA 2.06 and is
support on both the Power7 and Power8 processors. However, this
instruction is handled as illegal in the current QEMU emulation
machines. This patch enables the existing implemention of frsqrtes...
28288b48 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA 2.06 fcfid[u][s] Instructions

This patch adds the fcfids, fcfidu and fcfidus instructions which
were introduced in Power ISA 2.06B. A common macro is provided to
eliminate repetitious code, and the existing fcfid instruction is
refactored to use this macro....
c7386080 03/05/2014 04:06 am Tom Musta

target-ppc: Fix and enable fri[mnpz]

The fri* series of instructions was introduced prior to ISA 2.06 and
is supported on Power7 and Power8 hardware. However, the instruction
is still considered illegal in the P7 and P8 QEMU emulation models.
This patch enables these instructions for the P7 and P8 machines....
29a0e4e9 03/05/2014 04:06 am Tom Musta

target-ppc: Add Flag for Power ISA V2.06 Floating Point Test Instructions

This patch adds a flag for Floating Point Test instructions that were
introduced in Power ISA V2.06B.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
587c51f7 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions

This patch adds the byte and halfword variants of the Store Conditional
instructions. A common macro is introduced and the existing implementations
of stwcx. and stdcx. are refactored to use this macro....
1b0bd002 03/05/2014 04:06 am Tom Musta

target-ppc: Add Flag for ISA V2.06 Floating Point Conversion

This patch adds a flag for the floating point conversion instructions
introduced in Power ISA 2.06B.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
fab7fe42 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA2.06 Float to Integer Instructions

This patch adds the four floating point to integer conversion instructions
introduced by Power ISA V2.06:

- Floating Convert to Integer Word Unsigned (fctiwu)
  - Floating Convert to Integer Word Unsigned with Round Toward...
a98eb9e9 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA 2.06 divwe[o] Instructions

This patch addes the signed Divide Word Extended instructions
which were introduced in Power ISA 2.06B.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Signed-off-by: Alexander Graf <>
1fa6c533 03/05/2014 04:06 am Tom Musta

target-ppc: Add Flag for ISA2.06 Atomic Instructions

This patch adds a flag for the atomic instructions introduced
in Power ISA V2.06B.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Signed-off-by: Alexander Graf <>
5c77a786 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA2.06 lbarx, lharx Instructions

This patch adds the byte and halfword variants of the Load and
Reserve instructions. Since there is much commonality among
all forms of Load and Reserve, a macro is provided and the existing
implementations of lwarx and ldarx are refactoried to use this...
98d1eb27 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA2.06 divdeu[o] Instructions

This patch adds the Divide Doubleword Extended Unsigned
instructions. This instruction requires dividing a 128-bit
value by a 64 bit value. Since 128 bit integer division is
not supported in TCG, a helper is used. An architecture...
e44259b6 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA2.06 divde[o] Instructions

This patch adds the Divide Doubleword Extended instructions.
The implementation builds on the unsigned helper provided in
the previous patch.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
6a4fda33 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA 2.06 divweu[o] Instructions

This patch addes the Unsigned Divide Word Extended instructions
which were introduced in Power ISA 2.06B.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Signed-off-by: Alexander Graf <>
7ee19fb9 03/05/2014 04:06 am Tom Musta

target-ppc: Scalar Non-Signalling Conversions

This patch adds the non-signalling scalar conversion instructions:

- VSX Scalar Convert Single Precision to Double Precision
    Non-Signalling (xscvspdpn)
  - VSX Scalar Convert Double Precision to Single Precision...
86ba37ed 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA2.06 bpermd Instruction

This patch adds the Bit Permute Doubleword (bpermd) instruction,
which was introduced in Power ISA 2.06 as part of the base 64-bit
architecture.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
a824bc19 03/05/2014 04:06 am Tom Musta

target-ppc: Add Flag for ISA2.06 Divide Extended Instructions

This patch adds a flag for the Divide Extended instructions that
were introduced in Power ISA V2.06B. The flag is added to the
Power7 and Power8 models.

Signed-off-by: Tom Musta <>...
f5c0f7f9 03/05/2014 04:06 am Tom Musta

target-ppc: Move To/From VSR Instructions

This patch adds the Move To VSR instructions (mfvsrd, mfvsrwz)
and Move From VSR instructions (mtvsrd, mtvsrwa, mtvsrwz). These
instructions are unusual in that they are considered a floating
point instruction if the indexed VSR is in the first half of the...
097ec5d8 03/05/2014 04:06 am Tom Musta

target-ppc: Floating Merge Word Instructions

This patch adds the Floating Merge Even Word (fmrgew) and Floating
Merge Odd Word (fmrgow) instructions.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Signed-off-by: Alexander Graf <>
3d1140bf 03/05/2014 04:06 am Tom Musta

target-ppc: Scalar Round to Single Precision

This patch adds the VSX Scalar Round to Single Precision (xsrsp)
instruction.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Signed-off-by: Alexander Graf <>
968e76bc 03/05/2014 04:06 am Tom Musta

target-ppc: VSX Stage 4: add xsrsqrtesp

This patch adds the VSX Scalar Reciprocal Square Root Estimate
Single Precision (xsrsqrtesp) instruction.

The existing VSX_RSQRTE() macro is modified to support rounding
of the intermediate double-precision result to single precision....
f53f81e0 03/05/2014 04:06 am Tom Musta

target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds

This patch adds the Single Precision VSX Scalar Fused Multiply-Add
instructions: xsmaddasp, xsmaddmsp, xssubasp, xssubmsp, xsnmaddasp,
xsnmaddmsp, xsnmsubasp, xsnmsubmsp.

The existing VSX_MADD() macro is modified to support rounding of the...
74698350 03/05/2014 04:06 am Tom Musta

target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp

This patch adds the VSX Scalar Convert Unsigned Integer Doubleword
to Floating Point Format and Round to Single Precision (xscvuxdsp)
and VSX Scalar Convert Signed Integer Douglbeword to Floating Point...
67a33f37 03/05/2014 04:06 am Tom Musta

target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc

This patchs adds the VSX Logical instructions that are new with
ISA V2.07:

- VSX Logical Equivalence (xxleqv)
  - VSX Logical NAND (xxlnand)
  - VSX Logical ORC (xxlorc)

Signed-off-by: Tom Musta <>...
b24d0b47 03/05/2014 04:06 am Tom Musta

target-ppc: VSX Stage 4: Add xsdivsp

This patch adds the VSX Scalar Divide Single Precision (xsdivsp)
instruction.

The existing VSX_DIV macro is modified to support rounding of the
intermediate double precision result to single precision.

Signed-off-by: Tom Musta <>...
2c0c52ae 03/05/2014 04:06 am Tom Musta

target-ppc: VSX Stage 4: Add xsresp

This patch adds the VSX Scalar Reciprocal Estimate Single Precision
(xsresp) instruction.

The existing VSX_RE macro is modified to support rounding of the
intermediate double precision result to single precision.

Signed-off-by: Tom Musta <>...
cea4e574 03/05/2014 04:06 am Tom Musta

target-ppc: VSX Stage 4: Add xssqrtsp

This patch adds the VSX Scalar Square Root Single Precision (xssqrtsp)
instruction.

The existing VSX_SQRT() macro is modified to support rounding of the
intermediate double-precision result to single-precision.

Signed-off-by: Tom Musta <>...
e16a626b 03/05/2014 04:06 am Tom Musta

target-ppc: VSX Stage 4: Add stxsiwx and stxsspx

This patch adds two store scalar instructions:

- Store VSX Scalar as Integer Word Indexed (stxsiwx)
  - Store VSX Scalar Single-Precision Indexed (stxsspx)

Signed-off-by: Tom Musta <>...
3fd0aadf 03/05/2014 04:06 am Tom Musta

target-ppc: VSX Stage 4: Add xsaddsp and xssubsp

This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and
VSX Scalar Subtract Single-Precision (xssubsp) instructions.

The existing VSX_ADD_SUB macro is modified to support the rounding
of the (intermediate) result to single-precision....
ab9408a2 03/05/2014 04:06 am Tom Musta

target-ppc: VSX Stage 4: Add xsmulsp

This patch adds the VSX Scalar Multiply Single-Precision (xsmulsp)
instruction.

The existing VSX_MUL macro is modified to support rounding of the
intermediate result to single precision.

Signed-off-by: Tom Musta <>...
e072fe79 03/05/2014 04:06 am Tom Musta

target-ppc: VSX Stage 4: Refactor lxsdx

This patch refactors the lxsdx generator. Resuable code is isolated
into a macro. The macro will be used in subsequent patches in this
series to implement other scalar load instructions.

Signed-off-by: Tom Musta <>...
cac7f0ba 03/05/2014 04:06 am Tom Musta

target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx

This patch adds the scalar load instructions introduced in ISA
V2.07:

- Load VSX Scalar as Integer Word Algebraic Indexd (lxsiwax)
  - Load VSX Scalar as Integer Word and Zero Indexed (lxsiwzx)
  - Load VSX Scalar Single-Precision Indexed (lxsspx)...
f026da78 03/05/2014 04:06 am Tom Musta

target-ppc: VSX Stage 4: Refactor stxsdx

This patch refactors the stxsdx instruction. Reusable code is
extracted into a macro which will be used in subsequent patches
in this series.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
5177d2ca 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX ISA2.06 Integer Conversion Instructions

This patch adds the VSX Integer Conversion instructions defined by
V2.06 of the PowerPC ISA:

- xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws
  - xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws...
88e33d08 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX Rounding Instructions

This patch adds the VSX Round to Floating Point Integer instructions:

- xsrdpi, xsrdpic, xsrdpim, xsrdpip, xsrdpiz
  - xvrdpi, xvrdpic, xvrdpim, xvrdpip, xvrdpiz
  - xvrspi, xvrspic, xvrspim, xvrspip, xvrspiz
...
dbcc48fa 03/05/2014 04:06 am Tom Musta

target-ppc: VSX Stage 4: Add VSX 2.07 Flag

This patch adds a flag to identify those VSX instructions that are
new to Power ISA V2.07. The flag is added to the Power 8 processor
initialization so that the P8 models understand how to decode and
emulate instructions in this category....
959e9c9d 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX xmax/xmin Instructions

This patch adds the VSX floating point maximum and minimum
instructions:

- xsmaxdp, xvmaxdp, xvmaxsp
  - xsmindp, xvmindp, xvminsp

Because of the Power ISA definitions of maximum and minimum
on various boundary cases, the standard softfloat comparison...
354a6dec 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX Vector Compare Instructions

This patch adds the VSX floating point compare vector instructions:

- xvcmpeqdp[.], xvcmpgedp[.], xvcmpgtdp[.]
  - xvcmpeqsp[.], xvcmpgesp[.], xvcmpgtsp[.]

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
ed8ac568 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX Floating Point to Floating Point Conversion Instructions

This patch adds the VSX instructions that convert between floating
point formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
5cb151ac 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX ISA2.06 xtsqrt Instructions

This patch adds the VSX floating point test for software square
root instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp,
xvtsqrtdp, xvtsqrtsp.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
595c6eef 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX ISA2.06 Multiply Add Instructions

This patch adds the VSX floating point multiply/add instructions
defined by V2.06 of the PowerPC ISA:

- xsmaddadp,  xvmaddadp,  xvmaddasp
  - xsmaddmdp,  xvmaddmdp,  xvmaddmsp
  - xsmsubadp,  xvmsubadp,  xvmsubasp...
4f17e9c7 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX xscmp*dp Instructions

This patch adds the VSX scalar floating point compare ordered
and unordered instructions.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Signed-off-by: Alexander Graf <>
2009227f 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX ISA2.06 xre Instructions

This patch adds the VSX floating point reciprocal estimate instructions
defined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
d32404fe 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX ISA2.06 xsqrt Instructions

This patch adds the VSX floating point square root instructions
defined by V2.06 of the PowerPC ISA: xssqrtdp, xvsqrtdp, xvsqrtsp.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
d3f9df8f 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX ISA2.06 xrsqrte Instructions

This patch adds the VSX floating point reciprocal square root
estimate instructions defined by V2.06 of the PowerPC ISA: xsrsqrtedp,
xvrsqrtedp, xvrsqrtesp.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
bc80838f 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX ISA2.06 xtdiv Instructions

This patch adds the VSX floating point test for software divide
instructions defined by V2.06 of the PowerPC ISA: xstdivdp, xvtdivdp,
and xvtdivsp.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
ee6e02c0 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX ISA2.06 xadd/xsub Instructions

This patch adds the floating point addition and subtraction
instructions defined by V2.06 of the PowerPC ISA: xssubdp,
xvsubdp and xvsubsp.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
5e591d88 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX ISA2.06 xmul Instructions

This patch adds the VSX floating point multiply instructions defined
by V2.06 of the PowerPC ISA: xsmuldp, xvmuldp, xvmulsp.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
4b98eeef 03/05/2014 04:06 am Tom Musta

target-ppc: Add VSX ISA2.06 xdiv Instructions

This patch adds the VSX floating point divide instructions defined
by V2.06 of the PowerPC ISA: xsdivdp, xvdivdp, xvdivsp.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
4e381819 03/05/2014 04:06 am Alexey Kardashevskiy

target-ppc: disable unsupported modes for SPR_CTRL/SPR_UCTRL

The Figure 17 "SPR encodings" of the PowerISA 2.07 describes CTRL SPR as:
  1. spr5-9 spr0-4 name mtspr mfspr len cat
    136 00100 01000 CTRL - no 32 S...
priviledged
59800ec8 03/05/2014 04:06 am Tom Musta

target-ppc: Add set_fprf Argument to fload_invalid_op_excp()

The fload_invalid_op_excp() function sets assorted invalid
operation status bits. However, it also implicitly modifies
the FPRF field of the PowerPC FPSCR. Many VSX instructions
set invalid operation bits but do not alter FPRF. Thus the...
3c3cbbdc 03/05/2014 04:06 am Tom Musta

target-ppc: General Support for VSX Helpers

This patch adds general support that will be used by the VSX helper
routines:

- a union describing the various VSR subfields.
  - access routines to get and set VSRs
  - VSX decoders
  - a general routine to generate a handler that invokes a VSX...
6cd8712c 03/05/2014 04:06 am Greg Kurz

PPC: KVM: add support for LPCR

The LPCR special purpose register was introduced with the PowerPC 970MP family.

This patch initializes LPCR for the following families:
- 970 MP
- POWER5+
- POWER7
- POWER8

Signed-off-by: Greg Kurz <>...
0dc083fe 03/05/2014 04:06 am Alexey Kardashevskiy

target-ppc: fix Authority Mask Register init value

The existing default value (-1) of the AMR register forbids data access
to all 32 classes. Since the guest linux does not change this register,
we end up with the guest hanging right after switching from the real to...
363248e8 03/05/2014 04:06 am Cédric Le Goater

mmu-hash64: fix Virtual Page Class Key Protection

commit f80872e21c07edd06eb343eeeefc8af404b518a6 (mmu-hash64: Implement
Virtual Page Class Key Protection) added a new page protection
mechanism based on page keys and the AMR register to control access.

The AMR register allows or prohibits reads and/or writes on a page...
7a7c05d7 03/05/2014 04:06 am Alexey Kardashevskiy

PPC: KVM: fix "set one register"

Due to missing @one_reg_id assignment in _spr_register(),
the kvm_get_one_reg/kvm_set_one_reg API has never really been working.

This reenables the API by assigning the @one_reg_id field in the SPR
descriptor.

Signed-off-by: Alexey Kardashevskiy <>...
ca480de6 03/05/2014 04:06 am Anton Blanchard

target-ppc: dump DAR and DSISR

The DAR and DSISR can be very useful when debugging issues, so add
them to ppc_cpu_dump_state. We had another bug in this area: all
of the v2.06 MMU types were missing.

Signed-off-by: Anton Blanchard <>
Signed-off-by: Alexander Graf <>
81d2fb4d 03/05/2014 04:06 am Alexey Kardashevskiy

target-ppc: remove powerpc 970gx

The 970GX definition was added in 2007 and it made sense then but this
version has never been released to the markets and it does not exist in
the real world so there is no point in emulating it.

This removes 970GX.

Signed-off-by: Alexey Kardashevskiy <>...
0bfe9299 03/05/2014 04:06 am Alexey Kardashevskiy

target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers

Assuming that "U" in SPR_UCTRL is for "user", there is inconsistency with
970 user manuals/P5-bookIV/PowerISA204 which define the number as:
  1. spr5-9 spr0-4 name mtspr mfspr len cat...
priviledged
40194917 03/05/2014 04:06 am Alexey Kardashevskiy

target-ppc: remove embedded MMU SPRs from 970, P5+/7/7+/8

PowerISA 2.04+ puts MMUCFG and MMUCSR0 SPRs to "E" (embedded) category so
remove it from POWER7/8 class as it is "S" (server) category.

Signed-off-by: Alexey Kardashevskiy <>
Signed-off-by: Alexander Graf <>
88ccd23a 03/05/2014 04:06 am Alexey Kardashevskiy

target-ppc: remove unsupported SPRs from 970 and P5+

SPR_750FX_HID2 and L2CR are not defined in 970* user manuals nor POWER5
bookIV nor PowerISA 2.04, the numbers assigned to them are not defined
either so remove them.

Signed-off-by: Alexey Kardashevskiy <>...
a5100e75 03/05/2014 04:06 am Alexey Kardashevskiy

target-ppc: fix compile error when PPC_DUMP_CPU is enabled

Since last use of PPC_DUMP_CPU by whoever he/she was, env->tlb became
a union and POWERPC CPU class got QOM'ed so defining PPC_DUMP_CPU
breaks compile.

This fixes compiler errors.

Signed-off-by: Alexey Kardashevskiy <>...
6475c9f0 03/05/2014 04:06 am Alexey Kardashevskiy

target-ppc: fix LPCR SPR number

PowerISA defines LPCR SPR number as 318=0x13E but QEMU uses the value of
316.

This fixes the definition of LPCR SPR.

Signed-off-by: Alexey Kardashevskiy <>
Signed-off-by: Alexander Graf <>
61e8a923 02/20/2014 03:05 pm Peter Maydell

Merge remote-tracking branch 'remotes/afaerber/tags/qom-devices-for-peter' into staging

QOM infrastructure fixes and device conversions

  • QTest cleanups and test cases for PCI NICs
  • NAND fix for "info qtree"
  • Cleanup and extension of QOM machine tests...
933b19ea 02/14/2014 12:42 pm Alexander Graf

PPC: KVM: Add missing address space to ldl_phys helper

We now have to pass an address space to our _phys helpers. During the
transition apparently the EPR exit path missed out, so let's put it there.

Signed-off-by: Alexander Graf <>
Signed-off-by: Peter Maydell <>
292363e1 02/13/2014 06:47 pm Andreas Färber

target-ppc: Make ppc40x CPUs available in ppcemb

Not only 44x CPUs (BookE) but also 40x CPUs can run with 1k page size.

Move the criteria to a central inline function to avoid repetition
and #ifdef'fery. Update qom-test to no longer exempt them.

Signed-off-by: Andreas Färber <>
ab1da857 02/11/2014 02:57 pm Edgar E. Iglesias

exec: Make stl_*_phys input an AddressSpace

Reviewed-by: Peter Maydell <>
Signed-off-by: Edgar E. Iglesias <>
f606604f 02/11/2014 02:57 pm Edgar E. Iglesias

exec: Make stq_*_phys input an AddressSpace

Reviewed-by: Peter Maydell <>
Signed-off-by: Edgar E. Iglesias <>
2c17449b 02/11/2014 02:57 pm Edgar E. Iglesias

exec: Make ldq/ldub_*_phys input an AddressSpace

Reviewed-by: Peter Maydell <>
Signed-off-by: Edgar E. Iglesias <>
fdfba1a2 02/11/2014 02:56 pm Edgar E. Iglesias

exec: Make ldl_*_phys input an AddressSpace

Reviewed-by: Peter Maydell <>
Signed-off-by: Edgar E. Iglesias <>
f976b09e 12/22/2013 08:15 pm Alexander Graf

PPC: Fix compilation with TCG debug

The recent VSX patches broken compilation of QEMU when configurated
with --enable-debug, as it was treating "target long" TCG variables
as "i64" which is not true for 32bit targets.

This patch fixes all the places that the compiler has found to use...
c2b63f03 12/20/2013 02:58 am Alexander Graf

PPC: Add VSX to hflags

We generate different code depending on whether MSR_VSX is set or
clear, so it needs to be part of our hflags too which indicate whether
we're still in the same translation block cache bucket.

Signed-off-by: Alexander Graf <>
acc42968 12/20/2013 02:58 am Tom Musta

Add xxsldwi

This patch adds the VSX Shift Left Double by Word Immediate
(xxsldwi) instruction.

Signed-off-by: Tom Musta <>
Signed-off-by: Alexander Graf <>
76c15fe0 12/20/2013 02:58 am Tom Musta

Add xxspltw

This patch adds the VSX Splat Word (xxsplatw) instruction.

This is the first instruction to use the UIM immediate field
and consequently a decoder is also added.

V2: reworked implementation per Richard Henderson's comments.

Signed-off-by: Tom Musta <>...
551e3ef7 12/20/2013 02:58 am Tom Musta

Add xxsel

This patch adds the VSX Select (xxsel) instruction.

The xxsel instruction has four VSR operands. Thus the xC
instruction decoder is added.

The xxsel instruction is massively overloaded in the opcode
table since only bits 26 and 27 are opcode bits. This...
79ca8a6a 12/20/2013 02:58 am Tom Musta

Add Power7 VSX Logical Instructions

This patch adds the VSX logical instructions that are defined
by the Version 2.06 Power ISA (aka Power7):

- xxland
   - xxlandc
   - xxlor
   - xxlxor
   - xxlnor

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
ce577d2e 12/20/2013 02:58 am Tom Musta

Add xxmrgh/xxmrgl

This patch adds the VSX Merge High Word and VSX Merge Low Word
instructions.

V2: Now implemented using deposit (per Richard Henderson's comment)

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
be574920 12/20/2013 02:58 am Tom Musta

Add VSX Vector Move Instructions

This patch adds the vector move instructions:

- xvabsdp - Vector Absolute Value Double-Precision
  - xvnabsdp - Vector Negative Absolute Value Double-Precision
  - xvnegdp - Vector Negate Double-Precision
  - xvcpsgndp - Vector Copy Sign Double-Precision...
df020ce0 12/20/2013 02:58 am Tom Musta

Add VSX Scalar Move Instructions

This patch adds the VSX scalar move instructions:

- xsabsdp (Scalar Absolute Value Double-Precision)
  - xsnabspd (Scalar Negative Absolute Value Double-Precision)
  - xsnegdp (Scalar Negate Double-Precision)
  - xscpsgndp (Scalar Copy Sign Double-Precision)...
b650d6a2 12/20/2013 02:57 am Alexey Kardashevskiy

target-ppc: move POWER7+ to a separate family

So far POWER7+ was a part of POWER7 family. However it has a different
PVR base value so in order to support PVR masks, it needs a separate
family class.

This adds a new family class, PVR base and mask values and moves...
86e61ce3 12/20/2013 02:57 am Tom Musta

Add stxvw4x

This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)
instruction.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Reviewed-by: Paolo Bonzini <>
Signed-off-by: Alexander Graf <>
9231ba9e 12/20/2013 02:57 am Tom Musta

Add stxsdx

This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)
instruction.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Reviewed-by: Paolo Bonzini <>
Signed-off-by: Alexander Graf <>
897e61d1 12/20/2013 02:57 am Tom Musta

Add lxvw4x

This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
instruction.

V2: changed to use deposit_i64 per Richard Henderson's review.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Reviewed-by: Paolo Bonzini <>...
ca03b467 12/20/2013 02:57 am Tom Musta

Add lxvdsx

This patch adds the Load VSX Vector Doubleword & Splat Indexed
(lxvdsx) instruction.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Reviewed-by: Paolo Bonzini <>
Signed-off-by: Alexander Graf <>
fa1832d7 12/20/2013 02:57 am Tom Musta

Add lxsdx

This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.

The lower 8 bytes of the target register are undefined; this
implementation leaves those bytes unaltered.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
cd73f2c9 12/20/2013 02:57 am Tom Musta

Add xxpermdi

This patch adds the xxpermdi instruction. The instruction
uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX
and BX). This results in overloading of the opcode table
with aliases, which can be seen in the GEN_XX3FORM_DM
macro.

Signed-off-by: Tom Musta <>...
fbed2478 12/20/2013 02:57 am Tom Musta

Add stxvd2x

This patch adds the stxvd2x instruction.

Signed-off-by: Tom Musta <>
Signed-off-by: Anton Blanchard <>
Signed-off-by: Alexander Graf <>
304af367 12/20/2013 02:57 am Tom Musta

Add lxvd2x

This patch adds the lxvd2x instruction.

Signed-off-by: Tom Musta <>
Signed-off-by: Anton Blanchard <>
Signed-off-by: Alexander Graf <>
472b24ce 12/20/2013 02:57 am Tom Musta

Add VSR to Global Registers

This patch adds VSX VSRs to the the list of global register indices.
More specifically, it adds the lower halves of the first 32 VSRs to
the list of global register indices. The upper halves of the first
32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs...
f9fc6d81 12/20/2013 02:57 am Tom Musta

Add VSX Instruction Decoders

This patch adds decoders for the VSX fields XT, XS, XA, XB and
DM. The first four are split fields and a general helper for
these types of fields is also added.

Signed-off-by: Tom Musta <>
Signed-off-by: Anton Blanchard <>...
1f29871c 12/20/2013 02:57 am Tom Musta

Add MSR VSX and Associated Exception

This patch adds support for the VSX bit of the PowerPC Machine
State Register (MSR) as well as the corresponding VSX Unavailable
exception.

The VSX bit is added to the defined bits masks of the Power7 and
Power8 CPU models....
74f23997 12/20/2013 02:57 am Tom Musta

Declare and Enable VSX

This patch adds the flag POWERPC_FLAG_VSX to the list of defined
flags and also adds this flag to the list of supported features of
the Power7 and Power8 CPUs. Additionally, the VSX instructions
are added to the list of TCG-enabled instruction....
3bc9ccc0 12/20/2013 02:57 am Alexey Kardashevskiy

powerpc: add PVR mask support

IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is no significant change
in behavior between versions, there is no point to add every single CPU
version in QEMU's CPU list. Also, new CPU versions of already supported...
c65f9a07 12/20/2013 02:57 am Greg Kurz

target-ppc: add stubs for KVM breakpoints

The latest update to v3.13-rc3 (bf63839f) breaks the
ppc build with KVM:

kvm-all.o: In function `kvm_update_guest_debug':
kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug'
kvm-all.o: In function `kvm_insert_breakpoint':...
793826cd 10/26/2013 12:25 am Andreas Färber

target-ppc: Fill in OpenFirmware names for some PowerPCCPU families

Set the expected values for POWER7, POWER7+, POWER8 and POWER5+.
Note that POWER5+ and POWER7+ are intentionally lacking the '+', so the
lack of a POWER7P family constitutes no problem.
...
3bbf37f2 10/26/2013 12:25 am Andreas Färber

spapr: Use DeviceClass::fw_name for device tree CPU node

Instead of relying on cpu_model, obtain the device tree node label
per CPU. Use DeviceClass::fw_name as source.

Whenever DeviceClass::fw_name is unknown, default to "PowerPC,UNKNOWN".

As a consequence, spapr_fixup_cpu_dt() can operate on each CPU's fw_name,...