PPC: KVM: suppress warnings about not supported SPRs
PR KVM lacks support of many SPRs in set/get one register API but it doesreally break PR KVM. So convert them to switchable traces for now.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Add ISA2.06 lfiwzx Instruction
This patch adds the Load Floating Point as Integer Word andZero Indexed (lfiwzx) instruction which was introduced inPower ISA 2.06.
Signed-off-by: Tom Musta <tommusta@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>...
PPC: KVM: store SLB slot number
When ppc_store_slb() is called from kvm_arch_get_registers(), it storesa SLB in CPUPPCState::slb[slot]. However it drops the slot number fromESID so when kvm_arch_put_registers() puts SLBs back to KVM, they do nothave correct "index" field anymore. This broke migration with LPCR_AIR...
target-ppc: Add ISA 2.06 ftdiv Instruction
This patch adds the Floating Point Test for Divide instruction whichwas introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta <tommusta@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: Add ISA 2.06 ftsqrt
This patch adds the Floating Point Test for Square Root instructionwhich was introduced in Power ISA 2.06.
target-ppc: Enable frsqrtes on Power7 and Power8
The frsqrtes instruction was introduced prior to ISA 2.06 and issupport on both the Power7 and Power8 processors. However, thisinstruction is handled as illegal in the current QEMU emulationmachines. This patch enables the existing implemention of frsqrtes...
target-ppc: Add ISA 2.06 fcfid[u][s] Instructions
This patch adds the fcfids, fcfidu and fcfidus instructions whichwere introduced in Power ISA 2.06B. A common macro is provided toeliminate repetitious code, and the existing fcfid instruction isrefactored to use this macro....
target-ppc: Fix and enable fri[mnpz]
The fri* series of instructions was introduced prior to ISA 2.06 andis supported on Power7 and Power8 hardware. However, the instructionis still considered illegal in the P7 and P8 QEMU emulation models.This patch enables these instructions for the P7 and P8 machines....
target-ppc: Add Flag for Power ISA V2.06 Floating Point Test Instructions
This patch adds a flag for Floating Point Test instructions that wereintroduced in Power ISA V2.06B.
target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions
This patch adds the byte and halfword variants of the Store Conditionalinstructions. A common macro is introduced and the existing implementationsof stwcx. and stdcx. are refactored to use this macro....
target-ppc: Add Flag for ISA V2.06 Floating Point Conversion
This patch adds a flag for the floating point conversion instructionsintroduced in Power ISA 2.06B.
target-ppc: Add ISA2.06 Float to Integer Instructions
This patch adds the four floating point to integer conversion instructionsintroduced by Power ISA V2.06:
- Floating Convert to Integer Word Unsigned (fctiwu) - Floating Convert to Integer Word Unsigned with Round Toward...
target-ppc: Add ISA 2.06 divwe[o] Instructions
This patch addes the signed Divide Word Extended instructionswhich were introduced in Power ISA 2.06B.
target-ppc: Add Flag for ISA2.06 Atomic Instructions
This patch adds a flag for the atomic instructions introducedin Power ISA V2.06B.
target-ppc: Add ISA2.06 lbarx, lharx Instructions
This patch adds the byte and halfword variants of the Load andReserve instructions. Since there is much commonality amongall forms of Load and Reserve, a macro is provided and the existingimplementations of lwarx and ldarx are refactoried to use this...
target-ppc: Add ISA2.06 divdeu[o] Instructions
This patch adds the Divide Doubleword Extended Unsignedinstructions. This instruction requires dividing a 128-bitvalue by a 64 bit value. Since 128 bit integer division isnot supported in TCG, a helper is used. An architecture...
target-ppc: Add ISA2.06 divde[o] Instructions
This patch adds the Divide Doubleword Extended instructions.The implementation builds on the unsigned helper provided inthe previous patch.
target-ppc: Add ISA 2.06 divweu[o] Instructions
This patch addes the Unsigned Divide Word Extended instructionswhich were introduced in Power ISA 2.06B.
target-ppc: Scalar Non-Signalling Conversions
This patch adds the non-signalling scalar conversion instructions:
- VSX Scalar Convert Single Precision to Double Precision Non-Signalling (xscvspdpn) - VSX Scalar Convert Double Precision to Single Precision...
target-ppc: Add ISA2.06 bpermd Instruction
This patch adds the Bit Permute Doubleword (bpermd) instruction,which was introduced in Power ISA 2.06 as part of the base 64-bitarchitecture.
target-ppc: Add Flag for ISA2.06 Divide Extended Instructions
This patch adds a flag for the Divide Extended instructions thatwere introduced in Power ISA V2.06B. The flag is added to thePower7 and Power8 models.
Signed-off-by: Tom Musta <tommusta@gmail.com>...
target-ppc: Move To/From VSR Instructions
This patch adds the Move To VSR instructions (mfvsrd, mfvsrwz)and Move From VSR instructions (mtvsrd, mtvsrwa, mtvsrwz). Theseinstructions are unusual in that they are considered a floatingpoint instruction if the indexed VSR is in the first half of the...
target-ppc: Floating Merge Word Instructions
This patch adds the Floating Merge Even Word (fmrgew) and FloatingMerge Odd Word (fmrgow) instructions.
target-ppc: Scalar Round to Single Precision
This patch adds the VSX Scalar Round to Single Precision (xsrsp)instruction.
target-ppc: VSX Stage 4: add xsrsqrtesp
This patch adds the VSX Scalar Reciprocal Square Root EstimateSingle Precision (xsrsqrtesp) instruction.
The existing VSX_RSQRTE() macro is modified to support roundingof the intermediate double-precision result to single precision....
target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds
This patch adds the Single Precision VSX Scalar Fused Multiply-Addinstructions: xsmaddasp, xsmaddmsp, xssubasp, xssubmsp, xsnmaddasp,xsnmaddmsp, xsnmsubasp, xsnmsubmsp.
The existing VSX_MADD() macro is modified to support rounding of the...
target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp
This patch adds the VSX Scalar Convert Unsigned Integer Doublewordto Floating Point Format and Round to Single Precision (xscvuxdsp)and VSX Scalar Convert Signed Integer Douglbeword to Floating Point...
target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc
This patchs adds the VSX Logical instructions that are new withISA V2.07:
- VSX Logical Equivalence (xxleqv) - VSX Logical NAND (xxlnand) - VSX Logical ORC (xxlorc)
target-ppc: VSX Stage 4: Add xsdivsp
This patch adds the VSX Scalar Divide Single Precision (xsdivsp)instruction.
The existing VSX_DIV macro is modified to support rounding of theintermediate double precision result to single precision.
target-ppc: VSX Stage 4: Add xsresp
This patch adds the VSX Scalar Reciprocal Estimate Single Precision(xsresp) instruction.
The existing VSX_RE macro is modified to support rounding of theintermediate double precision result to single precision.
target-ppc: VSX Stage 4: Add xssqrtsp
This patch adds the VSX Scalar Square Root Single Precision (xssqrtsp)instruction.
The existing VSX_SQRT() macro is modified to support rounding of theintermediate double-precision result to single-precision.
target-ppc: VSX Stage 4: Add stxsiwx and stxsspx
This patch adds two store scalar instructions:
- Store VSX Scalar as Integer Word Indexed (stxsiwx) - Store VSX Scalar Single-Precision Indexed (stxsspx)
target-ppc: VSX Stage 4: Add xsaddsp and xssubsp
This patch adds the VSX Scalar Add Single-Precision (xsaddsp) andVSX Scalar Subtract Single-Precision (xssubsp) instructions.
The existing VSX_ADD_SUB macro is modified to support the roundingof the (intermediate) result to single-precision....
target-ppc: VSX Stage 4: Add xsmulsp
This patch adds the VSX Scalar Multiply Single-Precision (xsmulsp)instruction.
The existing VSX_MUL macro is modified to support rounding of theintermediate result to single precision.
target-ppc: VSX Stage 4: Refactor lxsdx
This patch refactors the lxsdx generator. Resuable code is isolatedinto a macro. The macro will be used in subsequent patches in thisseries to implement other scalar load instructions.
target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx
This patch adds the scalar load instructions introduced in ISAV2.07:
- Load VSX Scalar as Integer Word Algebraic Indexd (lxsiwax) - Load VSX Scalar as Integer Word and Zero Indexed (lxsiwzx) - Load VSX Scalar Single-Precision Indexed (lxsspx)...
target-ppc: VSX Stage 4: Refactor stxsdx
This patch refactors the stxsdx instruction. Reusable code isextracted into a macro which will be used in subsequent patchesin this series.
target-ppc: Add VSX ISA2.06 Integer Conversion Instructions
This patch adds the VSX Integer Conversion instructions defined byV2.06 of the PowerPC ISA:
- xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws - xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws...
target-ppc: Add VSX Rounding Instructions
This patch adds the VSX Round to Floating Point Integer instructions:
- xsrdpi, xsrdpic, xsrdpim, xsrdpip, xsrdpiz - xvrdpi, xvrdpic, xvrdpim, xvrdpip, xvrdpiz - xvrspi, xvrspic, xvrspim, xvrspip, xvrspiz...
target-ppc: VSX Stage 4: Add VSX 2.07 Flag
This patch adds a flag to identify those VSX instructions that arenew to Power ISA V2.07. The flag is added to the Power 8 processorinitialization so that the P8 models understand how to decode andemulate instructions in this category....
target-ppc: Add VSX xmax/xmin Instructions
This patch adds the VSX floating point maximum and minimuminstructions:
- xsmaxdp, xvmaxdp, xvmaxsp - xsmindp, xvmindp, xvminsp
Because of the Power ISA definitions of maximum and minimumon various boundary cases, the standard softfloat comparison...
target-ppc: Add VSX Vector Compare Instructions
This patch adds the VSX floating point compare vector instructions:
- xvcmpeqdp[.], xvcmpgedp[.], xvcmpgtdp[.] - xvcmpeqsp[.], xvcmpgesp[.], xvcmpgtsp[.]
target-ppc: Add VSX Floating Point to Floating Point Conversion Instructions
This patch adds the VSX instructions that convert between floatingpoint formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp.
target-ppc: Add VSX ISA2.06 xtsqrt Instructions
This patch adds the VSX floating point test for software squareroot instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp,xvtsqrtdp, xvtsqrtsp.
target-ppc: Add VSX ISA2.06 Multiply Add Instructions
This patch adds the VSX floating point multiply/add instructionsdefined by V2.06 of the PowerPC ISA:
- xsmaddadp, xvmaddadp, xvmaddasp - xsmaddmdp, xvmaddmdp, xvmaddmsp - xsmsubadp, xvmsubadp, xvmsubasp...
target-ppc: Add VSX xscmp*dp Instructions
This patch adds the VSX scalar floating point compare orderedand unordered instructions.
target-ppc: Add VSX ISA2.06 xre Instructions
This patch adds the VSX floating point reciprocal estimate instructionsdefined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp.
target-ppc: Add VSX ISA2.06 xsqrt Instructions
This patch adds the VSX floating point square root instructionsdefined by V2.06 of the PowerPC ISA: xssqrtdp, xvsqrtdp, xvsqrtsp.
target-ppc: Add VSX ISA2.06 xrsqrte Instructions
This patch adds the VSX floating point reciprocal square rootestimate instructions defined by V2.06 of the PowerPC ISA: xsrsqrtedp,xvrsqrtedp, xvrsqrtesp.
target-ppc: Add VSX ISA2.06 xtdiv Instructions
This patch adds the VSX floating point test for software divideinstructions defined by V2.06 of the PowerPC ISA: xstdivdp, xvtdivdp,and xvtdivsp.
target-ppc: Add VSX ISA2.06 xadd/xsub Instructions
This patch adds the floating point addition and subtractioninstructions defined by V2.06 of the PowerPC ISA: xssubdp,xvsubdp and xvsubsp.
target-ppc: Add VSX ISA2.06 xmul Instructions
This patch adds the VSX floating point multiply instructions definedby V2.06 of the PowerPC ISA: xsmuldp, xvmuldp, xvmulsp.
target-ppc: Add VSX ISA2.06 xdiv Instructions
This patch adds the VSX floating point divide instructions definedby V2.06 of the PowerPC ISA: xsdivdp, xvdivdp, xvdivsp.
target-ppc: disable unsupported modes for SPR_CTRL/SPR_UCTRL
priviledged
target-ppc: Add set_fprf Argument to fload_invalid_op_excp()
The fload_invalid_op_excp() function sets assorted invalidoperation status bits. However, it also implicitly modifiesthe FPRF field of the PowerPC FPSCR. Many VSX instructionsset invalid operation bits but do not alter FPRF. Thus the...
target-ppc: General Support for VSX Helpers
This patch adds general support that will be used by the VSX helperroutines:
- a union describing the various VSR subfields. - access routines to get and set VSRs - VSX decoders - a general routine to generate a handler that invokes a VSX...
PPC: KVM: add support for LPCR
The LPCR special purpose register was introduced with the PowerPC 970MP family.
This patch initializes LPCR for the following families:- 970 MP- POWER5+- POWER7- POWER8
Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com>...
target-ppc: fix Authority Mask Register init value
The existing default value (-1) of the AMR register forbids data accessto all 32 classes. Since the guest linux does not change this register,we end up with the guest hanging right after switching from the real to...
mmu-hash64: fix Virtual Page Class Key Protection
commit f80872e21c07edd06eb343eeeefc8af404b518a6 (mmu-hash64: ImplementVirtual Page Class Key Protection) added a new page protectionmechanism based on page keys and the AMR register to control access.
The AMR register allows or prohibits reads and/or writes on a page...
PPC: KVM: fix "set one register"
Due to missing @one_reg_id assignment in _spr_register(),the kvm_get_one_reg/kvm_set_one_reg API has never really been working.
This reenables the API by assigning the @one_reg_id field in the SPRdescriptor.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>...
target-ppc: dump DAR and DSISR
The DAR and DSISR can be very useful when debugging issues, so addthem to ppc_cpu_dump_state. We had another bug in this area: allof the v2.06 MMU types were missing.
Signed-off-by: Anton Blanchard <anton@samba.org>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: remove powerpc 970gx
The 970GX definition was added in 2007 and it made sense then but thisversion has never been released to the markets and it does not exist inthe real world so there is no point in emulating it.
This removes 970GX.
target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers
target-ppc: remove embedded MMU SPRs from 970, P5+/7/7+/8
PowerISA 2.04+ puts MMUCFG and MMUCSR0 SPRs to "E" (embedded) category soremove it from POWER7/8 class as it is "S" (server) category.
target-ppc: remove unsupported SPRs from 970 and P5+
SPR_750FX_HID2 and L2CR are not defined in 970* user manuals nor POWER5bookIV nor PowerISA 2.04, the numbers assigned to them are not definedeither so remove them.
target-ppc: fix compile error when PPC_DUMP_CPU is enabled
Since last use of PPC_DUMP_CPU by whoever he/she was, env->tlb becamea union and POWERPC CPU class got QOM'ed so defining PPC_DUMP_CPUbreaks compile.
This fixes compiler errors.
target-ppc: fix LPCR SPR number
PowerISA defines LPCR SPR number as 318=0x13E but QEMU uses the value of316.
This fixes the definition of LPCR SPR.
Merge remote-tracking branch 'remotes/afaerber/tags/qom-devices-for-peter' into staging
QOM infrastructure fixes and device conversions
PPC: KVM: Add missing address space to ldl_phys helper
We now have to pass an address space to our _phys helpers. During thetransition apparently the EPR exit path missed out, so let's put it there.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target-ppc: Make ppc40x CPUs available in ppcemb
Not only 44x CPUs (BookE) but also 40x CPUs can run with 1k page size.
Move the criteria to a central inline function to avoid repetitionand #ifdef'fery. Update qom-test to no longer exempt them.
Signed-off-by: Andreas Färber <afaerber@suse.de>
exec: Make stl_*_phys input an AddressSpace
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
exec: Make stq_*_phys input an AddressSpace
exec: Make ldq/ldub_*_phys input an AddressSpace
exec: Make ldl_*_phys input an AddressSpace
PPC: Fix compilation with TCG debug
The recent VSX patches broken compilation of QEMU when configuratedwith --enable-debug, as it was treating "target long" TCG variablesas "i64" which is not true for 32bit targets.
This patch fixes all the places that the compiler has found to use...
PPC: Add VSX to hflags
We generate different code depending on whether MSR_VSX is set orclear, so it needs to be part of our hflags too which indicate whetherwe're still in the same translation block cache bucket.
Signed-off-by: Alexander Graf <agraf@suse.de>
Add xxsldwi
This patch adds the VSX Shift Left Double by Word Immediate(xxsldwi) instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>
Add xxspltw
This patch adds the VSX Splat Word (xxsplatw) instruction.
This is the first instruction to use the UIM immediate fieldand consequently a decoder is also added.
V2: reworked implementation per Richard Henderson's comments.
Add xxsel
This patch adds the VSX Select (xxsel) instruction.
The xxsel instruction has four VSR operands. Thus the xCinstruction decoder is added.
The xxsel instruction is massively overloaded in the opcodetable since only bits 26 and 27 are opcode bits. This...
Add Power7 VSX Logical Instructions
This patch adds the VSX logical instructions that are definedby the Version 2.06 Power ISA (aka Power7):
- xxland - xxlandc - xxlor - xxlxor - xxlnor
Add xxmrgh/xxmrgl
This patch adds the VSX Merge High Word and VSX Merge Low Wordinstructions.
V2: Now implemented using deposit (per Richard Henderson's comment)
Add VSX Vector Move Instructions
This patch adds the vector move instructions:
- xvabsdp - Vector Absolute Value Double-Precision - xvnabsdp - Vector Negative Absolute Value Double-Precision - xvnegdp - Vector Negate Double-Precision - xvcpsgndp - Vector Copy Sign Double-Precision...
Add VSX Scalar Move Instructions
This patch adds the VSX scalar move instructions:
- xsabsdp (Scalar Absolute Value Double-Precision) - xsnabspd (Scalar Negative Absolute Value Double-Precision) - xsnegdp (Scalar Negate Double-Precision) - xscpsgndp (Scalar Copy Sign Double-Precision)...
target-ppc: move POWER7+ to a separate family
So far POWER7+ was a part of POWER7 family. However it has a differentPVR base value so in order to support PVR masks, it needs a separatefamily class.
This adds a new family class, PVR base and mask values and moves...
Add stxvw4x
This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Alexander Graf <agraf@suse.de>
Add stxsdx
This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)instruction.
Add lxvw4x
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)instruction.
V2: changed to use deposit_i64 per Richard Henderson's review.
Signed-off-by: Tom Musta <tommusta@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>...
Add lxvdsx
This patch adds the Load VSX Vector Doubleword & Splat Indexed(lxvdsx) instruction.
Add lxsdx
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)instruction.
The lower 8 bytes of the target register are undefined; thisimplementation leaves those bytes unaltered.
Add xxpermdi
This patch adds the xxpermdi instruction. The instructionuses bits 22, 23, 29 and 30 for non-opcode fields (DM, AXand BX). This results in overloading of the opcode tablewith aliases, which can be seen in the GEN_XX3FORM_DMmacro.
Add stxvd2x
This patch adds the stxvd2x instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>Signed-off-by: Anton Blanchard <anton@samba.org>Signed-off-by: Alexander Graf <agraf@suse.de>
Add lxvd2x
This patch adds the lxvd2x instruction.
Add VSR to Global Registers
This patch adds VSX VSRs to the the list of global register indices.More specifically, it adds the lower halves of the first 32 VSRs tothe list of global register indices. The upper halves of the first32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs...
Add VSX Instruction Decoders
This patch adds decoders for the VSX fields XT, XS, XA, XB andDM. The first four are split fields and a general helper forthese types of fields is also added.
Signed-off-by: Tom Musta <tommusta@gmail.com>Signed-off-by: Anton Blanchard <anton@samba.org>...
Add MSR VSX and Associated Exception
This patch adds support for the VSX bit of the PowerPC MachineState Register (MSR) as well as the corresponding VSX Unavailableexception.
The VSX bit is added to the defined bits masks of the Power7 andPower8 CPU models....
Declare and Enable VSX
This patch adds the flag POWERPC_FLAG_VSX to the list of definedflags and also adds this flag to the list of supported features ofthe Power7 and Power8 CPUs. Additionally, the VSX instructionsare added to the list of TCG-enabled instruction....
powerpc: add PVR mask support
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits anda CPU version in lower 16 bits. Since there is no significant changein behavior between versions, there is no point to add every single CPUversion in QEMU's CPU list. Also, new CPU versions of already supported...
target-ppc: add stubs for KVM breakpoints
The latest update to v3.13-rc3 (bf63839f) breaks theppc build with KVM:
kvm-all.o: In function `kvm_update_guest_debug':kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug'kvm-all.o: In function `kvm_insert_breakpoint':...
target-ppc: Fill in OpenFirmware names for some PowerPCCPU families
Set the expected values for POWER7, POWER7+, POWER8 and POWER5+.Note that POWER5+ and POWER7+ are intentionally lacking the '+', so thelack of a POWER7P family constitutes no problem....
spapr: Use DeviceClass::fw_name for device tree CPU node
Instead of relying on cpu_model, obtain the device tree node labelper CPU. Use DeviceClass::fw_name as source.
Whenever DeviceClass::fw_name is unknown, default to "PowerPC,UNKNOWN".
As a consequence, spapr_fixup_cpu_dt() can operate on each CPU's fw_name,...