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root / target-ppc @ b36f100e

Name Size
Makefile.objs 455 Bytes
STATUS 10.4 kB
arch_dump.c 6.5 kB
cpu-models.c 64.3 kB
cpu-models.h 29.7 kB
cpu-qom.h 3.6 kB
cpu.h 88.4 kB
excp_helper.c 34.7 kB
fpu_helper.c 107 kB
gdbstub.c 3.8 kB
helper.h 21.4 kB
helper_regs.h 3.4 kB
int_helper.c 55.3 kB
kvm-stub.c 400 Bytes
kvm.c 51.8 kB
kvm_ppc.c 1.2 kB
kvm_ppc.h 4.8 kB
machine.c 14.8 kB
mem_helper.c 8.3 kB
mfrom_table.c 3.3 kB
mfrom_table_gen.c 653 Bytes
misc_helper.c 3.5 kB
mmu-hash32.c 16 kB
mmu-hash32.h 3.3 kB
mmu-hash64.c 15.6 kB
mmu-hash64.h 4.7 kB
mmu_helper.c 88.4 kB
timebase_helper.c 4.3 kB
translate.c 413.5 kB
translate_init.c 300.6 kB
user_only_helper.c 1.4 kB

Latest revisions

# Date Author Comment
b36f100e 03/05/2014 04:06 am Alexey Kardashevskiy

PPC: KVM: suppress warnings about not supported SPRs

PR KVM lacks support of many SPRs in set/get one register API but it does
really break PR KVM. So convert them to switchable traces for now.

Signed-off-by: Alexey Kardashevskiy <>
Signed-off-by: Alexander Graf <>
66c3e328 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA2.06 lfiwzx Instruction

This patch adds the Load Floating Point as Integer Word and
Zero Indexed (lfiwzx) instruction which was introduced in
Power ISA 2.06.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
69b31b90 03/05/2014 04:06 am Alexey Kardashevskiy

PPC: KVM: store SLB slot number

When ppc_store_slb() is called from kvm_arch_get_registers(), it stores
a SLB in CPUPPCState::slb[slot]. However it drops the slot number from
ESID so when kvm_arch_put_registers() puts SLBs back to KVM, they do not
have correct "index" field anymore. This broke migration with LPCR_AIR...
da29cb7b 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA 2.06 ftdiv Instruction

This patch adds the Floating Point Test for Divide instruction which
was introduced in Power ISA 2.06B.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Signed-off-by: Alexander Graf <>
6d41d146 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA 2.06 ftsqrt

This patch adds the Floating Point Test for Square Root instruction
which was introduced in Power ISA 2.06.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>
Signed-off-by: Alexander Graf <>
ce8ca30b 03/05/2014 04:06 am Tom Musta

target-ppc: Enable frsqrtes on Power7 and Power8

The frsqrtes instruction was introduced prior to ISA 2.06 and is
support on both the Power7 and Power8 processors. However, this
instruction is handled as illegal in the current QEMU emulation
machines. This patch enables the existing implemention of frsqrtes...
28288b48 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA 2.06 fcfid[u][s] Instructions

This patch adds the fcfids, fcfidu and fcfidus instructions which
were introduced in Power ISA 2.06B. A common macro is provided to
eliminate repetitious code, and the existing fcfid instruction is
refactored to use this macro....
c7386080 03/05/2014 04:06 am Tom Musta

target-ppc: Fix and enable fri[mnpz]

The fri* series of instructions was introduced prior to ISA 2.06 and
is supported on Power7 and Power8 hardware. However, the instruction
is still considered illegal in the P7 and P8 QEMU emulation models.
This patch enables these instructions for the P7 and P8 machines....
29a0e4e9 03/05/2014 04:06 am Tom Musta

target-ppc: Add Flag for Power ISA V2.06 Floating Point Test Instructions

This patch adds a flag for Floating Point Test instructions that were
introduced in Power ISA V2.06B.

Signed-off-by: Tom Musta <>
Reviewed-by: Richard Henderson <>...
fab7fe42 03/05/2014 04:06 am Tom Musta

target-ppc: Add ISA2.06 Float to Integer Instructions

This patch adds the four floating point to integer conversion instructions
introduced by Power ISA V2.06:

- Floating Convert to Integer Word Unsigned (fctiwu)
  - Floating Convert to Integer Word Unsigned with Round Toward...

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